======================================================================== ** ELF Header Information File Name: bsp_led.o Machine class: ELFCLASS32 (32-bit) Data encoding: ELFDATA2LSB (Little endian) Header version: EV_CURRENT (Current version) Operating System ABI: none ABI Version: 0 File Type: ET_REL (Relocatable object) (1) Machine: EM_ARM (ARM) Entry offset (in SHF_ENTRYSECT section): 0x00000000 Flags: None (0x05000000) ARM ELF revision: 5 (ABI version 2) Built with Component: ARM Compiler 5.06 update 3 (build 300) Tool: armasm [4d35c6] Component: ARM Compiler 5.06 update 3 (build 300) Tool: armlink [4d35c9] Header size: 52 bytes (0x34) Program header entry size: 0 bytes (0x0) Section header entry size: 40 bytes (0x28) Program header entries: 0 Section header entries: 443 Program header offset: 0 (0x00000000) Section header offset: 979312 (0x000ef170) Section header string table index: 440 ======================================================================== ** Section #1 '.rev16_text' (SHT_PROGBITS) [SHF_ALLOC + SHF_EXECINSTR] Size : 4 bytes (alignment 4) Address: 0x00000000 ** Section #2 '.revsh_text' (SHT_PROGBITS) [SHF_ALLOC + SHF_EXECINSTR] Size : 4 bytes (alignment 4) Address: 0x00000000 ** Section #3 '.rrx_text' (SHT_PROGBITS) [SHF_ALLOC + SHF_EXECINSTR] Size : 6 bytes (alignment 4) Address: 0x00000000 ** Section #4 'i.LED_GPIO_Config' (SHT_PROGBITS) [SHF_ALLOC + SHF_EXECINSTR] Size : 168 bytes (alignment 4) Address: 0x00000000 ** Section #344 '.reli.LED_GPIO_Config' (SHT_REL) Size : 40 bytes (alignment 4) Symbol table #343 '.symtab' 5 relocations applied to section #4 'i.LED_GPIO_Config' ** Section #5 '.debug_info' (SHT_PROGBITS) Size : 276 bytes 000000: Header: size 0x110 bytes, dwarf version 3, abbrevp __ARM_asm.debug_abbrev.1, address size 4 00000b: 1 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\\..\\User\\led\\bsp_led.c 000029: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: armasm [4d35c6] 000071: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL库例程 - 副本\5-GPIO输出—使用固件库点亮LED灯-MDK\Project\RVMDK（uv5） 0000d6: DW_AT_low_pc .rev16_text 0000da: DW_AT_high_pc 0x4+.rev16_text 0000de: DW_AT_stmt_list 0x0 0000e2: 2 = 0x2e (DW_TAG_subprogram) 0000e3: DW_AT_name __asm___9_bsp_led_c_dd8e8b2c____REV16 000109: DW_AT_low_pc .rev16_text 00010d: DW_AT_high_pc 0x4+.rev16_text 000111: 0 null 000112: 0 padding 000113: 0 padding ** Section #345 '.rel.debug_info' (SHT_REL) Size : 48 bytes (alignment 4) Symbol table #343 '.symtab' 6 relocations applied to section #5 '.debug_info' ** Section #6 '.debug_line' (SHT_PROGBITS) Size : 100 bytes 000000: Header: length 96 (not including this field) version 3 prologue length 72 minimum instruction length 1 default is_stmt 1 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\\..\\Libraries\\CMSIS\\Include\\": 2e 2e 5c 5c 2e 2e 5c 5c 4c 69 62 72 61 72 69 65 73 5c 5c 43 4d 53 49 53 5c 5c 49 6e 63 6c 75 64 65 5c 5c 00 00003f: directory "" : 00 000040: file "cmsis_armcc.h": dir 1 time 0x0 length 0: 63 6d 73 69 73 5f 61 72 6d 63 63 2e 68 00 01 00 00 000051: file "" : 00 000052: DW_LNE_set_address .rev16_text: 00 05 02 00 00 00 00 000059: DW_LNS_advance_line 389 : 03 85 03 00005c: DW_LNS_copy : 01 00000000: ..\\..\\Libraries\\CMSIS\\Include\\cmsis_armcc.h:390.0 [ 00005d: SPECIAL(1, 2) : 1a 00000002: ..\\..\\Libraries\\CMSIS\\Include\\cmsis_armcc.h:391.0 [ 00005e: DW_LNS_advance_pc 0x2 : 02 02 000060: DW_LNS_negate_stmt : 06 000061: DW_LNE_end sequence : 00 01 01 00000004: ..\\..\\Libraries\\CMSIS\\Include\\cmsis_armcc.h:391.0 ** Section #346 '.rel.debug_line' (SHT_REL) Size : 8 bytes (alignment 4) Symbol table #343 '.symtab' 1 relocations applied to section #6 '.debug_line' ** Section #7 '.debug_info' (SHT_PROGBITS) Size : 276 bytes 000000: Header: size 0x110 bytes, dwarf version 3, abbrevp __ARM_asm.debug_abbrev.1, address size 4 00000b: 1 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\\..\\User\\led\\bsp_led.c 000029: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: armasm [4d35c6] 000071: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL库例程 - 副本\5-GPIO输出—使用固件库点亮LED灯-MDK\Project\RVMDK（uv5） 0000d6: DW_AT_low_pc .revsh_text 0000da: DW_AT_high_pc 0x4+.revsh_text 0000de: DW_AT_stmt_list 0x0 0000e2: 2 = 0x2e (DW_TAG_subprogram) 0000e3: DW_AT_name __asm___9_bsp_led_c_dd8e8b2c____REVSH 000109: DW_AT_low_pc .revsh_text 00010d: DW_AT_high_pc 0x4+.revsh_text 000111: 0 null 000112: 0 padding 000113: 0 padding ** Section #347 '.rel.debug_info' (SHT_REL) Size : 48 bytes (alignment 4) Symbol table #343 '.symtab' 6 relocations applied to section #7 '.debug_info' ** Section #8 '.debug_line' (SHT_PROGBITS) Size : 100 bytes 000000: Header: length 96 (not including this field) version 3 prologue length 72 minimum instruction length 1 default is_stmt 1 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\\..\\Libraries\\CMSIS\\Include\\": 2e 2e 5c 5c 2e 2e 5c 5c 4c 69 62 72 61 72 69 65 73 5c 5c 43 4d 53 49 53 5c 5c 49 6e 63 6c 75 64 65 5c 5c 00 00003f: directory "" : 00 000040: file "cmsis_armcc.h": dir 1 time 0x0 length 0: 63 6d 73 69 73 5f 61 72 6d 63 63 2e 68 00 01 00 00 000051: file "" : 00 000052: DW_LNE_set_address .revsh_text: 00 05 02 00 00 00 00 000059: DW_LNS_advance_line 403 : 03 93 03 00005c: DW_LNS_copy : 01 00000000: ..\\..\\Libraries\\CMSIS\\Include\\cmsis_armcc.h:404.0 [ 00005d: SPECIAL(1, 2) : 1a 00000002: ..\\..\\Libraries\\CMSIS\\Include\\cmsis_armcc.h:405.0 [ 00005e: DW_LNS_advance_pc 0x2 : 02 02 000060: DW_LNS_negate_stmt : 06 000061: DW_LNE_end sequence : 00 01 01 00000004: ..\\..\\Libraries\\CMSIS\\Include\\cmsis_armcc.h:405.0 ** Section #348 '.rel.debug_line' (SHT_REL) Size : 8 bytes (alignment 4) Symbol table #343 '.symtab' 1 relocations applied to section #8 '.debug_line' ** Section #9 '.debug_info' (SHT_PROGBITS) Size : 276 bytes 000000: Header: size 0x110 bytes, dwarf version 3, abbrevp __ARM_asm.debug_abbrev.1, address size 4 00000b: 1 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\\..\\User\\led\\bsp_led.c 000029: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: armasm [4d35c6] 000071: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL库例程 - 副本\5-GPIO输出—使用固件库点亮LED灯-MDK\Project\RVMDK（uv5） 0000d6: DW_AT_low_pc .rrx_text 0000da: DW_AT_high_pc 0x6+.rrx_text 0000de: DW_AT_stmt_list 0x0 0000e2: 2 = 0x2e (DW_TAG_subprogram) 0000e3: DW_AT_name __asm___9_bsp_led_c_dd8e8b2c____RRX 000107: DW_AT_low_pc .rrx_text 00010b: DW_AT_high_pc 0x6+.rrx_text 00010f: 0 null 000110: 0 padding 000111: 0 padding 000112: 0 padding 000113: 0 padding ** Section #349 '.rel.debug_info' (SHT_REL) Size : 48 bytes (alignment 4) Symbol table #343 '.symtab' 6 relocations applied to section #9 '.debug_info' ** Section #10 '.debug_line' (SHT_PROGBITS) Size : 100 bytes 000000: Header: length 96 (not including this field) version 3 prologue length 72 minimum instruction length 1 default is_stmt 1 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\\..\\Libraries\\CMSIS\\Include\\": 2e 2e 5c 5c 2e 2e 5c 5c 4c 69 62 72 61 72 69 65 73 5c 5c 43 4d 53 49 53 5c 5c 49 6e 63 6c 75 64 65 5c 5c 00 00003f: directory "" : 00 000040: file "cmsis_armcc.h": dir 1 time 0x0 length 0: 63 6d 73 69 73 5f 61 72 6d 63 63 2e 68 00 01 00 00 000051: file "" : 00 000052: DW_LNE_set_address .rrx_text : 00 05 02 00 00 00 00 000059: DW_LNS_advance_line 588 : 03 cc 04 00005c: DW_LNS_copy : 01 00000000: ..\\..\\Libraries\\CMSIS\\Include\\cmsis_armcc.h:589.0 [ 00005d: SPECIAL(1, 4) : 26 00000004: ..\\..\\Libraries\\CMSIS\\Include\\cmsis_armcc.h:590.0 [ 00005e: DW_LNS_advance_pc 0x2 : 02 02 000060: DW_LNS_negate_stmt : 06 000061: DW_LNE_end sequence : 00 01 01 00000006: ..\\..\\Libraries\\CMSIS\\Include\\cmsis_armcc.h:590.0 ** Section #350 '.rel.debug_line' (SHT_REL) Size : 8 bytes (alignment 4) Symbol table #343 '.symtab' 1 relocations applied to section #10 '.debug_line' ** Section #11 '.debug_frame' (SHT_PROGBITS) Size : 116 bytes CIE 000000: version 3, "armcc+", code align 000001, data align fffffffc, return reg r14 DW_CFA_def_cfa_sf r13=0 DW_CFA_undefined r0 DW_CFA_undefined r1 DW_CFA_undefined r2 DW_CFA_undefined r3 DW_CFA_same_value r4 DW_CFA_same_value r5 DW_CFA_same_value r6 DW_CFA_same_value r7 DW_CFA_same_value r8 DW_CFA_same_value r9 DW_CFA_same_value r10 DW_CFA_same_value r11 DW_CFA_undefined r12 DW_CFA_same_value r14 DW_CFA_undefined r256 DW_CFA_undefined r257 DW_CFA_undefined r258 DW_CFA_undefined r259 DW_CFA_undefined r260 DW_CFA_undefined r261 DW_CFA_undefined r262 DW_CFA_undefined r263 DW_CFA_same_value r264 DW_CFA_same_value r265 DW_CFA_same_value r266 DW_CFA_same_value r267 DW_CFA_same_value r268 DW_CFA_same_value r269 DW_CFA_same_value r270 DW_CFA_same_value r271 DW_CFA_nop DW_CFA_nop FDE 000064: CIE 000000, init loc 000000, range 000004 ** Section #351 '.rel.debug_frame' (SHT_REL) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' 2 relocations applied to section #11 '.debug_frame' ** Section #12 '.debug_frame' (SHT_PROGBITS) Size : 116 bytes CIE 000000: version 3, "armcc+", code align 000001, data align fffffffc, return reg r14 DW_CFA_def_cfa_sf r13=0 DW_CFA_undefined r0 DW_CFA_undefined r1 DW_CFA_undefined r2 DW_CFA_undefined r3 DW_CFA_same_value r4 DW_CFA_same_value r5 DW_CFA_same_value r6 DW_CFA_same_value r7 DW_CFA_same_value r8 DW_CFA_same_value r9 DW_CFA_same_value r10 DW_CFA_same_value r11 DW_CFA_undefined r12 DW_CFA_same_value r14 DW_CFA_undefined r256 DW_CFA_undefined r257 DW_CFA_undefined r258 DW_CFA_undefined r259 DW_CFA_undefined r260 DW_CFA_undefined r261 DW_CFA_undefined r262 DW_CFA_undefined r263 DW_CFA_same_value r264 DW_CFA_same_value r265 DW_CFA_same_value r266 DW_CFA_same_value r267 DW_CFA_same_value r268 DW_CFA_same_value r269 DW_CFA_same_value r270 DW_CFA_same_value r271 DW_CFA_nop DW_CFA_nop FDE 000064: CIE 000000, init loc 000000, range 000004 ** Section #352 '.rel.debug_frame' (SHT_REL) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' 2 relocations applied to section #12 '.debug_frame' ** Section #13 '.debug_frame' (SHT_PROGBITS) Size : 116 bytes CIE 000000: version 3, "armcc+", code align 000001, data align fffffffc, return reg r14 DW_CFA_def_cfa_sf r13=0 DW_CFA_undefined r0 DW_CFA_undefined r1 DW_CFA_undefined r2 DW_CFA_undefined r3 DW_CFA_same_value r4 DW_CFA_same_value r5 DW_CFA_same_value r6 DW_CFA_same_value r7 DW_CFA_same_value r8 DW_CFA_same_value r9 DW_CFA_same_value r10 DW_CFA_same_value r11 DW_CFA_undefined r12 DW_CFA_same_value r14 DW_CFA_undefined r256 DW_CFA_undefined r257 DW_CFA_undefined r258 DW_CFA_undefined r259 DW_CFA_undefined r260 DW_CFA_undefined r261 DW_CFA_undefined r262 DW_CFA_undefined r263 DW_CFA_same_value r264 DW_CFA_same_value r265 DW_CFA_same_value r266 DW_CFA_same_value r267 DW_CFA_same_value r268 DW_CFA_same_value r269 DW_CFA_same_value r270 DW_CFA_same_value r271 DW_CFA_nop DW_CFA_nop FDE 000064: CIE 000000, init loc 000000, range 000006 ** Section #353 '.rel.debug_frame' (SHT_REL) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' 2 relocations applied to section #13 '.debug_frame' ** Section #14 '.debug_frame' (SHT_PROGBITS) Size : 136 bytes CIE 000000: version 3, "armcc+", code align 000002, data align fffffffc, return reg r14 DW_CFA_def_cfa_sf r13=0 DW_CFA_undefined r0 DW_CFA_undefined r1 DW_CFA_undefined r2 DW_CFA_undefined r3 DW_CFA_same_value r4 DW_CFA_same_value r5 DW_CFA_same_value r6 DW_CFA_same_value r7 DW_CFA_same_value r8 DW_CFA_same_value r9 DW_CFA_same_value r10 DW_CFA_same_value r11 DW_CFA_undefined r12 DW_CFA_same_value r14 DW_CFA_undefined r256 DW_CFA_undefined r257 DW_CFA_undefined r258 DW_CFA_undefined r259 DW_CFA_undefined r260 DW_CFA_undefined r261 DW_CFA_undefined r262 DW_CFA_undefined r263 DW_CFA_same_value r264 DW_CFA_same_value r265 DW_CFA_same_value r266 DW_CFA_same_value r267 DW_CFA_same_value r268 DW_CFA_same_value r269 DW_CFA_same_value r270 DW_CFA_same_value r271 DW_CFA_nop DW_CFA_nop FDE 000064: CIE 000000, init loc 000000, range 00009c DW_CFA_advance_loc +0x4 = 0x000004 DW_CFA_def_cfa_offset_sf =0x14 DW_CFA_offset r4=0xffffffec DW_CFA_offset r5=0xfffffff0 DW_CFA_offset r6=0xfffffff4 DW_CFA_offset r7=0xfffffff8 DW_CFA_offset r14=0xfffffffc DW_CFA_advance_loc +0x4 = 0x000008 DW_CFA_def_cfa_offset_sf =0x30 DW_CFA_advance_loc1 +0x92 =0x00009a DW_CFA_def_cfa_offset_sf =0x14 ** Section #354 '.rel.debug_frame' (SHT_REL) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' 2 relocations applied to section #14 '.debug_frame' ** Section #15 '.debug_info' (SHT_PROGBITS) Size : 240 bytes 000000: Header: size 0xec bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\User\led\bsp_led.c 000025: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 00006c: DW_AT_language DW_LANG_C89 00006e: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 0000e5: DW_AT_macro_info 0x0 0000e9: DW_AT_stmt_list 0x0 0000ed: 0 null 0000ee: 0 padding 0000ef: 0 padding ** Section #355 '.rel.debug_info' (SHT_REL) Size : 24 bytes (alignment 4) Symbol table #343 '.symtab' 3 relocations applied to section #15 '.debug_info' ** Section #16 '.debug_info' (SHT_PROGBITS) Size : 416 bytes 000000: Header: size 0x19c bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 5 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\User\led\bsp_led.c 000025: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 00006c: DW_AT_language DW_LANG_C89 00006e: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 0000e5: DW_AT_low_pc i.LED_GPIO_Config 0000e9: DW_AT_high_pc 0x9c+i.LED_GPIO_Config 0000ed: DW_AT_stmt_list 0x0 0000f1: 63 = 0x2e (DW_TAG_subprogram) 0000f2: DW_AT_sibling 0x19e 0000f4: DW_AT_decl_file 0x1 0000f5: DW_AT_decl_line 0x19 0000f6: DW_AT_decl_column 0x6 0000f7: DW_AT_name LED_GPIO_Config 000107: DW_AT_external 0x1 000108: DW_AT_low_pc i.LED_GPIO_Config 00010c: DW_AT_high_pc 0x9c+i.LED_GPIO_Config 000110: DW_AT_frame_base 0x0 000114: 89 = 0x34 (DW_TAG_variable) 000115: DW_AT_name GPIO_InitStruct 000125: DW_AT_type indirect DW_FORM_ref_addr 0x162+__ARM_grp..debug_info$stm32f7xx_hal_gpio.h$.2_kF2000__UQBfUsVDnd_b00000 00012a: DW_AT_location block size 0x2 = { DW_OP_fbreg -48 } 00012d: 22 = 0xb (DW_TAG_lexical_block) 00012e: DW_AT_sibling 0x149 000130: DW_AT_low_pc 0x4+i.LED_GPIO_Config 000134: DW_AT_high_pc 0x14+i.LED_GPIO_Config 000138: 89 = 0x34 (DW_TAG_variable) 000139: DW_AT_name tmpreg 000140: DW_AT_type indirect DW_FORM_ref_addr 0xed+__ARM_grp..debug_info$bsp_led.c$.2_ce1000_8TrENnCvU$7_700000 000145: DW_AT_location block size 0x2 = { DW_OP_fbreg -28 } 000148: 0 null 000149: 22 = 0xb (DW_TAG_lexical_block) 00014a: DW_AT_sibling 0x165 00014c: DW_AT_low_pc 0x14+i.LED_GPIO_Config 000150: DW_AT_high_pc 0x24+i.LED_GPIO_Config 000154: 89 = 0x34 (DW_TAG_variable) 000155: DW_AT_name tmpreg 00015c: DW_AT_type indirect DW_FORM_ref_addr 0xed+__ARM_grp..debug_info$bsp_led.c$.2_ce1000_8TrENnCvU$7_700000 000161: DW_AT_location block size 0x2 = { DW_OP_fbreg -28 } 000164: 0 null 000165: 22 = 0xb (DW_TAG_lexical_block) 000166: DW_AT_sibling 0x181 000168: DW_AT_low_pc 0x24+i.LED_GPIO_Config 00016c: DW_AT_high_pc 0x34+i.LED_GPIO_Config 000170: 89 = 0x34 (DW_TAG_variable) 000171: DW_AT_name tmpreg 000178: DW_AT_type indirect DW_FORM_ref_addr 0xed+__ARM_grp..debug_info$bsp_led.c$.2_ce1000_8TrENnCvU$7_700000 00017d: DW_AT_location block size 0x2 = { DW_OP_fbreg -28 } 000180: 0 null 000181: 22 = 0xb (DW_TAG_lexical_block) 000182: DW_AT_sibling 0x19d 000184: DW_AT_low_pc 0x34+i.LED_GPIO_Config 000188: DW_AT_high_pc 0x98+i.LED_GPIO_Config 00018c: 89 = 0x34 (DW_TAG_variable) 00018d: DW_AT_name tmpreg 000194: DW_AT_type indirect DW_FORM_ref_addr 0xed+__ARM_grp..debug_info$bsp_led.c$.2_ce1000_8TrENnCvU$7_700000 000199: DW_AT_location block size 0x2 = { DW_OP_fbreg -28 } 00019c: 0 null 00019d: 0 null 00019e: 0 null 00019f: 0 padding ** Section #356 '.rel.debug_info' (SHT_REL) Size : 160 bytes (alignment 4) Symbol table #343 '.symtab' 20 relocations applied to section #16 '.debug_info' ** Section #17 '.debug_line' (SHT_PROGBITS) Size : 60 bytes 000000: Header: length 56 (not including this field) version 3 prologue length 47 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "" : 00 00001c: file "..\..\User\led\bsp_led.c": dir 0 time 0x0 length 0: 2e 2e 5c 2e 2e 5c 55 73 65 72 5c 6c 65 64 5c 62 73 70 5f 6c 65 64 2e 63 00 00 00 00 000038: file "" : 00 000039: DW_LNE_end sequence : 00 01 01 00000000: ..\..\User\led\bsp_led.c:1.0 ** Section #18 '.debug_line' (SHT_PROGBITS) Size : 184 bytes 000000: Header: length 180 (not including this field) version 3 prologue length 48 minimum instruction length 2 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\User\" : 2e 2e 5c 2e 2e 5c 55 73 65 72 5c 00 000027: directory "" : 00 000028: file "led\bsp_led.c": dir 1 time 0x0 length 0: 6c 65 64 5c 62 73 70 5f 6c 65 64 2e 63 00 01 00 00 000039: file "" : 00 00003a: DW_LNE_set_address i.LED_GPIO_Config: 00 05 02 00 00 00 00 000041: DW_LNS_set_column 5 : 05 05 000043: DW_LNS_advance_line 31 : 03 1f 000045: DW_LNS_negate_stmt : 06 000046: DW_LNS_copy : 01 00000000: ..\..\User\led\bsp_led.c:32.5 [ 000047: DW_LNS_set_column 1 : 05 01 000049: DW_LNS_advance_line -6 : 03 7a 00004b: SPECIAL(0, 1) : 13 00000002: ..\..\User\led\bsp_led.c:26.1 [ 00004c: DW_LNS_set_column 5 : 05 05 00004e: DW_LNS_advance_line 6 : 03 06 000050: SPECIAL(0, 1) : 13 00000004: ..\..\User\led\bsp_led.c:32.5 [ 000051: DW_LNS_set_column 1 : 05 01 000053: DW_LNS_advance_line -6 : 03 7a 000055: DW_LNS_negate_stmt : 06 000056: SPECIAL(0, 1) : 13 00000006: ..\..\User\led\bsp_led.c:26.1 000057: DW_LNS_set_column 5 : 05 05 000059: DW_LNS_advance_line 6 : 03 06 00005b: SPECIAL(0, 1) : 13 00000008: ..\..\User\led\bsp_led.c:32.5 00005c: DW_LNS_negate_stmt : 06 00005d: SPECIAL(0, 3) : 1f 0000000e: ..\..\User\led\bsp_led.c:32.5 [ 00005e: DW_LNS_negate_stmt : 06 00005f: SPECIAL(0, 1) : 13 00000010: ..\..\User\led\bsp_led.c:32.5 000060: DW_LNS_negate_stmt : 06 000061: SPECIAL(1, 2) : 1a 00000014: ..\..\User\led\bsp_led.c:33.5 [ 000062: DW_LNS_negate_stmt : 06 000063: SPECIAL(0, 1) : 13 00000016: ..\..\User\led\bsp_led.c:33.5 000064: DW_LNS_negate_stmt : 06 000065: SPECIAL(0, 4) : 25 0000001e: ..\..\User\led\bsp_led.c:33.5 [ 000066: DW_LNS_negate_stmt : 06 000067: SPECIAL(0, 1) : 13 00000020: ..\..\User\led\bsp_led.c:33.5 000068: DW_LNS_negate_stmt : 06 000069: SPECIAL(1, 2) : 1a 00000024: ..\..\User\led\bsp_led.c:34.5 [ 00006a: DW_LNS_negate_stmt : 06 00006b: SPECIAL(0, 1) : 13 00000026: ..\..\User\led\bsp_led.c:34.5 00006c: DW_LNS_negate_stmt : 06 00006d: SPECIAL(0, 4) : 25 0000002e: ..\..\User\led\bsp_led.c:34.5 [ 00006e: DW_LNS_negate_stmt : 06 00006f: SPECIAL(0, 1) : 13 00000030: ..\..\User\led\bsp_led.c:34.5 000070: DW_LNS_negate_stmt : 06 000071: SPECIAL(1, 2) : 1a 00000034: ..\..\User\led\bsp_led.c:35.5 [ 000072: DW_LNS_negate_stmt : 06 000073: SPECIAL(0, 1) : 13 00000036: ..\..\User\led\bsp_led.c:35.5 000074: DW_LNS_negate_stmt : 06 000075: SPECIAL(0, 4) : 25 0000003e: ..\..\User\led\bsp_led.c:35.5 [ 000076: SPECIAL(3, 1) : 16 00000040: ..\..\User\led\bsp_led.c:38.5 [ 000077: DW_LNS_negate_stmt : 06 000078: SPECIAL(0, 1) : 13 00000042: ..\..\User\led\bsp_led.c:38.5 000079: DW_LNS_advance_line 12 : 03 0c 00007b: SPECIAL(0, 1) : 13 00000044: ..\..\User\led\bsp_led.c:50.5 00007c: DW_LNS_negate_stmt : 06 00007d: SPECIAL(0, 1) : 13 00000046: ..\..\User\led\bsp_led.c:50.5 [ 00007e: DW_LNS_advance_line -15 : 03 71 000080: DW_LNS_negate_stmt : 06 000081: SPECIAL(0, 1) : 13 00000048: ..\..\User\led\bsp_led.c:35.5 000082: DW_LNS_advance_line 6 : 03 06 000084: DW_LNS_negate_stmt : 06 000085: SPECIAL(0, 2) : 19 0000004c: ..\..\User\led\bsp_led.c:41.5 [ 000086: DW_LNS_negate_stmt : 06 000087: SPECIAL(0, 1) : 13 0000004e: ..\..\User\led\bsp_led.c:41.5 000088: DW_LNS_advance_line 6 : 03 06 00008a: DW_LNS_negate_stmt : 06 00008b: SPECIAL(0, 1) : 13 00000050: ..\..\User\led\bsp_led.c:47.5 [ 00008c: DW_LNS_advance_line -6 : 03 7a 00008e: DW_LNS_negate_stmt : 06 00008f: SPECIAL(0, 1) : 13 00000052: ..\..\User\led\bsp_led.c:41.5 000090: DW_LNS_advance_line 6 : 03 06 000092: SPECIAL(0, 2) : 19 00000056: ..\..\User\led\bsp_led.c:47.5 000093: SPECIAL(3, 1) : 16 00000058: ..\..\User\led\bsp_led.c:50.5 000094: DW_LNS_negate_stmt : 06 000095: SPECIAL(3, 4) : 28 00000060: ..\..\User\led\bsp_led.c:53.5 [ 000096: SPECIAL(1, 1) : 14 00000062: ..\..\User\led\bsp_led.c:54.5 [ 000097: DW_LNS_negate_stmt : 06 000098: SPECIAL(0, 1) : 13 00000064: ..\..\User\led\bsp_led.c:54.5 000099: DW_LNS_negate_stmt : 06 00009a: SPECIAL(3, 4) : 28 0000006c: ..\..\User\led\bsp_led.c:57.5 [ 00009b: SPECIAL(1, 1) : 14 0000006e: ..\..\User\led\bsp_led.c:58.5 [ 00009c: DW_LNS_negate_stmt : 06 00009d: SPECIAL(0, 1) : 13 00000070: ..\..\User\led\bsp_led.c:58.5 00009e: SPECIAL(4, 4) : 29 00000078: ..\..\User\led\bsp_led.c:62.5 00009f: DW_LNS_negate_stmt : 06 0000a0: SPECIAL(0, 1) : 13 0000007a: ..\..\User\led\bsp_led.c:62.5 [ 0000a1: DW_LNS_negate_stmt : 06 0000a2: SPECIAL(0, 1) : 13 0000007c: ..\..\User\led\bsp_led.c:62.5 0000a3: DW_LNS_negate_stmt : 06 0000a4: SPECIAL(3, 4) : 28 00000084: ..\..\User\led\bsp_led.c:65.5 [ 0000a5: DW_LNS_negate_stmt : 06 0000a6: SPECIAL(0, 1) : 13 00000086: ..\..\User\led\bsp_led.c:65.5 0000a7: DW_LNS_negate_stmt : 06 0000a8: SPECIAL(0, 2) : 19 0000008a: ..\..\User\led\bsp_led.c:65.5 [ 0000a9: SPECIAL(3, 2) : 1c 0000008e: ..\..\User\led\bsp_led.c:68.5 [ 0000aa: DW_LNS_negate_stmt : 06 0000ab: SPECIAL(0, 1) : 13 00000090: ..\..\User\led\bsp_led.c:68.5 0000ac: DW_LNS_set_column 1 : 05 01 0000ae: DW_LNS_negate_stmt : 06 0000af: SPECIAL(2, 4) : 27 00000098: ..\..\User\led\bsp_led.c:70.1 [ 0000b0: DW_LNS_negate_stmt : 06 0000b1: SPECIAL(0, 1) : 13 0000009a: ..\..\User\led\bsp_led.c:70.1 0000b2: DW_LNS_advance_pc 0x1 : 02 01 0000b4: DW_LNS_negate_stmt : 06 0000b5: DW_LNE_end sequence : 00 01 01 0000009c: ..\..\User\led\bsp_led.c:70.1 [ ** Section #357 '.rel.debug_line' (SHT_REL) Size : 8 bytes (alignment 4) Symbol table #343 '.symtab' 1 relocations applied to section #18 '.debug_line' ** Section #19 '.debug_loc' (SHT_PROGBITS) Size : 56 bytes 0x000000 [0x0 : 0x4] len 2 DW_OP_breg13 0 0x00000c [0x4 : 0x8] len 2 DW_OP_breg13 20 0x000018 [0x8 : 0x9a] len 2 DW_OP_breg13 48 0x000024 [0x9a : 0x9c] len 2 DW_OP_breg13 20 0x000030 End List ** Section #20 '.debug_macinfo' (SHT_PROGBITS) Size : 1172 bytes 000000: line 0 define __DATE__ "Sep 11 2017" 000019: line 0 define __TIME__ "10:47:57" 00002f: line 0 define __STDC__ 1 00003c: line 0 define __STDC_VERSION__ 199409L 000057: line 0 define __EDG__ 1 000063: line 0 define __EDG_VERSION__ 407 000079: line 0 define __EDG_SIZE_TYPE__ unsigned int 00009a: line 0 define __EDG_PTRDIFF_TYPE__ int 0000b5: line 0 define __sizeof_int 4 0000c6: line 0 define __sizeof_long 4 0000d8: line 0 define __sizeof_ptr 4 0000e9: line 0 define __ARMCC_VERSION 5060300 000103: line 0 define __TARGET_CPU_CORTEX_M7_FP_DP 1 000124: line 0 define __TARGET_FPU_FPV5_D16 1 00013e: line 0 define __MICROLIB 1 00014d: line 0 define __UVISION_VERSION 521 000165: line 0 define STM32F767xx 1 000175: line 0 define USE_HAL_DRIVER 1 000188: line 0 define STM32F767xx 1 000198: line 0 define __CC_ARM 1 0001a5: line 0 define __arm 1 0001af: line 0 define __arm__ 1 0001bb: line 0 define __TARGET_ARCH_7E_M 1 0001d2: line 0 define __TARGET_ARCH_ARM 0 0001e8: line 0 define __TARGET_ARCH_THUMB 4 000200: line 0 define __TARGET_ARCH_A64 0 000216: line 0 define __TARGET_ARCH_AARCH32 1 000230: line 0 define __TARGET_PROFILE_M 1 000247: line 0 define __TARGET_FEATURE_HALFWORD 1 000265: line 0 define __TARGET_FEATURE_THUMB 1 000280: line 0 define __TARGET_FEATURE_MULTIPLY 1 00029e: line 0 define __TARGET_FEATURE_DSPMUL 1 0002ba: line 0 define __TARGET_FEATURE_DOUBLEWORD 1 0002da: line 0 define __TARGET_FEATURE_DIVIDE 1 0002f6: line 0 define __TARGET_FEATURE_UNALIGNED 1 000315: line 0 define __TARGET_FEATURE_CLZ 1 00032e: line 0 define __TARGET_FEATURE_DMB 1 000347: line 0 define __TARGET_FPU_VFPV5 1 00035e: line 0 define __TARGET_FPU_VFP 1 000373: line 0 define __TARGET_FPU_VFP_SINGLE 1 00038f: line 0 define __TARGET_FPU_VFP_DOUBLE 1 0003ab: line 0 define __TARGET_FEATURE_EXTENSION_REGISTER_COUNT 16 0003da: line 0 define __APCS_INTERWORK 1 0003ef: line 0 define __FP_FAST_FMAF 1 000402: line 0 define __FP_FAST_FMA 1 000414: line 0 define __FP_FAST_FMAL 1 000427: line 0 define __thumb 1 000433: line 0 define __thumb__ 1 000441: line 0 define __t32__ 1 00044d: line 0 define __OPTIMISE_SPACE 1 000462: line 0 define __OPT_SMALL_ASSERT 1 000479: line 0 define __OPTIMISE_LEVEL 2 00048e: include at line 0 - file 1 000491: end include 000492: end of translation unit ** Section #21 '.debug_pubnames' (SHT_PROGBITS) Size : 38 bytes 0x00000000: Compilation unit (38 bytes) vsn 2: 0x00000006: reference to offset __ARM_grp_.debug_info$9 0x0000000a: 416 bytes generated for unit 0x0000000e: Offset 0xf1 (0xf1) 0x00000012: 4c 45 44 5f 47 50 49 4f 5f 43 6f 6e LED_GPIO_Con 0x0000001e: 66 69 67 00 fig 0x00000022: End of list for compilation unit (zero offset) ** Section #358 '.rel.debug_pubnames' (SHT_REL) Size : 8 bytes (alignment 4) Symbol table #343 '.symtab' 1 relocations applied to section #21 '.debug_pubnames' ** Section #22 '__ARM_asm.debug_abbrev.1' (SHT_GROUP) Size : 8 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #23 '.debug_abbrev' (SHT_PROGBITS) [SHF_GROUP] Size : 32 bytes 00000000 1: children: DW_TAG_compile_unit 000003 DW_AT_name DW_FORM_string 000005 DW_AT_producer DW_FORM_string 000007 DW_AT_comp_dir DW_FORM_string 000009 DW_AT_low_pc DW_FORM_addr 00000b DW_AT_high_pc DW_FORM_addr 00000d DW_AT_stmt_list DW_FORM_data4 00000011 2: no children: DW_TAG_subprogram 000014 DW_AT_name DW_FORM_string 000016 DW_AT_low_pc DW_FORM_addr 000018 DW_AT_high_pc DW_FORM_addr ** Section #24 '__ARM_grp.stdint.h.2_4H1000_rQLou6Y$5Wb_300000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #25 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 2200 bytes 000000: include at line 0 - file 1 000003: line 11 define __stdint_h 000011: line 12 define __ARMCLIB_VERSION 5060016 00002d: line 19 define __INT64 __int64 00003f: line 20 define __INT64_C_SUFFIX__ ll 000057: line 22 define __PASTE2(x,y) x ## y 00006e: line 23 define __PASTE(x,y) __PASTE2(x, y) 00008c: line 24 define __INT64_C(x) __ESCAPE__(__PASTE(x, __INT64_C_SUFFIX__)) 0000c6: line 25 define __UINT64_C(x) __ESCAPE__(__PASTE(x ## u, __INT64_C_SUFFIX__)) 000106: line 28 define __LONGLONG long long 00011d: line 35 define __STDINT_DECLS 00012f: line 37 undef __CLIBNS 00013a: line 44 define __CLIBNS 000146: line 115 define INT8_MIN -128 000156: line 116 define INT16_MIN -32768 000169: line 117 define INT32_MIN (~0x7fffffff) 000183: line 118 define INT64_MIN __INT64_C(~0x7fffffffffffffff) 0001ae: line 121 define INT8_MAX 127 0001bd: line 122 define INT16_MAX 32767 0001cf: line 123 define INT32_MAX 2147483647 0001e6: line 124 define INT64_MAX __INT64_C(9223372036854775807) 000211: line 127 define UINT8_MAX 255 000221: line 128 define UINT16_MAX 65535 000235: line 129 define UINT32_MAX 4294967295u 00024f: line 130 define UINT64_MAX __UINT64_C(18446744073709551615) 00027e: line 135 define INT_LEAST8_MIN -128 000295: line 136 define INT_LEAST16_MIN -32768 0002af: line 137 define INT_LEAST32_MIN (~0x7fffffff) 0002d0: line 138 define INT_LEAST64_MIN __INT64_C(~0x7fffffffffffffff) 000302: line 141 define INT_LEAST8_MAX 127 000318: line 142 define INT_LEAST16_MAX 32767 000331: line 143 define INT_LEAST32_MAX 2147483647 00034f: line 144 define INT_LEAST64_MAX __INT64_C(9223372036854775807) 000381: line 147 define UINT_LEAST8_MAX 255 000398: line 148 define UINT_LEAST16_MAX 65535 0003b2: line 149 define UINT_LEAST32_MAX 4294967295u 0003d2: line 150 define UINT_LEAST64_MAX __UINT64_C(18446744073709551615) 000407: line 155 define INT_FAST8_MIN (~0x7fffffff) 000426: line 156 define INT_FAST16_MIN (~0x7fffffff) 000446: line 157 define INT_FAST32_MIN (~0x7fffffff) 000466: line 158 define INT_FAST64_MIN __INT64_C(~0x7fffffffffffffff) 000497: line 161 define INT_FAST8_MAX 2147483647 0004b3: line 162 define INT_FAST16_MAX 2147483647 0004d0: line 163 define INT_FAST32_MAX 2147483647 0004ed: line 164 define INT_FAST64_MAX __INT64_C(9223372036854775807) 00051e: line 167 define UINT_FAST8_MAX 4294967295u 00053c: line 168 define UINT_FAST16_MAX 4294967295u 00055b: line 169 define UINT_FAST32_MAX 4294967295u 00057a: line 170 define UINT_FAST64_MAX __UINT64_C(18446744073709551615) 0005ae: line 178 define INTPTR_MIN INT32_MIN 0005c6: line 185 define INTPTR_MAX INT32_MAX 0005de: line 192 define UINTPTR_MAX UINT32_MAX 0005f8: line 198 define INTMAX_MIN __ESCAPE__(~0x7fffffffffffffffll) 000628: line 201 define INTMAX_MAX __ESCAPE__(9223372036854775807ll) 000658: line 204 define UINTMAX_MAX __ESCAPE__(18446744073709551615ull) 00068b: line 213 define PTRDIFF_MIN INT32_MIN 0006a4: line 214 define PTRDIFF_MAX INT32_MAX 0006bd: line 218 define SIG_ATOMIC_MIN (~0x7fffffff) 0006dd: line 219 define SIG_ATOMIC_MAX 2147483647 0006fa: line 225 define SIZE_MAX UINT32_MAX 000711: line 231 undef WCHAR_MIN 00071e: line 232 undef WCHAR_MAX 00072b: line 238 define WCHAR_MIN 0 00073a: line 239 define WCHAR_MAX 65535 00074d: line 243 define WINT_MIN (~0x7fffffff) 000767: line 244 define WINT_MAX 2147483647 00077e: line 251 define INT8_C(x) (x) 00078f: line 252 define INT16_C(x) (x) 0007a1: line 253 define INT32_C(x) (x) 0007b3: line 254 define INT64_C(x) __INT64_C(x) 0007ce: line 256 define UINT8_C(x) (x ## u) 0007e5: line 257 define UINT16_C(x) (x ## u) 0007fd: line 258 define UINT32_C(x) (x ## u) 000815: line 259 define UINT64_C(x) __UINT64_C(x) 000832: line 262 define INTMAX_C(x) __ESCAPE__(x ## ll) 000855: line 263 define UINTMAX_C(x) __ESCAPE__(x ## ull) 00087a: line 306 undef __INT64 000885: line 307 undef __LONGLONG 000893: end include 000894: end of translation unit ** Section #26 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 104 bytes 000000: Header: length 100 (not including this field) version 3 prologue length 88 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "D:\Program Files (x86)\Keil_v5\ARM\ARMCC\Bin\..\include\": 44 3a 5c 50 72 6f 67 72 61 6d 20 46 69 6c 65 73 20 28 78 38 36 29 5c 4b 65 69 6c 5f 76 35 5c 41 52 4d 5c 41 52 4d 43 43 5c 42 69 6e 5c 2e 2e 5c 69 6e 63 6c 75 64 65 5c 00 000054: directory "" : 00 000055: file "stdint.h": dir 1 time 0x0 length 0: 73 74 64 69 6e 74 2e 68 00 01 00 00 000061: file "" : 00 000062: DW_LNS_negate_stmt : 06 000063: DW_LNS_negate_stmt : 06 000064: DW_LNS_negate_stmt : 06 000065: DW_LNE_end sequence : 00 01 01 00000000: D:\Program Files (x86)\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h:1.0 [ ** Section #27 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 800 bytes 000000: Header: size 0x31c bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 16 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name D:\Program Files (x86)\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h 00004d: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000094: DW_AT_language DW_LANG_C89 000096: DW_AT_macro_info 0x0 00009a: DW_AT_stmt_list 0x0 00009e: 4 = 0x24 (DW_TAG_base_type) 00009f: DW_AT_byte_size 0x1 0000a0: DW_AT_encoding DW_ATE_signed_char 0000a1: DW_AT_name signed char 0000ad: 4 = 0x24 (DW_TAG_base_type) 0000ae: DW_AT_byte_size 0x2 0000af: DW_AT_encoding DW_ATE_signed 0000b0: DW_AT_name short 0000b6: 4 = 0x24 (DW_TAG_base_type) 0000b7: DW_AT_byte_size 0x4 0000b8: DW_AT_encoding DW_ATE_signed 0000b9: DW_AT_name int 0000bd: 4 = 0x24 (DW_TAG_base_type) 0000be: DW_AT_byte_size 0x8 0000bf: DW_AT_encoding DW_ATE_signed 0000c0: DW_AT_name long long 0000ca: 4 = 0x24 (DW_TAG_base_type) 0000cb: DW_AT_byte_size 0x1 0000cc: DW_AT_encoding DW_ATE_unsigned_char 0000cd: DW_AT_name unsigned char 0000db: 4 = 0x24 (DW_TAG_base_type) 0000dc: DW_AT_byte_size 0x2 0000dd: DW_AT_encoding DW_ATE_unsigned 0000de: DW_AT_name unsigned short 0000ed: 4 = 0x24 (DW_TAG_base_type) 0000ee: DW_AT_byte_size 0x4 0000ef: DW_AT_encoding DW_ATE_unsigned 0000f0: DW_AT_name unsigned int 0000fd: 4 = 0x24 (DW_TAG_base_type) 0000fe: DW_AT_byte_size 0x8 0000ff: DW_AT_encoding DW_ATE_unsigned 000100: DW_AT_name unsigned long long 000113: 80 = 0x16 (DW_TAG_typedef) 000114: DW_AT_name int8_t 00011b: DW_AT_type indirect DW_FORM_ref2 0x9e 00011e: DW_AT_decl_file 0x1 00011f: DW_AT_decl_line 0x38 000120: DW_AT_decl_column 0x20 000121: 80 = 0x16 (DW_TAG_typedef) 000122: DW_AT_name int16_t 00012a: DW_AT_type indirect DW_FORM_ref2 0xad 00012d: DW_AT_decl_file 0x1 00012e: DW_AT_decl_line 0x39 00012f: DW_AT_decl_column 0x20 000130: 80 = 0x16 (DW_TAG_typedef) 000131: DW_AT_name int32_t 000139: DW_AT_type indirect DW_FORM_ref2 0xb6 00013c: DW_AT_decl_file 0x1 00013d: DW_AT_decl_line 0x3a 00013e: DW_AT_decl_column 0x20 00013f: 80 = 0x16 (DW_TAG_typedef) 000140: DW_AT_name int64_t 000148: DW_AT_type indirect DW_FORM_ref2 0xbd 00014b: DW_AT_decl_file 0x1 00014c: DW_AT_decl_line 0x3b 00014d: DW_AT_decl_column 0x20 00014e: 80 = 0x16 (DW_TAG_typedef) 00014f: DW_AT_name uint8_t 000157: DW_AT_type indirect DW_FORM_ref2 0xca 00015a: DW_AT_decl_file 0x1 00015b: DW_AT_decl_line 0x3e 00015c: DW_AT_decl_column 0x20 00015d: 80 = 0x16 (DW_TAG_typedef) 00015e: DW_AT_name uint16_t 000167: DW_AT_type indirect DW_FORM_ref2 0xdb 00016a: DW_AT_decl_file 0x1 00016b: DW_AT_decl_line 0x3f 00016c: DW_AT_decl_column 0x20 00016d: 80 = 0x16 (DW_TAG_typedef) 00016e: DW_AT_name uint32_t 000177: DW_AT_type indirect DW_FORM_ref2 0xed 00017a: DW_AT_decl_file 0x1 00017b: DW_AT_decl_line 0x40 00017c: DW_AT_decl_column 0x20 00017d: 80 = 0x16 (DW_TAG_typedef) 00017e: DW_AT_name uint64_t 000187: DW_AT_type indirect DW_FORM_ref2 0xfd 00018a: DW_AT_decl_file 0x1 00018b: DW_AT_decl_line 0x41 00018c: DW_AT_decl_column 0x20 00018d: 80 = 0x16 (DW_TAG_typedef) 00018e: DW_AT_name int_least8_t 00019b: DW_AT_type indirect DW_FORM_ref2 0x9e 00019e: DW_AT_decl_file 0x1 00019f: DW_AT_decl_line 0x47 0001a0: DW_AT_decl_column 0x20 0001a1: 80 = 0x16 (DW_TAG_typedef) 0001a2: DW_AT_name int_least16_t 0001b0: DW_AT_type indirect DW_FORM_ref2 0xad 0001b3: DW_AT_decl_file 0x1 0001b4: DW_AT_decl_line 0x48 0001b5: DW_AT_decl_column 0x20 0001b6: 80 = 0x16 (DW_TAG_typedef) 0001b7: DW_AT_name int_least32_t 0001c5: DW_AT_type indirect DW_FORM_ref2 0xb6 0001c8: DW_AT_decl_file 0x1 0001c9: DW_AT_decl_line 0x49 0001ca: DW_AT_decl_column 0x20 0001cb: 80 = 0x16 (DW_TAG_typedef) 0001cc: DW_AT_name int_least64_t 0001da: DW_AT_type indirect DW_FORM_ref2 0xbd 0001dd: DW_AT_decl_file 0x1 0001de: DW_AT_decl_line 0x4a 0001df: DW_AT_decl_column 0x20 0001e0: 80 = 0x16 (DW_TAG_typedef) 0001e1: DW_AT_name uint_least8_t 0001ef: DW_AT_type indirect DW_FORM_ref2 0xca 0001f2: DW_AT_decl_file 0x1 0001f3: DW_AT_decl_line 0x4d 0001f4: DW_AT_decl_column 0x20 0001f5: 80 = 0x16 (DW_TAG_typedef) 0001f6: DW_AT_name uint_least16_t 000205: DW_AT_type indirect DW_FORM_ref2 0xdb 000208: DW_AT_decl_file 0x1 000209: DW_AT_decl_line 0x4e 00020a: DW_AT_decl_column 0x20 00020b: 80 = 0x16 (DW_TAG_typedef) 00020c: DW_AT_name uint_least32_t 00021b: DW_AT_type indirect DW_FORM_ref2 0xed 00021e: DW_AT_decl_file 0x1 00021f: DW_AT_decl_line 0x4f 000220: DW_AT_decl_column 0x20 000221: 80 = 0x16 (DW_TAG_typedef) 000222: DW_AT_name uint_least64_t 000231: DW_AT_type indirect DW_FORM_ref2 0xfd 000234: DW_AT_decl_file 0x1 000235: DW_AT_decl_line 0x50 000236: DW_AT_decl_column 0x20 000237: 80 = 0x16 (DW_TAG_typedef) 000238: DW_AT_name int_fast8_t 000244: DW_AT_type indirect DW_FORM_ref2 0xb6 000247: DW_AT_decl_file 0x1 000248: DW_AT_decl_line 0x55 000249: DW_AT_decl_column 0x20 00024a: 80 = 0x16 (DW_TAG_typedef) 00024b: DW_AT_name int_fast16_t 000258: DW_AT_type indirect DW_FORM_ref2 0xb6 00025b: DW_AT_decl_file 0x1 00025c: DW_AT_decl_line 0x56 00025d: DW_AT_decl_column 0x20 00025e: 80 = 0x16 (DW_TAG_typedef) 00025f: DW_AT_name int_fast32_t 00026c: DW_AT_type indirect DW_FORM_ref2 0xb6 00026f: DW_AT_decl_file 0x1 000270: DW_AT_decl_line 0x57 000271: DW_AT_decl_column 0x20 000272: 80 = 0x16 (DW_TAG_typedef) 000273: DW_AT_name int_fast64_t 000280: DW_AT_type indirect DW_FORM_ref2 0xbd 000283: DW_AT_decl_file 0x1 000284: DW_AT_decl_line 0x58 000285: DW_AT_decl_column 0x20 000286: 80 = 0x16 (DW_TAG_typedef) 000287: DW_AT_name uint_fast8_t 000294: DW_AT_type indirect DW_FORM_ref2 0xed 000297: DW_AT_decl_file 0x1 000298: DW_AT_decl_line 0x5b 000299: DW_AT_decl_column 0x20 00029a: 80 = 0x16 (DW_TAG_typedef) 00029b: DW_AT_name uint_fast16_t 0002a9: DW_AT_type indirect DW_FORM_ref2 0xed 0002ac: DW_AT_decl_file 0x1 0002ad: DW_AT_decl_line 0x5c 0002ae: DW_AT_decl_column 0x20 0002af: 80 = 0x16 (DW_TAG_typedef) 0002b0: DW_AT_name uint_fast32_t 0002be: DW_AT_type indirect DW_FORM_ref2 0xed 0002c1: DW_AT_decl_file 0x1 0002c2: DW_AT_decl_line 0x5d 0002c3: DW_AT_decl_column 0x20 0002c4: 80 = 0x16 (DW_TAG_typedef) 0002c5: DW_AT_name uint_fast64_t 0002d3: DW_AT_type indirect DW_FORM_ref2 0xfd 0002d6: DW_AT_decl_file 0x1 0002d7: DW_AT_decl_line 0x5e 0002d8: DW_AT_decl_column 0x20 0002d9: 80 = 0x16 (DW_TAG_typedef) 0002da: DW_AT_name intptr_t 0002e3: DW_AT_type indirect DW_FORM_ref2 0xb6 0002e6: DW_AT_decl_file 0x1 0002e7: DW_AT_decl_line 0x65 0002e8: DW_AT_decl_column 0x20 0002e9: 80 = 0x16 (DW_TAG_typedef) 0002ea: DW_AT_name uintptr_t 0002f4: DW_AT_type indirect DW_FORM_ref2 0xed 0002f7: DW_AT_decl_file 0x1 0002f8: DW_AT_decl_line 0x66 0002f9: DW_AT_decl_column 0x20 0002fa: 80 = 0x16 (DW_TAG_typedef) 0002fb: DW_AT_name intmax_t 000304: DW_AT_type indirect DW_FORM_ref2 0xbd 000307: DW_AT_decl_file 0x1 000308: DW_AT_decl_line 0x6a 000309: DW_AT_decl_column 0x21 00030a: 80 = 0x16 (DW_TAG_typedef) 00030b: DW_AT_name uintmax_t 000315: DW_AT_type indirect DW_FORM_ref2 0xfd 000318: DW_AT_decl_file 0x1 000319: DW_AT_decl_line 0x6b 00031a: DW_AT_decl_column 0x21 00031b: 0 null 00031c: 0 padding 00031d: 0 padding 00031e: 0 padding 00031f: 0 padding ** Section #359 '.rel.debug_info' (SHT_REL) Size : 24 bytes (alignment 4) Symbol table #343 '.symtab' 3 relocations applied to section #27 '.debug_info' ** Section #28 '__ARM_grp.cmsis_armcc.h.2_8Y2000_sPdhgNI8nIf_Q00000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #29 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 2968 bytes 000000: include at line 0 - file 1 000003: line 36 define __CMSIS_ARMCC_H 000016: line 191 define __enable_fault_irq __enable_fiq 000039: line 199 define __disable_fault_irq __disable_fiq 00005e: line 313 define __NOP __nop 00006d: line 320 define __WFI __wfi 00007c: line 328 define __WFE __wfe 00008b: line 335 define __SEV __sev 00009a: line 344 define __ISB() do { __schedule_barrier(); __isb(0xF); __schedule_barrier(); } while (0U) 0000ef: line 355 define __DSB() do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U) 000144: line 366 define __DMB() do { __schedule_barrier(); __dmb(0xF); __schedule_barrier(); } while (0U) 000199: line 378 define __REV __rev 0001a8: line 417 define __ROR __ror 0001b7: line 427 define __BKPT(value) __breakpoint(value) 0001dc: line 437 define __RBIT __rbit 0001ed: line 463 define __CLZ __clz 0001fc: line 477 define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") 000264: line 490 define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") 0002cc: line 503 define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") 000335: line 518 define __STREXB(value,ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") 00039d: line 533 define __STREXH(value,ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") 000405: line 548 define __STREXW(value,ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") 00046d: line 556 define __CLREX __clrex 000480: line 566 define __SSAT __ssat 000491: line 576 define __USAT __usat 0004a2: line 601 define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) 0004cb: line 610 define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) 0004f4: line 619 define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) 00051d: line 628 define __STRBT(value,ptr) __strt(value, ptr) 000546: line 637 define __STRHT(value,ptr) __strt(value, ptr) 00056f: line 646 define __STRT(value,ptr) __strt(value, ptr) 000597: line 661 define __SADD8 __sadd8 0005aa: line 662 define __QADD8 __qadd8 0005bd: line 663 define __SHADD8 __shadd8 0005d2: line 664 define __UADD8 __uadd8 0005e5: line 665 define __UQADD8 __uqadd8 0005fa: line 666 define __UHADD8 __uhadd8 00060f: line 667 define __SSUB8 __ssub8 000622: line 668 define __QSUB8 __qsub8 000635: line 669 define __SHSUB8 __shsub8 00064a: line 670 define __USUB8 __usub8 00065d: line 671 define __UQSUB8 __uqsub8 000672: line 672 define __UHSUB8 __uhsub8 000687: line 673 define __SADD16 __sadd16 00069c: line 674 define __QADD16 __qadd16 0006b1: line 675 define __SHADD16 __shadd16 0006c8: line 676 define __UADD16 __uadd16 0006dd: line 677 define __UQADD16 __uqadd16 0006f4: line 678 define __UHADD16 __uhadd16 00070b: line 679 define __SSUB16 __ssub16 000720: line 680 define __QSUB16 __qsub16 000735: line 681 define __SHSUB16 __shsub16 00074c: line 682 define __USUB16 __usub16 000761: line 683 define __UQSUB16 __uqsub16 000778: line 684 define __UHSUB16 __uhsub16 00078f: line 685 define __SASX __sasx 0007a0: line 686 define __QASX __qasx 0007b1: line 687 define __SHASX __shasx 0007c4: line 688 define __UASX __uasx 0007d5: line 689 define __UQASX __uqasx 0007e8: line 690 define __UHASX __uhasx 0007fb: line 691 define __SSAX __ssax 00080c: line 692 define __QSAX __qsax 00081d: line 693 define __SHSAX __shsax 000830: line 694 define __USAX __usax 000841: line 695 define __UQSAX __uqsax 000854: line 696 define __UHSAX __uhsax 000867: line 697 define __USAD8 __usad8 00087a: line 698 define __USADA8 __usada8 00088f: line 699 define __SSAT16 __ssat16 0008a4: line 700 define __USAT16 __usat16 0008b9: line 701 define __UXTB16 __uxtb16 0008ce: line 702 define __UXTAB16 __uxtab16 0008e5: line 703 define __SXTB16 __sxtb16 0008fa: line 704 define __SXTAB16 __sxtab16 000911: line 705 define __SMUAD __smuad 000924: line 706 define __SMUADX __smuadx 000939: line 707 define __SMLAD __smlad 00094c: line 708 define __SMLADX __smladx 000961: line 709 define __SMLALD __smlald 000976: line 710 define __SMLALDX __smlaldx 00098d: line 711 define __SMUSD __smusd 0009a0: line 712 define __SMUSDX __smusdx 0009b5: line 713 define __SMLSD __smlsd 0009c8: line 714 define __SMLSDX __smlsdx 0009dd: line 715 define __SMLSLD __smlsld 0009f2: line 716 define __SMLSLDX __smlsldx 000a09: line 717 define __SEL __sel 000a18: line 718 define __QADD __qadd 000a29: line 719 define __QSUB __qsub 000a3a: line 721 define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) 000ab2: line 724 define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) 000b2a: line 727 define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + ((int64_t)(ARG3) << 32U) ) >> 32U)) 000b93: end include 000b94: end of translation unit ** Section #30 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 80 bytes 000000: Header: length 76 (not including this field) version 3 prologue length 67 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\CMSIS\Include\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 43 4d 53 49 53 5c 49 6e 63 6c 75 64 65 5c 00 00003a: directory "" : 00 00003b: file "cmsis_armcc.h": dir 1 time 0x0 length 0: 63 6d 73 69 73 5f 61 72 6d 63 63 2e 68 00 01 00 00 00004c: file "" : 00 00004d: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\CMSIS\Include\cmsis_armcc.h:1.0 ** Section #31 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 1396 bytes 000000: Header: size 0x570 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\CMSIS\Include\cmsis_armcc.h 000038: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 00007f: DW_AT_language DW_LANG_C89 000081: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 0000f8: DW_AT_macro_info 0x0 0000fc: DW_AT_stmt_list 0x0 000100: 59 = 0x2e (DW_TAG_subprogram) 000101: DW_AT_sibling 0x140 000103: DW_AT_decl_file 0x1 000104: DW_AT_decl_line 0x39 000105: DW_AT_decl_column 0x1a 000106: DW_AT_name __get_CONTROL 000114: DW_AT_external 0x0 000115: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00011a: 97 = 0x34 (DW_TAG_variable) 00011b: DW_AT_name __result 000124: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000129: DW_AT_artificial 0x1 00012a: 89 = 0x34 (DW_TAG_variable) 00012b: DW_AT_name __regControl 000138: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00013d: DW_AT_location block size 0x1 = { DW_OP_reg0 } 00013f: 0 null 000140: 60 = 0x2e (DW_TAG_subprogram) 000141: DW_AT_sibling 0x179 000143: DW_AT_decl_file 0x1 000144: DW_AT_decl_line 0x45 000145: DW_AT_decl_column 0x16 000146: DW_AT_name __set_CONTROL 000154: DW_AT_external 0x0 000155: 36 = 0x5 (DW_TAG_formal_parameter) 000156: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00015b: DW_AT_name control 000163: 89 = 0x34 (DW_TAG_variable) 000164: DW_AT_name __regControl 000171: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000176: DW_AT_location block size 0x1 = { DW_OP_reg0 } 000178: 0 null 000179: 59 = 0x2e (DW_TAG_subprogram) 00017a: DW_AT_sibling 0x1b3 00017c: DW_AT_decl_file 0x1 00017d: DW_AT_decl_line 0x51 00017e: DW_AT_decl_column 0x1a 00017f: DW_AT_name __get_IPSR 00018a: DW_AT_external 0x0 00018b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000190: 97 = 0x34 (DW_TAG_variable) 000191: DW_AT_name __result 00019a: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00019f: DW_AT_artificial 0x1 0001a0: 89 = 0x34 (DW_TAG_variable) 0001a1: DW_AT_name __regIPSR 0001ab: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001b0: DW_AT_location block size 0x1 = { DW_OP_reg0 } 0001b2: 0 null 0001b3: 59 = 0x2e (DW_TAG_subprogram) 0001b4: DW_AT_sibling 0x1ed 0001b6: DW_AT_decl_file 0x1 0001b7: DW_AT_decl_line 0x5d 0001b8: DW_AT_decl_column 0x1a 0001b9: DW_AT_name __get_APSR 0001c4: DW_AT_external 0x0 0001c5: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001ca: 97 = 0x34 (DW_TAG_variable) 0001cb: DW_AT_name __result 0001d4: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001d9: DW_AT_artificial 0x1 0001da: 89 = 0x34 (DW_TAG_variable) 0001db: DW_AT_name __regAPSR 0001e5: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001ea: DW_AT_location block size 0x1 = { DW_OP_reg0 } 0001ec: 0 null 0001ed: 59 = 0x2e (DW_TAG_subprogram) 0001ee: DW_AT_sibling 0x227 0001f0: DW_AT_decl_file 0x1 0001f1: DW_AT_decl_line 0x69 0001f2: DW_AT_decl_column 0x1a 0001f3: DW_AT_name __get_xPSR 0001fe: DW_AT_external 0x0 0001ff: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000204: 97 = 0x34 (DW_TAG_variable) 000205: DW_AT_name __result 00020e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000213: DW_AT_artificial 0x1 000214: 89 = 0x34 (DW_TAG_variable) 000215: DW_AT_name __regXPSR 00021f: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000224: DW_AT_location block size 0x1 = { DW_OP_reg0 } 000226: 0 null 000227: 59 = 0x2e (DW_TAG_subprogram) 000228: DW_AT_sibling 0x26f 00022a: DW_AT_decl_file 0x1 00022b: DW_AT_decl_line 0x75 00022c: DW_AT_decl_column 0x1a 00022d: DW_AT_name __get_PSP 000237: DW_AT_external 0x0 000238: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00023d: 97 = 0x34 (DW_TAG_variable) 00023e: DW_AT_name __result 000247: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00024c: DW_AT_artificial 0x1 00024d: 89 = 0x34 (DW_TAG_variable) 00024e: DW_AT_name __regProcessStackPointer 000267: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00026c: DW_AT_location block size 0x1 = { DW_OP_reg0 } 00026e: 0 null 00026f: 60 = 0x2e (DW_TAG_subprogram) 000270: DW_AT_sibling 0x2b8 000272: DW_AT_decl_file 0x1 000273: DW_AT_decl_line 0x81 000275: DW_AT_decl_column 0x16 000276: DW_AT_name __set_PSP 000280: DW_AT_external 0x0 000281: 36 = 0x5 (DW_TAG_formal_parameter) 000282: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000287: DW_AT_name topOfProcStack 000296: 89 = 0x34 (DW_TAG_variable) 000297: DW_AT_name __regProcessStackPointer 0002b0: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002b5: DW_AT_location block size 0x1 = { DW_OP_reg0 } 0002b7: 0 null 0002b8: 59 = 0x2e (DW_TAG_subprogram) 0002b9: DW_AT_sibling 0x2fe 0002bb: DW_AT_decl_file 0x1 0002bc: DW_AT_decl_line 0x8d 0002be: DW_AT_decl_column 0x1a 0002bf: DW_AT_name __get_MSP 0002c9: DW_AT_external 0x0 0002ca: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002cf: 97 = 0x34 (DW_TAG_variable) 0002d0: DW_AT_name __result 0002d9: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002de: DW_AT_artificial 0x1 0002df: 89 = 0x34 (DW_TAG_variable) 0002e0: DW_AT_name __regMainStackPointer 0002f6: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002fb: DW_AT_location block size 0x1 = { DW_OP_reg0 } 0002fd: 0 null 0002fe: 60 = 0x2e (DW_TAG_subprogram) 0002ff: DW_AT_sibling 0x344 000301: DW_AT_decl_file 0x1 000302: DW_AT_decl_line 0x99 000304: DW_AT_decl_column 0x16 000305: DW_AT_name __set_MSP 00030f: DW_AT_external 0x0 000310: 36 = 0x5 (DW_TAG_formal_parameter) 000311: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000316: DW_AT_name topOfMainStack 000325: 89 = 0x34 (DW_TAG_variable) 000326: DW_AT_name __regMainStackPointer 00033c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000341: DW_AT_location block size 0x1 = { DW_OP_reg0 } 000343: 0 null 000344: 59 = 0x2e (DW_TAG_subprogram) 000345: DW_AT_sibling 0x385 000347: DW_AT_decl_file 0x1 000348: DW_AT_decl_line 0xa5 00034a: DW_AT_decl_column 0x1a 00034b: DW_AT_name __get_PRIMASK 000359: DW_AT_external 0x0 00035a: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00035f: 97 = 0x34 (DW_TAG_variable) 000360: DW_AT_name __result 000369: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00036e: DW_AT_artificial 0x1 00036f: 89 = 0x34 (DW_TAG_variable) 000370: DW_AT_name __regPriMask 00037d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000382: DW_AT_location block size 0x1 = { DW_OP_reg0 } 000384: 0 null 000385: 60 = 0x2e (DW_TAG_subprogram) 000386: DW_AT_sibling 0x3bf 000388: DW_AT_decl_file 0x1 000389: DW_AT_decl_line 0xb1 00038b: DW_AT_decl_column 0x16 00038c: DW_AT_name __set_PRIMASK 00039a: DW_AT_external 0x0 00039b: 36 = 0x5 (DW_TAG_formal_parameter) 00039c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003a1: DW_AT_name priMask 0003a9: 89 = 0x34 (DW_TAG_variable) 0003aa: DW_AT_name __regPriMask 0003b7: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003bc: DW_AT_location block size 0x1 = { DW_OP_reg0 } 0003be: 0 null 0003bf: 59 = 0x2e (DW_TAG_subprogram) 0003c0: DW_AT_sibling 0x400 0003c2: DW_AT_decl_file 0x1 0003c3: DW_AT_decl_line 0xcf 0003c5: DW_AT_decl_column 0x1b 0003c6: DW_AT_name __get_BASEPRI 0003d4: DW_AT_external 0x0 0003d5: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003da: 97 = 0x34 (DW_TAG_variable) 0003db: DW_AT_name __result 0003e4: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003e9: DW_AT_artificial 0x1 0003ea: 89 = 0x34 (DW_TAG_variable) 0003eb: DW_AT_name __regBasePri 0003f8: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003fd: DW_AT_location block size 0x1 = { DW_OP_reg0 } 0003ff: 0 null 000400: 60 = 0x2e (DW_TAG_subprogram) 000401: DW_AT_sibling 0x43a 000403: DW_AT_decl_file 0x1 000404: DW_AT_decl_line 0xdb 000406: DW_AT_decl_column 0x16 000407: DW_AT_name __set_BASEPRI 000415: DW_AT_external 0x0 000416: 36 = 0x5 (DW_TAG_formal_parameter) 000417: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00041c: DW_AT_name basePri 000424: 89 = 0x34 (DW_TAG_variable) 000425: DW_AT_name __regBasePri 000432: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000437: DW_AT_location block size 0x1 = { DW_OP_reg0 } 000439: 0 null 00043a: 60 = 0x2e (DW_TAG_subprogram) 00043b: DW_AT_sibling 0x47b 00043d: DW_AT_decl_file 0x1 00043e: DW_AT_decl_line 0xe8 000440: DW_AT_decl_column 0x16 000441: DW_AT_name __set_BASEPRI_MAX 000453: DW_AT_external 0x0 000454: 36 = 0x5 (DW_TAG_formal_parameter) 000455: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00045a: DW_AT_name basePri 000462: 89 = 0x34 (DW_TAG_variable) 000463: DW_AT_name __regBasePriMax 000473: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000478: DW_AT_location block size 0x1 = { DW_OP_reg0 } 00047a: 0 null 00047b: 59 = 0x2e (DW_TAG_subprogram) 00047c: DW_AT_sibling 0x4c0 00047e: DW_AT_decl_file 0x1 00047f: DW_AT_decl_line 0xf4 000481: DW_AT_decl_column 0x1a 000482: DW_AT_name __get_FAULTMASK 000492: DW_AT_external 0x0 000493: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000498: 97 = 0x34 (DW_TAG_variable) 000499: DW_AT_name __result 0004a2: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004a7: DW_AT_artificial 0x1 0004a8: 89 = 0x34 (DW_TAG_variable) 0004a9: DW_AT_name __regFaultMask 0004b8: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004bd: DW_AT_location block size 0x1 = { DW_OP_reg0 } 0004bf: 0 null 0004c0: 60 = 0x2e (DW_TAG_subprogram) 0004c1: DW_AT_sibling 0x500 0004c3: DW_AT_decl_file 0x1 0004c4: DW_AT_decl_line 0x100 0004c6: DW_AT_decl_column 0x16 0004c7: DW_AT_name __set_FAULTMASK 0004d7: DW_AT_external 0x0 0004d8: 36 = 0x5 (DW_TAG_formal_parameter) 0004d9: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004de: DW_AT_name faultMask 0004e8: 89 = 0x34 (DW_TAG_variable) 0004e9: DW_AT_name __regFaultMask 0004f8: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004fd: DW_AT_location block size 0x1 = { DW_OP_reg0 } 0004ff: 0 null 000500: 59 = 0x2e (DW_TAG_subprogram) 000501: DW_AT_sibling 0x53d 000503: DW_AT_decl_file 0x1 000504: DW_AT_decl_line 0x110 000506: DW_AT_decl_column 0x1a 000507: DW_AT_name __get_FPSCR 000513: DW_AT_external 0x0 000514: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000519: 97 = 0x34 (DW_TAG_variable) 00051a: DW_AT_name __result 000523: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000528: DW_AT_artificial 0x1 000529: 89 = 0x34 (DW_TAG_variable) 00052a: DW_AT_name __regfpscr 000535: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00053a: DW_AT_location block size 0x1 = { DW_OP_reg0 } 00053c: 0 null 00053d: 60 = 0x2e (DW_TAG_subprogram) 00053e: DW_AT_sibling 0x571 000540: DW_AT_decl_file 0x1 000541: DW_AT_decl_line 0x120 000543: DW_AT_decl_column 0x16 000544: DW_AT_name __set_FPSCR 000550: DW_AT_external 0x0 000551: 36 = 0x5 (DW_TAG_formal_parameter) 000552: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000557: DW_AT_name fpscr 00055d: 89 = 0x34 (DW_TAG_variable) 00055e: DW_AT_name __regfpscr 000569: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00056e: DW_AT_location block size 0x1 = { DW_OP_reg0 } 000570: 0 null 000571: 0 null 000572: 0 padding 000573: 0 padding ** Section #360 '.rel.debug_info' (SHT_REL) Size : 392 bytes (alignment 4) Symbol table #343 '.symtab' 49 relocations applied to section #31 '.debug_info' ** Section #32 '__ARM_grp.core_cmInstr.h.2_Mu0000_28gTu79Dpm6_300000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #33 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 32 bytes 000000: include at line 0 - file 1 000003: line 42 define __CORE_CMINSTR_H 000017: include at line 53 - file 2 00001a: end include 00001b: end include 00001c: end of translation unit ** Section #34 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 100 bytes 000000: Header: length 96 (not including this field) version 3 prologue length 85 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\CMSIS\Include\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 43 4d 53 49 53 5c 49 6e 63 6c 75 64 65 5c 00 00003a: directory "" : 00 00003b: file "core_cmInstr.h": dir 1 time 0x0 length 0: 63 6f 72 65 5f 63 6d 49 6e 73 74 72 2e 68 00 01 00 00 00004d: file "cmsis_armcc.h": dir 1 time 0x0 length 0: 63 6d 73 69 73 5f 61 72 6d 63 63 2e 68 00 01 00 00 00005e: file "" : 00 00005f: DW_LNS_negate_stmt : 06 000060: DW_LNS_negate_stmt : 06 000061: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\CMSIS\Include\core_cmInstr.h:1.0 ** Section #35 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 260 bytes 000000: Header: size 0x100 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\CMSIS\Include\core_cmInstr.h 000039: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000080: DW_AT_language DW_LANG_C89 000082: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 0000f9: DW_AT_macro_info 0x0 0000fd: DW_AT_stmt_list 0x0 000101: 0 null 000102: 0 padding 000103: 0 padding ** Section #361 '.rel.debug_info' (SHT_REL) Size : 24 bytes (alignment 4) Symbol table #343 '.symtab' 3 relocations applied to section #35 '.debug_info' ** Section #36 '__ARM_grp.core_cmFunc.h.2_Eu0000_WC9obG9TST2_300000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #37 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 28 bytes 000000: include at line 0 - file 1 000003: line 42 define __CORE_CMFUNC_H 000016: include at line 53 - file 2 000019: end include 00001a: end include 00001b: end of translation unit ** Section #38 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 100 bytes 000000: Header: length 96 (not including this field) version 3 prologue length 84 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\CMSIS\Include\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 43 4d 53 49 53 5c 49 6e 63 6c 75 64 65 5c 00 00003a: directory "" : 00 00003b: file "core_cmFunc.h": dir 1 time 0x0 length 0: 63 6f 72 65 5f 63 6d 46 75 6e 63 2e 68 00 01 00 00 00004c: file "cmsis_armcc.h": dir 1 time 0x0 length 0: 63 6d 73 69 73 5f 61 72 6d 63 63 2e 68 00 01 00 00 00005d: file "" : 00 00005e: DW_LNS_negate_stmt : 06 00005f: DW_LNS_negate_stmt : 06 000060: DW_LNS_negate_stmt : 06 000061: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\CMSIS\Include\core_cmFunc.h:1.0 [ ** Section #39 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 260 bytes 000000: Header: size 0x100 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\CMSIS\Include\core_cmFunc.h 000038: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 00007f: DW_AT_language DW_LANG_C89 000081: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 0000f8: DW_AT_macro_info 0x0 0000fc: DW_AT_stmt_list 0x0 000100: 0 null 000101: 0 padding 000102: 0 padding 000103: 0 padding ** Section #362 '.rel.debug_info' (SHT_REL) Size : 24 bytes (alignment 4) Symbol table #343 '.symtab' 3 relocations applied to section #39 '.debug_info' ** Section #40 '__ARM_grp.core_cmSimd.h.2_Eu0000_ZMu5h8mgjPa_300000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #41 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 28 bytes 000000: include at line 0 - file 1 000003: line 42 define __CORE_CMSIMD_H 000016: include at line 57 - file 2 000019: end include 00001a: end include 00001b: end of translation unit ** Section #42 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 100 bytes 000000: Header: length 96 (not including this field) version 3 prologue length 84 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\CMSIS\Include\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 43 4d 53 49 53 5c 49 6e 63 6c 75 64 65 5c 00 00003a: directory "" : 00 00003b: file "core_cmSimd.h": dir 1 time 0x0 length 0: 63 6f 72 65 5f 63 6d 53 69 6d 64 2e 68 00 01 00 00 00004c: file "cmsis_armcc.h": dir 1 time 0x0 length 0: 63 6d 73 69 73 5f 61 72 6d 63 63 2e 68 00 01 00 00 00005d: file "" : 00 00005e: DW_LNS_negate_stmt : 06 00005f: DW_LNS_negate_stmt : 06 000060: DW_LNS_negate_stmt : 06 000061: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\CMSIS\Include\core_cmSimd.h:1.0 [ ** Section #43 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 260 bytes 000000: Header: size 0x100 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\CMSIS\Include\core_cmSimd.h 000038: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 00007f: DW_AT_language DW_LANG_C89 000081: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 0000f8: DW_AT_macro_info 0x0 0000fc: DW_AT_stmt_list 0x0 000100: 0 null 000101: 0 padding 000102: 0 padding 000103: 0 padding ** Section #363 '.rel.debug_info' (SHT_REL) Size : 24 bytes (alignment 4) Symbol table #343 '.symtab' 3 relocations applied to section #43 '.debug_info' ** Section #44 '__ARM_grp.core_cm7.h.2_bKb200_paF20BtQ$86_H60000' (SHT_GROUP) Size : 20 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #45 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 25560 bytes 000000: include at line 0 - file 1 000003: line 42 define __CORE_CM7_H_GENERIC 00001b: include at line 44 - file 2 00001e: end include 00001f: line 74 define __CM7_CMSIS_VERSION_MAIN (0x04U) 000042: line 75 define __CM7_CMSIS_VERSION_SUB (0x1EU) 000064: line 76 define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | __CM7_CMSIS_VERSION_SUB ) 0000b9: line 79 define __CORTEX_M (0x07U) 0000ce: line 83 define __ASM __asm 0000dc: line 84 define __INLINE __inline 0000f0: line 85 define __STATIC_INLINE static __inline 000112: line 127 define __FPU_USED 1U 000122: include at line 210 - file 3 000126: end include 000127: include at line 211 - file 4 00012b: end include 00012c: include at line 212 - file 5 000130: end include 000131: line 223 define __CORE_CM7_H_DEPENDANT 00014c: line 283 define __I volatile const 000162: line 285 define __O volatile 000172: line 286 define __IO volatile 000183: line 289 define __IM volatile const 00019a: line 290 define __OM volatile 0001ab: line 291 define __IOM volatile 0001bd: line 340 define APSR_N_Pos 31U 0001cf: line 341 define APSR_N_Msk (1UL << APSR_N_Pos) 0001f1: line 343 define APSR_Z_Pos 30U 000203: line 344 define APSR_Z_Msk (1UL << APSR_Z_Pos) 000225: line 346 define APSR_C_Pos 29U 000237: line 347 define APSR_C_Msk (1UL << APSR_C_Pos) 000259: line 349 define APSR_V_Pos 28U 00026b: line 350 define APSR_V_Msk (1UL << APSR_V_Pos) 00028d: line 352 define APSR_Q_Pos 27U 00029f: line 353 define APSR_Q_Msk (1UL << APSR_Q_Pos) 0002c1: line 355 define APSR_GE_Pos 16U 0002d4: line 356 define APSR_GE_Msk (0xFUL << APSR_GE_Pos) 0002fa: line 373 define IPSR_ISR_Pos 0U 00030d: line 374 define IPSR_ISR_Msk (0x1FFUL ) 000328: line 400 define xPSR_N_Pos 31U 00033a: line 401 define xPSR_N_Msk (1UL << xPSR_N_Pos) 00035c: line 403 define xPSR_Z_Pos 30U 00036e: line 404 define xPSR_Z_Msk (1UL << xPSR_Z_Pos) 000390: line 406 define xPSR_C_Pos 29U 0003a2: line 407 define xPSR_C_Msk (1UL << xPSR_C_Pos) 0003c4: line 409 define xPSR_V_Pos 28U 0003d6: line 410 define xPSR_V_Msk (1UL << xPSR_V_Pos) 0003f8: line 412 define xPSR_Q_Pos 27U 00040a: line 413 define xPSR_Q_Msk (1UL << xPSR_Q_Pos) 00042c: line 415 define xPSR_IT_Pos 25U 00043f: line 416 define xPSR_IT_Msk (3UL << xPSR_IT_Pos) 000463: line 418 define xPSR_T_Pos 24U 000475: line 419 define xPSR_T_Msk (1UL << xPSR_T_Pos) 000497: line 421 define xPSR_GE_Pos 16U 0004aa: line 422 define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) 0004d0: line 424 define xPSR_ISR_Pos 0U 0004e3: line 425 define xPSR_ISR_Msk (0x1FFUL ) 0004fe: line 444 define CONTROL_FPCA_Pos 2U 000515: line 445 define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) 000543: line 447 define CONTROL_SPSEL_Pos 1U 00055b: line 448 define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) 00058b: line 450 define CONTROL_nPRIV_Pos 0U 0005a3: line 451 define CONTROL_nPRIV_Msk (1UL ) 0005bf: line 484 define NVIC_STIR_INTID_Pos 0U 0005d9: line 485 define NVIC_STIR_INTID_Msk (0x1FFUL ) 0005fb: line 555 define SCB_CPUID_IMPLEMENTER_Pos 24U 00061c: line 556 define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) 00065f: line 558 define SCB_CPUID_VARIANT_Pos 20U 00067c: line 559 define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) 0006b6: line 561 define SCB_CPUID_ARCHITECTURE_Pos 16U 0006d8: line 562 define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) 00071c: line 564 define SCB_CPUID_PARTNO_Pos 4U 000737: line 565 define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) 000771: line 567 define SCB_CPUID_REVISION_Pos 0U 00078e: line 568 define SCB_CPUID_REVISION_Msk (0xFUL ) 0007b1: line 571 define SCB_ICSR_NMIPENDSET_Pos 31U 0007d0: line 572 define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) 00080c: line 574 define SCB_ICSR_PENDSVSET_Pos 28U 00082a: line 575 define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) 000864: line 577 define SCB_ICSR_PENDSVCLR_Pos 27U 000882: line 578 define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) 0008bc: line 580 define SCB_ICSR_PENDSTSET_Pos 26U 0008da: line 581 define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) 000914: line 583 define SCB_ICSR_PENDSTCLR_Pos 25U 000932: line 584 define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) 00096c: line 586 define SCB_ICSR_ISRPREEMPT_Pos 23U 00098b: line 587 define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) 0009c7: line 589 define SCB_ICSR_ISRPENDING_Pos 22U 0009e6: line 590 define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) 000a22: line 592 define SCB_ICSR_VECTPENDING_Pos 12U 000a42: line 593 define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) 000a84: line 595 define SCB_ICSR_RETTOBASE_Pos 11U 000aa2: line 596 define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) 000adc: line 598 define SCB_ICSR_VECTACTIVE_Pos 0U 000afa: line 599 define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL ) 000b20: line 602 define SCB_VTOR_TBLOFF_Pos 7U 000b3a: line 603 define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) 000b76: line 606 define SCB_AIRCR_VECTKEY_Pos 16U 000b93: line 607 define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) 000bd0: line 609 define SCB_AIRCR_VECTKEYSTAT_Pos 16U 000bf1: line 610 define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) 000c36: line 612 define SCB_AIRCR_ENDIANESS_Pos 15U 000c55: line 613 define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) 000c91: line 615 define SCB_AIRCR_PRIGROUP_Pos 8U 000cae: line 616 define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) 000ce8: line 618 define SCB_AIRCR_SYSRESETREQ_Pos 2U 000d08: line 619 define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) 000d48: line 621 define SCB_AIRCR_VECTCLRACTIVE_Pos 1U 000d6a: line 622 define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) 000dae: line 624 define SCB_AIRCR_VECTRESET_Pos 0U 000dcc: line 625 define SCB_AIRCR_VECTRESET_Msk (1UL ) 000dee: line 628 define SCB_SCR_SEVONPEND_Pos 4U 000e0a: line 629 define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) 000e42: line 631 define SCB_SCR_SLEEPDEEP_Pos 2U 000e5e: line 632 define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) 000e96: line 634 define SCB_SCR_SLEEPONEXIT_Pos 1U 000eb4: line 635 define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) 000ef0: line 638 define SCB_CCR_BP_Pos 18U 000f06: line 639 define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) 000f30: line 641 define SCB_CCR_IC_Pos 17U 000f46: line 642 define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) 000f70: line 644 define SCB_CCR_DC_Pos 16U 000f86: line 645 define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) 000fb0: line 647 define SCB_CCR_STKALIGN_Pos 9U 000fcb: line 648 define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) 001001: line 650 define SCB_CCR_BFHFNMIGN_Pos 8U 00101d: line 651 define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) 001055: line 653 define SCB_CCR_DIV_0_TRP_Pos 4U 001071: line 654 define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) 0010a9: line 656 define SCB_CCR_UNALIGN_TRP_Pos 3U 0010c7: line 657 define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) 001103: line 659 define SCB_CCR_USERSETMPEND_Pos 1U 001122: line 660 define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) 001160: line 662 define SCB_CCR_NONBASETHRDENA_Pos 0U 001181: line 663 define SCB_CCR_NONBASETHRDENA_Msk (1UL ) 0011a6: line 666 define SCB_SHCSR_USGFAULTENA_Pos 18U 0011c7: line 667 define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) 001207: line 669 define SCB_SHCSR_BUSFAULTENA_Pos 17U 001228: line 670 define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) 001268: line 672 define SCB_SHCSR_MEMFAULTENA_Pos 16U 001289: line 673 define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) 0012c9: line 675 define SCB_SHCSR_SVCALLPENDED_Pos 15U 0012eb: line 676 define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) 00132d: line 678 define SCB_SHCSR_BUSFAULTPENDED_Pos 14U 001351: line 679 define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) 001397: line 681 define SCB_SHCSR_MEMFAULTPENDED_Pos 13U 0013bb: line 682 define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) 001401: line 684 define SCB_SHCSR_USGFAULTPENDED_Pos 12U 001425: line 685 define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) 00146b: line 687 define SCB_SHCSR_SYSTICKACT_Pos 11U 00148b: line 688 define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) 0014c9: line 690 define SCB_SHCSR_PENDSVACT_Pos 10U 0014e8: line 691 define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) 001524: line 693 define SCB_SHCSR_MONITORACT_Pos 8U 001543: line 694 define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) 001581: line 696 define SCB_SHCSR_SVCALLACT_Pos 7U 00159f: line 697 define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) 0015db: line 699 define SCB_SHCSR_USGFAULTACT_Pos 3U 0015fb: line 700 define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) 00163b: line 702 define SCB_SHCSR_BUSFAULTACT_Pos 1U 00165b: line 703 define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) 00169b: line 705 define SCB_SHCSR_MEMFAULTACT_Pos 0U 0016bb: line 706 define SCB_SHCSR_MEMFAULTACT_Msk (1UL ) 0016df: line 709 define SCB_CFSR_USGFAULTSR_Pos 16U 0016fe: line 710 define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) 00173f: line 712 define SCB_CFSR_BUSFAULTSR_Pos 8U 00175d: line 713 define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) 00179c: line 715 define SCB_CFSR_MEMFAULTSR_Pos 0U 0017ba: line 716 define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL ) 0017df: line 719 define SCB_HFSR_DEBUGEVT_Pos 31U 0017fc: line 720 define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) 001834: line 722 define SCB_HFSR_FORCED_Pos 30U 00184f: line 723 define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) 001883: line 725 define SCB_HFSR_VECTTBL_Pos 1U 00189e: line 726 define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) 0018d4: line 729 define SCB_DFSR_EXTERNAL_Pos 4U 0018f0: line 730 define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) 001928: line 732 define SCB_DFSR_VCATCH_Pos 3U 001942: line 733 define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) 001976: line 735 define SCB_DFSR_DWTTRAP_Pos 2U 001991: line 736 define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) 0019c7: line 738 define SCB_DFSR_BKPT_Pos 1U 0019df: line 739 define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) 001a0f: line 741 define SCB_DFSR_HALTED_Pos 0U 001a29: line 742 define SCB_DFSR_HALTED_Msk (1UL ) 001a47: line 745 define SCB_CLIDR_LOUU_Pos 27U 001a61: line 746 define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) 001a93: line 748 define SCB_CLIDR_LOC_Pos 24U 001aac: line 749 define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) 001adc: line 752 define SCB_CTR_FORMAT_Pos 29U 001af6: line 753 define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) 001b28: line 755 define SCB_CTR_CWG_Pos 24U 001b3f: line 756 define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) 001b6d: line 758 define SCB_CTR_ERG_Pos 20U 001b84: line 759 define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) 001bb2: line 761 define SCB_CTR_DMINLINE_Pos 16U 001bce: line 762 define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) 001c06: line 764 define SCB_CTR_IMINLINE_Pos 0U 001c21: line 765 define SCB_CTR_IMINLINE_Msk (0xFUL ) 001c42: line 768 define SCB_CCSIDR_WT_Pos 31U 001c5b: line 769 define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) 001c8b: line 771 define SCB_CCSIDR_WB_Pos 30U 001ca4: line 772 define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) 001cd4: line 774 define SCB_CCSIDR_RA_Pos 29U 001ced: line 775 define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) 001d1d: line 777 define SCB_CCSIDR_WA_Pos 28U 001d36: line 778 define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) 001d66: line 780 define SCB_CCSIDR_NUMSETS_Pos 13U 001d84: line 781 define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) 001dc3: line 783 define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U 001de6: line 784 define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) 001e30: line 786 define SCB_CCSIDR_LINESIZE_Pos 0U 001e4e: line 787 define SCB_CCSIDR_LINESIZE_Msk (7UL ) 001e70: line 790 define SCB_CSSELR_LEVEL_Pos 1U 001e8b: line 791 define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) 001ec1: line 793 define SCB_CSSELR_IND_Pos 0U 001eda: line 794 define SCB_CSSELR_IND_Msk (1UL ) 001ef7: line 797 define SCB_STIR_INTID_Pos 0U 001f10: line 798 define SCB_STIR_INTID_Msk (0x1FFUL ) 001f31: line 801 define SCB_DCISW_WAY_Pos 30U 001f4a: line 802 define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) 001f7a: line 804 define SCB_DCISW_SET_Pos 5U 001f92: line 805 define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) 001fc6: line 808 define SCB_DCCSW_WAY_Pos 30U 001fdf: line 809 define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) 00200f: line 811 define SCB_DCCSW_SET_Pos 5U 002027: line 812 define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) 00205b: line 815 define SCB_DCCISW_WAY_Pos 30U 002075: line 816 define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) 0020a7: line 818 define SCB_DCCISW_SET_Pos 5U 0020c0: line 819 define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) 0020f6: line 822 define SCB_ITCMCR_SZ_Pos 3U 00210e: line 823 define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) 002140: line 825 define SCB_ITCMCR_RETEN_Pos 2U 00215b: line 826 define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) 002191: line 828 define SCB_ITCMCR_RMW_Pos 1U 0021aa: line 829 define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) 0021dc: line 831 define SCB_ITCMCR_EN_Pos 0U 0021f4: line 832 define SCB_ITCMCR_EN_Msk (1UL ) 002210: line 835 define SCB_DTCMCR_SZ_Pos 3U 002228: line 836 define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) 00225a: line 838 define SCB_DTCMCR_RETEN_Pos 2U 002275: line 839 define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) 0022ab: line 841 define SCB_DTCMCR_RMW_Pos 1U 0022c4: line 842 define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) 0022f6: line 844 define SCB_DTCMCR_EN_Pos 0U 00230e: line 845 define SCB_DTCMCR_EN_Msk (1UL ) 00232a: line 848 define SCB_AHBPCR_SZ_Pos 1U 002342: line 849 define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) 002372: line 851 define SCB_AHBPCR_EN_Pos 0U 00238a: line 852 define SCB_AHBPCR_EN_Msk (1UL ) 0023a6: line 855 define SCB_CACR_FORCEWT_Pos 2U 0023c1: line 856 define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) 0023f7: line 858 define SCB_CACR_ECCEN_Pos 1U 002410: line 859 define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) 002442: line 861 define SCB_CACR_SIWT_Pos 0U 00245a: line 862 define SCB_CACR_SIWT_Msk (1UL ) 002476: line 865 define SCB_AHBSCR_INITCOUNT_Pos 11U 002496: line 866 define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) 0024d7: line 868 define SCB_AHBSCR_TPRI_Pos 2U 0024f1: line 869 define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) 002529: line 871 define SCB_AHBSCR_CTL_Pos 0U 002542: line 872 define SCB_AHBSCR_CTL_Msk (3UL ) 00255f: line 875 define SCB_ABFSR_AXIMTYPE_Pos 8U 00257c: line 876 define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) 0025b6: line 878 define SCB_ABFSR_EPPB_Pos 4U 0025cf: line 879 define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) 002601: line 881 define SCB_ABFSR_AXIM_Pos 3U 00261a: line 882 define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) 00264c: line 884 define SCB_ABFSR_AHBP_Pos 2U 002665: line 885 define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) 002697: line 887 define SCB_ABFSR_DTCM_Pos 1U 0026b0: line 888 define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) 0026e2: line 890 define SCB_ABFSR_ITCM_Pos 0U 0026fb: line 891 define SCB_ABFSR_ITCM_Msk (1UL ) 002718: line 914 define SCnSCB_ICTR_INTLINESNUM_Pos 0U 00273a: line 915 define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL ) 002762: line 918 define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U 002789: line 919 define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) 0027d5: line 921 define SCnSCB_ACTLR_DISRAMODE_Pos 11U 0027f7: line 922 define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) 002839: line 924 define SCnSCB_ACTLR_FPEXCODIS_Pos 10U 00285b: line 925 define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) 00289d: line 927 define SCnSCB_ACTLR_DISFOLD_Pos 2U 0028bc: line 928 define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) 0028fa: line 930 define SCnSCB_ACTLR_DISMCYCINT_Pos 0U 00291c: line 931 define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL ) 002942: line 955 define SysTick_CTRL_COUNTFLAG_Pos 16U 002964: line 956 define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) 0029a6: line 958 define SysTick_CTRL_CLKSOURCE_Pos 2U 0029c7: line 959 define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) 002a09: line 961 define SysTick_CTRL_TICKINT_Pos 1U 002a28: line 962 define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) 002a66: line 964 define SysTick_CTRL_ENABLE_Pos 0U 002a84: line 965 define SysTick_CTRL_ENABLE_Msk (1UL ) 002aa6: line 968 define SysTick_LOAD_RELOAD_Pos 0U 002ac4: line 969 define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL ) 002aed: line 972 define SysTick_VAL_CURRENT_Pos 0U 002b0b: line 973 define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL ) 002b34: line 976 define SysTick_CALIB_NOREF_Pos 31U 002b53: line 977 define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) 002b8f: line 979 define SysTick_CALIB_SKEW_Pos 30U 002bad: line 980 define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) 002be7: line 982 define SysTick_CALIB_TENMS_Pos 0U 002c05: line 983 define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL ) 002c2e: line 1035 define ITM_TPR_PRIVMASK_Pos 0U 002c49: line 1036 define ITM_TPR_PRIVMASK_Msk (0xFUL ) 002c6a: line 1039 define ITM_TCR_BUSY_Pos 23U 002c82: line 1040 define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) 002cb0: line 1042 define ITM_TCR_TraceBusID_Pos 16U 002cce: line 1043 define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) 002d0b: line 1045 define ITM_TCR_GTSFREQ_Pos 10U 002d26: line 1046 define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) 002d5a: line 1048 define ITM_TCR_TSPrescale_Pos 8U 002d77: line 1049 define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) 002db1: line 1051 define ITM_TCR_SWOENA_Pos 4U 002dca: line 1052 define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) 002dfc: line 1054 define ITM_TCR_DWTENA_Pos 3U 002e15: line 1055 define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) 002e47: line 1057 define ITM_TCR_SYNCENA_Pos 2U 002e61: line 1058 define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) 002e95: line 1060 define ITM_TCR_TSENA_Pos 1U 002ead: line 1061 define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) 002edd: line 1063 define ITM_TCR_ITMENA_Pos 0U 002ef6: line 1064 define ITM_TCR_ITMENA_Msk (1UL ) 002f13: line 1067 define ITM_IWR_ATVALIDM_Pos 0U 002f2e: line 1068 define ITM_IWR_ATVALIDM_Msk (1UL ) 002f4d: line 1071 define ITM_IRR_ATREADYM_Pos 0U 002f68: line 1072 define ITM_IRR_ATREADYM_Msk (1UL ) 002f87: line 1075 define ITM_IMCR_INTEGRATION_Pos 0U 002fa6: line 1076 define ITM_IMCR_INTEGRATION_Msk (1UL ) 002fc9: line 1079 define ITM_LSR_ByteAcc_Pos 2U 002fe3: line 1080 define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) 003017: line 1082 define ITM_LSR_Access_Pos 1U 003030: line 1083 define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) 003062: line 1085 define ITM_LSR_Present_Pos 0U 00307c: line 1086 define ITM_LSR_Present_Msk (1UL ) 00309a: line 1132 define DWT_CTRL_NUMCOMP_Pos 28U 0030b6: line 1133 define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) 0030ee: line 1135 define DWT_CTRL_NOTRCPKT_Pos 27U 00310b: line 1136 define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) 003145: line 1138 define DWT_CTRL_NOEXTTRIG_Pos 26U 003163: line 1139 define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) 00319f: line 1141 define DWT_CTRL_NOCYCCNT_Pos 25U 0031bc: line 1142 define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) 0031f6: line 1144 define DWT_CTRL_NOPRFCNT_Pos 24U 003213: line 1145 define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) 00324d: line 1147 define DWT_CTRL_CYCEVTENA_Pos 22U 00326b: line 1148 define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) 0032a7: line 1150 define DWT_CTRL_FOLDEVTENA_Pos 21U 0032c6: line 1151 define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) 003304: line 1153 define DWT_CTRL_LSUEVTENA_Pos 20U 003322: line 1154 define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) 00335e: line 1156 define DWT_CTRL_SLEEPEVTENA_Pos 19U 00337e: line 1157 define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) 0033be: line 1159 define DWT_CTRL_EXCEVTENA_Pos 18U 0033dc: line 1160 define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) 003418: line 1162 define DWT_CTRL_CPIEVTENA_Pos 17U 003436: line 1163 define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) 003472: line 1165 define DWT_CTRL_EXCTRCENA_Pos 16U 003490: line 1166 define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) 0034cc: line 1168 define DWT_CTRL_PCSAMPLENA_Pos 12U 0034eb: line 1169 define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) 003529: line 1171 define DWT_CTRL_SYNCTAP_Pos 10U 003545: line 1172 define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) 00357d: line 1174 define DWT_CTRL_CYCTAP_Pos 9U 003597: line 1175 define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) 0035cd: line 1177 define DWT_CTRL_POSTINIT_Pos 5U 0035e9: line 1178 define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) 003623: line 1180 define DWT_CTRL_POSTPRESET_Pos 1U 003641: line 1181 define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) 00367f: line 1183 define DWT_CTRL_CYCCNTENA_Pos 0U 00369c: line 1184 define DWT_CTRL_CYCCNTENA_Msk (0x1UL ) 0036bf: line 1187 define DWT_CPICNT_CPICNT_Pos 0U 0036db: line 1188 define DWT_CPICNT_CPICNT_Msk (0xFFUL ) 0036fe: line 1191 define DWT_EXCCNT_EXCCNT_Pos 0U 00371a: line 1192 define DWT_EXCCNT_EXCCNT_Msk (0xFFUL ) 00373d: line 1195 define DWT_SLEEPCNT_SLEEPCNT_Pos 0U 00375d: line 1196 define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL ) 003784: line 1199 define DWT_LSUCNT_LSUCNT_Pos 0U 0037a0: line 1200 define DWT_LSUCNT_LSUCNT_Msk (0xFFUL ) 0037c3: line 1203 define DWT_FOLDCNT_FOLDCNT_Pos 0U 0037e1: line 1204 define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL ) 003806: line 1207 define DWT_MASK_MASK_Pos 0U 00381e: line 1208 define DWT_MASK_MASK_Msk (0x1FUL ) 00383d: line 1211 define DWT_FUNCTION_MATCHED_Pos 24U 00385d: line 1212 define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) 00389d: line 1214 define DWT_FUNCTION_DATAVADDR1_Pos 16U 0038c0: line 1215 define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) 003906: line 1217 define DWT_FUNCTION_DATAVADDR0_Pos 12U 003929: line 1218 define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) 00396f: line 1220 define DWT_FUNCTION_DATAVSIZE_Pos 10U 003991: line 1221 define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) 0039d5: line 1223 define DWT_FUNCTION_LNK1ENA_Pos 9U 0039f4: line 1224 define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) 003a34: line 1226 define DWT_FUNCTION_DATAVMATCH_Pos 8U 003a56: line 1227 define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) 003a9c: line 1229 define DWT_FUNCTION_CYCMATCH_Pos 7U 003abc: line 1230 define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) 003afe: line 1232 define DWT_FUNCTION_EMITRANGE_Pos 5U 003b1f: line 1233 define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) 003b63: line 1235 define DWT_FUNCTION_FUNCTION_Pos 0U 003b83: line 1236 define DWT_FUNCTION_FUNCTION_Msk (0xFUL ) 003ba9: line 1280 define TPI_ACPR_PRESCALER_Pos 0U 003bc6: line 1281 define TPI_ACPR_PRESCALER_Msk (0x1FFFUL ) 003bec: line 1284 define TPI_SPPR_TXMODE_Pos 0U 003c06: line 1285 define TPI_SPPR_TXMODE_Msk (0x3UL ) 003c26: line 1288 define TPI_FFSR_FtNonStop_Pos 3U 003c43: line 1289 define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) 003c7f: line 1291 define TPI_FFSR_TCPresent_Pos 2U 003c9c: line 1292 define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) 003cd8: line 1294 define TPI_FFSR_FtStopped_Pos 1U 003cf5: line 1295 define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) 003d31: line 1297 define TPI_FFSR_FlInProg_Pos 0U 003d4d: line 1298 define TPI_FFSR_FlInProg_Msk (0x1UL ) 003d6f: line 1301 define TPI_FFCR_TrigIn_Pos 8U 003d89: line 1302 define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) 003dbf: line 1304 define TPI_FFCR_EnFCont_Pos 1U 003dda: line 1305 define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) 003e12: line 1308 define TPI_TRIGGER_TRIGGER_Pos 0U 003e30: line 1309 define TPI_TRIGGER_TRIGGER_Msk (0x1UL ) 003e54: line 1312 define TPI_FIFO0_ITM_ATVALID_Pos 29U 003e75: line 1313 define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) 003eb7: line 1315 define TPI_FIFO0_ITM_bytecount_Pos 27U 003eda: line 1316 define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) 003f20: line 1318 define TPI_FIFO0_ETM_ATVALID_Pos 26U 003f41: line 1319 define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) 003f83: line 1321 define TPI_FIFO0_ETM_bytecount_Pos 24U 003fa6: line 1322 define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) 003fec: line 1324 define TPI_FIFO0_ETM2_Pos 16U 004006: line 1325 define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) 00403b: line 1327 define TPI_FIFO0_ETM1_Pos 8U 004054: line 1328 define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) 004089: line 1330 define TPI_FIFO0_ETM0_Pos 0U 0040a2: line 1331 define TPI_FIFO0_ETM0_Msk (0xFFUL ) 0040c2: line 1334 define TPI_ITATBCTR2_ATREADY_Pos 0U 0040e2: line 1335 define TPI_ITATBCTR2_ATREADY_Msk (0x1UL ) 004108: line 1338 define TPI_FIFO1_ITM_ATVALID_Pos 29U 004129: line 1339 define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) 00416b: line 1341 define TPI_FIFO1_ITM_bytecount_Pos 27U 00418e: line 1342 define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) 0041d4: line 1344 define TPI_FIFO1_ETM_ATVALID_Pos 26U 0041f5: line 1345 define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) 004237: line 1347 define TPI_FIFO1_ETM_bytecount_Pos 24U 00425a: line 1348 define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) 0042a0: line 1350 define TPI_FIFO1_ITM2_Pos 16U 0042ba: line 1351 define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) 0042ef: line 1353 define TPI_FIFO1_ITM1_Pos 8U 004308: line 1354 define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) 00433d: line 1356 define TPI_FIFO1_ITM0_Pos 0U 004356: line 1357 define TPI_FIFO1_ITM0_Msk (0xFFUL ) 004376: line 1360 define TPI_ITATBCTR0_ATREADY_Pos 0U 004396: line 1361 define TPI_ITATBCTR0_ATREADY_Msk (0x1UL ) 0043bc: line 1364 define TPI_ITCTRL_Mode_Pos 0U 0043d6: line 1365 define TPI_ITCTRL_Mode_Msk (0x1UL ) 0043f6: line 1368 define TPI_DEVID_NRZVALID_Pos 11U 004414: line 1369 define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) 004450: line 1371 define TPI_DEVID_MANCVALID_Pos 10U 00446f: line 1372 define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) 0044ad: line 1374 define TPI_DEVID_PTINVALID_Pos 9U 0044cb: line 1375 define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) 004509: line 1377 define TPI_DEVID_MinBufSz_Pos 6U 004526: line 1378 define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) 004562: line 1380 define TPI_DEVID_AsynClkIn_Pos 5U 004580: line 1381 define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) 0045be: line 1383 define TPI_DEVID_NrTraceInput_Pos 0U 0045df: line 1384 define TPI_DEVID_NrTraceInput_Msk (0x1FUL ) 004607: line 1387 define TPI_DEVTYPE_MajorType_Pos 4U 004627: line 1388 define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) 004669: line 1390 define TPI_DEVTYPE_SubType_Pos 0U 004687: line 1391 define TPI_DEVTYPE_SubType_Msk (0xFUL ) 0046ab: line 1423 define MPU_TYPE_IREGION_Pos 16U 0046c7: line 1424 define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) 004700: line 1426 define MPU_TYPE_DREGION_Pos 8U 00471b: line 1427 define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) 004754: line 1429 define MPU_TYPE_SEPARATE_Pos 0U 004770: line 1430 define MPU_TYPE_SEPARATE_Msk (1UL ) 004790: line 1433 define MPU_CTRL_PRIVDEFENA_Pos 2U 0047ae: line 1434 define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) 0047ea: line 1436 define MPU_CTRL_HFNMIENA_Pos 1U 004806: line 1437 define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) 00483e: line 1439 define MPU_CTRL_ENABLE_Pos 0U 004858: line 1440 define MPU_CTRL_ENABLE_Msk (1UL ) 004876: line 1443 define MPU_RNR_REGION_Pos 0U 00488f: line 1444 define MPU_RNR_REGION_Msk (0xFFUL ) 0048af: line 1447 define MPU_RBAR_ADDR_Pos 5U 0048c7: line 1448 define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) 0048ff: line 1450 define MPU_RBAR_VALID_Pos 4U 004918: line 1451 define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) 00494a: line 1453 define MPU_RBAR_REGION_Pos 0U 004964: line 1454 define MPU_RBAR_REGION_Msk (0xFUL ) 004984: line 1457 define MPU_RASR_ATTRS_Pos 16U 00499e: line 1458 define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) 0049d5: line 1460 define MPU_RASR_XN_Pos 28U 0049ec: line 1461 define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) 004a18: line 1463 define MPU_RASR_AP_Pos 24U 004a2f: line 1464 define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) 004a5d: line 1466 define MPU_RASR_TEX_Pos 19U 004a75: line 1467 define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) 004aa5: line 1469 define MPU_RASR_S_Pos 18U 004abb: line 1470 define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) 004ae5: line 1472 define MPU_RASR_C_Pos 17U 004afb: line 1473 define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) 004b25: line 1475 define MPU_RASR_B_Pos 16U 004b3b: line 1476 define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) 004b65: line 1478 define MPU_RASR_SRD_Pos 8U 004b7c: line 1479 define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) 004bad: line 1481 define MPU_RASR_SIZE_Pos 1U 004bc5: line 1482 define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) 004bf8: line 1484 define MPU_RASR_ENABLE_Pos 0U 004c12: line 1485 define MPU_RASR_ENABLE_Msk (1UL ) 004c30: line 1514 define FPU_FPCCR_ASPEN_Pos 31U 004c4b: line 1515 define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) 004c7f: line 1517 define FPU_FPCCR_LSPEN_Pos 30U 004c9a: line 1518 define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) 004cce: line 1520 define FPU_FPCCR_MONRDY_Pos 8U 004ce9: line 1521 define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) 004d1f: line 1523 define FPU_FPCCR_BFRDY_Pos 6U 004d39: line 1524 define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) 004d6d: line 1526 define FPU_FPCCR_MMRDY_Pos 5U 004d87: line 1527 define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) 004dbb: line 1529 define FPU_FPCCR_HFRDY_Pos 4U 004dd5: line 1530 define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) 004e09: line 1532 define FPU_FPCCR_THREAD_Pos 3U 004e24: line 1533 define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) 004e5a: line 1535 define FPU_FPCCR_USER_Pos 1U 004e73: line 1536 define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) 004ea5: line 1538 define FPU_FPCCR_LSPACT_Pos 0U 004ec0: line 1539 define FPU_FPCCR_LSPACT_Msk (1UL ) 004edf: line 1542 define FPU_FPCAR_ADDRESS_Pos 3U 004efb: line 1543 define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) 004f3c: line 1546 define FPU_FPDSCR_AHP_Pos 26U 004f56: line 1547 define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) 004f88: line 1549 define FPU_FPDSCR_DN_Pos 25U 004fa1: line 1550 define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) 004fd1: line 1552 define FPU_FPDSCR_FZ_Pos 24U 004fea: line 1553 define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) 00501a: line 1555 define FPU_FPDSCR_RMode_Pos 22U 005036: line 1556 define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) 00506c: line 1559 define FPU_MVFR0_FP_rounding_modes_Pos 28U 005093: line 1560 define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) 0050e1: line 1562 define FPU_MVFR0_Short_vectors_Pos 24U 005104: line 1563 define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) 00514a: line 1565 define FPU_MVFR0_Square_root_Pos 20U 00516b: line 1566 define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) 0051ad: line 1568 define FPU_MVFR0_Divide_Pos 16U 0051c9: line 1569 define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) 005201: line 1571 define FPU_MVFR0_FP_excep_trapping_Pos 12U 005228: line 1572 define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) 005276: line 1574 define FPU_MVFR0_Double_precision_Pos 8U 00529b: line 1575 define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) 0052e7: line 1577 define FPU_MVFR0_Single_precision_Pos 4U 00530c: line 1578 define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) 005358: line 1580 define FPU_MVFR0_A_SIMD_registers_Pos 0U 00537d: line 1581 define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL ) 0053a8: line 1584 define FPU_MVFR1_FP_fused_MAC_Pos 28U 0053ca: line 1585 define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) 00540e: line 1587 define FPU_MVFR1_FP_HPFP_Pos 24U 00542b: line 1588 define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) 005465: line 1590 define FPU_MVFR1_D_NaN_mode_Pos 4U 005484: line 1591 define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) 0054c4: line 1593 define FPU_MVFR1_FtZ_mode_Pos 0U 0054e1: line 1594 define FPU_MVFR1_FtZ_mode_Msk (0xFUL ) 005504: line 1621 define CoreDebug_DHCSR_DBGKEY_Pos 16U 005526: line 1622 define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) 00556d: line 1624 define CoreDebug_DHCSR_S_RESET_ST_Pos 25U 005593: line 1625 define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) 0055dd: line 1627 define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U 005604: line 1628 define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) 005650: line 1630 define CoreDebug_DHCSR_S_LOCKUP_Pos 19U 005674: line 1631 define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) 0056ba: line 1633 define CoreDebug_DHCSR_S_SLEEP_Pos 18U 0056dd: line 1634 define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) 005721: line 1636 define CoreDebug_DHCSR_S_HALT_Pos 17U 005743: line 1637 define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) 005785: line 1639 define CoreDebug_DHCSR_S_REGRDY_Pos 16U 0057a9: line 1640 define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) 0057ef: line 1642 define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U 005815: line 1643 define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) 005861: line 1645 define CoreDebug_DHCSR_C_MASKINTS_Pos 3U 005886: line 1646 define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) 0058d0: line 1648 define CoreDebug_DHCSR_C_STEP_Pos 2U 0058f1: line 1649 define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) 005933: line 1651 define CoreDebug_DHCSR_C_HALT_Pos 1U 005954: line 1652 define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) 005996: line 1654 define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U 0059ba: line 1655 define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL ) 0059e2: line 1658 define CoreDebug_DCRSR_REGWnR_Pos 16U 005a04: line 1659 define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) 005a46: line 1661 define CoreDebug_DCRSR_REGSEL_Pos 0U 005a67: line 1662 define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL ) 005a8f: line 1665 define CoreDebug_DEMCR_TRCENA_Pos 24U 005ab1: line 1666 define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) 005af3: line 1668 define CoreDebug_DEMCR_MON_REQ_Pos 19U 005b16: line 1669 define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) 005b5a: line 1671 define CoreDebug_DEMCR_MON_STEP_Pos 18U 005b7e: line 1672 define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) 005bc4: line 1674 define CoreDebug_DEMCR_MON_PEND_Pos 17U 005be8: line 1675 define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) 005c2e: line 1677 define CoreDebug_DEMCR_MON_EN_Pos 16U 005c50: line 1678 define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) 005c92: line 1680 define CoreDebug_DEMCR_VC_HARDERR_Pos 10U 005cb8: line 1681 define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) 005d02: line 1683 define CoreDebug_DEMCR_VC_INTERR_Pos 9U 005d26: line 1684 define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) 005d6e: line 1686 define CoreDebug_DEMCR_VC_BUSERR_Pos 8U 005d92: line 1687 define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) 005dda: line 1689 define CoreDebug_DEMCR_VC_STATERR_Pos 7U 005dff: line 1690 define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) 005e49: line 1692 define CoreDebug_DEMCR_VC_CHKERR_Pos 6U 005e6d: line 1693 define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) 005eb5: line 1695 define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U 005eda: line 1696 define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) 005f24: line 1698 define CoreDebug_DEMCR_VC_MMERR_Pos 4U 005f47: line 1699 define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) 005f8d: line 1701 define CoreDebug_DEMCR_VC_CORERESET_Pos 0U 005fb4: line 1702 define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL ) 005fdf: line 1720 define _VAL2FLD(field,value) ((value << field ## _Pos) & field ## _Msk) 006023: line 1728 define _FLD2VAL(field,value) ((value & field ## _Msk) >> field ## _Pos) 006067: line 1741 define SCS_BASE (0xE000E000UL) 006082: line 1742 define ITM_BASE (0xE0000000UL) 00609d: line 1743 define DWT_BASE (0xE0001000UL) 0060b8: line 1744 define TPI_BASE (0xE0040000UL) 0060d3: line 1745 define CoreDebug_BASE (0xE000EDF0UL) 0060f4: line 1746 define SysTick_BASE (SCS_BASE + 0x0010UL) 00611a: line 1747 define NVIC_BASE (SCS_BASE + 0x0100UL) 00613d: line 1748 define SCB_BASE (SCS_BASE + 0x0D00UL) 00615f: line 1750 define SCnSCB ((SCnSCB_Type *) SCS_BASE ) 006185: line 1751 define SCB ((SCB_Type *) SCB_BASE ) 0061a5: line 1752 define SysTick ((SysTick_Type *) SysTick_BASE ) 0061d1: line 1753 define NVIC ((NVIC_Type *) NVIC_BASE ) 0061f4: line 1754 define ITM ((ITM_Type *) ITM_BASE ) 006214: line 1755 define DWT ((DWT_Type *) DWT_BASE ) 006234: line 1756 define TPI ((TPI_Type *) TPI_BASE ) 006254: line 1757 define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) 006285: line 1760 define MPU_BASE (SCS_BASE + 0x0D90UL) 0062a7: line 1761 define MPU ((MPU_Type *) MPU_BASE ) 0062c7: line 1765 define FPU_BASE (SCS_BASE + 0x0F30UL) 0062e9: line 1766 define FPU ((FPU_Type *) FPU_BASE ) 006309: line 2065 define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) 006362: line 2066 define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) 0063b1: line 2436 define ITM_RXBUFFER_EMPTY 0x5AA55AA5U 0063d3: end include 0063d4: end of translation unit ** Section #46 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 200 bytes 000000: Header: length 196 (not including this field) version 3 prologue length 185 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\CMSIS\Include\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 43 4d 53 49 53 5c 49 6e 63 6c 75 64 65 5c 00 00003a: directory "D:\Program Files (x86)\Keil_v5\ARM\ARMCC\Bin\..\include\": 44 3a 5c 50 72 6f 67 72 61 6d 20 46 69 6c 65 73 20 28 78 38 36 29 5c 4b 65 69 6c 5f 76 35 5c 41 52 4d 5c 41 52 4d 43 43 5c 42 69 6e 5c 2e 2e 5c 69 6e 63 6c 75 64 65 5c 00 000073: directory "" : 00 000074: file "core_cm7.h": dir 1 time 0x0 length 0: 63 6f 72 65 5f 63 6d 37 2e 68 00 01 00 00 000082: file "stdint.h": dir 2 time 0x0 length 0: 73 74 64 69 6e 74 2e 68 00 02 00 00 00008e: file "core_cmInstr.h": dir 1 time 0x0 length 0: 63 6f 72 65 5f 63 6d 49 6e 73 74 72 2e 68 00 01 00 00 0000a0: file "core_cmFunc.h": dir 1 time 0x0 length 0: 63 6f 72 65 5f 63 6d 46 75 6e 63 2e 68 00 01 00 00 0000b1: file "core_cmSimd.h": dir 1 time 0x0 length 0: 63 6f 72 65 5f 63 6d 53 69 6d 64 2e 68 00 01 00 00 0000c2: file "" : 00 0000c3: DW_LNS_negate_stmt : 06 0000c4: DW_LNS_negate_stmt : 06 0000c5: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\CMSIS\Include\core_cm7.h:1.0 ** Section #47 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 5936 bytes 000000: Header: size 0x172c bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\CMSIS\Include\core_cm7.h 000035: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 00007c: DW_AT_language DW_LANG_C89 00007e: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 0000f5: DW_AT_macro_info 0x0 0000f9: DW_AT_stmt_list 0x0 0000fd: 42 = 0x13 (DW_TAG_structure_type) 0000fe: DW_AT_sibling 0x185 000100: DW_AT_byte_size 0x4 000101: 33 = 0xd (DW_TAG_member) 000102: DW_AT_name _reserved0 00010d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000112: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000115: DW_AT_byte_size 0x4 000116: DW_AT_bit_size 0x10 000117: DW_AT_bit_offset 0x10 000118: 33 = 0xd (DW_TAG_member) 000119: DW_AT_name GE 00011c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000121: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000124: DW_AT_byte_size 0x4 000125: DW_AT_bit_size 0x4 000126: DW_AT_bit_offset 0xc 000127: 33 = 0xd (DW_TAG_member) 000128: DW_AT_name _reserved1 000133: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000138: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00013b: DW_AT_byte_size 0x4 00013c: DW_AT_bit_size 0x7 00013d: DW_AT_bit_offset 0x5 00013e: 33 = 0xd (DW_TAG_member) 00013f: DW_AT_name Q 000141: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000146: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000149: DW_AT_byte_size 0x4 00014a: DW_AT_bit_size 0x1 00014b: DW_AT_bit_offset 0x4 00014c: 33 = 0xd (DW_TAG_member) 00014d: DW_AT_name V 00014f: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000154: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000157: DW_AT_byte_size 0x4 000158: DW_AT_bit_size 0x1 000159: DW_AT_bit_offset 0x3 00015a: 33 = 0xd (DW_TAG_member) 00015b: DW_AT_name C 00015d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000162: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000165: DW_AT_byte_size 0x4 000166: DW_AT_bit_size 0x1 000167: DW_AT_bit_offset 0x2 000168: 33 = 0xd (DW_TAG_member) 000169: DW_AT_name Z 00016b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000170: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000173: DW_AT_byte_size 0x4 000174: DW_AT_bit_size 0x1 000175: DW_AT_bit_offset 0x1 000176: 33 = 0xd (DW_TAG_member) 000177: DW_AT_name N 000179: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00017e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000181: DW_AT_byte_size 0x4 000182: DW_AT_bit_size 0x1 000183: DW_AT_bit_offset 0x0 000184: 0 null 000185: 83 = 0x17 (DW_TAG_union_type) 000186: DW_AT_sibling 0x198 000188: DW_AT_byte_size 0x4 000189: 31 = 0xd (DW_TAG_member) 00018a: DW_AT_name b 00018c: DW_AT_type indirect DW_FORM_ref2 0xfd 00018f: 31 = 0xd (DW_TAG_member) 000190: DW_AT_name w 000192: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000197: 0 null 000198: 80 = 0x16 (DW_TAG_typedef) 000199: DW_AT_name APSR_Type 0001a3: DW_AT_type indirect DW_FORM_ref2 0x185 0001a6: DW_AT_decl_file 0x1 0001a7: DW_AT_decl_line 0x151 0001a9: DW_AT_decl_column 0x3 0001aa: 42 = 0x13 (DW_TAG_structure_type) 0001ab: DW_AT_sibling 0x1d6 0001ad: DW_AT_byte_size 0x4 0001ae: 33 = 0xd (DW_TAG_member) 0001af: DW_AT_name ISR 0001b3: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001b8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0001bb: DW_AT_byte_size 0x4 0001bc: DW_AT_bit_size 0x9 0001bd: DW_AT_bit_offset 0x17 0001be: 33 = 0xd (DW_TAG_member) 0001bf: DW_AT_name _reserved0 0001ca: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001cf: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0001d2: DW_AT_byte_size 0x4 0001d3: DW_AT_bit_size 0x17 0001d4: DW_AT_bit_offset 0x0 0001d5: 0 null 0001d6: 83 = 0x17 (DW_TAG_union_type) 0001d7: DW_AT_sibling 0x1e9 0001d9: DW_AT_byte_size 0x4 0001da: 31 = 0xd (DW_TAG_member) 0001db: DW_AT_name b 0001dd: DW_AT_type indirect DW_FORM_ref2 0x1aa 0001e0: 31 = 0xd (DW_TAG_member) 0001e1: DW_AT_name w 0001e3: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001e8: 0 null 0001e9: 80 = 0x16 (DW_TAG_typedef) 0001ea: DW_AT_name IPSR_Type 0001f4: DW_AT_type indirect DW_FORM_ref2 0x1d6 0001f7: DW_AT_decl_file 0x1 0001f8: DW_AT_decl_line 0x172 0001fa: DW_AT_decl_column 0x3 0001fb: 42 = 0x13 (DW_TAG_structure_type) 0001fc: DW_AT_sibling 0x2b0 0001fe: DW_AT_byte_size 0x4 0001ff: 33 = 0xd (DW_TAG_member) 000200: DW_AT_name ISR 000204: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000209: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00020c: DW_AT_byte_size 0x4 00020d: DW_AT_bit_size 0x9 00020e: DW_AT_bit_offset 0x17 00020f: 33 = 0xd (DW_TAG_member) 000210: DW_AT_name _reserved0 00021b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000220: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000223: DW_AT_byte_size 0x4 000224: DW_AT_bit_size 0x7 000225: DW_AT_bit_offset 0x10 000226: 33 = 0xd (DW_TAG_member) 000227: DW_AT_name GE 00022a: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00022f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000232: DW_AT_byte_size 0x4 000233: DW_AT_bit_size 0x4 000234: DW_AT_bit_offset 0xc 000235: 33 = 0xd (DW_TAG_member) 000236: DW_AT_name _reserved1 000241: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000246: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000249: DW_AT_byte_size 0x4 00024a: DW_AT_bit_size 0x4 00024b: DW_AT_bit_offset 0x8 00024c: 33 = 0xd (DW_TAG_member) 00024d: DW_AT_name T 00024f: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000254: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000257: DW_AT_byte_size 0x4 000258: DW_AT_bit_size 0x1 000259: DW_AT_bit_offset 0x7 00025a: 33 = 0xd (DW_TAG_member) 00025b: DW_AT_name IT 00025e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000263: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000266: DW_AT_byte_size 0x4 000267: DW_AT_bit_size 0x2 000268: DW_AT_bit_offset 0x5 000269: 33 = 0xd (DW_TAG_member) 00026a: DW_AT_name Q 00026c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000271: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000274: DW_AT_byte_size 0x4 000275: DW_AT_bit_size 0x1 000276: DW_AT_bit_offset 0x4 000277: 33 = 0xd (DW_TAG_member) 000278: DW_AT_name V 00027a: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00027f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000282: DW_AT_byte_size 0x4 000283: DW_AT_bit_size 0x1 000284: DW_AT_bit_offset 0x3 000285: 33 = 0xd (DW_TAG_member) 000286: DW_AT_name C 000288: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00028d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000290: DW_AT_byte_size 0x4 000291: DW_AT_bit_size 0x1 000292: DW_AT_bit_offset 0x2 000293: 33 = 0xd (DW_TAG_member) 000294: DW_AT_name Z 000296: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00029b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00029e: DW_AT_byte_size 0x4 00029f: DW_AT_bit_size 0x1 0002a0: DW_AT_bit_offset 0x1 0002a1: 33 = 0xd (DW_TAG_member) 0002a2: DW_AT_name N 0002a4: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002a9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0002ac: DW_AT_byte_size 0x4 0002ad: DW_AT_bit_size 0x1 0002ae: DW_AT_bit_offset 0x0 0002af: 0 null 0002b0: 83 = 0x17 (DW_TAG_union_type) 0002b1: DW_AT_sibling 0x2c3 0002b3: DW_AT_byte_size 0x4 0002b4: 31 = 0xd (DW_TAG_member) 0002b5: DW_AT_name b 0002b7: DW_AT_type indirect DW_FORM_ref2 0x1fb 0002ba: 31 = 0xd (DW_TAG_member) 0002bb: DW_AT_name w 0002bd: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002c2: 0 null 0002c3: 80 = 0x16 (DW_TAG_typedef) 0002c4: DW_AT_name xPSR_Type 0002ce: DW_AT_type indirect DW_FORM_ref2 0x2b0 0002d1: DW_AT_decl_file 0x1 0002d2: DW_AT_decl_line 0x18d 0002d4: DW_AT_decl_column 0x3 0002d5: 42 = 0x13 (DW_TAG_structure_type) 0002d6: DW_AT_sibling 0x326 0002d8: DW_AT_byte_size 0x4 0002d9: 33 = 0xd (DW_TAG_member) 0002da: DW_AT_name nPRIV 0002e0: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002e5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0002e8: DW_AT_byte_size 0x4 0002e9: DW_AT_bit_size 0x1 0002ea: DW_AT_bit_offset 0x1f 0002eb: 33 = 0xd (DW_TAG_member) 0002ec: DW_AT_name SPSEL 0002f2: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002f7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0002fa: DW_AT_byte_size 0x4 0002fb: DW_AT_bit_size 0x1 0002fc: DW_AT_bit_offset 0x1e 0002fd: 33 = 0xd (DW_TAG_member) 0002fe: DW_AT_name FPCA 000303: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000308: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00030b: DW_AT_byte_size 0x4 00030c: DW_AT_bit_size 0x1 00030d: DW_AT_bit_offset 0x1d 00030e: 33 = 0xd (DW_TAG_member) 00030f: DW_AT_name _reserved0 00031a: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00031f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000322: DW_AT_byte_size 0x4 000323: DW_AT_bit_size 0x1d 000324: DW_AT_bit_offset 0x0 000325: 0 null 000326: 83 = 0x17 (DW_TAG_union_type) 000327: DW_AT_sibling 0x339 000329: DW_AT_byte_size 0x4 00032a: 31 = 0xd (DW_TAG_member) 00032b: DW_AT_name b 00032d: DW_AT_type indirect DW_FORM_ref2 0x2d5 000330: 31 = 0xd (DW_TAG_member) 000331: DW_AT_name w 000333: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000338: 0 null 000339: 80 = 0x16 (DW_TAG_typedef) 00033a: DW_AT_name CONTROL_Type 000347: DW_AT_type indirect DW_FORM_ref2 0x326 00034a: DW_AT_decl_file 0x1 00034b: DW_AT_decl_line 0x1b9 00034d: DW_AT_decl_column 0x3 00034e: 42 = 0x13 (DW_TAG_structure_type) 00034f: DW_AT_sibling 0x490 000351: DW_AT_byte_size 0xe04 000353: 3 = 0x1 (DW_TAG_array_type) 000354: DW_AT_sibling 0x35c 000356: DW_AT_type indirect DW_FORM_ref2 0x490 000359: 1 = 0x21 (DW_TAG_subrange_type) 00035a: DW_AT_upper_bound 0x7 00035b: 0 null 00035c: 30 = 0xd (DW_TAG_member) 00035d: DW_AT_name ISER 000362: DW_AT_type indirect DW_FORM_ref2 0x353 000365: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000368: 3 = 0x1 (DW_TAG_array_type) 000369: DW_AT_sibling 0x373 00036b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000370: 1 = 0x21 (DW_TAG_subrange_type) 000371: DW_AT_upper_bound 0x17 000372: 0 null 000373: 30 = 0xd (DW_TAG_member) 000374: DW_AT_name RESERVED0 00037e: DW_AT_type indirect DW_FORM_ref2 0x368 000381: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 000384: 3 = 0x1 (DW_TAG_array_type) 000385: DW_AT_sibling 0x38d 000387: DW_AT_type indirect DW_FORM_ref2 0x490 00038a: 1 = 0x21 (DW_TAG_subrange_type) 00038b: DW_AT_upper_bound 0x7 00038c: 0 null 00038d: 30 = 0xd (DW_TAG_member) 00038e: DW_AT_name ICER 000393: DW_AT_type indirect DW_FORM_ref2 0x384 000396: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 128 } 00039a: 3 = 0x1 (DW_TAG_array_type) 00039b: DW_AT_sibling 0x3a5 00039d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003a2: 1 = 0x21 (DW_TAG_subrange_type) 0003a3: DW_AT_upper_bound 0x17 0003a4: 0 null 0003a5: 30 = 0xd (DW_TAG_member) 0003a6: DW_AT_name RSERVED1 0003af: DW_AT_type indirect DW_FORM_ref2 0x39a 0003b2: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 160 } 0003b6: 3 = 0x1 (DW_TAG_array_type) 0003b7: DW_AT_sibling 0x3bf 0003b9: DW_AT_type indirect DW_FORM_ref2 0x490 0003bc: 1 = 0x21 (DW_TAG_subrange_type) 0003bd: DW_AT_upper_bound 0x7 0003be: 0 null 0003bf: 30 = 0xd (DW_TAG_member) 0003c0: DW_AT_name ISPR 0003c5: DW_AT_type indirect DW_FORM_ref2 0x3b6 0003c8: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 256 } 0003cc: 3 = 0x1 (DW_TAG_array_type) 0003cd: DW_AT_sibling 0x3d7 0003cf: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003d4: 1 = 0x21 (DW_TAG_subrange_type) 0003d5: DW_AT_upper_bound 0x17 0003d6: 0 null 0003d7: 30 = 0xd (DW_TAG_member) 0003d8: DW_AT_name RESERVED2 0003e2: DW_AT_type indirect DW_FORM_ref2 0x3cc 0003e5: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 288 } 0003e9: 3 = 0x1 (DW_TAG_array_type) 0003ea: DW_AT_sibling 0x3f2 0003ec: DW_AT_type indirect DW_FORM_ref2 0x490 0003ef: 1 = 0x21 (DW_TAG_subrange_type) 0003f0: DW_AT_upper_bound 0x7 0003f1: 0 null 0003f2: 30 = 0xd (DW_TAG_member) 0003f3: DW_AT_name ICPR 0003f8: DW_AT_type indirect DW_FORM_ref2 0x3e9 0003fb: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 384 } 0003ff: 3 = 0x1 (DW_TAG_array_type) 000400: DW_AT_sibling 0x40a 000402: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000407: 1 = 0x21 (DW_TAG_subrange_type) 000408: DW_AT_upper_bound 0x17 000409: 0 null 00040a: 30 = 0xd (DW_TAG_member) 00040b: DW_AT_name RESERVED3 000415: DW_AT_type indirect DW_FORM_ref2 0x3ff 000418: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 416 } 00041c: 3 = 0x1 (DW_TAG_array_type) 00041d: DW_AT_sibling 0x425 00041f: DW_AT_type indirect DW_FORM_ref2 0x490 000422: 1 = 0x21 (DW_TAG_subrange_type) 000423: DW_AT_upper_bound 0x7 000424: 0 null 000425: 30 = 0xd (DW_TAG_member) 000426: DW_AT_name IABR 00042b: DW_AT_type indirect DW_FORM_ref2 0x41c 00042e: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 512 } 000432: 3 = 0x1 (DW_TAG_array_type) 000433: DW_AT_sibling 0x43d 000435: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00043a: 1 = 0x21 (DW_TAG_subrange_type) 00043b: DW_AT_upper_bound 0x37 00043c: 0 null 00043d: 30 = 0xd (DW_TAG_member) 00043e: DW_AT_name RESERVED4 000448: DW_AT_type indirect DW_FORM_ref2 0x432 00044b: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 544 } 00044f: 3 = 0x1 (DW_TAG_array_type) 000450: DW_AT_sibling 0x459 000452: DW_AT_type indirect DW_FORM_ref2 0x496 000455: 1 = 0x21 (DW_TAG_subrange_type) 000456: DW_AT_upper_bound 0xef 000458: 0 null 000459: 30 = 0xd (DW_TAG_member) 00045a: DW_AT_name IP 00045d: DW_AT_type indirect DW_FORM_ref2 0x44f 000460: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 768 } 000464: 3 = 0x1 (DW_TAG_array_type) 000465: DW_AT_sibling 0x470 000467: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00046c: 1 = 0x21 (DW_TAG_subrange_type) 00046d: DW_AT_upper_bound 0x283 00046f: 0 null 000470: 30 = 0xd (DW_TAG_member) 000471: DW_AT_name RESERVED5 00047b: DW_AT_type indirect DW_FORM_ref2 0x464 00047e: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 1008 } 000482: 30 = 0xd (DW_TAG_member) 000483: DW_AT_name STIR 000488: DW_AT_type indirect DW_FORM_ref2 0x490 00048b: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 3584 } 00048f: 0 null 000490: 116 = 0x35 (DW_TAG_volatile_type) 000491: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000496: 116 = 0x35 (DW_TAG_volatile_type) 000497: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00049c: 80 = 0x16 (DW_TAG_typedef) 00049d: DW_AT_name NVIC_Type 0004a7: DW_AT_type indirect DW_FORM_ref2 0x34e 0004aa: DW_AT_decl_file 0x1 0004ab: DW_AT_decl_line 0x1e1 0004ad: DW_AT_decl_column 0x4 0004ae: 42 = 0x13 (DW_TAG_structure_type) 0004af: DW_AT_sibling 0x7f1 0004b1: DW_AT_byte_size 0x2ac 0004b3: 30 = 0xd (DW_TAG_member) 0004b4: DW_AT_name CPUID 0004ba: DW_AT_type indirect DW_FORM_ref2 0x7f7 0004bd: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0004c0: 30 = 0xd (DW_TAG_member) 0004c1: DW_AT_name ICSR 0004c6: DW_AT_type indirect DW_FORM_ref2 0x490 0004c9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0004cc: 30 = 0xd (DW_TAG_member) 0004cd: DW_AT_name VTOR 0004d2: DW_AT_type indirect DW_FORM_ref2 0x490 0004d5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0004d8: 30 = 0xd (DW_TAG_member) 0004d9: DW_AT_name AIRCR 0004df: DW_AT_type indirect DW_FORM_ref2 0x490 0004e2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0004e5: 30 = 0xd (DW_TAG_member) 0004e6: DW_AT_name SCR 0004ea: DW_AT_type indirect DW_FORM_ref2 0x490 0004ed: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 0004f0: 30 = 0xd (DW_TAG_member) 0004f1: DW_AT_name CCR 0004f5: DW_AT_type indirect DW_FORM_ref2 0x490 0004f8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 0004fb: 3 = 0x1 (DW_TAG_array_type) 0004fc: DW_AT_sibling 0x504 0004fe: DW_AT_type indirect DW_FORM_ref2 0x496 000501: 1 = 0x21 (DW_TAG_subrange_type) 000502: DW_AT_upper_bound 0xb 000503: 0 null 000504: 30 = 0xd (DW_TAG_member) 000505: DW_AT_name SHPR 00050a: DW_AT_type indirect DW_FORM_ref2 0x4fb 00050d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 000510: 30 = 0xd (DW_TAG_member) 000511: DW_AT_name SHCSR 000517: DW_AT_type indirect DW_FORM_ref2 0x490 00051a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 00051d: 30 = 0xd (DW_TAG_member) 00051e: DW_AT_name CFSR 000523: DW_AT_type indirect DW_FORM_ref2 0x490 000526: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 000529: 30 = 0xd (DW_TAG_member) 00052a: DW_AT_name HFSR 00052f: DW_AT_type indirect DW_FORM_ref2 0x490 000532: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 000535: 30 = 0xd (DW_TAG_member) 000536: DW_AT_name DFSR 00053b: DW_AT_type indirect DW_FORM_ref2 0x490 00053e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 000541: 30 = 0xd (DW_TAG_member) 000542: DW_AT_name MMFAR 000548: DW_AT_type indirect DW_FORM_ref2 0x490 00054b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 00054e: 30 = 0xd (DW_TAG_member) 00054f: DW_AT_name BFAR 000554: DW_AT_type indirect DW_FORM_ref2 0x490 000557: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 00055a: 30 = 0xd (DW_TAG_member) 00055b: DW_AT_name AFSR 000560: DW_AT_type indirect DW_FORM_ref2 0x490 000563: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 60 } 000566: 3 = 0x1 (DW_TAG_array_type) 000567: DW_AT_sibling 0x56f 000569: DW_AT_type indirect DW_FORM_ref2 0x7f7 00056c: 1 = 0x21 (DW_TAG_subrange_type) 00056d: DW_AT_upper_bound 0x1 00056e: 0 null 00056f: 30 = 0xd (DW_TAG_member) 000570: DW_AT_name ID_PFR 000577: DW_AT_type indirect DW_FORM_ref2 0x566 00057a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 64 } 00057d: 30 = 0xd (DW_TAG_member) 00057e: DW_AT_name ID_DFR 000585: DW_AT_type indirect DW_FORM_ref2 0x7f7 000588: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 72 } 00058b: 30 = 0xd (DW_TAG_member) 00058c: DW_AT_name ID_AFR 000593: DW_AT_type indirect DW_FORM_ref2 0x7f7 000596: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 76 } 000599: 3 = 0x1 (DW_TAG_array_type) 00059a: DW_AT_sibling 0x5a2 00059c: DW_AT_type indirect DW_FORM_ref2 0x7f7 00059f: 1 = 0x21 (DW_TAG_subrange_type) 0005a0: DW_AT_upper_bound 0x3 0005a1: 0 null 0005a2: 30 = 0xd (DW_TAG_member) 0005a3: DW_AT_name ID_MFR 0005aa: DW_AT_type indirect DW_FORM_ref2 0x599 0005ad: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 80 } 0005b0: 3 = 0x1 (DW_TAG_array_type) 0005b1: DW_AT_sibling 0x5b9 0005b3: DW_AT_type indirect DW_FORM_ref2 0x7f7 0005b6: 1 = 0x21 (DW_TAG_subrange_type) 0005b7: DW_AT_upper_bound 0x4 0005b8: 0 null 0005b9: 30 = 0xd (DW_TAG_member) 0005ba: DW_AT_name ID_ISAR 0005c2: DW_AT_type indirect DW_FORM_ref2 0x5b0 0005c5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 96 } 0005c8: 3 = 0x1 (DW_TAG_array_type) 0005c9: DW_AT_sibling 0x5d3 0005cb: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0005d0: 1 = 0x21 (DW_TAG_subrange_type) 0005d1: DW_AT_upper_bound 0x0 0005d2: 0 null 0005d3: 30 = 0xd (DW_TAG_member) 0005d4: DW_AT_name RESERVED0 0005de: DW_AT_type indirect DW_FORM_ref2 0x5c8 0005e1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 116 } 0005e4: 30 = 0xd (DW_TAG_member) 0005e5: DW_AT_name CLIDR 0005eb: DW_AT_type indirect DW_FORM_ref2 0x7f7 0005ee: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 120 } 0005f1: 30 = 0xd (DW_TAG_member) 0005f2: DW_AT_name CTR 0005f6: DW_AT_type indirect DW_FORM_ref2 0x7f7 0005f9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 124 } 0005fc: 30 = 0xd (DW_TAG_member) 0005fd: DW_AT_name CCSIDR 000604: DW_AT_type indirect DW_FORM_ref2 0x7f7 000607: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 128 } 00060b: 30 = 0xd (DW_TAG_member) 00060c: DW_AT_name CSSELR 000613: DW_AT_type indirect DW_FORM_ref2 0x490 000616: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 132 } 00061a: 30 = 0xd (DW_TAG_member) 00061b: DW_AT_name CPACR 000621: DW_AT_type indirect DW_FORM_ref2 0x490 000624: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 136 } 000628: 3 = 0x1 (DW_TAG_array_type) 000629: DW_AT_sibling 0x633 00062b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000630: 1 = 0x21 (DW_TAG_subrange_type) 000631: DW_AT_upper_bound 0x5c 000632: 0 null 000633: 30 = 0xd (DW_TAG_member) 000634: DW_AT_name RESERVED3 00063e: DW_AT_type indirect DW_FORM_ref2 0x628 000641: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 140 } 000645: 30 = 0xd (DW_TAG_member) 000646: DW_AT_name STIR 00064b: DW_AT_type indirect DW_FORM_ref2 0x490 00064e: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 512 } 000652: 3 = 0x1 (DW_TAG_array_type) 000653: DW_AT_sibling 0x65d 000655: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00065a: 1 = 0x21 (DW_TAG_subrange_type) 00065b: DW_AT_upper_bound 0xe 00065c: 0 null 00065d: 30 = 0xd (DW_TAG_member) 00065e: DW_AT_name RESERVED4 000668: DW_AT_type indirect DW_FORM_ref2 0x652 00066b: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 516 } 00066f: 30 = 0xd (DW_TAG_member) 000670: DW_AT_name MVFR0 000676: DW_AT_type indirect DW_FORM_ref2 0x7f7 000679: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 576 } 00067d: 30 = 0xd (DW_TAG_member) 00067e: DW_AT_name MVFR1 000684: DW_AT_type indirect DW_FORM_ref2 0x7f7 000687: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 580 } 00068b: 30 = 0xd (DW_TAG_member) 00068c: DW_AT_name MVFR2 000692: DW_AT_type indirect DW_FORM_ref2 0x7f7 000695: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 584 } 000699: 3 = 0x1 (DW_TAG_array_type) 00069a: DW_AT_sibling 0x6a4 00069c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0006a1: 1 = 0x21 (DW_TAG_subrange_type) 0006a2: DW_AT_upper_bound 0x0 0006a3: 0 null 0006a4: 30 = 0xd (DW_TAG_member) 0006a5: DW_AT_name RESERVED5 0006af: DW_AT_type indirect DW_FORM_ref2 0x699 0006b2: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 588 } 0006b6: 30 = 0xd (DW_TAG_member) 0006b7: DW_AT_name ICIALLU 0006bf: DW_AT_type indirect DW_FORM_ref2 0x490 0006c2: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 592 } 0006c6: 3 = 0x1 (DW_TAG_array_type) 0006c7: DW_AT_sibling 0x6d1 0006c9: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0006ce: 1 = 0x21 (DW_TAG_subrange_type) 0006cf: DW_AT_upper_bound 0x0 0006d0: 0 null 0006d1: 30 = 0xd (DW_TAG_member) 0006d2: DW_AT_name RESERVED6 0006dc: DW_AT_type indirect DW_FORM_ref2 0x6c6 0006df: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 596 } 0006e3: 30 = 0xd (DW_TAG_member) 0006e4: DW_AT_name ICIMVAU 0006ec: DW_AT_type indirect DW_FORM_ref2 0x490 0006ef: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 600 } 0006f3: 30 = 0xd (DW_TAG_member) 0006f4: DW_AT_name DCIMVAC 0006fc: DW_AT_type indirect DW_FORM_ref2 0x490 0006ff: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 604 } 000703: 30 = 0xd (DW_TAG_member) 000704: DW_AT_name DCISW 00070a: DW_AT_type indirect DW_FORM_ref2 0x490 00070d: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 608 } 000711: 30 = 0xd (DW_TAG_member) 000712: DW_AT_name DCCMVAU 00071a: DW_AT_type indirect DW_FORM_ref2 0x490 00071d: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 612 } 000721: 30 = 0xd (DW_TAG_member) 000722: DW_AT_name DCCMVAC 00072a: DW_AT_type indirect DW_FORM_ref2 0x490 00072d: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 616 } 000731: 30 = 0xd (DW_TAG_member) 000732: DW_AT_name DCCSW 000738: DW_AT_type indirect DW_FORM_ref2 0x490 00073b: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 620 } 00073f: 30 = 0xd (DW_TAG_member) 000740: DW_AT_name DCCIMVAC 000749: DW_AT_type indirect DW_FORM_ref2 0x490 00074c: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 624 } 000750: 30 = 0xd (DW_TAG_member) 000751: DW_AT_name DCCISW 000758: DW_AT_type indirect DW_FORM_ref2 0x490 00075b: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 628 } 00075f: 3 = 0x1 (DW_TAG_array_type) 000760: DW_AT_sibling 0x76a 000762: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000767: 1 = 0x21 (DW_TAG_subrange_type) 000768: DW_AT_upper_bound 0x5 000769: 0 null 00076a: 30 = 0xd (DW_TAG_member) 00076b: DW_AT_name RESERVED7 000775: DW_AT_type indirect DW_FORM_ref2 0x75f 000778: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 632 } 00077c: 30 = 0xd (DW_TAG_member) 00077d: DW_AT_name ITCMCR 000784: DW_AT_type indirect DW_FORM_ref2 0x490 000787: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 656 } 00078b: 30 = 0xd (DW_TAG_member) 00078c: DW_AT_name DTCMCR 000793: DW_AT_type indirect DW_FORM_ref2 0x490 000796: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 660 } 00079a: 30 = 0xd (DW_TAG_member) 00079b: DW_AT_name AHBPCR 0007a2: DW_AT_type indirect DW_FORM_ref2 0x490 0007a5: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 664 } 0007a9: 30 = 0xd (DW_TAG_member) 0007aa: DW_AT_name CACR 0007af: DW_AT_type indirect DW_FORM_ref2 0x490 0007b2: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 668 } 0007b6: 30 = 0xd (DW_TAG_member) 0007b7: DW_AT_name AHBSCR 0007be: DW_AT_type indirect DW_FORM_ref2 0x490 0007c1: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 672 } 0007c5: 3 = 0x1 (DW_TAG_array_type) 0007c6: DW_AT_sibling 0x7d0 0007c8: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0007cd: 1 = 0x21 (DW_TAG_subrange_type) 0007ce: DW_AT_upper_bound 0x0 0007cf: 0 null 0007d0: 30 = 0xd (DW_TAG_member) 0007d1: DW_AT_name RESERVED8 0007db: DW_AT_type indirect DW_FORM_ref2 0x7c5 0007de: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 676 } 0007e2: 30 = 0xd (DW_TAG_member) 0007e3: DW_AT_name ABFSR 0007e9: DW_AT_type indirect DW_FORM_ref2 0x490 0007ec: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 680 } 0007f0: 0 null 0007f1: 17 = 0x26 (DW_TAG_const_type) 0007f2: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0007f7: 116 = 0x35 (DW_TAG_volatile_type) 0007f8: DW_AT_type indirect DW_FORM_ref2 0x7f1 0007fb: 80 = 0x16 (DW_TAG_typedef) 0007fc: DW_AT_name SCB_Type 000805: DW_AT_type indirect DW_FORM_ref2 0x4ae 000808: DW_AT_decl_file 0x1 000809: DW_AT_decl_line 0x228 00080b: DW_AT_decl_column 0x3 00080c: 42 = 0x13 (DW_TAG_structure_type) 00080d: DW_AT_sibling 0x846 00080f: DW_AT_byte_size 0xc 000810: 3 = 0x1 (DW_TAG_array_type) 000811: DW_AT_sibling 0x81b 000813: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000818: 1 = 0x21 (DW_TAG_subrange_type) 000819: DW_AT_upper_bound 0x0 00081a: 0 null 00081b: 30 = 0xd (DW_TAG_member) 00081c: DW_AT_name RESERVED0 000826: DW_AT_type indirect DW_FORM_ref2 0x810 000829: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00082c: 30 = 0xd (DW_TAG_member) 00082d: DW_AT_name ICTR 000832: DW_AT_type indirect DW_FORM_ref2 0x7f7 000835: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000838: 30 = 0xd (DW_TAG_member) 000839: DW_AT_name ACTLR 00083f: DW_AT_type indirect DW_FORM_ref2 0x490 000842: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000845: 0 null 000846: 80 = 0x16 (DW_TAG_typedef) 000847: DW_AT_name SCnSCB_Type 000853: DW_AT_type indirect DW_FORM_ref2 0x80c 000856: DW_AT_decl_file 0x1 000857: DW_AT_decl_line 0x38f 000859: DW_AT_decl_column 0x3 00085a: 42 = 0x13 (DW_TAG_structure_type) 00085b: DW_AT_sibling 0x88f 00085d: DW_AT_byte_size 0x10 00085e: 30 = 0xd (DW_TAG_member) 00085f: DW_AT_name CTRL 000864: DW_AT_type indirect DW_FORM_ref2 0x490 000867: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00086a: 30 = 0xd (DW_TAG_member) 00086b: DW_AT_name LOAD 000870: DW_AT_type indirect DW_FORM_ref2 0x490 000873: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000876: 30 = 0xd (DW_TAG_member) 000877: DW_AT_name VAL 00087b: DW_AT_type indirect DW_FORM_ref2 0x490 00087e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000881: 30 = 0xd (DW_TAG_member) 000882: DW_AT_name CALIB 000888: DW_AT_type indirect DW_FORM_ref2 0x7f7 00088b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00088e: 0 null 00088f: 80 = 0x16 (DW_TAG_typedef) 000890: DW_AT_name SysTick_Type 00089d: DW_AT_type indirect DW_FORM_ref2 0x85a 0008a0: DW_AT_decl_file 0x1 0008a1: DW_AT_decl_line 0x3b8 0008a3: DW_AT_decl_column 0x3 0008a4: 83 = 0x17 (DW_TAG_union_type) 0008a5: DW_AT_sibling 0x8c0 0008a7: DW_AT_byte_size 0x4 0008a8: 31 = 0xd (DW_TAG_member) 0008a9: DW_AT_name u8 0008ac: DW_AT_type indirect DW_FORM_ref2 0x496 0008af: 31 = 0xd (DW_TAG_member) 0008b0: DW_AT_name u16 0008b4: DW_AT_type indirect DW_FORM_ref2 0x8c0 0008b7: 31 = 0xd (DW_TAG_member) 0008b8: DW_AT_name u32 0008bc: DW_AT_type indirect DW_FORM_ref2 0x490 0008bf: 0 null 0008c0: 116 = 0x35 (DW_TAG_volatile_type) 0008c1: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0008c6: 42 = 0x13 (DW_TAG_structure_type) 0008c7: DW_AT_sibling 0xa8d 0008c9: DW_AT_byte_size 0x1000 0008cb: 3 = 0x1 (DW_TAG_array_type) 0008cc: DW_AT_sibling 0x8d4 0008ce: DW_AT_type indirect DW_FORM_ref2 0xa8d 0008d1: 1 = 0x21 (DW_TAG_subrange_type) 0008d2: DW_AT_upper_bound 0x1f 0008d3: 0 null 0008d4: 30 = 0xd (DW_TAG_member) 0008d5: DW_AT_name PORT 0008da: DW_AT_type indirect DW_FORM_ref2 0x8cb 0008dd: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0008e0: 3 = 0x1 (DW_TAG_array_type) 0008e1: DW_AT_sibling 0x8ec 0008e3: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0008e8: 1 = 0x21 (DW_TAG_subrange_type) 0008e9: DW_AT_upper_bound 0x35f 0008eb: 0 null 0008ec: 30 = 0xd (DW_TAG_member) 0008ed: DW_AT_name RESERVED0 0008f7: DW_AT_type indirect DW_FORM_ref2 0x8e0 0008fa: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 128 } 0008fe: 30 = 0xd (DW_TAG_member) 0008ff: DW_AT_name TER 000903: DW_AT_type indirect DW_FORM_ref2 0x490 000906: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 3584 } 00090a: 3 = 0x1 (DW_TAG_array_type) 00090b: DW_AT_sibling 0x915 00090d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000912: 1 = 0x21 (DW_TAG_subrange_type) 000913: DW_AT_upper_bound 0xe 000914: 0 null 000915: 30 = 0xd (DW_TAG_member) 000916: DW_AT_name RESERVED1 000920: DW_AT_type indirect DW_FORM_ref2 0x90a 000923: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 3588 } 000927: 30 = 0xd (DW_TAG_member) 000928: DW_AT_name TPR 00092c: DW_AT_type indirect DW_FORM_ref2 0x490 00092f: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 3648 } 000933: 3 = 0x1 (DW_TAG_array_type) 000934: DW_AT_sibling 0x93e 000936: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00093b: 1 = 0x21 (DW_TAG_subrange_type) 00093c: DW_AT_upper_bound 0xe 00093d: 0 null 00093e: 30 = 0xd (DW_TAG_member) 00093f: DW_AT_name RESERVED2 000949: DW_AT_type indirect DW_FORM_ref2 0x933 00094c: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 3652 } 000950: 30 = 0xd (DW_TAG_member) 000951: DW_AT_name TCR 000955: DW_AT_type indirect DW_FORM_ref2 0x490 000958: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 3712 } 00095c: 3 = 0x1 (DW_TAG_array_type) 00095d: DW_AT_sibling 0x967 00095f: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000964: 1 = 0x21 (DW_TAG_subrange_type) 000965: DW_AT_upper_bound 0x1c 000966: 0 null 000967: 30 = 0xd (DW_TAG_member) 000968: DW_AT_name RESERVED3 000972: DW_AT_type indirect DW_FORM_ref2 0x95c 000975: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 3716 } 000979: 30 = 0xd (DW_TAG_member) 00097a: DW_AT_name IWR 00097e: DW_AT_type indirect DW_FORM_ref2 0x490 000981: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 3832 } 000985: 30 = 0xd (DW_TAG_member) 000986: DW_AT_name IRR 00098a: DW_AT_type indirect DW_FORM_ref2 0x7f7 00098d: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 3836 } 000991: 30 = 0xd (DW_TAG_member) 000992: DW_AT_name IMCR 000997: DW_AT_type indirect DW_FORM_ref2 0x490 00099a: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 3840 } 00099e: 3 = 0x1 (DW_TAG_array_type) 00099f: DW_AT_sibling 0x9a9 0009a1: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0009a6: 1 = 0x21 (DW_TAG_subrange_type) 0009a7: DW_AT_upper_bound 0x2a 0009a8: 0 null 0009a9: 30 = 0xd (DW_TAG_member) 0009aa: DW_AT_name RESERVED4 0009b4: DW_AT_type indirect DW_FORM_ref2 0x99e 0009b7: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 3844 } 0009bb: 30 = 0xd (DW_TAG_member) 0009bc: DW_AT_name LAR 0009c0: DW_AT_type indirect DW_FORM_ref2 0x490 0009c3: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4016 } 0009c7: 30 = 0xd (DW_TAG_member) 0009c8: DW_AT_name LSR 0009cc: DW_AT_type indirect DW_FORM_ref2 0x7f7 0009cf: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4020 } 0009d3: 3 = 0x1 (DW_TAG_array_type) 0009d4: DW_AT_sibling 0x9de 0009d6: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0009db: 1 = 0x21 (DW_TAG_subrange_type) 0009dc: DW_AT_upper_bound 0x5 0009dd: 0 null 0009de: 30 = 0xd (DW_TAG_member) 0009df: DW_AT_name RESERVED5 0009e9: DW_AT_type indirect DW_FORM_ref2 0x9d3 0009ec: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4024 } 0009f0: 30 = 0xd (DW_TAG_member) 0009f1: DW_AT_name PID4 0009f6: DW_AT_type indirect DW_FORM_ref2 0x7f7 0009f9: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4048 } 0009fd: 30 = 0xd (DW_TAG_member) 0009fe: DW_AT_name PID5 000a03: DW_AT_type indirect DW_FORM_ref2 0x7f7 000a06: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4052 } 000a0a: 30 = 0xd (DW_TAG_member) 000a0b: DW_AT_name PID6 000a10: DW_AT_type indirect DW_FORM_ref2 0x7f7 000a13: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4056 } 000a17: 30 = 0xd (DW_TAG_member) 000a18: DW_AT_name PID7 000a1d: DW_AT_type indirect DW_FORM_ref2 0x7f7 000a20: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4060 } 000a24: 30 = 0xd (DW_TAG_member) 000a25: DW_AT_name PID0 000a2a: DW_AT_type indirect DW_FORM_ref2 0x7f7 000a2d: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4064 } 000a31: 30 = 0xd (DW_TAG_member) 000a32: DW_AT_name PID1 000a37: DW_AT_type indirect DW_FORM_ref2 0x7f7 000a3a: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4068 } 000a3e: 30 = 0xd (DW_TAG_member) 000a3f: DW_AT_name PID2 000a44: DW_AT_type indirect DW_FORM_ref2 0x7f7 000a47: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4072 } 000a4b: 30 = 0xd (DW_TAG_member) 000a4c: DW_AT_name PID3 000a51: DW_AT_type indirect DW_FORM_ref2 0x7f7 000a54: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4076 } 000a58: 30 = 0xd (DW_TAG_member) 000a59: DW_AT_name CID0 000a5e: DW_AT_type indirect DW_FORM_ref2 0x7f7 000a61: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4080 } 000a65: 30 = 0xd (DW_TAG_member) 000a66: DW_AT_name CID1 000a6b: DW_AT_type indirect DW_FORM_ref2 0x7f7 000a6e: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4084 } 000a72: 30 = 0xd (DW_TAG_member) 000a73: DW_AT_name CID2 000a78: DW_AT_type indirect DW_FORM_ref2 0x7f7 000a7b: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4088 } 000a7f: 30 = 0xd (DW_TAG_member) 000a80: DW_AT_name CID3 000a85: DW_AT_type indirect DW_FORM_ref2 0x7f7 000a88: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4092 } 000a8c: 0 null 000a8d: 116 = 0x35 (DW_TAG_volatile_type) 000a8e: DW_AT_type indirect DW_FORM_ref2 0x8a4 000a91: 80 = 0x16 (DW_TAG_typedef) 000a92: DW_AT_name ITM_Type 000a9b: DW_AT_type indirect DW_FORM_ref2 0x8c6 000a9e: DW_AT_decl_file 0x1 000a9f: DW_AT_decl_line 0x408 000aa1: DW_AT_decl_column 0x3 000aa2: 42 = 0x13 (DW_TAG_structure_type) 000aa3: DW_AT_sibling 0xc4c 000aa5: DW_AT_byte_size 0xfb8 000aa7: 30 = 0xd (DW_TAG_member) 000aa8: DW_AT_name CTRL 000aad: DW_AT_type indirect DW_FORM_ref2 0x490 000ab0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000ab3: 30 = 0xd (DW_TAG_member) 000ab4: DW_AT_name CYCCNT 000abb: DW_AT_type indirect DW_FORM_ref2 0x490 000abe: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000ac1: 30 = 0xd (DW_TAG_member) 000ac2: DW_AT_name CPICNT 000ac9: DW_AT_type indirect DW_FORM_ref2 0x490 000acc: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000acf: 30 = 0xd (DW_TAG_member) 000ad0: DW_AT_name EXCCNT 000ad7: DW_AT_type indirect DW_FORM_ref2 0x490 000ada: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000add: 30 = 0xd (DW_TAG_member) 000ade: DW_AT_name SLEEPCNT 000ae7: DW_AT_type indirect DW_FORM_ref2 0x490 000aea: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000aed: 30 = 0xd (DW_TAG_member) 000aee: DW_AT_name LSUCNT 000af5: DW_AT_type indirect DW_FORM_ref2 0x490 000af8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 000afb: 30 = 0xd (DW_TAG_member) 000afc: DW_AT_name FOLDCNT 000b04: DW_AT_type indirect DW_FORM_ref2 0x490 000b07: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 000b0a: 30 = 0xd (DW_TAG_member) 000b0b: DW_AT_name PCSR 000b10: DW_AT_type indirect DW_FORM_ref2 0x7f7 000b13: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 000b16: 30 = 0xd (DW_TAG_member) 000b17: DW_AT_name COMP0 000b1d: DW_AT_type indirect DW_FORM_ref2 0x490 000b20: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 000b23: 30 = 0xd (DW_TAG_member) 000b24: DW_AT_name MASK0 000b2a: DW_AT_type indirect DW_FORM_ref2 0x490 000b2d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 000b30: 30 = 0xd (DW_TAG_member) 000b31: DW_AT_name FUNCTION0 000b3b: DW_AT_type indirect DW_FORM_ref2 0x490 000b3e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 000b41: 3 = 0x1 (DW_TAG_array_type) 000b42: DW_AT_sibling 0xb4c 000b44: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000b49: 1 = 0x21 (DW_TAG_subrange_type) 000b4a: DW_AT_upper_bound 0x0 000b4b: 0 null 000b4c: 30 = 0xd (DW_TAG_member) 000b4d: DW_AT_name RESERVED0 000b57: DW_AT_type indirect DW_FORM_ref2 0xb41 000b5a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 000b5d: 30 = 0xd (DW_TAG_member) 000b5e: DW_AT_name COMP1 000b64: DW_AT_type indirect DW_FORM_ref2 0x490 000b67: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 000b6a: 30 = 0xd (DW_TAG_member) 000b6b: DW_AT_name MASK1 000b71: DW_AT_type indirect DW_FORM_ref2 0x490 000b74: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 000b77: 30 = 0xd (DW_TAG_member) 000b78: DW_AT_name FUNCTION1 000b82: DW_AT_type indirect DW_FORM_ref2 0x490 000b85: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 000b88: 3 = 0x1 (DW_TAG_array_type) 000b89: DW_AT_sibling 0xb93 000b8b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000b90: 1 = 0x21 (DW_TAG_subrange_type) 000b91: DW_AT_upper_bound 0x0 000b92: 0 null 000b93: 30 = 0xd (DW_TAG_member) 000b94: DW_AT_name RESERVED1 000b9e: DW_AT_type indirect DW_FORM_ref2 0xb88 000ba1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 60 } 000ba4: 30 = 0xd (DW_TAG_member) 000ba5: DW_AT_name COMP2 000bab: DW_AT_type indirect DW_FORM_ref2 0x490 000bae: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 64 } 000bb1: 30 = 0xd (DW_TAG_member) 000bb2: DW_AT_name MASK2 000bb8: DW_AT_type indirect DW_FORM_ref2 0x490 000bbb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 68 } 000bbe: 30 = 0xd (DW_TAG_member) 000bbf: DW_AT_name FUNCTION2 000bc9: DW_AT_type indirect DW_FORM_ref2 0x490 000bcc: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 72 } 000bcf: 3 = 0x1 (DW_TAG_array_type) 000bd0: DW_AT_sibling 0xbda 000bd2: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000bd7: 1 = 0x21 (DW_TAG_subrange_type) 000bd8: DW_AT_upper_bound 0x0 000bd9: 0 null 000bda: 30 = 0xd (DW_TAG_member) 000bdb: DW_AT_name RESERVED2 000be5: DW_AT_type indirect DW_FORM_ref2 0xbcf 000be8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 76 } 000beb: 30 = 0xd (DW_TAG_member) 000bec: DW_AT_name COMP3 000bf2: DW_AT_type indirect DW_FORM_ref2 0x490 000bf5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 80 } 000bf8: 30 = 0xd (DW_TAG_member) 000bf9: DW_AT_name MASK3 000bff: DW_AT_type indirect DW_FORM_ref2 0x490 000c02: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 84 } 000c05: 30 = 0xd (DW_TAG_member) 000c06: DW_AT_name FUNCTION3 000c10: DW_AT_type indirect DW_FORM_ref2 0x490 000c13: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 88 } 000c16: 3 = 0x1 (DW_TAG_array_type) 000c17: DW_AT_sibling 0xc22 000c19: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000c1e: 1 = 0x21 (DW_TAG_subrange_type) 000c1f: DW_AT_upper_bound 0x3d4 000c21: 0 null 000c22: 30 = 0xd (DW_TAG_member) 000c23: DW_AT_name RESERVED3 000c2d: DW_AT_type indirect DW_FORM_ref2 0xc16 000c30: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 92 } 000c33: 30 = 0xd (DW_TAG_member) 000c34: DW_AT_name LAR 000c38: DW_AT_type indirect DW_FORM_ref2 0x490 000c3b: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4016 } 000c3f: 30 = 0xd (DW_TAG_member) 000c40: DW_AT_name LSR 000c44: DW_AT_type indirect DW_FORM_ref2 0x7f7 000c47: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4020 } 000c4b: 0 null 000c4c: 80 = 0x16 (DW_TAG_typedef) 000c4d: DW_AT_name DWT_Type 000c56: DW_AT_type indirect DW_FORM_ref2 0xaa2 000c59: DW_AT_decl_file 0x1 000c5a: DW_AT_decl_line 0x469 000c5c: DW_AT_decl_column 0x3 000c5d: 42 = 0x13 (DW_TAG_structure_type) 000c5e: DW_AT_sibling 0xe27 000c60: DW_AT_byte_size 0xfd0 000c62: 30 = 0xd (DW_TAG_member) 000c63: DW_AT_name SSPSR 000c69: DW_AT_type indirect DW_FORM_ref2 0x490 000c6c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000c6f: 30 = 0xd (DW_TAG_member) 000c70: DW_AT_name CSPSR 000c76: DW_AT_type indirect DW_FORM_ref2 0x490 000c79: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000c7c: 3 = 0x1 (DW_TAG_array_type) 000c7d: DW_AT_sibling 0xc87 000c7f: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000c84: 1 = 0x21 (DW_TAG_subrange_type) 000c85: DW_AT_upper_bound 0x1 000c86: 0 null 000c87: 30 = 0xd (DW_TAG_member) 000c88: DW_AT_name RESERVED0 000c92: DW_AT_type indirect DW_FORM_ref2 0xc7c 000c95: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000c98: 30 = 0xd (DW_TAG_member) 000c99: DW_AT_name ACPR 000c9e: DW_AT_type indirect DW_FORM_ref2 0x490 000ca1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000ca4: 3 = 0x1 (DW_TAG_array_type) 000ca5: DW_AT_sibling 0xcaf 000ca7: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000cac: 1 = 0x21 (DW_TAG_subrange_type) 000cad: DW_AT_upper_bound 0x36 000cae: 0 null 000caf: 30 = 0xd (DW_TAG_member) 000cb0: DW_AT_name RESERVED1 000cba: DW_AT_type indirect DW_FORM_ref2 0xca4 000cbd: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 000cc0: 30 = 0xd (DW_TAG_member) 000cc1: DW_AT_name SPPR 000cc6: DW_AT_type indirect DW_FORM_ref2 0x490 000cc9: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 240 } 000ccd: 3 = 0x1 (DW_TAG_array_type) 000cce: DW_AT_sibling 0xcd9 000cd0: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000cd5: 1 = 0x21 (DW_TAG_subrange_type) 000cd6: DW_AT_upper_bound 0x82 000cd8: 0 null 000cd9: 30 = 0xd (DW_TAG_member) 000cda: DW_AT_name RESERVED2 000ce4: DW_AT_type indirect DW_FORM_ref2 0xccd 000ce7: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 244 } 000ceb: 30 = 0xd (DW_TAG_member) 000cec: DW_AT_name FFSR 000cf1: DW_AT_type indirect DW_FORM_ref2 0x7f7 000cf4: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 768 } 000cf8: 30 = 0xd (DW_TAG_member) 000cf9: DW_AT_name FFCR 000cfe: DW_AT_type indirect DW_FORM_ref2 0x490 000d01: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 772 } 000d05: 30 = 0xd (DW_TAG_member) 000d06: DW_AT_name FSCR 000d0b: DW_AT_type indirect DW_FORM_ref2 0x7f7 000d0e: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 776 } 000d12: 3 = 0x1 (DW_TAG_array_type) 000d13: DW_AT_sibling 0xd1e 000d15: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000d1a: 1 = 0x21 (DW_TAG_subrange_type) 000d1b: DW_AT_upper_bound 0x2f6 000d1d: 0 null 000d1e: 30 = 0xd (DW_TAG_member) 000d1f: DW_AT_name RESERVED3 000d29: DW_AT_type indirect DW_FORM_ref2 0xd12 000d2c: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 780 } 000d30: 30 = 0xd (DW_TAG_member) 000d31: DW_AT_name TRIGGER 000d39: DW_AT_type indirect DW_FORM_ref2 0x7f7 000d3c: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 3816 } 000d40: 30 = 0xd (DW_TAG_member) 000d41: DW_AT_name FIFO0 000d47: DW_AT_type indirect DW_FORM_ref2 0x7f7 000d4a: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 3820 } 000d4e: 30 = 0xd (DW_TAG_member) 000d4f: DW_AT_name ITATBCTR2 000d59: DW_AT_type indirect DW_FORM_ref2 0x7f7 000d5c: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 3824 } 000d60: 3 = 0x1 (DW_TAG_array_type) 000d61: DW_AT_sibling 0xd6b 000d63: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000d68: 1 = 0x21 (DW_TAG_subrange_type) 000d69: DW_AT_upper_bound 0x0 000d6a: 0 null 000d6b: 30 = 0xd (DW_TAG_member) 000d6c: DW_AT_name RESERVED4 000d76: DW_AT_type indirect DW_FORM_ref2 0xd60 000d79: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 3828 } 000d7d: 30 = 0xd (DW_TAG_member) 000d7e: DW_AT_name ITATBCTR0 000d88: DW_AT_type indirect DW_FORM_ref2 0x7f7 000d8b: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 3832 } 000d8f: 30 = 0xd (DW_TAG_member) 000d90: DW_AT_name FIFO1 000d96: DW_AT_type indirect DW_FORM_ref2 0x7f7 000d99: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 3836 } 000d9d: 30 = 0xd (DW_TAG_member) 000d9e: DW_AT_name ITCTRL 000da5: DW_AT_type indirect DW_FORM_ref2 0x490 000da8: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 3840 } 000dac: 3 = 0x1 (DW_TAG_array_type) 000dad: DW_AT_sibling 0xdb7 000daf: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000db4: 1 = 0x21 (DW_TAG_subrange_type) 000db5: DW_AT_upper_bound 0x26 000db6: 0 null 000db7: 30 = 0xd (DW_TAG_member) 000db8: DW_AT_name RESERVED5 000dc2: DW_AT_type indirect DW_FORM_ref2 0xdac 000dc5: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 3844 } 000dc9: 30 = 0xd (DW_TAG_member) 000dca: DW_AT_name CLAIMSET 000dd3: DW_AT_type indirect DW_FORM_ref2 0x490 000dd6: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4000 } 000dda: 30 = 0xd (DW_TAG_member) 000ddb: DW_AT_name CLAIMCLR 000de4: DW_AT_type indirect DW_FORM_ref2 0x490 000de7: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4004 } 000deb: 3 = 0x1 (DW_TAG_array_type) 000dec: DW_AT_sibling 0xdf6 000dee: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000df3: 1 = 0x21 (DW_TAG_subrange_type) 000df4: DW_AT_upper_bound 0x7 000df5: 0 null 000df6: 30 = 0xd (DW_TAG_member) 000df7: DW_AT_name RESERVED7 000e01: DW_AT_type indirect DW_FORM_ref2 0xdeb 000e04: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4008 } 000e08: 30 = 0xd (DW_TAG_member) 000e09: DW_AT_name DEVID 000e0f: DW_AT_type indirect DW_FORM_ref2 0x7f7 000e12: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4040 } 000e16: 30 = 0xd (DW_TAG_member) 000e17: DW_AT_name DEVTYPE 000e1f: DW_AT_type indirect DW_FORM_ref2 0x7f7 000e22: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4044 } 000e26: 0 null 000e27: 80 = 0x16 (DW_TAG_typedef) 000e28: DW_AT_name TPI_Type 000e31: DW_AT_type indirect DW_FORM_ref2 0xc5d 000e34: DW_AT_decl_file 0x1 000e35: DW_AT_decl_line 0x4fd 000e37: DW_AT_decl_column 0x3 000e38: 42 = 0x13 (DW_TAG_structure_type) 000e39: DW_AT_sibling 0xed2 000e3b: DW_AT_byte_size 0x2c 000e3c: 30 = 0xd (DW_TAG_member) 000e3d: DW_AT_name TYPE 000e42: DW_AT_type indirect DW_FORM_ref2 0x7f7 000e45: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000e48: 30 = 0xd (DW_TAG_member) 000e49: DW_AT_name CTRL 000e4e: DW_AT_type indirect DW_FORM_ref2 0x490 000e51: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000e54: 30 = 0xd (DW_TAG_member) 000e55: DW_AT_name RNR 000e59: DW_AT_type indirect DW_FORM_ref2 0x490 000e5c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000e5f: 30 = 0xd (DW_TAG_member) 000e60: DW_AT_name RBAR 000e65: DW_AT_type indirect DW_FORM_ref2 0x490 000e68: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000e6b: 30 = 0xd (DW_TAG_member) 000e6c: DW_AT_name RASR 000e71: DW_AT_type indirect DW_FORM_ref2 0x490 000e74: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000e77: 30 = 0xd (DW_TAG_member) 000e78: DW_AT_name RBAR_A1 000e80: DW_AT_type indirect DW_FORM_ref2 0x490 000e83: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 000e86: 30 = 0xd (DW_TAG_member) 000e87: DW_AT_name RASR_A1 000e8f: DW_AT_type indirect DW_FORM_ref2 0x490 000e92: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 000e95: 30 = 0xd (DW_TAG_member) 000e96: DW_AT_name RBAR_A2 000e9e: DW_AT_type indirect DW_FORM_ref2 0x490 000ea1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 000ea4: 30 = 0xd (DW_TAG_member) 000ea5: DW_AT_name RASR_A2 000ead: DW_AT_type indirect DW_FORM_ref2 0x490 000eb0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 000eb3: 30 = 0xd (DW_TAG_member) 000eb4: DW_AT_name RBAR_A3 000ebc: DW_AT_type indirect DW_FORM_ref2 0x490 000ebf: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 000ec2: 30 = 0xd (DW_TAG_member) 000ec3: DW_AT_name RASR_A3 000ecb: DW_AT_type indirect DW_FORM_ref2 0x490 000ece: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 000ed1: 0 null 000ed2: 80 = 0x16 (DW_TAG_typedef) 000ed3: DW_AT_name MPU_Type 000edc: DW_AT_type indirect DW_FORM_ref2 0xe38 000edf: DW_AT_decl_file 0x1 000ee0: DW_AT_decl_line 0x58c 000ee2: DW_AT_decl_column 0x3 000ee3: 42 = 0x13 (DW_TAG_structure_type) 000ee4: DW_AT_sibling 0xf53 000ee6: DW_AT_byte_size 0x1c 000ee7: 3 = 0x1 (DW_TAG_array_type) 000ee8: DW_AT_sibling 0xef2 000eea: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000eef: 1 = 0x21 (DW_TAG_subrange_type) 000ef0: DW_AT_upper_bound 0x0 000ef1: 0 null 000ef2: 30 = 0xd (DW_TAG_member) 000ef3: DW_AT_name RESERVED0 000efd: DW_AT_type indirect DW_FORM_ref2 0xee7 000f00: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000f03: 30 = 0xd (DW_TAG_member) 000f04: DW_AT_name FPCCR 000f0a: DW_AT_type indirect DW_FORM_ref2 0x490 000f0d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000f10: 30 = 0xd (DW_TAG_member) 000f11: DW_AT_name FPCAR 000f17: DW_AT_type indirect DW_FORM_ref2 0x490 000f1a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000f1d: 30 = 0xd (DW_TAG_member) 000f1e: DW_AT_name FPDSCR 000f25: DW_AT_type indirect DW_FORM_ref2 0x490 000f28: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000f2b: 30 = 0xd (DW_TAG_member) 000f2c: DW_AT_name MVFR0 000f32: DW_AT_type indirect DW_FORM_ref2 0x7f7 000f35: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000f38: 30 = 0xd (DW_TAG_member) 000f39: DW_AT_name MVFR1 000f3f: DW_AT_type indirect DW_FORM_ref2 0x7f7 000f42: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 000f45: 30 = 0xd (DW_TAG_member) 000f46: DW_AT_name MVFR2 000f4c: DW_AT_type indirect DW_FORM_ref2 0x7f7 000f4f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 000f52: 0 null 000f53: 80 = 0x16 (DW_TAG_typedef) 000f54: DW_AT_name FPU_Type 000f5d: DW_AT_type indirect DW_FORM_ref2 0xee3 000f60: DW_AT_decl_file 0x1 000f61: DW_AT_decl_line 0x5e7 000f63: DW_AT_decl_column 0x3 000f64: 42 = 0x13 (DW_TAG_structure_type) 000f65: DW_AT_sibling 0xf9d 000f67: DW_AT_byte_size 0x10 000f68: 30 = 0xd (DW_TAG_member) 000f69: DW_AT_name DHCSR 000f6f: DW_AT_type indirect DW_FORM_ref2 0x490 000f72: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000f75: 30 = 0xd (DW_TAG_member) 000f76: DW_AT_name DCRSR 000f7c: DW_AT_type indirect DW_FORM_ref2 0x490 000f7f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000f82: 30 = 0xd (DW_TAG_member) 000f83: DW_AT_name DCRDR 000f89: DW_AT_type indirect DW_FORM_ref2 0x490 000f8c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000f8f: 30 = 0xd (DW_TAG_member) 000f90: DW_AT_name DEMCR 000f96: DW_AT_type indirect DW_FORM_ref2 0x490 000f99: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000f9c: 0 null 000f9d: 80 = 0x16 (DW_TAG_typedef) 000f9e: DW_AT_name CoreDebug_Type 000fad: DW_AT_type indirect DW_FORM_ref2 0xf64 000fb0: DW_AT_decl_file 0x1 000fb1: DW_AT_decl_line 0x652 000fb3: DW_AT_decl_column 0x3 000fb4: 116 = 0x35 (DW_TAG_volatile_type) 000fb5: DW_AT_type indirect DW_FORM_ref_addr 0x130+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000fba: 113 = 0x34 (DW_TAG_variable) 000fbb: DW_AT_name ITM_RxBuffer 000fc8: DW_AT_type indirect DW_FORM_ref2 0xfb4 000fcb: DW_AT_external 0x1 000fcc: DW_AT_declaration 0x1 000fcd: 60 = 0x2e (DW_TAG_subprogram) 000fce: DW_AT_sibling 0x102a 000fd0: DW_AT_decl_file 0x1 000fd1: DW_AT_decl_line 0x70c 000fd3: DW_AT_decl_column 0x16 000fd4: DW_AT_name NVIC_SetPriorityGrouping 000fed: DW_AT_external 0x0 000fee: 36 = 0x5 (DW_TAG_formal_parameter) 000fef: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000ff4: DW_AT_name PriorityGroup 001002: 92 = 0x34 (DW_TAG_variable) 001003: DW_AT_name reg_value 00100d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001012: 92 = 0x34 (DW_TAG_variable) 001013: DW_AT_name PriorityGroupTmp 001024: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001029: 0 null 00102a: 59 = 0x2e (DW_TAG_subprogram) 00102b: DW_AT_sibling 0x1061 00102d: DW_AT_decl_file 0x1 00102e: DW_AT_decl_line 0x71f 001030: DW_AT_decl_column 0x1a 001031: DW_AT_name NVIC_GetPriorityGrouping 00104a: DW_AT_external 0x0 00104b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001050: 97 = 0x34 (DW_TAG_variable) 001051: DW_AT_name __result 00105a: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00105f: DW_AT_artificial 0x1 001060: 0 null 001061: 60 = 0x2e (DW_TAG_subprogram) 001062: DW_AT_sibling 0x1084 001064: DW_AT_decl_file 0x1 001065: DW_AT_decl_line 0x72a 001067: DW_AT_decl_column 0x16 001068: DW_AT_name NVIC_EnableIRQ 001077: DW_AT_external 0x0 001078: 36 = 0x5 (DW_TAG_formal_parameter) 001079: DW_AT_type indirect DW_FORM_ref_addr 0x86c+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 00107e: DW_AT_name IRQn 001083: 0 null 001084: 60 = 0x2e (DW_TAG_subprogram) 001085: DW_AT_sibling 0x10a8 001087: DW_AT_decl_file 0x1 001088: DW_AT_decl_line 0x735 00108a: DW_AT_decl_column 0x16 00108b: DW_AT_name NVIC_DisableIRQ 00109b: DW_AT_external 0x0 00109c: 36 = 0x5 (DW_TAG_formal_parameter) 00109d: DW_AT_type indirect DW_FORM_ref_addr 0x86c+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 0010a2: DW_AT_name IRQn 0010a7: 0 null 0010a8: 59 = 0x2e (DW_TAG_subprogram) 0010a9: DW_AT_sibling 0x10e4 0010ab: DW_AT_decl_file 0x1 0010ac: DW_AT_decl_line 0x742 0010ae: DW_AT_decl_column 0x1a 0010af: DW_AT_name NVIC_GetPendingIRQ 0010c2: DW_AT_external 0x0 0010c3: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0010c8: 36 = 0x5 (DW_TAG_formal_parameter) 0010c9: DW_AT_type indirect DW_FORM_ref_addr 0x86c+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 0010ce: DW_AT_name IRQn 0010d3: 97 = 0x34 (DW_TAG_variable) 0010d4: DW_AT_name __result 0010dd: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0010e2: DW_AT_artificial 0x1 0010e3: 0 null 0010e4: 60 = 0x2e (DW_TAG_subprogram) 0010e5: DW_AT_sibling 0x110b 0010e7: DW_AT_decl_file 0x1 0010e8: DW_AT_decl_line 0x74d 0010ea: DW_AT_decl_column 0x16 0010eb: DW_AT_name NVIC_SetPendingIRQ 0010fe: DW_AT_external 0x0 0010ff: 36 = 0x5 (DW_TAG_formal_parameter) 001100: DW_AT_type indirect DW_FORM_ref_addr 0x86c+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 001105: DW_AT_name IRQn 00110a: 0 null 00110b: 60 = 0x2e (DW_TAG_subprogram) 00110c: DW_AT_sibling 0x1134 00110e: DW_AT_decl_file 0x1 00110f: DW_AT_decl_line 0x758 001111: DW_AT_decl_column 0x16 001112: DW_AT_name NVIC_ClearPendingIRQ 001127: DW_AT_external 0x0 001128: 36 = 0x5 (DW_TAG_formal_parameter) 001129: DW_AT_type indirect DW_FORM_ref_addr 0x86c+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 00112e: DW_AT_name IRQn 001133: 0 null 001134: 59 = 0x2e (DW_TAG_subprogram) 001135: DW_AT_sibling 0x116c 001137: DW_AT_decl_file 0x1 001138: DW_AT_decl_line 0x765 00113a: DW_AT_decl_column 0x1a 00113b: DW_AT_name NVIC_GetActive 00114a: DW_AT_external 0x0 00114b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001150: 36 = 0x5 (DW_TAG_formal_parameter) 001151: DW_AT_type indirect DW_FORM_ref_addr 0x86c+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 001156: DW_AT_name IRQn 00115b: 97 = 0x34 (DW_TAG_variable) 00115c: DW_AT_name __result 001165: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00116a: DW_AT_artificial 0x1 00116b: 0 null 00116c: 60 = 0x2e (DW_TAG_subprogram) 00116d: DW_AT_sibling 0x11a0 00116f: DW_AT_decl_file 0x1 001170: DW_AT_decl_line 0x772 001172: DW_AT_decl_column 0x16 001173: DW_AT_name NVIC_SetPriority 001184: DW_AT_external 0x0 001185: 36 = 0x5 (DW_TAG_formal_parameter) 001186: DW_AT_type indirect DW_FORM_ref_addr 0x86c+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 00118b: DW_AT_name IRQn 001190: 36 = 0x5 (DW_TAG_formal_parameter) 001191: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001196: DW_AT_name priority 00119f: 0 null 0011a0: 59 = 0x2e (DW_TAG_subprogram) 0011a1: DW_AT_sibling 0x11da 0011a3: DW_AT_decl_file 0x1 0011a4: DW_AT_decl_line 0x788 0011a6: DW_AT_decl_column 0x1a 0011a7: DW_AT_name NVIC_GetPriority 0011b8: DW_AT_external 0x0 0011b9: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0011be: 36 = 0x5 (DW_TAG_formal_parameter) 0011bf: DW_AT_type indirect DW_FORM_ref_addr 0x86c+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 0011c4: DW_AT_name IRQn 0011c9: 97 = 0x34 (DW_TAG_variable) 0011ca: DW_AT_name __result 0011d3: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0011d8: DW_AT_artificial 0x1 0011d9: 0 null 0011da: 59 = 0x2e (DW_TAG_subprogram) 0011db: DW_AT_sibling 0x128f 0011dd: DW_AT_decl_file 0x1 0011de: DW_AT_decl_line 0x7a1 0011e0: DW_AT_decl_column 0x1a 0011e1: DW_AT_name NVIC_EncodePriority 0011f5: DW_AT_external 0x0 0011f6: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0011fb: 36 = 0x5 (DW_TAG_formal_parameter) 0011fc: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001201: DW_AT_name PriorityGroup 00120f: 36 = 0x5 (DW_TAG_formal_parameter) 001210: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001215: DW_AT_name PreemptPriority 001225: 36 = 0x5 (DW_TAG_formal_parameter) 001226: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00122b: DW_AT_name SubPriority 001237: 97 = 0x34 (DW_TAG_variable) 001238: DW_AT_name __result 001241: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001246: DW_AT_artificial 0x1 001247: 92 = 0x34 (DW_TAG_variable) 001248: DW_AT_name PriorityGroupTmp 001259: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00125e: 92 = 0x34 (DW_TAG_variable) 00125f: DW_AT_name PreemptPriorityBits 001273: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001278: 92 = 0x34 (DW_TAG_variable) 001279: DW_AT_name SubPriorityBits 001289: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00128e: 0 null 00128f: 60 = 0x2e (DW_TAG_subprogram) 001290: DW_AT_sibling 0x133c 001292: DW_AT_decl_file 0x1 001293: DW_AT_decl_line 0x7bc 001295: DW_AT_decl_column 0x16 001296: DW_AT_name NVIC_DecodePriority 0012aa: DW_AT_external 0x0 0012ab: 36 = 0x5 (DW_TAG_formal_parameter) 0012ac: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0012b1: DW_AT_name Priority 0012ba: 36 = 0x5 (DW_TAG_formal_parameter) 0012bb: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0012c0: DW_AT_name PriorityGroup 0012ce: 36 = 0x5 (DW_TAG_formal_parameter) 0012cf: DW_AT_type indirect DW_FORM_ref2 0x1342 0012d2: DW_AT_name pPreemptPriority 0012e3: 36 = 0x5 (DW_TAG_formal_parameter) 0012e4: DW_AT_type indirect DW_FORM_ref2 0x1342 0012e7: DW_AT_name pSubPriority 0012f4: 92 = 0x34 (DW_TAG_variable) 0012f5: DW_AT_name PriorityGroupTmp 001306: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00130b: 92 = 0x34 (DW_TAG_variable) 00130c: DW_AT_name PreemptPriorityBits 001320: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001325: 92 = 0x34 (DW_TAG_variable) 001326: DW_AT_name SubPriorityBits 001336: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00133b: 0 null 00133c: 34 = 0xf (DW_TAG_pointer_type) 00133d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001342: 17 = 0x26 (DW_TAG_const_type) 001343: DW_AT_type indirect DW_FORM_ref2 0x133c 001346: 60 = 0x2e (DW_TAG_subprogram) 001347: DW_AT_sibling 0x1360 001349: DW_AT_decl_file 0x1 00134a: DW_AT_decl_line 0x7ce 00134c: DW_AT_decl_column 0x16 00134d: DW_AT_name NVIC_SystemReset 00135e: DW_AT_external 0x0 00135f: 0 null 001360: 59 = 0x2e (DW_TAG_subprogram) 001361: DW_AT_sibling 0x1399 001363: DW_AT_decl_file 0x1 001364: DW_AT_decl_line 0x7f0 001366: DW_AT_decl_column 0x1a 001367: DW_AT_name SCB_GetFPUType 001376: DW_AT_external 0x0 001377: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00137c: 97 = 0x34 (DW_TAG_variable) 00137d: DW_AT_name __result 001386: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00138b: DW_AT_artificial 0x1 00138c: 92 = 0x34 (DW_TAG_variable) 00138d: DW_AT_name mvfr0 001393: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001398: 0 null 001399: 60 = 0x2e (DW_TAG_subprogram) 00139a: DW_AT_sibling 0x13b3 00139c: DW_AT_decl_file 0x1 00139d: DW_AT_decl_line 0x819 00139f: DW_AT_decl_column 0x16 0013a0: DW_AT_name SCB_EnableICache 0013b1: DW_AT_external 0x0 0013b2: 0 null 0013b3: 60 = 0x2e (DW_TAG_subprogram) 0013b4: DW_AT_sibling 0x13ce 0013b6: DW_AT_decl_file 0x1 0013b7: DW_AT_decl_line 0x82a 0013b9: DW_AT_decl_column 0x16 0013ba: DW_AT_name SCB_DisableICache 0013cc: DW_AT_external 0x0 0013cd: 0 null 0013ce: 60 = 0x2e (DW_TAG_subprogram) 0013cf: DW_AT_sibling 0x13ec 0013d1: DW_AT_decl_file 0x1 0013d2: DW_AT_decl_line 0x83b 0013d4: DW_AT_decl_column 0x16 0013d5: DW_AT_name SCB_InvalidateICache 0013ea: DW_AT_external 0x0 0013eb: 0 null 0013ec: 60 = 0x2e (DW_TAG_subprogram) 0013ed: DW_AT_sibling 0x1429 0013ef: DW_AT_decl_file 0x1 0013f0: DW_AT_decl_line 0x84b 0013f2: DW_AT_decl_column 0x16 0013f3: DW_AT_name SCB_EnableDCache 001404: DW_AT_external 0x0 001405: 92 = 0x34 (DW_TAG_variable) 001406: DW_AT_name ccsidr 00140d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001412: 92 = 0x34 (DW_TAG_variable) 001413: DW_AT_name sets 001418: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00141d: 92 = 0x34 (DW_TAG_variable) 00141e: DW_AT_name ways 001423: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001428: 0 null 001429: 60 = 0x2e (DW_TAG_subprogram) 00142a: DW_AT_sibling 0x1467 00142c: DW_AT_decl_file 0x1 00142d: DW_AT_decl_line 0x871 00142f: DW_AT_decl_column 0x16 001430: DW_AT_name SCB_DisableDCache 001442: DW_AT_external 0x0 001443: 92 = 0x34 (DW_TAG_variable) 001444: DW_AT_name ccsidr 00144b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001450: 92 = 0x34 (DW_TAG_variable) 001451: DW_AT_name sets 001456: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00145b: 92 = 0x34 (DW_TAG_variable) 00145c: DW_AT_name ways 001461: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001466: 0 null 001467: 60 = 0x2e (DW_TAG_subprogram) 001468: DW_AT_sibling 0x14a8 00146a: DW_AT_decl_file 0x1 00146b: DW_AT_decl_line 0x896 00146d: DW_AT_decl_column 0x16 00146e: DW_AT_name SCB_InvalidateDCache 001483: DW_AT_external 0x0 001484: 92 = 0x34 (DW_TAG_variable) 001485: DW_AT_name ccsidr 00148c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001491: 92 = 0x34 (DW_TAG_variable) 001492: DW_AT_name sets 001497: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00149c: 92 = 0x34 (DW_TAG_variable) 00149d: DW_AT_name ways 0014a2: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0014a7: 0 null 0014a8: 60 = 0x2e (DW_TAG_subprogram) 0014a9: DW_AT_sibling 0x14e4 0014ab: DW_AT_decl_file 0x1 0014ac: DW_AT_decl_line 0x8b9 0014ae: DW_AT_decl_column 0x16 0014af: DW_AT_name SCB_CleanDCache 0014bf: DW_AT_external 0x0 0014c0: 92 = 0x34 (DW_TAG_variable) 0014c1: DW_AT_name ccsidr 0014c8: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0014cd: 92 = 0x34 (DW_TAG_variable) 0014ce: DW_AT_name sets 0014d3: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0014d8: 92 = 0x34 (DW_TAG_variable) 0014d9: DW_AT_name ways 0014de: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0014e3: 0 null 0014e4: 60 = 0x2e (DW_TAG_subprogram) 0014e5: DW_AT_sibling 0x152a 0014e7: DW_AT_decl_file 0x1 0014e8: DW_AT_decl_line 0x8dc 0014ea: DW_AT_decl_column 0x16 0014eb: DW_AT_name SCB_CleanInvalidateDCache 001505: DW_AT_external 0x0 001506: 92 = 0x34 (DW_TAG_variable) 001507: DW_AT_name ccsidr 00150e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001513: 92 = 0x34 (DW_TAG_variable) 001514: DW_AT_name sets 001519: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00151e: 92 = 0x34 (DW_TAG_variable) 00151f: DW_AT_name ways 001524: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001529: 0 null 00152a: 60 = 0x2e (DW_TAG_subprogram) 00152b: DW_AT_sibling 0x1590 00152d: DW_AT_decl_file 0x1 00152e: DW_AT_decl_line 0x901 001530: DW_AT_decl_column 0x16 001531: DW_AT_name SCB_InvalidateDCache_by_Addr 00154e: DW_AT_external 0x0 00154f: 36 = 0x5 (DW_TAG_formal_parameter) 001550: DW_AT_type indirect DW_FORM_ref2 0x133c 001553: DW_AT_name addr 001558: 36 = 0x5 (DW_TAG_formal_parameter) 001559: DW_AT_type indirect DW_FORM_ref_addr 0x130+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00155e: DW_AT_name dsize 001564: 92 = 0x34 (DW_TAG_variable) 001565: DW_AT_name op_size 00156d: DW_AT_type indirect DW_FORM_ref_addr 0x130+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001572: 92 = 0x34 (DW_TAG_variable) 001573: DW_AT_name op_addr 00157b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001580: 92 = 0x34 (DW_TAG_variable) 001581: DW_AT_name linesize 00158a: DW_AT_type indirect DW_FORM_ref_addr 0x130+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00158f: 0 null 001590: 60 = 0x2e (DW_TAG_subprogram) 001591: DW_AT_sibling 0x15f1 001593: DW_AT_decl_file 0x1 001594: DW_AT_decl_line 0x91c 001596: DW_AT_decl_column 0x16 001597: DW_AT_name SCB_CleanDCache_by_Addr 0015af: DW_AT_external 0x0 0015b0: 36 = 0x5 (DW_TAG_formal_parameter) 0015b1: DW_AT_type indirect DW_FORM_ref2 0x133c 0015b4: DW_AT_name addr 0015b9: 36 = 0x5 (DW_TAG_formal_parameter) 0015ba: DW_AT_type indirect DW_FORM_ref_addr 0x130+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0015bf: DW_AT_name dsize 0015c5: 92 = 0x34 (DW_TAG_variable) 0015c6: DW_AT_name op_size 0015ce: DW_AT_type indirect DW_FORM_ref_addr 0x130+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0015d3: 92 = 0x34 (DW_TAG_variable) 0015d4: DW_AT_name op_addr 0015dc: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0015e1: 92 = 0x34 (DW_TAG_variable) 0015e2: DW_AT_name linesize 0015eb: DW_AT_type indirect DW_FORM_ref_addr 0x130+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0015f0: 0 null 0015f1: 60 = 0x2e (DW_TAG_subprogram) 0015f2: DW_AT_sibling 0x165c 0015f4: DW_AT_decl_file 0x1 0015f5: DW_AT_decl_line 0x937 0015f7: DW_AT_decl_column 0x16 0015f8: DW_AT_name SCB_CleanInvalidateDCache_by_Addr 00161a: DW_AT_external 0x0 00161b: 36 = 0x5 (DW_TAG_formal_parameter) 00161c: DW_AT_type indirect DW_FORM_ref2 0x133c 00161f: DW_AT_name addr 001624: 36 = 0x5 (DW_TAG_formal_parameter) 001625: DW_AT_type indirect DW_FORM_ref_addr 0x130+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00162a: DW_AT_name dsize 001630: 92 = 0x34 (DW_TAG_variable) 001631: DW_AT_name op_size 001639: DW_AT_type indirect DW_FORM_ref_addr 0x130+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00163e: 92 = 0x34 (DW_TAG_variable) 00163f: DW_AT_name op_addr 001647: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00164c: 92 = 0x34 (DW_TAG_variable) 00164d: DW_AT_name linesize 001656: DW_AT_type indirect DW_FORM_ref_addr 0x130+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00165b: 0 null 00165c: 59 = 0x2e (DW_TAG_subprogram) 00165d: DW_AT_sibling 0x1695 00165f: DW_AT_decl_file 0x1 001660: DW_AT_decl_line 0x965 001662: DW_AT_decl_column 0x1a 001663: DW_AT_name SysTick_Config 001672: DW_AT_external 0x0 001673: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001678: 36 = 0x5 (DW_TAG_formal_parameter) 001679: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00167e: DW_AT_name ticks 001684: 97 = 0x34 (DW_TAG_variable) 001685: DW_AT_name __result 00168e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001693: DW_AT_artificial 0x1 001694: 0 null 001695: 59 = 0x2e (DW_TAG_subprogram) 001696: DW_AT_sibling 0x16c9 001698: DW_AT_decl_file 0x1 001699: DW_AT_decl_line 0x98f 00169b: DW_AT_decl_column 0x1a 00169c: DW_AT_name ITM_SendChar 0016a9: DW_AT_external 0x0 0016aa: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0016af: 36 = 0x5 (DW_TAG_formal_parameter) 0016b0: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0016b5: DW_AT_name ch 0016b8: 97 = 0x34 (DW_TAG_variable) 0016b9: DW_AT_name __result 0016c2: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0016c7: DW_AT_artificial 0x1 0016c8: 0 null 0016c9: 59 = 0x2e (DW_TAG_subprogram) 0016ca: DW_AT_sibling 0x1700 0016cc: DW_AT_decl_file 0x1 0016cd: DW_AT_decl_line 0x9a4 0016cf: DW_AT_decl_column 0x19 0016d0: DW_AT_name ITM_ReceiveChar 0016e0: DW_AT_external 0x0 0016e1: DW_AT_type indirect DW_FORM_ref_addr 0x130+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0016e6: 97 = 0x34 (DW_TAG_variable) 0016e7: DW_AT_name __result 0016f0: DW_AT_type indirect DW_FORM_ref_addr 0x130+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0016f5: DW_AT_artificial 0x1 0016f6: 92 = 0x34 (DW_TAG_variable) 0016f7: DW_AT_name ch 0016fa: DW_AT_type indirect DW_FORM_ref_addr 0x130+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0016ff: 0 null 001700: 59 = 0x2e (DW_TAG_subprogram) 001701: DW_AT_sibling 0x172c 001703: DW_AT_decl_file 0x1 001704: DW_AT_decl_line 0x9b8 001706: DW_AT_decl_column 0x19 001707: DW_AT_name ITM_CheckChar 001715: DW_AT_external 0x0 001716: DW_AT_type indirect DW_FORM_ref_addr 0x130+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00171b: 97 = 0x34 (DW_TAG_variable) 00171c: DW_AT_name __result 001725: DW_AT_type indirect DW_FORM_ref_addr 0x130+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00172a: DW_AT_artificial 0x1 00172b: 0 null 00172c: 0 null 00172d: 0 padding 00172e: 0 padding 00172f: 0 padding ** Section #364 '.rel.debug_info' (SHT_REL) Size : 1152 bytes (alignment 4) Symbol table #343 '.symtab' 144 relocations applied to section #47 '.debug_info' ** Section #48 '.debug_pubnames' (SHT_PROGBITS) [SHF_GROUP] Size : 35 bytes 0x00000000: Compilation unit (35 bytes) vsn 2: 0x00000006: reference to offset __ARM_grp..debug_info$core_cm7.h$.2_bKb200_paF20BtQ$86_H60000 0x0000000a: 5936 bytes generated for unit 0x0000000e: Offset 0xfba (0xfba) 0x00000012: 49 54 4d 5f 52 78 42 75 66 66 65 72 ITM_RxBuffer 0x0000001e: 00 0x0000001f: End of list for compilation unit (zero offset) ** Section #365 '.rel.debug_pubnames' (SHT_REL) Size : 8 bytes (alignment 4) Symbol table #343 '.symtab' 1 relocations applied to section #48 '.debug_pubnames' ** Section #49 '__ARM_grp.system_stm32f7xx.h.2_ux2000_UVE2frAAF_e_h00000' (SHT_GROUP) Size : 20 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #50 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 32 bytes 000000: include at line 0 - file 1 000003: line 50 define __SYSTEM_STM32F7XX_H 00001b: end include 00001c: end of translation unit ** Section #51 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 108 bytes 000000: Header: length 104 (not including this field) version 3 prologue length 92 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\CMSIS\Device\ST\STM32F7xx\Include\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 43 4d 53 49 53 5c 44 65 76 69 63 65 5c 53 54 5c 53 54 4d 33 32 46 37 78 78 5c 49 6e 63 6c 75 64 65 5c 00 00004e: directory "" : 00 00004f: file "system_stm32f7xx.h": dir 1 time 0x0 length 0: 73 79 73 74 65 6d 5f 73 74 6d 33 32 66 37 78 78 2e 68 00 01 00 00 000065: file "" : 00 000066: DW_LNS_negate_stmt : 06 000067: DW_LNS_negate_stmt : 06 000068: DW_LNS_negate_stmt : 06 000069: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\CMSIS\Device\ST\STM32F7xx\Include\system_stm32f7xx.h:1.0 [ ** Section #52 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 372 bytes 000000: Header: size 0x170 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\CMSIS\Device\ST\STM32F7xx\Include\system_stm32f7xx.h 000051: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000098: DW_AT_language DW_LANG_C89 00009a: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 000111: DW_AT_macro_info 0x0 000115: DW_AT_stmt_list 0x0 000119: 113 = 0x34 (DW_TAG_variable) 00011a: DW_AT_name SystemCoreClock 00012a: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00012f: DW_AT_external 0x1 000130: DW_AT_declaration 0x1 000131: 17 = 0x26 (DW_TAG_const_type) 000132: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000137: 3 = 0x1 (DW_TAG_array_type) 000138: DW_AT_sibling 0x140 00013a: DW_AT_type indirect DW_FORM_ref2 0x131 00013d: 1 = 0x21 (DW_TAG_subrange_type) 00013e: DW_AT_upper_bound 0xf 00013f: 0 null 000140: 113 = 0x34 (DW_TAG_variable) 000141: DW_AT_name AHBPrescTable 00014f: DW_AT_type indirect DW_FORM_ref2 0x137 000152: DW_AT_external 0x1 000153: DW_AT_declaration 0x1 000154: 3 = 0x1 (DW_TAG_array_type) 000155: DW_AT_sibling 0x15d 000157: DW_AT_type indirect DW_FORM_ref2 0x131 00015a: 1 = 0x21 (DW_TAG_subrange_type) 00015b: DW_AT_upper_bound 0x7 00015c: 0 null 00015d: 113 = 0x34 (DW_TAG_variable) 00015e: DW_AT_name APBPrescTable 00016c: DW_AT_type indirect DW_FORM_ref2 0x154 00016f: DW_AT_external 0x1 000170: DW_AT_declaration 0x1 000171: 0 null 000172: 0 padding 000173: 0 padding ** Section #366 '.rel.debug_info' (SHT_REL) Size : 40 bytes (alignment 4) Symbol table #343 '.symtab' 5 relocations applied to section #52 '.debug_info' ** Section #53 '.debug_pubnames' (SHT_PROGBITS) [SHF_GROUP] Size : 74 bytes 0x00000000: Compilation unit (74 bytes) vsn 2: 0x00000006: reference to offset __ARM_grp..debug_info$system_stm32f7xx.h$.2_ux2000_UVE2frAAF_e_h00000 0x0000000a: 372 bytes generated for unit 0x0000000e: Offset 0x119 (0x119) 0x00000012: 53 79 73 74 65 6d 43 6f 72 65 43 6c SystemCoreCl 0x0000001e: 6f 63 6b 00 ock 0x00000022: Offset 0x140 (0x140) 0x00000026: 41 48 42 50 72 65 73 63 54 61 62 6c AHBPrescTabl 0x00000032: 65 00 e 0x00000034: Offset 0x15d (0x15d) 0x00000038: 41 50 42 50 72 65 73 63 54 61 62 6c APBPrescTabl 0x00000044: 65 00 e 0x00000046: End of list for compilation unit (zero offset) ** Section #367 '.rel.debug_pubnames' (SHT_REL) Size : 8 bytes (alignment 4) Symbol table #343 '.symtab' 1 relocations applied to section #53 '.debug_pubnames' ** Section #54 '__ARM_grp.stm32f767xx.h.2_8vN100_X1EE77Qf3Q1_510000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #55 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 223048 bytes 000000: include at line 0 - file 1 000003: line 53 define __STM32F767xx_H 000016: line 196 define __CM7_REV 0x0100U 00002b: line 197 define __MPU_PRESENT 1 00003e: line 198 define __NVIC_PRIO_BITS 4 000054: line 199 define __Vendor_SysTickConfig 0 000070: line 200 define __FPU_PRESENT 1 000083: line 201 define __ICACHE_PRESENT 1 000099: line 202 define __DCACHE_PRESENT 1 0000af: include at line 203 - file 2 0000b3: end include 0000b4: include at line 206 - file 3 0000b8: end include 0000b9: include at line 207 - file 4 0000bd: end include 0000be: line 1309 define RAMITCM_BASE 0x00000000U 0000da: line 1310 define FLASHITCM_BASE 0x00200000U 0000f8: line 1311 define FLASHAXI_BASE 0x08000000U 000115: line 1312 define RAMDTCM_BASE 0x20000000U 000131: line 1313 define PERIPH_BASE 0x40000000U 00014c: line 1314 define BKPSRAM_BASE 0x40024000U 000168: line 1315 define QSPI_BASE 0x90000000U 000181: line 1316 define FMC_R_BASE 0xA0000000U 00019b: line 1317 define QSPI_R_BASE 0xA0001000U 0001b6: line 1318 define SRAM1_BASE 0x20020000U 0001d0: line 1319 define SRAM2_BASE 0x2007C000U 0001ea: line 1320 define FLASH_END 0x081FFFFFU 000203: line 1323 define FLASH_BASE FLASHAXI_BASE 00021f: line 1326 define APB1PERIPH_BASE PERIPH_BASE 00023e: line 1327 define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) 00026d: line 1328 define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) 00029c: line 1329 define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U) 0002cb: line 1332 define TIM2_BASE (APB1PERIPH_BASE + 0x0000U) 0002f4: line 1333 define TIM3_BASE (APB1PERIPH_BASE + 0x0400U) 00031d: line 1334 define TIM4_BASE (APB1PERIPH_BASE + 0x0800U) 000346: line 1335 define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U) 00036f: line 1336 define TIM6_BASE (APB1PERIPH_BASE + 0x1000U) 000398: line 1337 define TIM7_BASE (APB1PERIPH_BASE + 0x1400U) 0003c1: line 1338 define TIM12_BASE (APB1PERIPH_BASE + 0x1800U) 0003eb: line 1339 define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U) 000415: line 1340 define TIM14_BASE (APB1PERIPH_BASE + 0x2000U) 00043f: line 1341 define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U) 00046a: line 1342 define RTC_BASE (APB1PERIPH_BASE + 0x2800U) 000492: line 1343 define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U) 0004bb: line 1344 define IWDG_BASE (APB1PERIPH_BASE + 0x3000U) 0004e4: line 1345 define CAN3_BASE (APB1PERIPH_BASE + 0x3400U) 00050d: line 1346 define SPI2_BASE (APB1PERIPH_BASE + 0x3800U) 000536: line 1347 define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U) 00055f: line 1348 define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U) 00058b: line 1349 define USART2_BASE (APB1PERIPH_BASE + 0x4400U) 0005b6: line 1350 define USART3_BASE (APB1PERIPH_BASE + 0x4800U) 0005e1: line 1351 define UART4_BASE (APB1PERIPH_BASE + 0x4C00U) 00060b: line 1352 define UART5_BASE (APB1PERIPH_BASE + 0x5000U) 000635: line 1353 define I2C1_BASE (APB1PERIPH_BASE + 0x5400U) 00065e: line 1354 define I2C2_BASE (APB1PERIPH_BASE + 0x5800U) 000687: line 1355 define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U) 0006b0: line 1356 define I2C4_BASE (APB1PERIPH_BASE + 0x6000U) 0006d9: line 1357 define CAN1_BASE (APB1PERIPH_BASE + 0x6400U) 000702: line 1358 define CAN2_BASE (APB1PERIPH_BASE + 0x6800U) 00072b: line 1359 define CEC_BASE (APB1PERIPH_BASE + 0x6C00U) 000753: line 1360 define PWR_BASE (APB1PERIPH_BASE + 0x7000U) 00077b: line 1361 define DAC_BASE (APB1PERIPH_BASE + 0x7400U) 0007a3: line 1362 define UART7_BASE (APB1PERIPH_BASE + 0x7800U) 0007cd: line 1363 define UART8_BASE (APB1PERIPH_BASE + 0x7C00U) 0007f7: line 1366 define TIM1_BASE (APB2PERIPH_BASE + 0x0000U) 000820: line 1367 define TIM8_BASE (APB2PERIPH_BASE + 0x0400U) 000849: line 1368 define USART1_BASE (APB2PERIPH_BASE + 0x1000U) 000874: line 1369 define USART6_BASE (APB2PERIPH_BASE + 0x1400U) 00089f: line 1370 define SDMMC2_BASE (APB2PERIPH_BASE + 0x1C00U) 0008ca: line 1371 define ADC1_BASE (APB2PERIPH_BASE + 0x2000U) 0008f3: line 1372 define ADC2_BASE (APB2PERIPH_BASE + 0x2100U) 00091c: line 1373 define ADC3_BASE (APB2PERIPH_BASE + 0x2200U) 000945: line 1374 define ADC_BASE (APB2PERIPH_BASE + 0x2300U) 00096d: line 1375 define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00U) 000998: line 1376 define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) 0009c1: line 1377 define SPI4_BASE (APB2PERIPH_BASE + 0x3400U) 0009ea: line 1378 define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U) 000a15: line 1379 define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U) 000a3e: line 1380 define TIM9_BASE (APB2PERIPH_BASE + 0x4000U) 000a67: line 1381 define TIM10_BASE (APB2PERIPH_BASE + 0x4400U) 000a91: line 1382 define TIM11_BASE (APB2PERIPH_BASE + 0x4800U) 000abb: line 1383 define SPI5_BASE (APB2PERIPH_BASE + 0x5000U) 000ae4: line 1384 define SPI6_BASE (APB2PERIPH_BASE + 0x5400U) 000b0d: line 1385 define SAI1_BASE (APB2PERIPH_BASE + 0x5800U) 000b36: line 1386 define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U) 000b5f: line 1387 define SAI1_Block_A_BASE (SAI1_BASE + 0x004U) 000b89: line 1388 define SAI1_Block_B_BASE (SAI1_BASE + 0x024U) 000bb3: line 1389 define SAI2_Block_A_BASE (SAI2_BASE + 0x004U) 000bdd: line 1390 define SAI2_Block_B_BASE (SAI2_BASE + 0x024U) 000c07: line 1391 define LTDC_BASE (APB2PERIPH_BASE + 0x6800U) 000c30: line 1392 define LTDC_Layer1_BASE (LTDC_BASE + 0x84U) 000c58: line 1393 define LTDC_Layer2_BASE (LTDC_BASE + 0x104U) 000c81: line 1394 define DFSDM1_BASE (APB2PERIPH_BASE + 0x7400U) 000cac: line 1395 define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00U) 000cda: line 1396 define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20U) 000d08: line 1397 define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40U) 000d36: line 1398 define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60U) 000d64: line 1399 define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80U) 000d92: line 1400 define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0U) 000dc0: line 1401 define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0U) 000dee: line 1402 define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0U) 000e1c: line 1403 define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100U) 000e4a: line 1404 define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U) 000e78: line 1405 define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200U) 000ea6: line 1406 define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280U) 000ed4: line 1407 define MDIOS_BASE (APB2PERIPH_BASE + 0x7800U) 000efe: line 1409 define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U) 000f28: line 1410 define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U) 000f52: line 1411 define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U) 000f7c: line 1412 define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U) 000fa6: line 1413 define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U) 000fd0: line 1414 define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U) 000ffa: line 1415 define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U) 001024: line 1416 define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U) 00104e: line 1417 define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U) 001078: line 1418 define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U) 0010a2: line 1419 define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U) 0010cc: line 1420 define CRC_BASE (AHB1PERIPH_BASE + 0x3000U) 0010f4: line 1421 define RCC_BASE (AHB1PERIPH_BASE + 0x3800U) 00111c: line 1422 define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U) 001148: line 1423 define UID_BASE 0x1FF0F420U 001160: line 1424 define FLASHSIZE_BASE 0x1FF0F442U 00117e: line 1425 define PACKAGESIZE_BASE 0x1FFF7BF0U 00119e: line 1426 define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U) 0011c7: line 1427 define DMA1_Stream0_BASE (DMA1_BASE + 0x010U) 0011f1: line 1428 define DMA1_Stream1_BASE (DMA1_BASE + 0x028U) 00121b: line 1429 define DMA1_Stream2_BASE (DMA1_BASE + 0x040U) 001245: line 1430 define DMA1_Stream3_BASE (DMA1_BASE + 0x058U) 00126f: line 1431 define DMA1_Stream4_BASE (DMA1_BASE + 0x070U) 001299: line 1432 define DMA1_Stream5_BASE (DMA1_BASE + 0x088U) 0012c3: line 1433 define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U) 0012ed: line 1434 define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U) 001317: line 1435 define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U) 001340: line 1436 define DMA2_Stream0_BASE (DMA2_BASE + 0x010U) 00136a: line 1437 define DMA2_Stream1_BASE (DMA2_BASE + 0x028U) 001394: line 1438 define DMA2_Stream2_BASE (DMA2_BASE + 0x040U) 0013be: line 1439 define DMA2_Stream3_BASE (DMA2_BASE + 0x058U) 0013e8: line 1440 define DMA2_Stream4_BASE (DMA2_BASE + 0x070U) 001412: line 1441 define DMA2_Stream5_BASE (DMA2_BASE + 0x088U) 00143c: line 1442 define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U) 001466: line 1443 define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U) 001490: line 1444 define ETH_BASE (AHB1PERIPH_BASE + 0x8000U) 0014b8: line 1445 define ETH_MAC_BASE (ETH_BASE) 0014d3: line 1446 define ETH_MMC_BASE (ETH_BASE + 0x0100U) 0014f8: line 1447 define ETH_PTP_BASE (ETH_BASE + 0x0700U) 00151d: line 1448 define ETH_DMA_BASE (ETH_BASE + 0x1000U) 001542: line 1449 define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U) 00156c: line 1451 define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U) 001596: line 1452 define JPEG_BASE (AHB2PERIPH_BASE + 0x51000U) 0015c0: line 1453 define RNG_BASE (AHB2PERIPH_BASE + 0x60800U) 0015e9: line 1455 define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U) 001614: line 1456 define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U) 001640: line 1457 define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U) 00166b: line 1458 define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U) 001698: line 1461 define DBGMCU_BASE 0xE0042000U 0016b3: line 1464 define USB_OTG_HS_PERIPH_BASE 0x40040000U 0016d9: line 1465 define USB_OTG_FS_PERIPH_BASE 0x50000000U 0016ff: line 1467 define USB_OTG_GLOBAL_BASE 0x000U 00171d: line 1468 define USB_OTG_DEVICE_BASE 0x800U 00173b: line 1469 define USB_OTG_IN_ENDPOINT_BASE 0x900U 00175e: line 1470 define USB_OTG_OUT_ENDPOINT_BASE 0xB00U 001782: line 1471 define USB_OTG_EP_REG_SIZE 0x20U 00179f: line 1472 define USB_OTG_HOST_BASE 0x400U 0017bb: line 1473 define USB_OTG_HOST_PORT_BASE 0x440U 0017dc: line 1474 define USB_OTG_HOST_CHANNEL_BASE 0x500U 001800: line 1475 define USB_OTG_HOST_CHANNEL_SIZE 0x20U 001823: line 1476 define USB_OTG_PCGCCTL_BASE 0xE00U 001842: line 1477 define USB_OTG_FIFO_BASE 0x1000U 00185f: line 1478 define USB_OTG_FIFO_SIZE 0x1000U 00187c: line 1487 define TIM2 ((TIM_TypeDef *) TIM2_BASE) 0018a0: line 1488 define TIM3 ((TIM_TypeDef *) TIM3_BASE) 0018c4: line 1489 define TIM4 ((TIM_TypeDef *) TIM4_BASE) 0018e8: line 1490 define TIM5 ((TIM_TypeDef *) TIM5_BASE) 00190c: line 1491 define TIM6 ((TIM_TypeDef *) TIM6_BASE) 001930: line 1492 define TIM7 ((TIM_TypeDef *) TIM7_BASE) 001954: line 1493 define TIM12 ((TIM_TypeDef *) TIM12_BASE) 00197a: line 1494 define TIM13 ((TIM_TypeDef *) TIM13_BASE) 0019a0: line 1495 define TIM14 ((TIM_TypeDef *) TIM14_BASE) 0019c6: line 1496 define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) 0019f0: line 1497 define RTC ((RTC_TypeDef *) RTC_BASE) 001a12: line 1498 define WWDG ((WWDG_TypeDef *) WWDG_BASE) 001a37: line 1499 define IWDG ((IWDG_TypeDef *) IWDG_BASE) 001a5c: line 1500 define SPI2 ((SPI_TypeDef *) SPI2_BASE) 001a80: line 1501 define SPI3 ((SPI_TypeDef *) SPI3_BASE) 001aa4: line 1502 define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) 001ad2: line 1503 define USART2 ((USART_TypeDef *) USART2_BASE) 001afc: line 1504 define USART3 ((USART_TypeDef *) USART3_BASE) 001b26: line 1505 define UART4 ((USART_TypeDef *) UART4_BASE) 001b4e: line 1506 define UART5 ((USART_TypeDef *) UART5_BASE) 001b76: line 1507 define I2C1 ((I2C_TypeDef *) I2C1_BASE) 001b9a: line 1508 define I2C2 ((I2C_TypeDef *) I2C2_BASE) 001bbe: line 1509 define I2C3 ((I2C_TypeDef *) I2C3_BASE) 001be2: line 1510 define I2C4 ((I2C_TypeDef *) I2C4_BASE) 001c06: line 1511 define CAN1 ((CAN_TypeDef *) CAN1_BASE) 001c2a: line 1512 define CAN2 ((CAN_TypeDef *) CAN2_BASE) 001c4e: line 1513 define CEC ((CEC_TypeDef *) CEC_BASE) 001c70: line 1514 define PWR ((PWR_TypeDef *) PWR_BASE) 001c92: line 1515 define DAC ((DAC_TypeDef *) DAC_BASE) 001cb4: line 1516 define UART7 ((USART_TypeDef *) UART7_BASE) 001cdc: line 1517 define UART8 ((USART_TypeDef *) UART8_BASE) 001d04: line 1518 define TIM1 ((TIM_TypeDef *) TIM1_BASE) 001d28: line 1519 define TIM8 ((TIM_TypeDef *) TIM8_BASE) 001d4c: line 1520 define USART1 ((USART_TypeDef *) USART1_BASE) 001d76: line 1521 define USART6 ((USART_TypeDef *) USART6_BASE) 001da0: line 1522 define ADC ((ADC_Common_TypeDef *) ADC_BASE) 001dc9: line 1523 define ADC1 ((ADC_TypeDef *) ADC1_BASE) 001ded: line 1524 define ADC2 ((ADC_TypeDef *) ADC2_BASE) 001e11: line 1525 define ADC3 ((ADC_TypeDef *) ADC3_BASE) 001e35: line 1526 define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) 001e5f: line 1527 define SPI1 ((SPI_TypeDef *) SPI1_BASE) 001e83: line 1528 define SPI4 ((SPI_TypeDef *) SPI4_BASE) 001ea7: line 1529 define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) 001ed2: line 1530 define EXTI ((EXTI_TypeDef *) EXTI_BASE) 001ef7: line 1531 define TIM9 ((TIM_TypeDef *) TIM9_BASE) 001f1b: line 1532 define TIM10 ((TIM_TypeDef *) TIM10_BASE) 001f41: line 1533 define TIM11 ((TIM_TypeDef *) TIM11_BASE) 001f67: line 1534 define SPI5 ((SPI_TypeDef *) SPI5_BASE) 001f8b: line 1535 define SPI6 ((SPI_TypeDef *) SPI6_BASE) 001faf: line 1536 define SAI1 ((SAI_TypeDef *) SAI1_BASE) 001fd3: line 1537 define SAI2 ((SAI_TypeDef *) SAI2_BASE) 001ff7: line 1538 define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) 002030: line 1539 define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) 002069: line 1540 define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) 0020a2: line 1541 define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) 0020db: line 1542 define LTDC ((LTDC_TypeDef *)LTDC_BASE) 0020ff: line 1543 define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) 002137: line 1544 define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) 00216f: line 1545 define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) 002196: line 1546 define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) 0021bd: line 1547 define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) 0021e4: line 1548 define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) 00220b: line 1549 define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) 002232: line 1550 define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) 002259: line 1551 define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) 002280: line 1552 define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) 0022a7: line 1553 define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) 0022ce: line 1554 define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) 0022f5: line 1555 define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) 00231c: line 1556 define CRC ((CRC_TypeDef *) CRC_BASE) 00233e: line 1557 define RCC ((RCC_TypeDef *) RCC_BASE) 002360: line 1558 define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) 00238a: line 1559 define DMA1 ((DMA_TypeDef *) DMA1_BASE) 0023ae: line 1560 define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) 0023e9: line 1561 define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) 002424: line 1562 define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) 00245f: line 1563 define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) 00249a: line 1564 define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) 0024d5: line 1565 define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) 002510: line 1566 define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) 00254b: line 1567 define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) 002586: line 1568 define DMA2 ((DMA_TypeDef *) DMA2_BASE) 0025aa: line 1569 define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) 0025e5: line 1570 define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) 002620: line 1571 define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) 00265b: line 1572 define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) 002696: line 1573 define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) 0026d1: line 1574 define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) 00270c: line 1575 define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) 002747: line 1576 define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) 002782: line 1577 define ETH ((ETH_TypeDef *) ETH_BASE) 0027a4: line 1578 define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) 0027cb: line 1579 define DCMI ((DCMI_TypeDef *) DCMI_BASE) 0027f0: line 1580 define RNG ((RNG_TypeDef *) RNG_BASE) 002812: line 1581 define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) 002848: line 1582 define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) 002881: line 1583 define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) 0028b7: line 1584 define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) 0028f3: line 1585 define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) 002920: line 1586 define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) 00294b: line 1587 define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) 00298c: line 1588 define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) 0029cd: line 1589 define CAN3 ((CAN_TypeDef *) CAN3_BASE) 0029f1: line 1590 define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE) 002a1b: line 1591 define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) 002a43: line 1592 define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE) 002a87: line 1593 define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE) 002acb: line 1594 define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE) 002b0f: line 1595 define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE) 002b53: line 1596 define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE) 002b97: line 1597 define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE) 002bdb: line 1598 define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE) 002c1f: line 1599 define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE) 002c63: line 1600 define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE) 002ca4: line 1601 define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE) 002ce5: line 1602 define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE) 002d26: line 1603 define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE) 002d67: line 1604 define JPEG ((JPEG_TypeDef *) JPEG_BASE) 002d8c: line 1628 define ADC_SR_AWD 0x00000001U 002da6: line 1629 define ADC_SR_EOC 0x00000002U 002dc0: line 1630 define ADC_SR_JEOC 0x00000004U 002ddb: line 1631 define ADC_SR_JSTRT 0x00000008U 002df7: line 1632 define ADC_SR_STRT 0x00000010U 002e12: line 1633 define ADC_SR_OVR 0x00000020U 002e2c: line 1636 define ADC_CR1_AWDCH 0x0000001FU 002e49: line 1637 define ADC_CR1_AWDCH_0 0x00000001U 002e68: line 1638 define ADC_CR1_AWDCH_1 0x00000002U 002e87: line 1639 define ADC_CR1_AWDCH_2 0x00000004U 002ea6: line 1640 define ADC_CR1_AWDCH_3 0x00000008U 002ec5: line 1641 define ADC_CR1_AWDCH_4 0x00000010U 002ee4: line 1642 define ADC_CR1_EOCIE 0x00000020U 002f01: line 1643 define ADC_CR1_AWDIE 0x00000040U 002f1e: line 1644 define ADC_CR1_JEOCIE 0x00000080U 002f3c: line 1645 define ADC_CR1_SCAN 0x00000100U 002f58: line 1646 define ADC_CR1_AWDSGL 0x00000200U 002f76: line 1647 define ADC_CR1_JAUTO 0x00000400U 002f93: line 1648 define ADC_CR1_DISCEN 0x00000800U 002fb1: line 1649 define ADC_CR1_JDISCEN 0x00001000U 002fd0: line 1650 define ADC_CR1_DISCNUM 0x0000E000U 002fef: line 1651 define ADC_CR1_DISCNUM_0 0x00002000U 003010: line 1652 define ADC_CR1_DISCNUM_1 0x00004000U 003031: line 1653 define ADC_CR1_DISCNUM_2 0x00008000U 003052: line 1654 define ADC_CR1_JAWDEN 0x00400000U 003070: line 1655 define ADC_CR1_AWDEN 0x00800000U 00308d: line 1656 define ADC_CR1_RES 0x03000000U 0030a8: line 1657 define ADC_CR1_RES_0 0x01000000U 0030c5: line 1658 define ADC_CR1_RES_1 0x02000000U 0030e2: line 1659 define ADC_CR1_OVRIE 0x04000000U 0030ff: line 1662 define ADC_CR2_ADON 0x00000001U 00311b: line 1663 define ADC_CR2_CONT 0x00000002U 003137: line 1664 define ADC_CR2_DMA 0x00000100U 003152: line 1665 define ADC_CR2_DDS 0x00000200U 00316d: line 1666 define ADC_CR2_EOCS 0x00000400U 003189: line 1667 define ADC_CR2_ALIGN 0x00000800U 0031a6: line 1668 define ADC_CR2_JEXTSEL 0x000F0000U 0031c5: line 1669 define ADC_CR2_JEXTSEL_0 0x00010000U 0031e6: line 1670 define ADC_CR2_JEXTSEL_1 0x00020000U 003207: line 1671 define ADC_CR2_JEXTSEL_2 0x00040000U 003228: line 1672 define ADC_CR2_JEXTSEL_3 0x00080000U 003249: line 1673 define ADC_CR2_JEXTEN 0x00300000U 003267: line 1674 define ADC_CR2_JEXTEN_0 0x00100000U 003287: line 1675 define ADC_CR2_JEXTEN_1 0x00200000U 0032a7: line 1676 define ADC_CR2_JSWSTART 0x00400000U 0032c7: line 1677 define ADC_CR2_EXTSEL 0x0F000000U 0032e5: line 1678 define ADC_CR2_EXTSEL_0 0x01000000U 003305: line 1679 define ADC_CR2_EXTSEL_1 0x02000000U 003325: line 1680 define ADC_CR2_EXTSEL_2 0x04000000U 003345: line 1681 define ADC_CR2_EXTSEL_3 0x08000000U 003365: line 1682 define ADC_CR2_EXTEN 0x30000000U 003382: line 1683 define ADC_CR2_EXTEN_0 0x10000000U 0033a1: line 1684 define ADC_CR2_EXTEN_1 0x20000000U 0033c0: line 1685 define ADC_CR2_SWSTART 0x40000000U 0033df: line 1688 define ADC_SMPR1_SMP10 0x00000007U 0033fe: line 1689 define ADC_SMPR1_SMP10_0 0x00000001U 00341f: line 1690 define ADC_SMPR1_SMP10_1 0x00000002U 003440: line 1691 define ADC_SMPR1_SMP10_2 0x00000004U 003461: line 1692 define ADC_SMPR1_SMP11 0x00000038U 003480: line 1693 define ADC_SMPR1_SMP11_0 0x00000008U 0034a1: line 1694 define ADC_SMPR1_SMP11_1 0x00000010U 0034c2: line 1695 define ADC_SMPR1_SMP11_2 0x00000020U 0034e3: line 1696 define ADC_SMPR1_SMP12 0x000001C0U 003502: line 1697 define ADC_SMPR1_SMP12_0 0x00000040U 003523: line 1698 define ADC_SMPR1_SMP12_1 0x00000080U 003544: line 1699 define ADC_SMPR1_SMP12_2 0x00000100U 003565: line 1700 define ADC_SMPR1_SMP13 0x00000E00U 003584: line 1701 define ADC_SMPR1_SMP13_0 0x00000200U 0035a5: line 1702 define ADC_SMPR1_SMP13_1 0x00000400U 0035c6: line 1703 define ADC_SMPR1_SMP13_2 0x00000800U 0035e7: line 1704 define ADC_SMPR1_SMP14 0x00007000U 003606: line 1705 define ADC_SMPR1_SMP14_0 0x00001000U 003627: line 1706 define ADC_SMPR1_SMP14_1 0x00002000U 003648: line 1707 define ADC_SMPR1_SMP14_2 0x00004000U 003669: line 1708 define ADC_SMPR1_SMP15 0x00038000U 003688: line 1709 define ADC_SMPR1_SMP15_0 0x00008000U 0036a9: line 1710 define ADC_SMPR1_SMP15_1 0x00010000U 0036ca: line 1711 define ADC_SMPR1_SMP15_2 0x00020000U 0036eb: line 1712 define ADC_SMPR1_SMP16 0x001C0000U 00370a: line 1713 define ADC_SMPR1_SMP16_0 0x00040000U 00372b: line 1714 define ADC_SMPR1_SMP16_1 0x00080000U 00374c: line 1715 define ADC_SMPR1_SMP16_2 0x00100000U 00376d: line 1716 define ADC_SMPR1_SMP17 0x00E00000U 00378c: line 1717 define ADC_SMPR1_SMP17_0 0x00200000U 0037ad: line 1718 define ADC_SMPR1_SMP17_1 0x00400000U 0037ce: line 1719 define ADC_SMPR1_SMP17_2 0x00800000U 0037ef: line 1720 define ADC_SMPR1_SMP18 0x07000000U 00380e: line 1721 define ADC_SMPR1_SMP18_0 0x01000000U 00382f: line 1722 define ADC_SMPR1_SMP18_1 0x02000000U 003850: line 1723 define ADC_SMPR1_SMP18_2 0x04000000U 003871: line 1726 define ADC_SMPR2_SMP0 0x00000007U 00388f: line 1727 define ADC_SMPR2_SMP0_0 0x00000001U 0038af: line 1728 define ADC_SMPR2_SMP0_1 0x00000002U 0038cf: line 1729 define ADC_SMPR2_SMP0_2 0x00000004U 0038ef: line 1730 define ADC_SMPR2_SMP1 0x00000038U 00390d: line 1731 define ADC_SMPR2_SMP1_0 0x00000008U 00392d: line 1732 define ADC_SMPR2_SMP1_1 0x00000010U 00394d: line 1733 define ADC_SMPR2_SMP1_2 0x00000020U 00396d: line 1734 define ADC_SMPR2_SMP2 0x000001C0U 00398b: line 1735 define ADC_SMPR2_SMP2_0 0x00000040U 0039ab: line 1736 define ADC_SMPR2_SMP2_1 0x00000080U 0039cb: line 1737 define ADC_SMPR2_SMP2_2 0x00000100U 0039eb: line 1738 define ADC_SMPR2_SMP3 0x00000E00U 003a09: line 1739 define ADC_SMPR2_SMP3_0 0x00000200U 003a29: line 1740 define ADC_SMPR2_SMP3_1 0x00000400U 003a49: line 1741 define ADC_SMPR2_SMP3_2 0x00000800U 003a69: line 1742 define ADC_SMPR2_SMP4 0x00007000U 003a87: line 1743 define ADC_SMPR2_SMP4_0 0x00001000U 003aa7: line 1744 define ADC_SMPR2_SMP4_1 0x00002000U 003ac7: line 1745 define ADC_SMPR2_SMP4_2 0x00004000U 003ae7: line 1746 define ADC_SMPR2_SMP5 0x00038000U 003b05: line 1747 define ADC_SMPR2_SMP5_0 0x00008000U 003b25: line 1748 define ADC_SMPR2_SMP5_1 0x00010000U 003b45: line 1749 define ADC_SMPR2_SMP5_2 0x00020000U 003b65: line 1750 define ADC_SMPR2_SMP6 0x001C0000U 003b83: line 1751 define ADC_SMPR2_SMP6_0 0x00040000U 003ba3: line 1752 define ADC_SMPR2_SMP6_1 0x00080000U 003bc3: line 1753 define ADC_SMPR2_SMP6_2 0x00100000U 003be3: line 1754 define ADC_SMPR2_SMP7 0x00E00000U 003c01: line 1755 define ADC_SMPR2_SMP7_0 0x00200000U 003c21: line 1756 define ADC_SMPR2_SMP7_1 0x00400000U 003c41: line 1757 define ADC_SMPR2_SMP7_2 0x00800000U 003c61: line 1758 define ADC_SMPR2_SMP8 0x07000000U 003c7f: line 1759 define ADC_SMPR2_SMP8_0 0x01000000U 003c9f: line 1760 define ADC_SMPR2_SMP8_1 0x02000000U 003cbf: line 1761 define ADC_SMPR2_SMP8_2 0x04000000U 003cdf: line 1762 define ADC_SMPR2_SMP9 0x38000000U 003cfd: line 1763 define ADC_SMPR2_SMP9_0 0x08000000U 003d1d: line 1764 define ADC_SMPR2_SMP9_1 0x10000000U 003d3d: line 1765 define ADC_SMPR2_SMP9_2 0x20000000U 003d5d: line 1768 define ADC_JOFR1_JOFFSET1 0x0FFFU 003d7b: line 1771 define ADC_JOFR2_JOFFSET2 0x0FFFU 003d99: line 1774 define ADC_JOFR3_JOFFSET3 0x0FFFU 003db7: line 1777 define ADC_JOFR4_JOFFSET4 0x0FFFU 003dd5: line 1780 define ADC_HTR_HT 0x0FFFU 003deb: line 1783 define ADC_LTR_LT 0x0FFFU 003e01: line 1786 define ADC_SQR1_SQ13 0x0000001FU 003e1e: line 1787 define ADC_SQR1_SQ13_0 0x00000001U 003e3d: line 1788 define ADC_SQR1_SQ13_1 0x00000002U 003e5c: line 1789 define ADC_SQR1_SQ13_2 0x00000004U 003e7b: line 1790 define ADC_SQR1_SQ13_3 0x00000008U 003e9a: line 1791 define ADC_SQR1_SQ13_4 0x00000010U 003eb9: line 1792 define ADC_SQR1_SQ14 0x000003E0U 003ed6: line 1793 define ADC_SQR1_SQ14_0 0x00000020U 003ef5: line 1794 define ADC_SQR1_SQ14_1 0x00000040U 003f14: line 1795 define ADC_SQR1_SQ14_2 0x00000080U 003f33: line 1796 define ADC_SQR1_SQ14_3 0x00000100U 003f52: line 1797 define ADC_SQR1_SQ14_4 0x00000200U 003f71: line 1798 define ADC_SQR1_SQ15 0x00007C00U 003f8e: line 1799 define ADC_SQR1_SQ15_0 0x00000400U 003fad: line 1800 define ADC_SQR1_SQ15_1 0x00000800U 003fcc: line 1801 define ADC_SQR1_SQ15_2 0x00001000U 003feb: line 1802 define ADC_SQR1_SQ15_3 0x00002000U 00400a: line 1803 define ADC_SQR1_SQ15_4 0x00004000U 004029: line 1804 define ADC_SQR1_SQ16 0x000F8000U 004046: line 1805 define ADC_SQR1_SQ16_0 0x00008000U 004065: line 1806 define ADC_SQR1_SQ16_1 0x00010000U 004084: line 1807 define ADC_SQR1_SQ16_2 0x00020000U 0040a3: line 1808 define ADC_SQR1_SQ16_3 0x00040000U 0040c2: line 1809 define ADC_SQR1_SQ16_4 0x00080000U 0040e1: line 1810 define ADC_SQR1_L 0x00F00000U 0040fb: line 1811 define ADC_SQR1_L_0 0x00100000U 004117: line 1812 define ADC_SQR1_L_1 0x00200000U 004133: line 1813 define ADC_SQR1_L_2 0x00400000U 00414f: line 1814 define ADC_SQR1_L_3 0x00800000U 00416b: line 1817 define ADC_SQR2_SQ7 0x0000001FU 004187: line 1818 define ADC_SQR2_SQ7_0 0x00000001U 0041a5: line 1819 define ADC_SQR2_SQ7_1 0x00000002U 0041c3: line 1820 define ADC_SQR2_SQ7_2 0x00000004U 0041e1: line 1821 define ADC_SQR2_SQ7_3 0x00000008U 0041ff: line 1822 define ADC_SQR2_SQ7_4 0x00000010U 00421d: line 1823 define ADC_SQR2_SQ8 0x000003E0U 004239: line 1824 define ADC_SQR2_SQ8_0 0x00000020U 004257: line 1825 define ADC_SQR2_SQ8_1 0x00000040U 004275: line 1826 define ADC_SQR2_SQ8_2 0x00000080U 004293: line 1827 define ADC_SQR2_SQ8_3 0x00000100U 0042b1: line 1828 define ADC_SQR2_SQ8_4 0x00000200U 0042cf: line 1829 define ADC_SQR2_SQ9 0x00007C00U 0042eb: line 1830 define ADC_SQR2_SQ9_0 0x00000400U 004309: line 1831 define ADC_SQR2_SQ9_1 0x00000800U 004327: line 1832 define ADC_SQR2_SQ9_2 0x00001000U 004345: line 1833 define ADC_SQR2_SQ9_3 0x00002000U 004363: line 1834 define ADC_SQR2_SQ9_4 0x00004000U 004381: line 1835 define ADC_SQR2_SQ10 0x000F8000U 00439e: line 1836 define ADC_SQR2_SQ10_0 0x00008000U 0043bd: line 1837 define ADC_SQR2_SQ10_1 0x00010000U 0043dc: line 1838 define ADC_SQR2_SQ10_2 0x00020000U 0043fb: line 1839 define ADC_SQR2_SQ10_3 0x00040000U 00441a: line 1840 define ADC_SQR2_SQ10_4 0x00080000U 004439: line 1841 define ADC_SQR2_SQ11 0x01F00000U 004456: line 1842 define ADC_SQR2_SQ11_0 0x00100000U 004475: line 1843 define ADC_SQR2_SQ11_1 0x00200000U 004494: line 1844 define ADC_SQR2_SQ11_2 0x00400000U 0044b3: line 1845 define ADC_SQR2_SQ11_3 0x00800000U 0044d2: line 1846 define ADC_SQR2_SQ11_4 0x01000000U 0044f1: line 1847 define ADC_SQR2_SQ12 0x3E000000U 00450e: line 1848 define ADC_SQR2_SQ12_0 0x02000000U 00452d: line 1849 define ADC_SQR2_SQ12_1 0x04000000U 00454c: line 1850 define ADC_SQR2_SQ12_2 0x08000000U 00456b: line 1851 define ADC_SQR2_SQ12_3 0x10000000U 00458a: line 1852 define ADC_SQR2_SQ12_4 0x20000000U 0045a9: line 1855 define ADC_SQR3_SQ1 0x0000001FU 0045c5: line 1856 define ADC_SQR3_SQ1_0 0x00000001U 0045e3: line 1857 define ADC_SQR3_SQ1_1 0x00000002U 004601: line 1858 define ADC_SQR3_SQ1_2 0x00000004U 00461f: line 1859 define ADC_SQR3_SQ1_3 0x00000008U 00463d: line 1860 define ADC_SQR3_SQ1_4 0x00000010U 00465b: line 1861 define ADC_SQR3_SQ2 0x000003E0U 004677: line 1862 define ADC_SQR3_SQ2_0 0x00000020U 004695: line 1863 define ADC_SQR3_SQ2_1 0x00000040U 0046b3: line 1864 define ADC_SQR3_SQ2_2 0x00000080U 0046d1: line 1865 define ADC_SQR3_SQ2_3 0x00000100U 0046ef: line 1866 define ADC_SQR3_SQ2_4 0x00000200U 00470d: line 1867 define ADC_SQR3_SQ3 0x00007C00U 004729: line 1868 define ADC_SQR3_SQ3_0 0x00000400U 004747: line 1869 define ADC_SQR3_SQ3_1 0x00000800U 004765: line 1870 define ADC_SQR3_SQ3_2 0x00001000U 004783: line 1871 define ADC_SQR3_SQ3_3 0x00002000U 0047a1: line 1872 define ADC_SQR3_SQ3_4 0x00004000U 0047bf: line 1873 define ADC_SQR3_SQ4 0x000F8000U 0047db: line 1874 define ADC_SQR3_SQ4_0 0x00008000U 0047f9: line 1875 define ADC_SQR3_SQ4_1 0x00010000U 004817: line 1876 define ADC_SQR3_SQ4_2 0x00020000U 004835: line 1877 define ADC_SQR3_SQ4_3 0x00040000U 004853: line 1878 define ADC_SQR3_SQ4_4 0x00080000U 004871: line 1879 define ADC_SQR3_SQ5 0x01F00000U 00488d: line 1880 define ADC_SQR3_SQ5_0 0x00100000U 0048ab: line 1881 define ADC_SQR3_SQ5_1 0x00200000U 0048c9: line 1882 define ADC_SQR3_SQ5_2 0x00400000U 0048e7: line 1883 define ADC_SQR3_SQ5_3 0x00800000U 004905: line 1884 define ADC_SQR3_SQ5_4 0x01000000U 004923: line 1885 define ADC_SQR3_SQ6 0x3E000000U 00493f: line 1886 define ADC_SQR3_SQ6_0 0x02000000U 00495d: line 1887 define ADC_SQR3_SQ6_1 0x04000000U 00497b: line 1888 define ADC_SQR3_SQ6_2 0x08000000U 004999: line 1889 define ADC_SQR3_SQ6_3 0x10000000U 0049b7: line 1890 define ADC_SQR3_SQ6_4 0x20000000U 0049d5: line 1893 define ADC_JSQR_JSQ1 0x0000001FU 0049f2: line 1894 define ADC_JSQR_JSQ1_0 0x00000001U 004a11: line 1895 define ADC_JSQR_JSQ1_1 0x00000002U 004a30: line 1896 define ADC_JSQR_JSQ1_2 0x00000004U 004a4f: line 1897 define ADC_JSQR_JSQ1_3 0x00000008U 004a6e: line 1898 define ADC_JSQR_JSQ1_4 0x00000010U 004a8d: line 1899 define ADC_JSQR_JSQ2 0x000003E0U 004aaa: line 1900 define ADC_JSQR_JSQ2_0 0x00000020U 004ac9: line 1901 define ADC_JSQR_JSQ2_1 0x00000040U 004ae8: line 1902 define ADC_JSQR_JSQ2_2 0x00000080U 004b07: line 1903 define ADC_JSQR_JSQ2_3 0x00000100U 004b26: line 1904 define ADC_JSQR_JSQ2_4 0x00000200U 004b45: line 1905 define ADC_JSQR_JSQ3 0x00007C00U 004b62: line 1906 define ADC_JSQR_JSQ3_0 0x00000400U 004b81: line 1907 define ADC_JSQR_JSQ3_1 0x00000800U 004ba0: line 1908 define ADC_JSQR_JSQ3_2 0x00001000U 004bbf: line 1909 define ADC_JSQR_JSQ3_3 0x00002000U 004bde: line 1910 define ADC_JSQR_JSQ3_4 0x00004000U 004bfd: line 1911 define ADC_JSQR_JSQ4 0x000F8000U 004c1a: line 1912 define ADC_JSQR_JSQ4_0 0x00008000U 004c39: line 1913 define ADC_JSQR_JSQ4_1 0x00010000U 004c58: line 1914 define ADC_JSQR_JSQ4_2 0x00020000U 004c77: line 1915 define ADC_JSQR_JSQ4_3 0x00040000U 004c96: line 1916 define ADC_JSQR_JSQ4_4 0x00080000U 004cb5: line 1917 define ADC_JSQR_JL 0x00300000U 004cd0: line 1918 define ADC_JSQR_JL_0 0x00100000U 004ced: line 1919 define ADC_JSQR_JL_1 0x00200000U 004d0a: line 1922 define ADC_JDR1_JDATA ((uint16_t)0xFFFFU) 004d30: line 1925 define ADC_JDR2_JDATA ((uint16_t)0xFFFFU) 004d56: line 1928 define ADC_JDR3_JDATA ((uint16_t)0xFFFFU) 004d7c: line 1931 define ADC_JDR4_JDATA ((uint16_t)0xFFFFU) 004da2: line 1934 define ADC_DR_DATA 0x0000FFFFU 004dbd: line 1935 define ADC_DR_ADC2DATA 0xFFFF0000U 004ddc: line 1938 define ADC_CSR_AWD1 0x00000001U 004df8: line 1939 define ADC_CSR_EOC1 0x00000002U 004e14: line 1940 define ADC_CSR_JEOC1 0x00000004U 004e31: line 1941 define ADC_CSR_JSTRT1 0x00000008U 004e4f: line 1942 define ADC_CSR_STRT1 0x00000010U 004e6c: line 1943 define ADC_CSR_OVR1 0x00000020U 004e88: line 1944 define ADC_CSR_AWD2 0x00000100U 004ea4: line 1945 define ADC_CSR_EOC2 0x00000200U 004ec0: line 1946 define ADC_CSR_JEOC2 0x00000400U 004edd: line 1947 define ADC_CSR_JSTRT2 0x00000800U 004efb: line 1948 define ADC_CSR_STRT2 0x00001000U 004f18: line 1949 define ADC_CSR_OVR2 0x00002000U 004f34: line 1950 define ADC_CSR_AWD3 0x00010000U 004f50: line 1951 define ADC_CSR_EOC3 0x00020000U 004f6c: line 1952 define ADC_CSR_JEOC3 0x00040000U 004f89: line 1953 define ADC_CSR_JSTRT3 0x00080000U 004fa7: line 1954 define ADC_CSR_STRT3 0x00100000U 004fc4: line 1955 define ADC_CSR_OVR3 0x00200000U 004fe0: line 1958 define ADC_CSR_DOVR1 ADC_CSR_OVR1 004ffe: line 1959 define ADC_CSR_DOVR2 ADC_CSR_OVR2 00501c: line 1960 define ADC_CSR_DOVR3 ADC_CSR_OVR3 00503a: line 1964 define ADC_CCR_MULTI 0x0000001FU 005057: line 1965 define ADC_CCR_MULTI_0 0x00000001U 005076: line 1966 define ADC_CCR_MULTI_1 0x00000002U 005095: line 1967 define ADC_CCR_MULTI_2 0x00000004U 0050b4: line 1968 define ADC_CCR_MULTI_3 0x00000008U 0050d3: line 1969 define ADC_CCR_MULTI_4 0x00000010U 0050f2: line 1970 define ADC_CCR_DELAY 0x00000F00U 00510f: line 1971 define ADC_CCR_DELAY_0 0x00000100U 00512e: line 1972 define ADC_CCR_DELAY_1 0x00000200U 00514d: line 1973 define ADC_CCR_DELAY_2 0x00000400U 00516c: line 1974 define ADC_CCR_DELAY_3 0x00000800U 00518b: line 1975 define ADC_CCR_DDS 0x00002000U 0051a6: line 1976 define ADC_CCR_DMA 0x0000C000U 0051c1: line 1977 define ADC_CCR_DMA_0 0x00004000U 0051de: line 1978 define ADC_CCR_DMA_1 0x00008000U 0051fb: line 1979 define ADC_CCR_ADCPRE 0x00030000U 005219: line 1980 define ADC_CCR_ADCPRE_0 0x00010000U 005239: line 1981 define ADC_CCR_ADCPRE_1 0x00020000U 005259: line 1982 define ADC_CCR_VBATE 0x00400000U 005276: line 1983 define ADC_CCR_TSVREFE 0x00800000U 005295: line 1986 define ADC_CDR_DATA1 0x0000FFFFU 0052b2: line 1987 define ADC_CDR_DATA2 0xFFFF0000U 0052cf: line 1996 define CAN_MCR_INRQ 0x00000001U 0052eb: line 1997 define CAN_MCR_SLEEP 0x00000002U 005308: line 1998 define CAN_MCR_TXFP 0x00000004U 005324: line 1999 define CAN_MCR_RFLM 0x00000008U 005340: line 2000 define CAN_MCR_NART 0x00000010U 00535c: line 2001 define CAN_MCR_AWUM 0x00000020U 005378: line 2002 define CAN_MCR_ABOM 0x00000040U 005394: line 2003 define CAN_MCR_TTCM 0x00000080U 0053b0: line 2004 define CAN_MCR_RESET 0x00008000U 0053cd: line 2007 define CAN_MSR_INAK 0x00000001U 0053e9: line 2008 define CAN_MSR_SLAK 0x00000002U 005405: line 2009 define CAN_MSR_ERRI 0x00000004U 005421: line 2010 define CAN_MSR_WKUI 0x00000008U 00543d: line 2011 define CAN_MSR_SLAKI 0x00000010U 00545a: line 2012 define CAN_MSR_TXM 0x00000100U 005475: line 2013 define CAN_MSR_RXM 0x00000200U 005490: line 2014 define CAN_MSR_SAMP 0x00000400U 0054ac: line 2015 define CAN_MSR_RX 0x00000800U 0054c6: line 2018 define CAN_TSR_RQCP0 0x00000001U 0054e3: line 2019 define CAN_TSR_TXOK0 0x00000002U 005500: line 2020 define CAN_TSR_ALST0 0x00000004U 00551d: line 2021 define CAN_TSR_TERR0 0x00000008U 00553a: line 2022 define CAN_TSR_ABRQ0 0x00000080U 005557: line 2023 define CAN_TSR_RQCP1 0x00000100U 005574: line 2024 define CAN_TSR_TXOK1 0x00000200U 005591: line 2025 define CAN_TSR_ALST1 0x00000400U 0055ae: line 2026 define CAN_TSR_TERR1 0x00000800U 0055cb: line 2027 define CAN_TSR_ABRQ1 0x00008000U 0055e8: line 2028 define CAN_TSR_RQCP2 0x00010000U 005605: line 2029 define CAN_TSR_TXOK2 0x00020000U 005622: line 2030 define CAN_TSR_ALST2 0x00040000U 00563f: line 2031 define CAN_TSR_TERR2 0x00080000U 00565c: line 2032 define CAN_TSR_ABRQ2 0x00800000U 005679: line 2033 define CAN_TSR_CODE 0x03000000U 005695: line 2035 define CAN_TSR_TME 0x1C000000U 0056b0: line 2036 define CAN_TSR_TME0 0x04000000U 0056cc: line 2037 define CAN_TSR_TME1 0x08000000U 0056e8: line 2038 define CAN_TSR_TME2 0x10000000U 005704: line 2040 define CAN_TSR_LOW 0xE0000000U 00571f: line 2041 define CAN_TSR_LOW0 0x20000000U 00573b: line 2042 define CAN_TSR_LOW1 0x40000000U 005757: line 2043 define CAN_TSR_LOW2 0x80000000U 005773: line 2046 define CAN_RF0R_FMP0 0x00000003U 005790: line 2047 define CAN_RF0R_FULL0 0x00000008U 0057ae: line 2048 define CAN_RF0R_FOVR0 0x00000010U 0057cc: line 2049 define CAN_RF0R_RFOM0 0x00000020U 0057ea: line 2052 define CAN_RF1R_FMP1 0x00000003U 005807: line 2053 define CAN_RF1R_FULL1 0x00000008U 005825: line 2054 define CAN_RF1R_FOVR1 0x00000010U 005843: line 2055 define CAN_RF1R_RFOM1 0x00000020U 005861: line 2058 define CAN_IER_TMEIE 0x00000001U 00587e: line 2059 define CAN_IER_FMPIE0 0x00000002U 00589c: line 2060 define CAN_IER_FFIE0 0x00000004U 0058b9: line 2061 define CAN_IER_FOVIE0 0x00000008U 0058d7: line 2062 define CAN_IER_FMPIE1 0x00000010U 0058f5: line 2063 define CAN_IER_FFIE1 0x00000020U 005912: line 2064 define CAN_IER_FOVIE1 0x00000040U 005930: line 2065 define CAN_IER_EWGIE 0x00000100U 00594d: line 2066 define CAN_IER_EPVIE 0x00000200U 00596a: line 2067 define CAN_IER_BOFIE 0x00000400U 005987: line 2068 define CAN_IER_LECIE 0x00000800U 0059a4: line 2069 define CAN_IER_ERRIE 0x00008000U 0059c1: line 2070 define CAN_IER_WKUIE 0x00010000U 0059de: line 2071 define CAN_IER_SLKIE 0x00020000U 0059fb: line 2074 define CAN_ESR_EWGF 0x00000001U 005a17: line 2075 define CAN_ESR_EPVF 0x00000002U 005a33: line 2076 define CAN_ESR_BOFF 0x00000004U 005a4f: line 2078 define CAN_ESR_LEC 0x00000070U 005a6a: line 2079 define CAN_ESR_LEC_0 0x00000010U 005a87: line 2080 define CAN_ESR_LEC_1 0x00000020U 005aa4: line 2081 define CAN_ESR_LEC_2 0x00000040U 005ac1: line 2083 define CAN_ESR_TEC 0x00FF0000U 005adc: line 2084 define CAN_ESR_REC 0xFF000000U 005af7: line 2087 define CAN_BTR_BRP 0x000003FFU 005b12: line 2088 define CAN_BTR_TS1 0x000F0000U 005b2d: line 2089 define CAN_BTR_TS1_0 0x00010000U 005b4a: line 2090 define CAN_BTR_TS1_1 0x00020000U 005b67: line 2091 define CAN_BTR_TS1_2 0x00040000U 005b84: line 2092 define CAN_BTR_TS1_3 0x00080000U 005ba1: line 2093 define CAN_BTR_TS2 0x00700000U 005bbc: line 2094 define CAN_BTR_TS2_0 0x00100000U 005bd9: line 2095 define CAN_BTR_TS2_1 0x00200000U 005bf6: line 2096 define CAN_BTR_TS2_2 0x00400000U 005c13: line 2097 define CAN_BTR_SJW 0x03000000U 005c2e: line 2098 define CAN_BTR_SJW_0 0x01000000U 005c4b: line 2099 define CAN_BTR_SJW_1 0x02000000U 005c68: line 2100 define CAN_BTR_LBKM 0x40000000U 005c84: line 2101 define CAN_BTR_SILM 0x80000000U 005ca0: line 2105 define CAN_TI0R_TXRQ 0x00000001U 005cbd: line 2106 define CAN_TI0R_RTR 0x00000002U 005cd9: line 2107 define CAN_TI0R_IDE 0x00000004U 005cf5: line 2108 define CAN_TI0R_EXID 0x001FFFF8U 005d12: line 2109 define CAN_TI0R_STID 0xFFE00000U 005d2f: line 2112 define CAN_TDT0R_DLC 0x0000000FU 005d4c: line 2113 define CAN_TDT0R_TGT 0x00000100U 005d69: line 2114 define CAN_TDT0R_TIME 0xFFFF0000U 005d87: line 2117 define CAN_TDL0R_DATA0 0x000000FFU 005da6: line 2118 define CAN_TDL0R_DATA1 0x0000FF00U 005dc5: line 2119 define CAN_TDL0R_DATA2 0x00FF0000U 005de4: line 2120 define CAN_TDL0R_DATA3 0xFF000000U 005e03: line 2123 define CAN_TDH0R_DATA4 0x000000FFU 005e22: line 2124 define CAN_TDH0R_DATA5 0x0000FF00U 005e41: line 2125 define CAN_TDH0R_DATA6 0x00FF0000U 005e60: line 2126 define CAN_TDH0R_DATA7 0xFF000000U 005e7f: line 2129 define CAN_TI1R_TXRQ 0x00000001U 005e9c: line 2130 define CAN_TI1R_RTR 0x00000002U 005eb8: line 2131 define CAN_TI1R_IDE 0x00000004U 005ed4: line 2132 define CAN_TI1R_EXID 0x001FFFF8U 005ef1: line 2133 define CAN_TI1R_STID 0xFFE00000U 005f0e: line 2136 define CAN_TDT1R_DLC 0x0000000FU 005f2b: line 2137 define CAN_TDT1R_TGT 0x00000100U 005f48: line 2138 define CAN_TDT1R_TIME 0xFFFF0000U 005f66: line 2141 define CAN_TDL1R_DATA0 0x000000FFU 005f85: line 2142 define CAN_TDL1R_DATA1 0x0000FF00U 005fa4: line 2143 define CAN_TDL1R_DATA2 0x00FF0000U 005fc3: line 2144 define CAN_TDL1R_DATA3 0xFF000000U 005fe2: line 2147 define CAN_TDH1R_DATA4 0x000000FFU 006001: line 2148 define CAN_TDH1R_DATA5 0x0000FF00U 006020: line 2149 define CAN_TDH1R_DATA6 0x00FF0000U 00603f: line 2150 define CAN_TDH1R_DATA7 0xFF000000U 00605e: line 2153 define CAN_TI2R_TXRQ 0x00000001U 00607b: line 2154 define CAN_TI2R_RTR 0x00000002U 006097: line 2155 define CAN_TI2R_IDE 0x00000004U 0060b3: line 2156 define CAN_TI2R_EXID 0x001FFFF8U 0060d0: line 2157 define CAN_TI2R_STID 0xFFE00000U 0060ed: line 2160 define CAN_TDT2R_DLC 0x0000000FU 00610a: line 2161 define CAN_TDT2R_TGT 0x00000100U 006127: line 2162 define CAN_TDT2R_TIME 0xFFFF0000U 006145: line 2165 define CAN_TDL2R_DATA0 0x000000FFU 006164: line 2166 define CAN_TDL2R_DATA1 0x0000FF00U 006183: line 2167 define CAN_TDL2R_DATA2 0x00FF0000U 0061a2: line 2168 define CAN_TDL2R_DATA3 0xFF000000U 0061c1: line 2171 define CAN_TDH2R_DATA4 0x000000FFU 0061e0: line 2172 define CAN_TDH2R_DATA5 0x0000FF00U 0061ff: line 2173 define CAN_TDH2R_DATA6 0x00FF0000U 00621e: line 2174 define CAN_TDH2R_DATA7 0xFF000000U 00623d: line 2177 define CAN_RI0R_RTR 0x00000002U 006259: line 2178 define CAN_RI0R_IDE 0x00000004U 006275: line 2179 define CAN_RI0R_EXID 0x001FFFF8U 006292: line 2180 define CAN_RI0R_STID 0xFFE00000U 0062af: line 2183 define CAN_RDT0R_DLC 0x0000000FU 0062cc: line 2184 define CAN_RDT0R_FMI 0x0000FF00U 0062e9: line 2185 define CAN_RDT0R_TIME 0xFFFF0000U 006307: line 2188 define CAN_RDL0R_DATA0 0x000000FFU 006326: line 2189 define CAN_RDL0R_DATA1 0x0000FF00U 006345: line 2190 define CAN_RDL0R_DATA2 0x00FF0000U 006364: line 2191 define CAN_RDL0R_DATA3 0xFF000000U 006383: line 2194 define CAN_RDH0R_DATA4 0x000000FFU 0063a2: line 2195 define CAN_RDH0R_DATA5 0x0000FF00U 0063c1: line 2196 define CAN_RDH0R_DATA6 0x00FF0000U 0063e0: line 2197 define CAN_RDH0R_DATA7 0xFF000000U 0063ff: line 2200 define CAN_RI1R_RTR 0x00000002U 00641b: line 2201 define CAN_RI1R_IDE 0x00000004U 006437: line 2202 define CAN_RI1R_EXID 0x001FFFF8U 006454: line 2203 define CAN_RI1R_STID 0xFFE00000U 006471: line 2206 define CAN_RDT1R_DLC 0x0000000FU 00648e: line 2207 define CAN_RDT1R_FMI 0x0000FF00U 0064ab: line 2208 define CAN_RDT1R_TIME 0xFFFF0000U 0064c9: line 2211 define CAN_RDL1R_DATA0 0x000000FFU 0064e8: line 2212 define CAN_RDL1R_DATA1 0x0000FF00U 006507: line 2213 define CAN_RDL1R_DATA2 0x00FF0000U 006526: line 2214 define CAN_RDL1R_DATA3 0xFF000000U 006545: line 2217 define CAN_RDH1R_DATA4 0x000000FFU 006564: line 2218 define CAN_RDH1R_DATA5 0x0000FF00U 006583: line 2219 define CAN_RDH1R_DATA6 0x00FF0000U 0065a2: line 2220 define CAN_RDH1R_DATA7 0xFF000000U 0065c1: line 2224 define CAN_FMR_FINIT ((uint8_t)0x01U) 0065e3: line 2225 define CAN_FMR_CAN2SB 0x00003F00U 006601: line 2228 define CAN_FM1R_FBM 0x3FFFU 006619: line 2229 define CAN_FM1R_FBM0 0x0001U 006632: line 2230 define CAN_FM1R_FBM1 0x0002U 00664b: line 2231 define CAN_FM1R_FBM2 0x0004U 006664: line 2232 define CAN_FM1R_FBM3 0x0008U 00667d: line 2233 define CAN_FM1R_FBM4 0x0010U 006696: line 2234 define CAN_FM1R_FBM5 0x0020U 0066af: line 2235 define CAN_FM1R_FBM6 0x0040U 0066c8: line 2236 define CAN_FM1R_FBM7 0x0080U 0066e1: line 2237 define CAN_FM1R_FBM8 0x0100U 0066fa: line 2238 define CAN_FM1R_FBM9 0x0200U 006713: line 2239 define CAN_FM1R_FBM10 0x0400U 00672d: line 2240 define CAN_FM1R_FBM11 0x0800U 006747: line 2241 define CAN_FM1R_FBM12 0x1000U 006761: line 2242 define CAN_FM1R_FBM13 0x2000U 00677b: line 2245 define CAN_FS1R_FSC 0x00003FFFU 006797: line 2246 define CAN_FS1R_FSC0 0x00000001U 0067b4: line 2247 define CAN_FS1R_FSC1 0x00000002U 0067d1: line 2248 define CAN_FS1R_FSC2 0x00000004U 0067ee: line 2249 define CAN_FS1R_FSC3 0x00000008U 00680b: line 2250 define CAN_FS1R_FSC4 0x00000010U 006828: line 2251 define CAN_FS1R_FSC5 0x00000020U 006845: line 2252 define CAN_FS1R_FSC6 0x00000040U 006862: line 2253 define CAN_FS1R_FSC7 0x00000080U 00687f: line 2254 define CAN_FS1R_FSC8 0x00000100U 00689c: line 2255 define CAN_FS1R_FSC9 0x00000200U 0068b9: line 2256 define CAN_FS1R_FSC10 0x00000400U 0068d7: line 2257 define CAN_FS1R_FSC11 0x00000800U 0068f5: line 2258 define CAN_FS1R_FSC12 0x00001000U 006913: line 2259 define CAN_FS1R_FSC13 0x00002000U 006931: line 2262 define CAN_FFA1R_FFA 0x00003FFFU 00694e: line 2263 define CAN_FFA1R_FFA0 0x00000001U 00696c: line 2264 define CAN_FFA1R_FFA1 0x00000002U 00698a: line 2265 define CAN_FFA1R_FFA2 0x00000004U 0069a8: line 2266 define CAN_FFA1R_FFA3 0x00000008U 0069c6: line 2267 define CAN_FFA1R_FFA4 0x00000010U 0069e4: line 2268 define CAN_FFA1R_FFA5 0x00000020U 006a02: line 2269 define CAN_FFA1R_FFA6 0x00000040U 006a20: line 2270 define CAN_FFA1R_FFA7 0x00000080U 006a3e: line 2271 define CAN_FFA1R_FFA8 0x00000100U 006a5c: line 2272 define CAN_FFA1R_FFA9 0x00000200U 006a7a: line 2273 define CAN_FFA1R_FFA10 0x00000400U 006a99: line 2274 define CAN_FFA1R_FFA11 0x00000800U 006ab8: line 2275 define CAN_FFA1R_FFA12 0x00001000U 006ad7: line 2276 define CAN_FFA1R_FFA13 0x00002000U 006af6: line 2279 define CAN_FA1R_FACT 0x00003FFFU 006b13: line 2280 define CAN_FA1R_FACT0 0x00000001U 006b31: line 2281 define CAN_FA1R_FACT1 0x00000002U 006b4f: line 2282 define CAN_FA1R_FACT2 0x00000004U 006b6d: line 2283 define CAN_FA1R_FACT3 0x00000008U 006b8b: line 2284 define CAN_FA1R_FACT4 0x00000010U 006ba9: line 2285 define CAN_FA1R_FACT5 0x00000020U 006bc7: line 2286 define CAN_FA1R_FACT6 0x00000040U 006be5: line 2287 define CAN_FA1R_FACT7 0x00000080U 006c03: line 2288 define CAN_FA1R_FACT8 0x00000100U 006c21: line 2289 define CAN_FA1R_FACT9 0x00000200U 006c3f: line 2290 define CAN_FA1R_FACT10 0x00000400U 006c5e: line 2291 define CAN_FA1R_FACT11 0x00000800U 006c7d: line 2292 define CAN_FA1R_FACT12 0x00001000U 006c9c: line 2293 define CAN_FA1R_FACT13 0x00002000U 006cbb: line 2296 define CAN_F0R1_FB0 0x00000001U 006cd7: line 2297 define CAN_F0R1_FB1 0x00000002U 006cf3: line 2298 define CAN_F0R1_FB2 0x00000004U 006d0f: line 2299 define CAN_F0R1_FB3 0x00000008U 006d2b: line 2300 define CAN_F0R1_FB4 0x00000010U 006d47: line 2301 define CAN_F0R1_FB5 0x00000020U 006d63: line 2302 define CAN_F0R1_FB6 0x00000040U 006d7f: line 2303 define CAN_F0R1_FB7 0x00000080U 006d9b: line 2304 define CAN_F0R1_FB8 0x00000100U 006db7: line 2305 define CAN_F0R1_FB9 0x00000200U 006dd3: line 2306 define CAN_F0R1_FB10 0x00000400U 006df0: line 2307 define CAN_F0R1_FB11 0x00000800U 006e0d: line 2308 define CAN_F0R1_FB12 0x00001000U 006e2a: line 2309 define CAN_F0R1_FB13 0x00002000U 006e47: line 2310 define CAN_F0R1_FB14 0x00004000U 006e64: line 2311 define CAN_F0R1_FB15 0x00008000U 006e81: line 2312 define CAN_F0R1_FB16 0x00010000U 006e9e: line 2313 define CAN_F0R1_FB17 0x00020000U 006ebb: line 2314 define CAN_F0R1_FB18 0x00040000U 006ed8: line 2315 define CAN_F0R1_FB19 0x00080000U 006ef5: line 2316 define CAN_F0R1_FB20 0x00100000U 006f12: line 2317 define CAN_F0R1_FB21 0x00200000U 006f2f: line 2318 define CAN_F0R1_FB22 0x00400000U 006f4c: line 2319 define CAN_F0R1_FB23 0x00800000U 006f69: line 2320 define CAN_F0R1_FB24 0x01000000U 006f86: line 2321 define CAN_F0R1_FB25 0x02000000U 006fa3: line 2322 define CAN_F0R1_FB26 0x04000000U 006fc0: line 2323 define CAN_F0R1_FB27 0x08000000U 006fdd: line 2324 define CAN_F0R1_FB28 0x10000000U 006ffa: line 2325 define CAN_F0R1_FB29 0x20000000U 007017: line 2326 define CAN_F0R1_FB30 0x40000000U 007034: line 2327 define CAN_F0R1_FB31 0x80000000U 007051: line 2330 define CAN_F1R1_FB0 0x00000001U 00706d: line 2331 define CAN_F1R1_FB1 0x00000002U 007089: line 2332 define CAN_F1R1_FB2 0x00000004U 0070a5: line 2333 define CAN_F1R1_FB3 0x00000008U 0070c1: line 2334 define CAN_F1R1_FB4 0x00000010U 0070dd: line 2335 define CAN_F1R1_FB5 0x00000020U 0070f9: line 2336 define CAN_F1R1_FB6 0x00000040U 007115: line 2337 define CAN_F1R1_FB7 0x00000080U 007131: line 2338 define CAN_F1R1_FB8 0x00000100U 00714d: line 2339 define CAN_F1R1_FB9 0x00000200U 007169: line 2340 define CAN_F1R1_FB10 0x00000400U 007186: line 2341 define CAN_F1R1_FB11 0x00000800U 0071a3: line 2342 define CAN_F1R1_FB12 0x00001000U 0071c0: line 2343 define CAN_F1R1_FB13 0x00002000U 0071dd: line 2344 define CAN_F1R1_FB14 0x00004000U 0071fa: line 2345 define CAN_F1R1_FB15 0x00008000U 007217: line 2346 define CAN_F1R1_FB16 0x00010000U 007234: line 2347 define CAN_F1R1_FB17 0x00020000U 007251: line 2348 define CAN_F1R1_FB18 0x00040000U 00726e: line 2349 define CAN_F1R1_FB19 0x00080000U 00728b: line 2350 define CAN_F1R1_FB20 0x00100000U 0072a8: line 2351 define CAN_F1R1_FB21 0x00200000U 0072c5: line 2352 define CAN_F1R1_FB22 0x00400000U 0072e2: line 2353 define CAN_F1R1_FB23 0x00800000U 0072ff: line 2354 define CAN_F1R1_FB24 0x01000000U 00731c: line 2355 define CAN_F1R1_FB25 0x02000000U 007339: line 2356 define CAN_F1R1_FB26 0x04000000U 007356: line 2357 define CAN_F1R1_FB27 0x08000000U 007373: line 2358 define CAN_F1R1_FB28 0x10000000U 007390: line 2359 define CAN_F1R1_FB29 0x20000000U 0073ad: line 2360 define CAN_F1R1_FB30 0x40000000U 0073ca: line 2361 define CAN_F1R1_FB31 0x80000000U 0073e7: line 2364 define CAN_F2R1_FB0 0x00000001U 007403: line 2365 define CAN_F2R1_FB1 0x00000002U 00741f: line 2366 define CAN_F2R1_FB2 0x00000004U 00743b: line 2367 define CAN_F2R1_FB3 0x00000008U 007457: line 2368 define CAN_F2R1_FB4 0x00000010U 007473: line 2369 define CAN_F2R1_FB5 0x00000020U 00748f: line 2370 define CAN_F2R1_FB6 0x00000040U 0074ab: line 2371 define CAN_F2R1_FB7 0x00000080U 0074c7: line 2372 define CAN_F2R1_FB8 0x00000100U 0074e3: line 2373 define CAN_F2R1_FB9 0x00000200U 0074ff: line 2374 define CAN_F2R1_FB10 0x00000400U 00751c: line 2375 define CAN_F2R1_FB11 0x00000800U 007539: line 2376 define CAN_F2R1_FB12 0x00001000U 007556: line 2377 define CAN_F2R1_FB13 0x00002000U 007573: line 2378 define CAN_F2R1_FB14 0x00004000U 007590: line 2379 define CAN_F2R1_FB15 0x00008000U 0075ad: line 2380 define CAN_F2R1_FB16 0x00010000U 0075ca: line 2381 define CAN_F2R1_FB17 0x00020000U 0075e7: line 2382 define CAN_F2R1_FB18 0x00040000U 007604: line 2383 define CAN_F2R1_FB19 0x00080000U 007621: line 2384 define CAN_F2R1_FB20 0x00100000U 00763e: line 2385 define CAN_F2R1_FB21 0x00200000U 00765b: line 2386 define CAN_F2R1_FB22 0x00400000U 007678: line 2387 define CAN_F2R1_FB23 0x00800000U 007695: line 2388 define CAN_F2R1_FB24 0x01000000U 0076b2: line 2389 define CAN_F2R1_FB25 0x02000000U 0076cf: line 2390 define CAN_F2R1_FB26 0x04000000U 0076ec: line 2391 define CAN_F2R1_FB27 0x08000000U 007709: line 2392 define CAN_F2R1_FB28 0x10000000U 007726: line 2393 define CAN_F2R1_FB29 0x20000000U 007743: line 2394 define CAN_F2R1_FB30 0x40000000U 007760: line 2395 define CAN_F2R1_FB31 0x80000000U 00777d: line 2398 define CAN_F3R1_FB0 0x00000001U 007799: line 2399 define CAN_F3R1_FB1 0x00000002U 0077b5: line 2400 define CAN_F3R1_FB2 0x00000004U 0077d1: line 2401 define CAN_F3R1_FB3 0x00000008U 0077ed: line 2402 define CAN_F3R1_FB4 0x00000010U 007809: line 2403 define CAN_F3R1_FB5 0x00000020U 007825: line 2404 define CAN_F3R1_FB6 0x00000040U 007841: line 2405 define CAN_F3R1_FB7 0x00000080U 00785d: line 2406 define CAN_F3R1_FB8 0x00000100U 007879: line 2407 define CAN_F3R1_FB9 0x00000200U 007895: line 2408 define CAN_F3R1_FB10 0x00000400U 0078b2: line 2409 define CAN_F3R1_FB11 0x00000800U 0078cf: line 2410 define CAN_F3R1_FB12 0x00001000U 0078ec: line 2411 define CAN_F3R1_FB13 0x00002000U 007909: line 2412 define CAN_F3R1_FB14 0x00004000U 007926: line 2413 define CAN_F3R1_FB15 0x00008000U 007943: line 2414 define CAN_F3R1_FB16 0x00010000U 007960: line 2415 define CAN_F3R1_FB17 0x00020000U 00797d: line 2416 define CAN_F3R1_FB18 0x00040000U 00799a: line 2417 define CAN_F3R1_FB19 0x00080000U 0079b7: line 2418 define CAN_F3R1_FB20 0x00100000U 0079d4: line 2419 define CAN_F3R1_FB21 0x00200000U 0079f1: line 2420 define CAN_F3R1_FB22 0x00400000U 007a0e: line 2421 define CAN_F3R1_FB23 0x00800000U 007a2b: line 2422 define CAN_F3R1_FB24 0x01000000U 007a48: line 2423 define CAN_F3R1_FB25 0x02000000U 007a65: line 2424 define CAN_F3R1_FB26 0x04000000U 007a82: line 2425 define CAN_F3R1_FB27 0x08000000U 007a9f: line 2426 define CAN_F3R1_FB28 0x10000000U 007abc: line 2427 define CAN_F3R1_FB29 0x20000000U 007ad9: line 2428 define CAN_F3R1_FB30 0x40000000U 007af6: line 2429 define CAN_F3R1_FB31 0x80000000U 007b13: line 2432 define CAN_F4R1_FB0 0x00000001U 007b2f: line 2433 define CAN_F4R1_FB1 0x00000002U 007b4b: line 2434 define CAN_F4R1_FB2 0x00000004U 007b67: line 2435 define CAN_F4R1_FB3 0x00000008U 007b83: line 2436 define CAN_F4R1_FB4 0x00000010U 007b9f: line 2437 define CAN_F4R1_FB5 0x00000020U 007bbb: line 2438 define CAN_F4R1_FB6 0x00000040U 007bd7: line 2439 define CAN_F4R1_FB7 0x00000080U 007bf3: line 2440 define CAN_F4R1_FB8 0x00000100U 007c0f: line 2441 define CAN_F4R1_FB9 0x00000200U 007c2b: line 2442 define CAN_F4R1_FB10 0x00000400U 007c48: line 2443 define CAN_F4R1_FB11 0x00000800U 007c65: line 2444 define CAN_F4R1_FB12 0x00001000U 007c82: line 2445 define CAN_F4R1_FB13 0x00002000U 007c9f: line 2446 define CAN_F4R1_FB14 0x00004000U 007cbc: line 2447 define CAN_F4R1_FB15 0x00008000U 007cd9: line 2448 define CAN_F4R1_FB16 0x00010000U 007cf6: line 2449 define CAN_F4R1_FB17 0x00020000U 007d13: line 2450 define CAN_F4R1_FB18 0x00040000U 007d30: line 2451 define CAN_F4R1_FB19 0x00080000U 007d4d: line 2452 define CAN_F4R1_FB20 0x00100000U 007d6a: line 2453 define CAN_F4R1_FB21 0x00200000U 007d87: line 2454 define CAN_F4R1_FB22 0x00400000U 007da4: line 2455 define CAN_F4R1_FB23 0x00800000U 007dc1: line 2456 define CAN_F4R1_FB24 0x01000000U 007dde: line 2457 define CAN_F4R1_FB25 0x02000000U 007dfb: line 2458 define CAN_F4R1_FB26 0x04000000U 007e18: line 2459 define CAN_F4R1_FB27 0x08000000U 007e35: line 2460 define CAN_F4R1_FB28 0x10000000U 007e52: line 2461 define CAN_F4R1_FB29 0x20000000U 007e6f: line 2462 define CAN_F4R1_FB30 0x40000000U 007e8c: line 2463 define CAN_F4R1_FB31 0x80000000U 007ea9: line 2466 define CAN_F5R1_FB0 0x00000001U 007ec5: line 2467 define CAN_F5R1_FB1 0x00000002U 007ee1: line 2468 define CAN_F5R1_FB2 0x00000004U 007efd: line 2469 define CAN_F5R1_FB3 0x00000008U 007f19: line 2470 define CAN_F5R1_FB4 0x00000010U 007f35: line 2471 define CAN_F5R1_FB5 0x00000020U 007f51: line 2472 define CAN_F5R1_FB6 0x00000040U 007f6d: line 2473 define CAN_F5R1_FB7 0x00000080U 007f89: line 2474 define CAN_F5R1_FB8 0x00000100U 007fa5: line 2475 define CAN_F5R1_FB9 0x00000200U 007fc1: line 2476 define CAN_F5R1_FB10 0x00000400U 007fde: line 2477 define CAN_F5R1_FB11 0x00000800U 007ffb: line 2478 define CAN_F5R1_FB12 0x00001000U 008018: line 2479 define CAN_F5R1_FB13 0x00002000U 008035: line 2480 define CAN_F5R1_FB14 0x00004000U 008052: line 2481 define CAN_F5R1_FB15 0x00008000U 00806f: line 2482 define CAN_F5R1_FB16 0x00010000U 00808c: line 2483 define CAN_F5R1_FB17 0x00020000U 0080a9: line 2484 define CAN_F5R1_FB18 0x00040000U 0080c6: line 2485 define CAN_F5R1_FB19 0x00080000U 0080e3: line 2486 define CAN_F5R1_FB20 0x00100000U 008100: line 2487 define CAN_F5R1_FB21 0x00200000U 00811d: line 2488 define CAN_F5R1_FB22 0x00400000U 00813a: line 2489 define CAN_F5R1_FB23 0x00800000U 008157: line 2490 define CAN_F5R1_FB24 0x01000000U 008174: line 2491 define CAN_F5R1_FB25 0x02000000U 008191: line 2492 define CAN_F5R1_FB26 0x04000000U 0081ae: line 2493 define CAN_F5R1_FB27 0x08000000U 0081cb: line 2494 define CAN_F5R1_FB28 0x10000000U 0081e8: line 2495 define CAN_F5R1_FB29 0x20000000U 008205: line 2496 define CAN_F5R1_FB30 0x40000000U 008222: line 2497 define CAN_F5R1_FB31 0x80000000U 00823f: line 2500 define CAN_F6R1_FB0 0x00000001U 00825b: line 2501 define CAN_F6R1_FB1 0x00000002U 008277: line 2502 define CAN_F6R1_FB2 0x00000004U 008293: line 2503 define CAN_F6R1_FB3 0x00000008U 0082af: line 2504 define CAN_F6R1_FB4 0x00000010U 0082cb: line 2505 define CAN_F6R1_FB5 0x00000020U 0082e7: line 2506 define CAN_F6R1_FB6 0x00000040U 008303: line 2507 define CAN_F6R1_FB7 0x00000080U 00831f: line 2508 define CAN_F6R1_FB8 0x00000100U 00833b: line 2509 define CAN_F6R1_FB9 0x00000200U 008357: line 2510 define CAN_F6R1_FB10 0x00000400U 008374: line 2511 define CAN_F6R1_FB11 0x00000800U 008391: line 2512 define CAN_F6R1_FB12 0x00001000U 0083ae: line 2513 define CAN_F6R1_FB13 0x00002000U 0083cb: line 2514 define CAN_F6R1_FB14 0x00004000U 0083e8: line 2515 define CAN_F6R1_FB15 0x00008000U 008405: line 2516 define CAN_F6R1_FB16 0x00010000U 008422: line 2517 define CAN_F6R1_FB17 0x00020000U 00843f: line 2518 define CAN_F6R1_FB18 0x00040000U 00845c: line 2519 define CAN_F6R1_FB19 0x00080000U 008479: line 2520 define CAN_F6R1_FB20 0x00100000U 008496: line 2521 define CAN_F6R1_FB21 0x00200000U 0084b3: line 2522 define CAN_F6R1_FB22 0x00400000U 0084d0: line 2523 define CAN_F6R1_FB23 0x00800000U 0084ed: line 2524 define CAN_F6R1_FB24 0x01000000U 00850a: line 2525 define CAN_F6R1_FB25 0x02000000U 008527: line 2526 define CAN_F6R1_FB26 0x04000000U 008544: line 2527 define CAN_F6R1_FB27 0x08000000U 008561: line 2528 define CAN_F6R1_FB28 0x10000000U 00857e: line 2529 define CAN_F6R1_FB29 0x20000000U 00859b: line 2530 define CAN_F6R1_FB30 0x40000000U 0085b8: line 2531 define CAN_F6R1_FB31 0x80000000U 0085d5: line 2534 define CAN_F7R1_FB0 0x00000001U 0085f1: line 2535 define CAN_F7R1_FB1 0x00000002U 00860d: line 2536 define CAN_F7R1_FB2 0x00000004U 008629: line 2537 define CAN_F7R1_FB3 0x00000008U 008645: line 2538 define CAN_F7R1_FB4 0x00000010U 008661: line 2539 define CAN_F7R1_FB5 0x00000020U 00867d: line 2540 define CAN_F7R1_FB6 0x00000040U 008699: line 2541 define CAN_F7R1_FB7 0x00000080U 0086b5: line 2542 define CAN_F7R1_FB8 0x00000100U 0086d1: line 2543 define CAN_F7R1_FB9 0x00000200U 0086ed: line 2544 define CAN_F7R1_FB10 0x00000400U 00870a: line 2545 define CAN_F7R1_FB11 0x00000800U 008727: line 2546 define CAN_F7R1_FB12 0x00001000U 008744: line 2547 define CAN_F7R1_FB13 0x00002000U 008761: line 2548 define CAN_F7R1_FB14 0x00004000U 00877e: line 2549 define CAN_F7R1_FB15 0x00008000U 00879b: line 2550 define CAN_F7R1_FB16 0x00010000U 0087b8: line 2551 define CAN_F7R1_FB17 0x00020000U 0087d5: line 2552 define CAN_F7R1_FB18 0x00040000U 0087f2: line 2553 define CAN_F7R1_FB19 0x00080000U 00880f: line 2554 define CAN_F7R1_FB20 0x00100000U 00882c: line 2555 define CAN_F7R1_FB21 0x00200000U 008849: line 2556 define CAN_F7R1_FB22 0x00400000U 008866: line 2557 define CAN_F7R1_FB23 0x00800000U 008883: line 2558 define CAN_F7R1_FB24 0x01000000U 0088a0: line 2559 define CAN_F7R1_FB25 0x02000000U 0088bd: line 2560 define CAN_F7R1_FB26 0x04000000U 0088da: line 2561 define CAN_F7R1_FB27 0x08000000U 0088f7: line 2562 define CAN_F7R1_FB28 0x10000000U 008914: line 2563 define CAN_F7R1_FB29 0x20000000U 008931: line 2564 define CAN_F7R1_FB30 0x40000000U 00894e: line 2565 define CAN_F7R1_FB31 0x80000000U 00896b: line 2568 define CAN_F8R1_FB0 0x00000001U 008987: line 2569 define CAN_F8R1_FB1 0x00000002U 0089a3: line 2570 define CAN_F8R1_FB2 0x00000004U 0089bf: line 2571 define CAN_F8R1_FB3 0x00000008U 0089db: line 2572 define CAN_F8R1_FB4 0x00000010U 0089f7: line 2573 define CAN_F8R1_FB5 0x00000020U 008a13: line 2574 define CAN_F8R1_FB6 0x00000040U 008a2f: line 2575 define CAN_F8R1_FB7 0x00000080U 008a4b: line 2576 define CAN_F8R1_FB8 0x00000100U 008a67: line 2577 define CAN_F8R1_FB9 0x00000200U 008a83: line 2578 define CAN_F8R1_FB10 0x00000400U 008aa0: line 2579 define CAN_F8R1_FB11 0x00000800U 008abd: line 2580 define CAN_F8R1_FB12 0x00001000U 008ada: line 2581 define CAN_F8R1_FB13 0x00002000U 008af7: line 2582 define CAN_F8R1_FB14 0x00004000U 008b14: line 2583 define CAN_F8R1_FB15 0x00008000U 008b31: line 2584 define CAN_F8R1_FB16 0x00010000U 008b4e: line 2585 define CAN_F8R1_FB17 0x00020000U 008b6b: line 2586 define CAN_F8R1_FB18 0x00040000U 008b88: line 2587 define CAN_F8R1_FB19 0x00080000U 008ba5: line 2588 define CAN_F8R1_FB20 0x00100000U 008bc2: line 2589 define CAN_F8R1_FB21 0x00200000U 008bdf: line 2590 define CAN_F8R1_FB22 0x00400000U 008bfc: line 2591 define CAN_F8R1_FB23 0x00800000U 008c19: line 2592 define CAN_F8R1_FB24 0x01000000U 008c36: line 2593 define CAN_F8R1_FB25 0x02000000U 008c53: line 2594 define CAN_F8R1_FB26 0x04000000U 008c70: line 2595 define CAN_F8R1_FB27 0x08000000U 008c8d: line 2596 define CAN_F8R1_FB28 0x10000000U 008caa: line 2597 define CAN_F8R1_FB29 0x20000000U 008cc7: line 2598 define CAN_F8R1_FB30 0x40000000U 008ce4: line 2599 define CAN_F8R1_FB31 0x80000000U 008d01: line 2602 define CAN_F9R1_FB0 0x00000001U 008d1d: line 2603 define CAN_F9R1_FB1 0x00000002U 008d39: line 2604 define CAN_F9R1_FB2 0x00000004U 008d55: line 2605 define CAN_F9R1_FB3 0x00000008U 008d71: line 2606 define CAN_F9R1_FB4 0x00000010U 008d8d: line 2607 define CAN_F9R1_FB5 0x00000020U 008da9: line 2608 define CAN_F9R1_FB6 0x00000040U 008dc5: line 2609 define CAN_F9R1_FB7 0x00000080U 008de1: line 2610 define CAN_F9R1_FB8 0x00000100U 008dfd: line 2611 define CAN_F9R1_FB9 0x00000200U 008e19: line 2612 define CAN_F9R1_FB10 0x00000400U 008e36: line 2613 define CAN_F9R1_FB11 0x00000800U 008e53: line 2614 define CAN_F9R1_FB12 0x00001000U 008e70: line 2615 define CAN_F9R1_FB13 0x00002000U 008e8d: line 2616 define CAN_F9R1_FB14 0x00004000U 008eaa: line 2617 define CAN_F9R1_FB15 0x00008000U 008ec7: line 2618 define CAN_F9R1_FB16 0x00010000U 008ee4: line 2619 define CAN_F9R1_FB17 0x00020000U 008f01: line 2620 define CAN_F9R1_FB18 0x00040000U 008f1e: line 2621 define CAN_F9R1_FB19 0x00080000U 008f3b: line 2622 define CAN_F9R1_FB20 0x00100000U 008f58: line 2623 define CAN_F9R1_FB21 0x00200000U 008f75: line 2624 define CAN_F9R1_FB22 0x00400000U 008f92: line 2625 define CAN_F9R1_FB23 0x00800000U 008faf: line 2626 define CAN_F9R1_FB24 0x01000000U 008fcc: line 2627 define CAN_F9R1_FB25 0x02000000U 008fe9: line 2628 define CAN_F9R1_FB26 0x04000000U 009006: line 2629 define CAN_F9R1_FB27 0x08000000U 009023: line 2630 define CAN_F9R1_FB28 0x10000000U 009040: line 2631 define CAN_F9R1_FB29 0x20000000U 00905d: line 2632 define CAN_F9R1_FB30 0x40000000U 00907a: line 2633 define CAN_F9R1_FB31 0x80000000U 009097: line 2636 define CAN_F10R1_FB0 0x00000001U 0090b4: line 2637 define CAN_F10R1_FB1 0x00000002U 0090d1: line 2638 define CAN_F10R1_FB2 0x00000004U 0090ee: line 2639 define CAN_F10R1_FB3 0x00000008U 00910b: line 2640 define CAN_F10R1_FB4 0x00000010U 009128: line 2641 define CAN_F10R1_FB5 0x00000020U 009145: line 2642 define CAN_F10R1_FB6 0x00000040U 009162: line 2643 define CAN_F10R1_FB7 0x00000080U 00917f: line 2644 define CAN_F10R1_FB8 0x00000100U 00919c: line 2645 define CAN_F10R1_FB9 0x00000200U 0091b9: line 2646 define CAN_F10R1_FB10 0x00000400U 0091d7: line 2647 define CAN_F10R1_FB11 0x00000800U 0091f5: line 2648 define CAN_F10R1_FB12 0x00001000U 009213: line 2649 define CAN_F10R1_FB13 0x00002000U 009231: line 2650 define CAN_F10R1_FB14 0x00004000U 00924f: line 2651 define CAN_F10R1_FB15 0x00008000U 00926d: line 2652 define CAN_F10R1_FB16 0x00010000U 00928b: line 2653 define CAN_F10R1_FB17 0x00020000U 0092a9: line 2654 define CAN_F10R1_FB18 0x00040000U 0092c7: line 2655 define CAN_F10R1_FB19 0x00080000U 0092e5: line 2656 define CAN_F10R1_FB20 0x00100000U 009303: line 2657 define CAN_F10R1_FB21 0x00200000U 009321: line 2658 define CAN_F10R1_FB22 0x00400000U 00933f: line 2659 define CAN_F10R1_FB23 0x00800000U 00935d: line 2660 define CAN_F10R1_FB24 0x01000000U 00937b: line 2661 define CAN_F10R1_FB25 0x02000000U 009399: line 2662 define CAN_F10R1_FB26 0x04000000U 0093b7: line 2663 define CAN_F10R1_FB27 0x08000000U 0093d5: line 2664 define CAN_F10R1_FB28 0x10000000U 0093f3: line 2665 define CAN_F10R1_FB29 0x20000000U 009411: line 2666 define CAN_F10R1_FB30 0x40000000U 00942f: line 2667 define CAN_F10R1_FB31 0x80000000U 00944d: line 2670 define CAN_F11R1_FB0 0x00000001U 00946a: line 2671 define CAN_F11R1_FB1 0x00000002U 009487: line 2672 define CAN_F11R1_FB2 0x00000004U 0094a4: line 2673 define CAN_F11R1_FB3 0x00000008U 0094c1: line 2674 define CAN_F11R1_FB4 0x00000010U 0094de: line 2675 define CAN_F11R1_FB5 0x00000020U 0094fb: line 2676 define CAN_F11R1_FB6 0x00000040U 009518: line 2677 define CAN_F11R1_FB7 0x00000080U 009535: line 2678 define CAN_F11R1_FB8 0x00000100U 009552: line 2679 define CAN_F11R1_FB9 0x00000200U 00956f: line 2680 define CAN_F11R1_FB10 0x00000400U 00958d: line 2681 define CAN_F11R1_FB11 0x00000800U 0095ab: line 2682 define CAN_F11R1_FB12 0x00001000U 0095c9: line 2683 define CAN_F11R1_FB13 0x00002000U 0095e7: line 2684 define CAN_F11R1_FB14 0x00004000U 009605: line 2685 define CAN_F11R1_FB15 0x00008000U 009623: line 2686 define CAN_F11R1_FB16 0x00010000U 009641: line 2687 define CAN_F11R1_FB17 0x00020000U 00965f: line 2688 define CAN_F11R1_FB18 0x00040000U 00967d: line 2689 define CAN_F11R1_FB19 0x00080000U 00969b: line 2690 define CAN_F11R1_FB20 0x00100000U 0096b9: line 2691 define CAN_F11R1_FB21 0x00200000U 0096d7: line 2692 define CAN_F11R1_FB22 0x00400000U 0096f5: line 2693 define CAN_F11R1_FB23 0x00800000U 009713: line 2694 define CAN_F11R1_FB24 0x01000000U 009731: line 2695 define CAN_F11R1_FB25 0x02000000U 00974f: line 2696 define CAN_F11R1_FB26 0x04000000U 00976d: line 2697 define CAN_F11R1_FB27 0x08000000U 00978b: line 2698 define CAN_F11R1_FB28 0x10000000U 0097a9: line 2699 define CAN_F11R1_FB29 0x20000000U 0097c7: line 2700 define CAN_F11R1_FB30 0x40000000U 0097e5: line 2701 define CAN_F11R1_FB31 0x80000000U 009803: line 2704 define CAN_F12R1_FB0 0x00000001U 009820: line 2705 define CAN_F12R1_FB1 0x00000002U 00983d: line 2706 define CAN_F12R1_FB2 0x00000004U 00985a: line 2707 define CAN_F12R1_FB3 0x00000008U 009877: line 2708 define CAN_F12R1_FB4 0x00000010U 009894: line 2709 define CAN_F12R1_FB5 0x00000020U 0098b1: line 2710 define CAN_F12R1_FB6 0x00000040U 0098ce: line 2711 define CAN_F12R1_FB7 0x00000080U 0098eb: line 2712 define CAN_F12R1_FB8 0x00000100U 009908: line 2713 define CAN_F12R1_FB9 0x00000200U 009925: line 2714 define CAN_F12R1_FB10 0x00000400U 009943: line 2715 define CAN_F12R1_FB11 0x00000800U 009961: line 2716 define CAN_F12R1_FB12 0x00001000U 00997f: line 2717 define CAN_F12R1_FB13 0x00002000U 00999d: line 2718 define CAN_F12R1_FB14 0x00004000U 0099bb: line 2719 define CAN_F12R1_FB15 0x00008000U 0099d9: line 2720 define CAN_F12R1_FB16 0x00010000U 0099f7: line 2721 define CAN_F12R1_FB17 0x00020000U 009a15: line 2722 define CAN_F12R1_FB18 0x00040000U 009a33: line 2723 define CAN_F12R1_FB19 0x00080000U 009a51: line 2724 define CAN_F12R1_FB20 0x00100000U 009a6f: line 2725 define CAN_F12R1_FB21 0x00200000U 009a8d: line 2726 define CAN_F12R1_FB22 0x00400000U 009aab: line 2727 define CAN_F12R1_FB23 0x00800000U 009ac9: line 2728 define CAN_F12R1_FB24 0x01000000U 009ae7: line 2729 define CAN_F12R1_FB25 0x02000000U 009b05: line 2730 define CAN_F12R1_FB26 0x04000000U 009b23: line 2731 define CAN_F12R1_FB27 0x08000000U 009b41: line 2732 define CAN_F12R1_FB28 0x10000000U 009b5f: line 2733 define CAN_F12R1_FB29 0x20000000U 009b7d: line 2734 define CAN_F12R1_FB30 0x40000000U 009b9b: line 2735 define CAN_F12R1_FB31 0x80000000U 009bb9: line 2738 define CAN_F13R1_FB0 0x00000001U 009bd6: line 2739 define CAN_F13R1_FB1 0x00000002U 009bf3: line 2740 define CAN_F13R1_FB2 0x00000004U 009c10: line 2741 define CAN_F13R1_FB3 0x00000008U 009c2d: line 2742 define CAN_F13R1_FB4 0x00000010U 009c4a: line 2743 define CAN_F13R1_FB5 0x00000020U 009c67: line 2744 define CAN_F13R1_FB6 0x00000040U 009c84: line 2745 define CAN_F13R1_FB7 0x00000080U 009ca1: line 2746 define CAN_F13R1_FB8 0x00000100U 009cbe: line 2747 define CAN_F13R1_FB9 0x00000200U 009cdb: line 2748 define CAN_F13R1_FB10 0x00000400U 009cf9: line 2749 define CAN_F13R1_FB11 0x00000800U 009d17: line 2750 define CAN_F13R1_FB12 0x00001000U 009d35: line 2751 define CAN_F13R1_FB13 0x00002000U 009d53: line 2752 define CAN_F13R1_FB14 0x00004000U 009d71: line 2753 define CAN_F13R1_FB15 0x00008000U 009d8f: line 2754 define CAN_F13R1_FB16 0x00010000U 009dad: line 2755 define CAN_F13R1_FB17 0x00020000U 009dcb: line 2756 define CAN_F13R1_FB18 0x00040000U 009de9: line 2757 define CAN_F13R1_FB19 0x00080000U 009e07: line 2758 define CAN_F13R1_FB20 0x00100000U 009e25: line 2759 define CAN_F13R1_FB21 0x00200000U 009e43: line 2760 define CAN_F13R1_FB22 0x00400000U 009e61: line 2761 define CAN_F13R1_FB23 0x00800000U 009e7f: line 2762 define CAN_F13R1_FB24 0x01000000U 009e9d: line 2763 define CAN_F13R1_FB25 0x02000000U 009ebb: line 2764 define CAN_F13R1_FB26 0x04000000U 009ed9: line 2765 define CAN_F13R1_FB27 0x08000000U 009ef7: line 2766 define CAN_F13R1_FB28 0x10000000U 009f15: line 2767 define CAN_F13R1_FB29 0x20000000U 009f33: line 2768 define CAN_F13R1_FB30 0x40000000U 009f51: line 2769 define CAN_F13R1_FB31 0x80000000U 009f6f: line 2772 define CAN_F0R2_FB0 0x00000001U 009f8b: line 2773 define CAN_F0R2_FB1 0x00000002U 009fa7: line 2774 define CAN_F0R2_FB2 0x00000004U 009fc3: line 2775 define CAN_F0R2_FB3 0x00000008U 009fdf: line 2776 define CAN_F0R2_FB4 0x00000010U 009ffb: line 2777 define CAN_F0R2_FB5 0x00000020U 00a017: line 2778 define CAN_F0R2_FB6 0x00000040U 00a033: line 2779 define CAN_F0R2_FB7 0x00000080U 00a04f: line 2780 define CAN_F0R2_FB8 0x00000100U 00a06b: line 2781 define CAN_F0R2_FB9 0x00000200U 00a087: line 2782 define CAN_F0R2_FB10 0x00000400U 00a0a4: line 2783 define CAN_F0R2_FB11 0x00000800U 00a0c1: line 2784 define CAN_F0R2_FB12 0x00001000U 00a0de: line 2785 define CAN_F0R2_FB13 0x00002000U 00a0fb: line 2786 define CAN_F0R2_FB14 0x00004000U 00a118: line 2787 define CAN_F0R2_FB15 0x00008000U 00a135: line 2788 define CAN_F0R2_FB16 0x00010000U 00a152: line 2789 define CAN_F0R2_FB17 0x00020000U 00a16f: line 2790 define CAN_F0R2_FB18 0x00040000U 00a18c: line 2791 define CAN_F0R2_FB19 0x00080000U 00a1a9: line 2792 define CAN_F0R2_FB20 0x00100000U 00a1c6: line 2793 define CAN_F0R2_FB21 0x00200000U 00a1e3: line 2794 define CAN_F0R2_FB22 0x00400000U 00a200: line 2795 define CAN_F0R2_FB23 0x00800000U 00a21d: line 2796 define CAN_F0R2_FB24 0x01000000U 00a23a: line 2797 define CAN_F0R2_FB25 0x02000000U 00a257: line 2798 define CAN_F0R2_FB26 0x04000000U 00a274: line 2799 define CAN_F0R2_FB27 0x08000000U 00a291: line 2800 define CAN_F0R2_FB28 0x10000000U 00a2ae: line 2801 define CAN_F0R2_FB29 0x20000000U 00a2cb: line 2802 define CAN_F0R2_FB30 0x40000000U 00a2e8: line 2803 define CAN_F0R2_FB31 0x80000000U 00a305: line 2806 define CAN_F1R2_FB0 0x00000001U 00a321: line 2807 define CAN_F1R2_FB1 0x00000002U 00a33d: line 2808 define CAN_F1R2_FB2 0x00000004U 00a359: line 2809 define CAN_F1R2_FB3 0x00000008U 00a375: line 2810 define CAN_F1R2_FB4 0x00000010U 00a391: line 2811 define CAN_F1R2_FB5 0x00000020U 00a3ad: line 2812 define CAN_F1R2_FB6 0x00000040U 00a3c9: line 2813 define CAN_F1R2_FB7 0x00000080U 00a3e5: line 2814 define CAN_F1R2_FB8 0x00000100U 00a401: line 2815 define CAN_F1R2_FB9 0x00000200U 00a41d: line 2816 define CAN_F1R2_FB10 0x00000400U 00a43a: line 2817 define CAN_F1R2_FB11 0x00000800U 00a457: line 2818 define CAN_F1R2_FB12 0x00001000U 00a474: line 2819 define CAN_F1R2_FB13 0x00002000U 00a491: line 2820 define CAN_F1R2_FB14 0x00004000U 00a4ae: line 2821 define CAN_F1R2_FB15 0x00008000U 00a4cb: line 2822 define CAN_F1R2_FB16 0x00010000U 00a4e8: line 2823 define CAN_F1R2_FB17 0x00020000U 00a505: line 2824 define CAN_F1R2_FB18 0x00040000U 00a522: line 2825 define CAN_F1R2_FB19 0x00080000U 00a53f: line 2826 define CAN_F1R2_FB20 0x00100000U 00a55c: line 2827 define CAN_F1R2_FB21 0x00200000U 00a579: line 2828 define CAN_F1R2_FB22 0x00400000U 00a596: line 2829 define CAN_F1R2_FB23 0x00800000U 00a5b3: line 2830 define CAN_F1R2_FB24 0x01000000U 00a5d0: line 2831 define CAN_F1R2_FB25 0x02000000U 00a5ed: line 2832 define CAN_F1R2_FB26 0x04000000U 00a60a: line 2833 define CAN_F1R2_FB27 0x08000000U 00a627: line 2834 define CAN_F1R2_FB28 0x10000000U 00a644: line 2835 define CAN_F1R2_FB29 0x20000000U 00a661: line 2836 define CAN_F1R2_FB30 0x40000000U 00a67e: line 2837 define CAN_F1R2_FB31 0x80000000U 00a69b: line 2840 define CAN_F2R2_FB0 0x00000001U 00a6b7: line 2841 define CAN_F2R2_FB1 0x00000002U 00a6d3: line 2842 define CAN_F2R2_FB2 0x00000004U 00a6ef: line 2843 define CAN_F2R2_FB3 0x00000008U 00a70b: line 2844 define CAN_F2R2_FB4 0x00000010U 00a727: line 2845 define CAN_F2R2_FB5 0x00000020U 00a743: line 2846 define CAN_F2R2_FB6 0x00000040U 00a75f: line 2847 define CAN_F2R2_FB7 0x00000080U 00a77b: line 2848 define CAN_F2R2_FB8 0x00000100U 00a797: line 2849 define CAN_F2R2_FB9 0x00000200U 00a7b3: line 2850 define CAN_F2R2_FB10 0x00000400U 00a7d0: line 2851 define CAN_F2R2_FB11 0x00000800U 00a7ed: line 2852 define CAN_F2R2_FB12 0x00001000U 00a80a: line 2853 define CAN_F2R2_FB13 0x00002000U 00a827: line 2854 define CAN_F2R2_FB14 0x00004000U 00a844: line 2855 define CAN_F2R2_FB15 0x00008000U 00a861: line 2856 define CAN_F2R2_FB16 0x00010000U 00a87e: line 2857 define CAN_F2R2_FB17 0x00020000U 00a89b: line 2858 define CAN_F2R2_FB18 0x00040000U 00a8b8: line 2859 define CAN_F2R2_FB19 0x00080000U 00a8d5: line 2860 define CAN_F2R2_FB20 0x00100000U 00a8f2: line 2861 define CAN_F2R2_FB21 0x00200000U 00a90f: line 2862 define CAN_F2R2_FB22 0x00400000U 00a92c: line 2863 define CAN_F2R2_FB23 0x00800000U 00a949: line 2864 define CAN_F2R2_FB24 0x01000000U 00a966: line 2865 define CAN_F2R2_FB25 0x02000000U 00a983: line 2866 define CAN_F2R2_FB26 0x04000000U 00a9a0: line 2867 define CAN_F2R2_FB27 0x08000000U 00a9bd: line 2868 define CAN_F2R2_FB28 0x10000000U 00a9da: line 2869 define CAN_F2R2_FB29 0x20000000U 00a9f7: line 2870 define CAN_F2R2_FB30 0x40000000U 00aa14: line 2871 define CAN_F2R2_FB31 0x80000000U 00aa31: line 2874 define CAN_F3R2_FB0 0x00000001U 00aa4d: line 2875 define CAN_F3R2_FB1 0x00000002U 00aa69: line 2876 define CAN_F3R2_FB2 0x00000004U 00aa85: line 2877 define CAN_F3R2_FB3 0x00000008U 00aaa1: line 2878 define CAN_F3R2_FB4 0x00000010U 00aabd: line 2879 define CAN_F3R2_FB5 0x00000020U 00aad9: line 2880 define CAN_F3R2_FB6 0x00000040U 00aaf5: line 2881 define CAN_F3R2_FB7 0x00000080U 00ab11: line 2882 define CAN_F3R2_FB8 0x00000100U 00ab2d: line 2883 define CAN_F3R2_FB9 0x00000200U 00ab49: line 2884 define CAN_F3R2_FB10 0x00000400U 00ab66: line 2885 define CAN_F3R2_FB11 0x00000800U 00ab83: line 2886 define CAN_F3R2_FB12 0x00001000U 00aba0: line 2887 define CAN_F3R2_FB13 0x00002000U 00abbd: line 2888 define CAN_F3R2_FB14 0x00004000U 00abda: line 2889 define CAN_F3R2_FB15 0x00008000U 00abf7: line 2890 define CAN_F3R2_FB16 0x00010000U 00ac14: line 2891 define CAN_F3R2_FB17 0x00020000U 00ac31: line 2892 define CAN_F3R2_FB18 0x00040000U 00ac4e: line 2893 define CAN_F3R2_FB19 0x00080000U 00ac6b: line 2894 define CAN_F3R2_FB20 0x00100000U 00ac88: line 2895 define CAN_F3R2_FB21 0x00200000U 00aca5: line 2896 define CAN_F3R2_FB22 0x00400000U 00acc2: line 2897 define CAN_F3R2_FB23 0x00800000U 00acdf: line 2898 define CAN_F3R2_FB24 0x01000000U 00acfc: line 2899 define CAN_F3R2_FB25 0x02000000U 00ad19: line 2900 define CAN_F3R2_FB26 0x04000000U 00ad36: line 2901 define CAN_F3R2_FB27 0x08000000U 00ad53: line 2902 define CAN_F3R2_FB28 0x10000000U 00ad70: line 2903 define CAN_F3R2_FB29 0x20000000U 00ad8d: line 2904 define CAN_F3R2_FB30 0x40000000U 00adaa: line 2905 define CAN_F3R2_FB31 0x80000000U 00adc7: line 2908 define CAN_F4R2_FB0 0x00000001U 00ade3: line 2909 define CAN_F4R2_FB1 0x00000002U 00adff: line 2910 define CAN_F4R2_FB2 0x00000004U 00ae1b: line 2911 define CAN_F4R2_FB3 0x00000008U 00ae37: line 2912 define CAN_F4R2_FB4 0x00000010U 00ae53: line 2913 define CAN_F4R2_FB5 0x00000020U 00ae6f: line 2914 define CAN_F4R2_FB6 0x00000040U 00ae8b: line 2915 define CAN_F4R2_FB7 0x00000080U 00aea7: line 2916 define CAN_F4R2_FB8 0x00000100U 00aec3: line 2917 define CAN_F4R2_FB9 0x00000200U 00aedf: line 2918 define CAN_F4R2_FB10 0x00000400U 00aefc: line 2919 define CAN_F4R2_FB11 0x00000800U 00af19: line 2920 define CAN_F4R2_FB12 0x00001000U 00af36: line 2921 define CAN_F4R2_FB13 0x00002000U 00af53: line 2922 define CAN_F4R2_FB14 0x00004000U 00af70: line 2923 define CAN_F4R2_FB15 0x00008000U 00af8d: line 2924 define CAN_F4R2_FB16 0x00010000U 00afaa: line 2925 define CAN_F4R2_FB17 0x00020000U 00afc7: line 2926 define CAN_F4R2_FB18 0x00040000U 00afe4: line 2927 define CAN_F4R2_FB19 0x00080000U 00b001: line 2928 define CAN_F4R2_FB20 0x00100000U 00b01e: line 2929 define CAN_F4R2_FB21 0x00200000U 00b03b: line 2930 define CAN_F4R2_FB22 0x00400000U 00b058: line 2931 define CAN_F4R2_FB23 0x00800000U 00b075: line 2932 define CAN_F4R2_FB24 0x01000000U 00b092: line 2933 define CAN_F4R2_FB25 0x02000000U 00b0af: line 2934 define CAN_F4R2_FB26 0x04000000U 00b0cc: line 2935 define CAN_F4R2_FB27 0x08000000U 00b0e9: line 2936 define CAN_F4R2_FB28 0x10000000U 00b106: line 2937 define CAN_F4R2_FB29 0x20000000U 00b123: line 2938 define CAN_F4R2_FB30 0x40000000U 00b140: line 2939 define CAN_F4R2_FB31 0x80000000U 00b15d: line 2942 define CAN_F5R2_FB0 0x00000001U 00b179: line 2943 define CAN_F5R2_FB1 0x00000002U 00b195: line 2944 define CAN_F5R2_FB2 0x00000004U 00b1b1: line 2945 define CAN_F5R2_FB3 0x00000008U 00b1cd: line 2946 define CAN_F5R2_FB4 0x00000010U 00b1e9: line 2947 define CAN_F5R2_FB5 0x00000020U 00b205: line 2948 define CAN_F5R2_FB6 0x00000040U 00b221: line 2949 define CAN_F5R2_FB7 0x00000080U 00b23d: line 2950 define CAN_F5R2_FB8 0x00000100U 00b259: line 2951 define CAN_F5R2_FB9 0x00000200U 00b275: line 2952 define CAN_F5R2_FB10 0x00000400U 00b292: line 2953 define CAN_F5R2_FB11 0x00000800U 00b2af: line 2954 define CAN_F5R2_FB12 0x00001000U 00b2cc: line 2955 define CAN_F5R2_FB13 0x00002000U 00b2e9: line 2956 define CAN_F5R2_FB14 0x00004000U 00b306: line 2957 define CAN_F5R2_FB15 0x00008000U 00b323: line 2958 define CAN_F5R2_FB16 0x00010000U 00b340: line 2959 define CAN_F5R2_FB17 0x00020000U 00b35d: line 2960 define CAN_F5R2_FB18 0x00040000U 00b37a: line 2961 define CAN_F5R2_FB19 0x00080000U 00b397: line 2962 define CAN_F5R2_FB20 0x00100000U 00b3b4: line 2963 define CAN_F5R2_FB21 0x00200000U 00b3d1: line 2964 define CAN_F5R2_FB22 0x00400000U 00b3ee: line 2965 define CAN_F5R2_FB23 0x00800000U 00b40b: line 2966 define CAN_F5R2_FB24 0x01000000U 00b428: line 2967 define CAN_F5R2_FB25 0x02000000U 00b445: line 2968 define CAN_F5R2_FB26 0x04000000U 00b462: line 2969 define CAN_F5R2_FB27 0x08000000U 00b47f: line 2970 define CAN_F5R2_FB28 0x10000000U 00b49c: line 2971 define CAN_F5R2_FB29 0x20000000U 00b4b9: line 2972 define CAN_F5R2_FB30 0x40000000U 00b4d6: line 2973 define CAN_F5R2_FB31 0x80000000U 00b4f3: line 2976 define CAN_F6R2_FB0 0x00000001U 00b50f: line 2977 define CAN_F6R2_FB1 0x00000002U 00b52b: line 2978 define CAN_F6R2_FB2 0x00000004U 00b547: line 2979 define CAN_F6R2_FB3 0x00000008U 00b563: line 2980 define CAN_F6R2_FB4 0x00000010U 00b57f: line 2981 define CAN_F6R2_FB5 0x00000020U 00b59b: line 2982 define CAN_F6R2_FB6 0x00000040U 00b5b7: line 2983 define CAN_F6R2_FB7 0x00000080U 00b5d3: line 2984 define CAN_F6R2_FB8 0x00000100U 00b5ef: line 2985 define CAN_F6R2_FB9 0x00000200U 00b60b: line 2986 define CAN_F6R2_FB10 0x00000400U 00b628: line 2987 define CAN_F6R2_FB11 0x00000800U 00b645: line 2988 define CAN_F6R2_FB12 0x00001000U 00b662: line 2989 define CAN_F6R2_FB13 0x00002000U 00b67f: line 2990 define CAN_F6R2_FB14 0x00004000U 00b69c: line 2991 define CAN_F6R2_FB15 0x00008000U 00b6b9: line 2992 define CAN_F6R2_FB16 0x00010000U 00b6d6: line 2993 define CAN_F6R2_FB17 0x00020000U 00b6f3: line 2994 define CAN_F6R2_FB18 0x00040000U 00b710: line 2995 define CAN_F6R2_FB19 0x00080000U 00b72d: line 2996 define CAN_F6R2_FB20 0x00100000U 00b74a: line 2997 define CAN_F6R2_FB21 0x00200000U 00b767: line 2998 define CAN_F6R2_FB22 0x00400000U 00b784: line 2999 define CAN_F6R2_FB23 0x00800000U 00b7a1: line 3000 define CAN_F6R2_FB24 0x01000000U 00b7be: line 3001 define CAN_F6R2_FB25 0x02000000U 00b7db: line 3002 define CAN_F6R2_FB26 0x04000000U 00b7f8: line 3003 define CAN_F6R2_FB27 0x08000000U 00b815: line 3004 define CAN_F6R2_FB28 0x10000000U 00b832: line 3005 define CAN_F6R2_FB29 0x20000000U 00b84f: line 3006 define CAN_F6R2_FB30 0x40000000U 00b86c: line 3007 define CAN_F6R2_FB31 0x80000000U 00b889: line 3010 define CAN_F7R2_FB0 0x00000001U 00b8a5: line 3011 define CAN_F7R2_FB1 0x00000002U 00b8c1: line 3012 define CAN_F7R2_FB2 0x00000004U 00b8dd: line 3013 define CAN_F7R2_FB3 0x00000008U 00b8f9: line 3014 define CAN_F7R2_FB4 0x00000010U 00b915: line 3015 define CAN_F7R2_FB5 0x00000020U 00b931: line 3016 define CAN_F7R2_FB6 0x00000040U 00b94d: line 3017 define CAN_F7R2_FB7 0x00000080U 00b969: line 3018 define CAN_F7R2_FB8 0x00000100U 00b985: line 3019 define CAN_F7R2_FB9 0x00000200U 00b9a1: line 3020 define CAN_F7R2_FB10 0x00000400U 00b9be: line 3021 define CAN_F7R2_FB11 0x00000800U 00b9db: line 3022 define CAN_F7R2_FB12 0x00001000U 00b9f8: line 3023 define CAN_F7R2_FB13 0x00002000U 00ba15: line 3024 define CAN_F7R2_FB14 0x00004000U 00ba32: line 3025 define CAN_F7R2_FB15 0x00008000U 00ba4f: line 3026 define CAN_F7R2_FB16 0x00010000U 00ba6c: line 3027 define CAN_F7R2_FB17 0x00020000U 00ba89: line 3028 define CAN_F7R2_FB18 0x00040000U 00baa6: line 3029 define CAN_F7R2_FB19 0x00080000U 00bac3: line 3030 define CAN_F7R2_FB20 0x00100000U 00bae0: line 3031 define CAN_F7R2_FB21 0x00200000U 00bafd: line 3032 define CAN_F7R2_FB22 0x00400000U 00bb1a: line 3033 define CAN_F7R2_FB23 0x00800000U 00bb37: line 3034 define CAN_F7R2_FB24 0x01000000U 00bb54: line 3035 define CAN_F7R2_FB25 0x02000000U 00bb71: line 3036 define CAN_F7R2_FB26 0x04000000U 00bb8e: line 3037 define CAN_F7R2_FB27 0x08000000U 00bbab: line 3038 define CAN_F7R2_FB28 0x10000000U 00bbc8: line 3039 define CAN_F7R2_FB29 0x20000000U 00bbe5: line 3040 define CAN_F7R2_FB30 0x40000000U 00bc02: line 3041 define CAN_F7R2_FB31 0x80000000U 00bc1f: line 3044 define CAN_F8R2_FB0 0x00000001U 00bc3b: line 3045 define CAN_F8R2_FB1 0x00000002U 00bc57: line 3046 define CAN_F8R2_FB2 0x00000004U 00bc73: line 3047 define CAN_F8R2_FB3 0x00000008U 00bc8f: line 3048 define CAN_F8R2_FB4 0x00000010U 00bcab: line 3049 define CAN_F8R2_FB5 0x00000020U 00bcc7: line 3050 define CAN_F8R2_FB6 0x00000040U 00bce3: line 3051 define CAN_F8R2_FB7 0x00000080U 00bcff: line 3052 define CAN_F8R2_FB8 0x00000100U 00bd1b: line 3053 define CAN_F8R2_FB9 0x00000200U 00bd37: line 3054 define CAN_F8R2_FB10 0x00000400U 00bd54: line 3055 define CAN_F8R2_FB11 0x00000800U 00bd71: line 3056 define CAN_F8R2_FB12 0x00001000U 00bd8e: line 3057 define CAN_F8R2_FB13 0x00002000U 00bdab: line 3058 define CAN_F8R2_FB14 0x00004000U 00bdc8: line 3059 define CAN_F8R2_FB15 0x00008000U 00bde5: line 3060 define CAN_F8R2_FB16 0x00010000U 00be02: line 3061 define CAN_F8R2_FB17 0x00020000U 00be1f: line 3062 define CAN_F8R2_FB18 0x00040000U 00be3c: line 3063 define CAN_F8R2_FB19 0x00080000U 00be59: line 3064 define CAN_F8R2_FB20 0x00100000U 00be76: line 3065 define CAN_F8R2_FB21 0x00200000U 00be93: line 3066 define CAN_F8R2_FB22 0x00400000U 00beb0: line 3067 define CAN_F8R2_FB23 0x00800000U 00becd: line 3068 define CAN_F8R2_FB24 0x01000000U 00beea: line 3069 define CAN_F8R2_FB25 0x02000000U 00bf07: line 3070 define CAN_F8R2_FB26 0x04000000U 00bf24: line 3071 define CAN_F8R2_FB27 0x08000000U 00bf41: line 3072 define CAN_F8R2_FB28 0x10000000U 00bf5e: line 3073 define CAN_F8R2_FB29 0x20000000U 00bf7b: line 3074 define CAN_F8R2_FB30 0x40000000U 00bf98: line 3075 define CAN_F8R2_FB31 0x80000000U 00bfb5: line 3078 define CAN_F9R2_FB0 0x00000001U 00bfd1: line 3079 define CAN_F9R2_FB1 0x00000002U 00bfed: line 3080 define CAN_F9R2_FB2 0x00000004U 00c009: line 3081 define CAN_F9R2_FB3 0x00000008U 00c025: line 3082 define CAN_F9R2_FB4 0x00000010U 00c041: line 3083 define CAN_F9R2_FB5 0x00000020U 00c05d: line 3084 define CAN_F9R2_FB6 0x00000040U 00c079: line 3085 define CAN_F9R2_FB7 0x00000080U 00c095: line 3086 define CAN_F9R2_FB8 0x00000100U 00c0b1: line 3087 define CAN_F9R2_FB9 0x00000200U 00c0cd: line 3088 define CAN_F9R2_FB10 0x00000400U 00c0ea: line 3089 define CAN_F9R2_FB11 0x00000800U 00c107: line 3090 define CAN_F9R2_FB12 0x00001000U 00c124: line 3091 define CAN_F9R2_FB13 0x00002000U 00c141: line 3092 define CAN_F9R2_FB14 0x00004000U 00c15e: line 3093 define CAN_F9R2_FB15 0x00008000U 00c17b: line 3094 define CAN_F9R2_FB16 0x00010000U 00c198: line 3095 define CAN_F9R2_FB17 0x00020000U 00c1b5: line 3096 define CAN_F9R2_FB18 0x00040000U 00c1d2: line 3097 define CAN_F9R2_FB19 0x00080000U 00c1ef: line 3098 define CAN_F9R2_FB20 0x00100000U 00c20c: line 3099 define CAN_F9R2_FB21 0x00200000U 00c229: line 3100 define CAN_F9R2_FB22 0x00400000U 00c246: line 3101 define CAN_F9R2_FB23 0x00800000U 00c263: line 3102 define CAN_F9R2_FB24 0x01000000U 00c280: line 3103 define CAN_F9R2_FB25 0x02000000U 00c29d: line 3104 define CAN_F9R2_FB26 0x04000000U 00c2ba: line 3105 define CAN_F9R2_FB27 0x08000000U 00c2d7: line 3106 define CAN_F9R2_FB28 0x10000000U 00c2f4: line 3107 define CAN_F9R2_FB29 0x20000000U 00c311: line 3108 define CAN_F9R2_FB30 0x40000000U 00c32e: line 3109 define CAN_F9R2_FB31 0x80000000U 00c34b: line 3112 define CAN_F10R2_FB0 0x00000001U 00c368: line 3113 define CAN_F10R2_FB1 0x00000002U 00c385: line 3114 define CAN_F10R2_FB2 0x00000004U 00c3a2: line 3115 define CAN_F10R2_FB3 0x00000008U 00c3bf: line 3116 define CAN_F10R2_FB4 0x00000010U 00c3dc: line 3117 define CAN_F10R2_FB5 0x00000020U 00c3f9: line 3118 define CAN_F10R2_FB6 0x00000040U 00c416: line 3119 define CAN_F10R2_FB7 0x00000080U 00c433: line 3120 define CAN_F10R2_FB8 0x00000100U 00c450: line 3121 define CAN_F10R2_FB9 0x00000200U 00c46d: line 3122 define CAN_F10R2_FB10 0x00000400U 00c48b: line 3123 define CAN_F10R2_FB11 0x00000800U 00c4a9: line 3124 define CAN_F10R2_FB12 0x00001000U 00c4c7: line 3125 define CAN_F10R2_FB13 0x00002000U 00c4e5: line 3126 define CAN_F10R2_FB14 0x00004000U 00c503: line 3127 define CAN_F10R2_FB15 0x00008000U 00c521: line 3128 define CAN_F10R2_FB16 0x00010000U 00c53f: line 3129 define CAN_F10R2_FB17 0x00020000U 00c55d: line 3130 define CAN_F10R2_FB18 0x00040000U 00c57b: line 3131 define CAN_F10R2_FB19 0x00080000U 00c599: line 3132 define CAN_F10R2_FB20 0x00100000U 00c5b7: line 3133 define CAN_F10R2_FB21 0x00200000U 00c5d5: line 3134 define CAN_F10R2_FB22 0x00400000U 00c5f3: line 3135 define CAN_F10R2_FB23 0x00800000U 00c611: line 3136 define CAN_F10R2_FB24 0x01000000U 00c62f: line 3137 define CAN_F10R2_FB25 0x02000000U 00c64d: line 3138 define CAN_F10R2_FB26 0x04000000U 00c66b: line 3139 define CAN_F10R2_FB27 0x08000000U 00c689: line 3140 define CAN_F10R2_FB28 0x10000000U 00c6a7: line 3141 define CAN_F10R2_FB29 0x20000000U 00c6c5: line 3142 define CAN_F10R2_FB30 0x40000000U 00c6e3: line 3143 define CAN_F10R2_FB31 0x80000000U 00c701: line 3146 define CAN_F11R2_FB0 0x00000001U 00c71e: line 3147 define CAN_F11R2_FB1 0x00000002U 00c73b: line 3148 define CAN_F11R2_FB2 0x00000004U 00c758: line 3149 define CAN_F11R2_FB3 0x00000008U 00c775: line 3150 define CAN_F11R2_FB4 0x00000010U 00c792: line 3151 define CAN_F11R2_FB5 0x00000020U 00c7af: line 3152 define CAN_F11R2_FB6 0x00000040U 00c7cc: line 3153 define CAN_F11R2_FB7 0x00000080U 00c7e9: line 3154 define CAN_F11R2_FB8 0x00000100U 00c806: line 3155 define CAN_F11R2_FB9 0x00000200U 00c823: line 3156 define CAN_F11R2_FB10 0x00000400U 00c841: line 3157 define CAN_F11R2_FB11 0x00000800U 00c85f: line 3158 define CAN_F11R2_FB12 0x00001000U 00c87d: line 3159 define CAN_F11R2_FB13 0x00002000U 00c89b: line 3160 define CAN_F11R2_FB14 0x00004000U 00c8b9: line 3161 define CAN_F11R2_FB15 0x00008000U 00c8d7: line 3162 define CAN_F11R2_FB16 0x00010000U 00c8f5: line 3163 define CAN_F11R2_FB17 0x00020000U 00c913: line 3164 define CAN_F11R2_FB18 0x00040000U 00c931: line 3165 define CAN_F11R2_FB19 0x00080000U 00c94f: line 3166 define CAN_F11R2_FB20 0x00100000U 00c96d: line 3167 define CAN_F11R2_FB21 0x00200000U 00c98b: line 3168 define CAN_F11R2_FB22 0x00400000U 00c9a9: line 3169 define CAN_F11R2_FB23 0x00800000U 00c9c7: line 3170 define CAN_F11R2_FB24 0x01000000U 00c9e5: line 3171 define CAN_F11R2_FB25 0x02000000U 00ca03: line 3172 define CAN_F11R2_FB26 0x04000000U 00ca21: line 3173 define CAN_F11R2_FB27 0x08000000U 00ca3f: line 3174 define CAN_F11R2_FB28 0x10000000U 00ca5d: line 3175 define CAN_F11R2_FB29 0x20000000U 00ca7b: line 3176 define CAN_F11R2_FB30 0x40000000U 00ca99: line 3177 define CAN_F11R2_FB31 0x80000000U 00cab7: line 3180 define CAN_F12R2_FB0 0x00000001U 00cad4: line 3181 define CAN_F12R2_FB1 0x00000002U 00caf1: line 3182 define CAN_F12R2_FB2 0x00000004U 00cb0e: line 3183 define CAN_F12R2_FB3 0x00000008U 00cb2b: line 3184 define CAN_F12R2_FB4 0x00000010U 00cb48: line 3185 define CAN_F12R2_FB5 0x00000020U 00cb65: line 3186 define CAN_F12R2_FB6 0x00000040U 00cb82: line 3187 define CAN_F12R2_FB7 0x00000080U 00cb9f: line 3188 define CAN_F12R2_FB8 0x00000100U 00cbbc: line 3189 define CAN_F12R2_FB9 0x00000200U 00cbd9: line 3190 define CAN_F12R2_FB10 0x00000400U 00cbf7: line 3191 define CAN_F12R2_FB11 0x00000800U 00cc15: line 3192 define CAN_F12R2_FB12 0x00001000U 00cc33: line 3193 define CAN_F12R2_FB13 0x00002000U 00cc51: line 3194 define CAN_F12R2_FB14 0x00004000U 00cc6f: line 3195 define CAN_F12R2_FB15 0x00008000U 00cc8d: line 3196 define CAN_F12R2_FB16 0x00010000U 00ccab: line 3197 define CAN_F12R2_FB17 0x00020000U 00ccc9: line 3198 define CAN_F12R2_FB18 0x00040000U 00cce7: line 3199 define CAN_F12R2_FB19 0x00080000U 00cd05: line 3200 define CAN_F12R2_FB20 0x00100000U 00cd23: line 3201 define CAN_F12R2_FB21 0x00200000U 00cd41: line 3202 define CAN_F12R2_FB22 0x00400000U 00cd5f: line 3203 define CAN_F12R2_FB23 0x00800000U 00cd7d: line 3204 define CAN_F12R2_FB24 0x01000000U 00cd9b: line 3205 define CAN_F12R2_FB25 0x02000000U 00cdb9: line 3206 define CAN_F12R2_FB26 0x04000000U 00cdd7: line 3207 define CAN_F12R2_FB27 0x08000000U 00cdf5: line 3208 define CAN_F12R2_FB28 0x10000000U 00ce13: line 3209 define CAN_F12R2_FB29 0x20000000U 00ce31: line 3210 define CAN_F12R2_FB30 0x40000000U 00ce4f: line 3211 define CAN_F12R2_FB31 0x80000000U 00ce6d: line 3214 define CAN_F13R2_FB0 0x00000001U 00ce8a: line 3215 define CAN_F13R2_FB1 0x00000002U 00cea7: line 3216 define CAN_F13R2_FB2 0x00000004U 00cec4: line 3217 define CAN_F13R2_FB3 0x00000008U 00cee1: line 3218 define CAN_F13R2_FB4 0x00000010U 00cefe: line 3219 define CAN_F13R2_FB5 0x00000020U 00cf1b: line 3220 define CAN_F13R2_FB6 0x00000040U 00cf38: line 3221 define CAN_F13R2_FB7 0x00000080U 00cf55: line 3222 define CAN_F13R2_FB8 0x00000100U 00cf72: line 3223 define CAN_F13R2_FB9 0x00000200U 00cf8f: line 3224 define CAN_F13R2_FB10 0x00000400U 00cfad: line 3225 define CAN_F13R2_FB11 0x00000800U 00cfcb: line 3226 define CAN_F13R2_FB12 0x00001000U 00cfe9: line 3227 define CAN_F13R2_FB13 0x00002000U 00d007: line 3228 define CAN_F13R2_FB14 0x00004000U 00d025: line 3229 define CAN_F13R2_FB15 0x00008000U 00d043: line 3230 define CAN_F13R2_FB16 0x00010000U 00d061: line 3231 define CAN_F13R2_FB17 0x00020000U 00d07f: line 3232 define CAN_F13R2_FB18 0x00040000U 00d09d: line 3233 define CAN_F13R2_FB19 0x00080000U 00d0bb: line 3234 define CAN_F13R2_FB20 0x00100000U 00d0d9: line 3235 define CAN_F13R2_FB21 0x00200000U 00d0f7: line 3236 define CAN_F13R2_FB22 0x00400000U 00d115: line 3237 define CAN_F13R2_FB23 0x00800000U 00d133: line 3238 define CAN_F13R2_FB24 0x01000000U 00d151: line 3239 define CAN_F13R2_FB25 0x02000000U 00d16f: line 3240 define CAN_F13R2_FB26 0x04000000U 00d18d: line 3241 define CAN_F13R2_FB27 0x08000000U 00d1ab: line 3242 define CAN_F13R2_FB28 0x10000000U 00d1c9: line 3243 define CAN_F13R2_FB29 0x20000000U 00d1e7: line 3244 define CAN_F13R2_FB30 0x40000000U 00d205: line 3245 define CAN_F13R2_FB31 0x80000000U 00d223: line 3254 define CEC_CR_CECEN 0x00000001U 00d23f: line 3255 define CEC_CR_TXSOM 0x00000002U 00d25b: line 3256 define CEC_CR_TXEOM 0x00000004U 00d277: line 3259 define CEC_CFGR_SFT 0x00000007U 00d293: line 3260 define CEC_CFGR_RXTOL 0x00000008U 00d2b1: line 3261 define CEC_CFGR_BRESTP 0x00000010U 00d2d0: line 3262 define CEC_CFGR_BREGEN 0x00000020U 00d2ef: line 3263 define CEC_CFGR_LBPEGEN 0x00000040U 00d30f: line 3264 define CEC_CFGR_BRDNOGEN 0x00000080U 00d330: line 3265 define CEC_CFGR_SFTOPT 0x00000100U 00d34f: line 3266 define CEC_CFGR_OAR 0x7FFF0000U 00d36b: line 3267 define CEC_CFGR_LSTN 0x80000000U 00d388: line 3270 define CEC_TXDR_TXD 0x000000FFU 00d3a4: line 3273 define CEC_TXDR_RXD 0x000000FFU 00d3c0: line 3276 define CEC_ISR_RXBR 0x00000001U 00d3dc: line 3277 define CEC_ISR_RXEND 0x00000002U 00d3f9: line 3278 define CEC_ISR_RXOVR 0x00000004U 00d416: line 3279 define CEC_ISR_BRE 0x00000008U 00d431: line 3280 define CEC_ISR_SBPE 0x00000010U 00d44d: line 3281 define CEC_ISR_LBPE 0x00000020U 00d469: line 3282 define CEC_ISR_RXACKE 0x00000040U 00d487: line 3283 define CEC_ISR_ARBLST 0x00000080U 00d4a5: line 3284 define CEC_ISR_TXBR 0x00000100U 00d4c1: line 3285 define CEC_ISR_TXEND 0x00000200U 00d4de: line 3286 define CEC_ISR_TXUDR 0x00000400U 00d4fb: line 3287 define CEC_ISR_TXERR 0x00000800U 00d518: line 3288 define CEC_ISR_TXACKE 0x00001000U 00d536: line 3291 define CEC_IER_RXBRIE 0x00000001U 00d554: line 3292 define CEC_IER_RXENDIE 0x00000002U 00d573: line 3293 define CEC_IER_RXOVRIE 0x00000004U 00d592: line 3294 define CEC_IER_BREIE 0x00000008U 00d5af: line 3295 define CEC_IER_SBPEIE 0x00000010U 00d5cd: line 3296 define CEC_IER_LBPEIE 0x00000020U 00d5eb: line 3297 define CEC_IER_RXACKEIE 0x00000040U 00d60b: line 3298 define CEC_IER_ARBLSTIE 0x00000080U 00d62b: line 3299 define CEC_IER_TXBRIE 0x00000100U 00d649: line 3300 define CEC_IER_TXENDIE 0x00000200U 00d668: line 3301 define CEC_IER_TXUDRIE 0x00000400U 00d687: line 3302 define CEC_IER_TXERRIE 0x00000800U 00d6a6: line 3303 define CEC_IER_TXACKEIE 0x00001000U 00d6c6: line 3311 define CRC_DR_DR 0xFFFFFFFFU 00d6df: line 3314 define CRC_IDR_IDR 0x000000FFU 00d6fa: line 3317 define CRC_CR_RESET 0x00000001U 00d716: line 3318 define CRC_CR_POLYSIZE 0x00000018U 00d735: line 3319 define CRC_CR_POLYSIZE_0 0x00000008U 00d756: line 3320 define CRC_CR_POLYSIZE_1 0x00000010U 00d777: line 3321 define CRC_CR_REV_IN 0x00000060U 00d794: line 3322 define CRC_CR_REV_IN_0 0x00000020U 00d7b3: line 3323 define CRC_CR_REV_IN_1 0x00000040U 00d7d2: line 3324 define CRC_CR_REV_OUT 0x00000080U 00d7f0: line 3327 define CRC_INIT_INIT 0xFFFFFFFFU 00d80d: line 3330 define CRC_POL_POL 0xFFFFFFFFU 00d828: line 3339 define DAC_CR_EN1 0x00000001U 00d842: line 3340 define DAC_CR_BOFF1 0x00000002U 00d85e: line 3341 define DAC_CR_TEN1 0x00000004U 00d879: line 3342 define DAC_CR_TSEL1 0x00000038U 00d895: line 3343 define DAC_CR_TSEL1_0 0x00000008U 00d8b3: line 3344 define DAC_CR_TSEL1_1 0x00000010U 00d8d1: line 3345 define DAC_CR_TSEL1_2 0x00000020U 00d8ef: line 3346 define DAC_CR_WAVE1 0x000000C0U 00d90b: line 3347 define DAC_CR_WAVE1_0 0x00000040U 00d929: line 3348 define DAC_CR_WAVE1_1 0x00000080U 00d947: line 3349 define DAC_CR_MAMP1 0x00000F00U 00d963: line 3350 define DAC_CR_MAMP1_0 0x00000100U 00d981: line 3351 define DAC_CR_MAMP1_1 0x00000200U 00d99f: line 3352 define DAC_CR_MAMP1_2 0x00000400U 00d9bd: line 3353 define DAC_CR_MAMP1_3 0x00000800U 00d9db: line 3354 define DAC_CR_DMAEN1 0x00001000U 00d9f8: line 3355 define DAC_CR_DMAUDRIE1 0x00002000U 00da18: line 3356 define DAC_CR_EN2 0x00010000U 00da32: line 3357 define DAC_CR_BOFF2 0x00020000U 00da4e: line 3358 define DAC_CR_TEN2 0x00040000U 00da69: line 3359 define DAC_CR_TSEL2 0x00380000U 00da85: line 3360 define DAC_CR_TSEL2_0 0x00080000U 00daa3: line 3361 define DAC_CR_TSEL2_1 0x00100000U 00dac1: line 3362 define DAC_CR_TSEL2_2 0x00200000U 00dadf: line 3363 define DAC_CR_WAVE2 0x00C00000U 00dafb: line 3364 define DAC_CR_WAVE2_0 0x00400000U 00db19: line 3365 define DAC_CR_WAVE2_1 0x00800000U 00db37: line 3366 define DAC_CR_MAMP2 0x0F000000U 00db53: line 3367 define DAC_CR_MAMP2_0 0x01000000U 00db71: line 3368 define DAC_CR_MAMP2_1 0x02000000U 00db8f: line 3369 define DAC_CR_MAMP2_2 0x04000000U 00dbad: line 3370 define DAC_CR_MAMP2_3 0x08000000U 00dbcb: line 3371 define DAC_CR_DMAEN2 0x10000000U 00dbe8: line 3372 define DAC_CR_DMAUDRIE2 0x20000000U 00dc08: line 3375 define DAC_SWTRIGR_SWTRIG1 0x01U 00dc25: line 3376 define DAC_SWTRIGR_SWTRIG2 0x02U 00dc42: line 3379 define DAC_DHR12R1_DACC1DHR 0x0FFFU 00dc62: line 3382 define DAC_DHR12L1_DACC1DHR 0xFFF0U 00dc82: line 3385 define DAC_DHR8R1_DACC1DHR 0xFFU 00dc9f: line 3388 define DAC_DHR12R2_DACC2DHR 0x0FFFU 00dcbf: line 3391 define DAC_DHR12L2_DACC2DHR 0xFFF0U 00dcdf: line 3394 define DAC_DHR8R2_DACC2DHR 0xFFU 00dcfc: line 3397 define DAC_DHR12RD_DACC1DHR 0x00000FFFU 00dd20: line 3398 define DAC_DHR12RD_DACC2DHR 0x0FFF0000U 00dd44: line 3401 define DAC_DHR12LD_DACC1DHR 0x0000FFF0U 00dd68: line 3402 define DAC_DHR12LD_DACC2DHR 0xFFF00000U 00dd8c: line 3405 define DAC_DHR8RD_DACC1DHR 0x00FFU 00ddab: line 3406 define DAC_DHR8RD_DACC2DHR 0xFF00U 00ddca: line 3409 define DAC_DOR1_DACC1DOR 0x0FFFU 00dde7: line 3412 define DAC_DOR2_DACC2DOR 0x0FFFU 00de04: line 3415 define DAC_SR_DMAUDR1 0x00002000U 00de22: line 3416 define DAC_SR_DMAUDR2 0x20000000U 00de40: line 3427 define DFSDM_CHCFGR1_DFSDMEN 0x80000000U 00de65: line 3428 define DFSDM_CHCFGR1_CKOUTSRC 0x40000000U 00de8b: line 3429 define DFSDM_CHCFGR1_CKOUTDIV 0x00FF0000U 00deb1: line 3430 define DFSDM_CHCFGR1_DATPACK 0x0000C000U 00ded6: line 3431 define DFSDM_CHCFGR1_DATPACK_1 0x00008000U 00defd: line 3432 define DFSDM_CHCFGR1_DATPACK_0 0x00004000U 00df24: line 3433 define DFSDM_CHCFGR1_DATMPX 0x00003000U 00df48: line 3434 define DFSDM_CHCFGR1_DATMPX_1 0x00002000U 00df6e: line 3435 define DFSDM_CHCFGR1_DATMPX_0 0x00001000U 00df94: line 3436 define DFSDM_CHCFGR1_CHINSEL 0x00000100U 00dfb9: line 3437 define DFSDM_CHCFGR1_CHEN 0x00000080U 00dfdb: line 3438 define DFSDM_CHCFGR1_CKABEN 0x00000040U 00dfff: line 3439 define DFSDM_CHCFGR1_SCDEN 0x00000020U 00e022: line 3440 define DFSDM_CHCFGR1_SPICKSEL 0x0000000CU 00e048: line 3441 define DFSDM_CHCFGR1_SPICKSEL_1 0x00000008U 00e070: line 3442 define DFSDM_CHCFGR1_SPICKSEL_0 0x00000004U 00e098: line 3443 define DFSDM_CHCFGR1_SITP 0x00000003U 00e0ba: line 3444 define DFSDM_CHCFGR1_SITP_1 0x00000002U 00e0de: line 3445 define DFSDM_CHCFGR1_SITP_0 0x00000001U 00e102: line 3448 define DFSDM_CHCFGR2_OFFSET 0xFFFFFF00U 00e126: line 3449 define DFSDM_CHCFGR2_DTRBS 0x000000F8U 00e149: line 3452 define DFSDM_CHAWSCDR_AWFORD 0x00C00000U 00e16e: line 3453 define DFSDM_CHAWSCDR_AWFORD_1 0x00800000U 00e195: line 3454 define DFSDM_CHAWSCDR_AWFORD_0 0x00400000U 00e1bc: line 3455 define DFSDM_CHAWSCDR_AWFOSR 0x001F0000U 00e1e1: line 3456 define DFSDM_CHAWSCDR_BKSCD 0x0000F000U 00e205: line 3457 define DFSDM_CHAWSCDR_SCDT 0x000000FFU 00e228: line 3460 define DFSDM_CHWDATR_WDATA 0x0000FFFFU 00e24b: line 3463 define DFSDM_CHDATINR_INDAT0 0x0000FFFFU 00e270: line 3464 define DFSDM_CHDATINR_INDAT1 0xFFFF0000U 00e295: line 3469 define DFSDM_FLTCR1_AWFSEL 0x40000000U 00e2b8: line 3470 define DFSDM_FLTCR1_FAST 0x20000000U 00e2d9: line 3471 define DFSDM_FLTCR1_RCH 0x07000000U 00e2f9: line 3472 define DFSDM_FLTCR1_RDMAEN 0x00200000U 00e31c: line 3473 define DFSDM_FLTCR1_RSYNC 0x00080000U 00e33e: line 3474 define DFSDM_FLTCR1_RCONT 0x00040000U 00e360: line 3475 define DFSDM_FLTCR1_RSWSTART 0x00020000U 00e385: line 3476 define DFSDM_FLTCR1_JEXTEN 0x00006000U 00e3a8: line 3477 define DFSDM_FLTCR1_JEXTEN_1 0x00004000U 00e3cd: line 3478 define DFSDM_FLTCR1_JEXTEN_0 0x00002000U 00e3f2: line 3479 define DFSDM_FLTCR1_JEXTSEL 0x00001F00U 00e416: line 3480 define DFSDM_FLTCR1_JEXTSEL_0 0x00000100U 00e43c: line 3481 define DFSDM_FLTCR1_JEXTSEL_1 0x00000200U 00e462: line 3482 define DFSDM_FLTCR1_JEXTSEL_2 0x00000400U 00e488: line 3483 define DFSDM_FLTCR1_JEXTSEL_3 0x00000800U 00e4ae: line 3484 define DFSDM_FLTCR1_JEXTSEL_4 0x00001000U 00e4d4: line 3485 define DFSDM_FLTCR1_JDMAEN 0x00000020U 00e4f7: line 3486 define DFSDM_FLTCR1_JSCAN 0x00000010U 00e519: line 3487 define DFSDM_FLTCR1_JSYNC 0x00000008U 00e53b: line 3488 define DFSDM_FLTCR1_JSWSTART 0x00000002U 00e560: line 3489 define DFSDM_FLTCR1_DFEN 0x00000001U 00e581: line 3492 define DFSDM_FLTCR2_AWDCH 0x00FF0000U 00e5a3: line 3493 define DFSDM_FLTCR2_EXCH 0x0000FF00U 00e5c4: line 3494 define DFSDM_FLTCR2_CKABIE 0x00000040U 00e5e7: line 3495 define DFSDM_FLTCR2_SCDIE 0x00000020U 00e609: line 3496 define DFSDM_FLTCR2_AWDIE 0x00000010U 00e62b: line 3497 define DFSDM_FLTCR2_ROVRIE 0x00000008U 00e64e: line 3498 define DFSDM_FLTCR2_JOVRIE 0x00000004U 00e671: line 3499 define DFSDM_FLTCR2_REOCIE 0x00000002U 00e694: line 3500 define DFSDM_FLTCR2_JEOCIE 0x00000001U 00e6b7: line 3503 define DFSDM_FLTISR_SCDF 0xFF000000U 00e6d8: line 3504 define DFSDM_FLTISR_CKABF 0x00FF0000U 00e6fa: line 3505 define DFSDM_FLTISR_RCIP 0x00004000U 00e71b: line 3506 define DFSDM_FLTISR_JCIP 0x00002000U 00e73c: line 3507 define DFSDM_FLTISR_AWDF 0x00000010U 00e75d: line 3508 define DFSDM_FLTISR_ROVRF 0x00000008U 00e77f: line 3509 define DFSDM_FLTISR_JOVRF 0x00000004U 00e7a1: line 3510 define DFSDM_FLTISR_REOCF 0x00000002U 00e7c3: line 3511 define DFSDM_FLTISR_JEOCF 0x00000001U 00e7e5: line 3514 define DFSDM_FLTICR_CLRSCSDF 0xFF000000U 00e80a: line 3515 define DFSDM_FLTICR_CLRCKABF 0x00FF0000U 00e82f: line 3516 define DFSDM_FLTICR_CLRROVRF 0x00000008U 00e854: line 3517 define DFSDM_FLTICR_CLRJOVRF 0x00000004U 00e879: line 3520 define DFSDM_FLTJCHGR_JCHG 0x000000FFU 00e89c: line 3523 define DFSDM_FLTFCR_FORD 0xE0000000U 00e8bd: line 3524 define DFSDM_FLTFCR_FORD_2 0x80000000U 00e8e0: line 3525 define DFSDM_FLTFCR_FORD_1 0x40000000U 00e903: line 3526 define DFSDM_FLTFCR_FORD_0 0x20000000U 00e926: line 3527 define DFSDM_FLTFCR_FOSR 0x03FF0000U 00e947: line 3528 define DFSDM_FLTFCR_IOSR 0x000000FFU 00e968: line 3531 define DFSDM_FLTJDATAR_JDATA 0xFFFFFF00U 00e98d: line 3532 define DFSDM_FLTJDATAR_JDATACH 0x00000007U 00e9b4: line 3535 define DFSDM_FLTRDATAR_RDATA 0xFFFFFF00U 00e9d9: line 3536 define DFSDM_FLTRDATAR_RPEND 0x00000010U 00e9fe: line 3537 define DFSDM_FLTRDATAR_RDATACH 0x00000007U 00ea25: line 3540 define DFSDM_FLTAWHTR_AWHT 0xFFFFFF00U 00ea48: line 3541 define DFSDM_FLTAWHTR_BKAWH 0x0000000FU 00ea6c: line 3544 define DFSDM_FLTAWLTR_AWLT 0xFFFFFF00U 00ea8f: line 3545 define DFSDM_FLTAWLTR_BKAWL 0x0000000FU 00eab3: line 3548 define DFSDM_FLTAWSR_AWHTF 0x0000FF00U 00ead6: line 3549 define DFSDM_FLTAWSR_AWLTF 0x000000FFU 00eaf9: line 3552 define DFSDM_FLTAWCFR_CLRAWHTF 0x0000FF00U 00eb20: line 3553 define DFSDM_FLTAWCFR_CLRAWLTF 0x000000FFU 00eb47: line 3556 define DFSDM_FLTEXMAX_EXMAX 0xFFFFFF00U 00eb6b: line 3557 define DFSDM_FLTEXMAX_EXMAXCH 0x00000007U 00eb91: line 3560 define DFSDM_FLTEXMIN_EXMIN 0xFFFFFF00U 00ebb5: line 3561 define DFSDM_FLTEXMIN_EXMINCH 0x00000007U 00ebdb: line 3564 define DFSDM_FLTCNVTIMR_CNVCNT 0xFFFFFFF0U 00ec02: line 3578 define DCMI_CR_CAPTURE 0x00000001U 00ec21: line 3579 define DCMI_CR_CM 0x00000002U 00ec3b: line 3580 define DCMI_CR_CROP 0x00000004U 00ec57: line 3581 define DCMI_CR_JPEG 0x00000008U 00ec73: line 3582 define DCMI_CR_ESS 0x00000010U 00ec8e: line 3583 define DCMI_CR_PCKPOL 0x00000020U 00ecac: line 3584 define DCMI_CR_HSPOL 0x00000040U 00ecc9: line 3585 define DCMI_CR_VSPOL 0x00000080U 00ece6: line 3586 define DCMI_CR_FCRC_0 0x00000100U 00ed04: line 3587 define DCMI_CR_FCRC_1 0x00000200U 00ed22: line 3588 define DCMI_CR_EDM_0 0x00000400U 00ed3f: line 3589 define DCMI_CR_EDM_1 0x00000800U 00ed5c: line 3590 define DCMI_CR_CRE 0x00001000U 00ed77: line 3591 define DCMI_CR_ENABLE 0x00004000U 00ed95: line 3592 define DCMI_CR_BSM 0x00030000U 00edb0: line 3593 define DCMI_CR_BSM_0 0x00010000U 00edcd: line 3594 define DCMI_CR_BSM_1 0x00020000U 00edea: line 3595 define DCMI_CR_OEBS 0x00040000U 00ee06: line 3596 define DCMI_CR_LSM 0x00080000U 00ee21: line 3597 define DCMI_CR_OELS 0x00100000U 00ee3d: line 3600 define DCMI_SR_HSYNC 0x00000001U 00ee5a: line 3601 define DCMI_SR_VSYNC 0x00000002U 00ee77: line 3602 define DCMI_SR_FNE 0x00000004U 00ee92: line 3605 define DCMI_RIS_FRAME_RIS 0x00000001U 00eeb4: line 3606 define DCMI_RIS_OVR_RIS 0x00000002U 00eed4: line 3607 define DCMI_RIS_ERR_RIS 0x00000004U 00eef4: line 3608 define DCMI_RIS_VSYNC_RIS 0x00000008U 00ef16: line 3609 define DCMI_RIS_LINE_RIS 0x00000010U 00ef37: line 3612 define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS 00ef61: line 3613 define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS 00ef87: line 3614 define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS 00efad: line 3615 define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS 00efd7: line 3616 define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS 00efff: line 3619 define DCMI_IER_FRAME_IE 0x00000001U 00f020: line 3620 define DCMI_IER_OVR_IE 0x00000002U 00f03f: line 3621 define DCMI_IER_ERR_IE 0x00000004U 00f05e: line 3622 define DCMI_IER_VSYNC_IE 0x00000008U 00f07f: line 3623 define DCMI_IER_LINE_IE 0x00000010U 00f09f: line 3627 define DCMI_MIS_FRAME_MIS 0x00000001U 00f0c1: line 3628 define DCMI_MIS_OVR_MIS 0x00000002U 00f0e1: line 3629 define DCMI_MIS_ERR_MIS 0x00000004U 00f101: line 3630 define DCMI_MIS_VSYNC_MIS 0x00000008U 00f123: line 3631 define DCMI_MIS_LINE_MIS 0x00000010U 00f144: line 3635 define DCMI_ICR_FRAME_ISC 0x00000001U 00f166: line 3636 define DCMI_ICR_OVR_ISC 0x00000002U 00f186: line 3637 define DCMI_ICR_ERR_ISC 0x00000004U 00f1a6: line 3638 define DCMI_ICR_VSYNC_ISC 0x00000008U 00f1c8: line 3639 define DCMI_ICR_LINE_ISC 0x00000010U 00f1e9: line 3643 define DCMI_ESCR_FSC 0x000000FFU 00f206: line 3644 define DCMI_ESCR_LSC 0x0000FF00U 00f223: line 3645 define DCMI_ESCR_LEC 0x00FF0000U 00f240: line 3646 define DCMI_ESCR_FEC 0xFF000000U 00f25d: line 3649 define DCMI_ESUR_FSU 0x000000FFU 00f27a: line 3650 define DCMI_ESUR_LSU 0x0000FF00U 00f297: line 3651 define DCMI_ESUR_LEU 0x00FF0000U 00f2b4: line 3652 define DCMI_ESUR_FEU 0xFF000000U 00f2d1: line 3655 define DCMI_CWSTRT_HOFFCNT 0x00003FFFU 00f2f4: line 3656 define DCMI_CWSTRT_VST 0x1FFF0000U 00f313: line 3659 define DCMI_CWSIZE_CAPCNT 0x00003FFFU 00f335: line 3660 define DCMI_CWSIZE_VLINE 0x3FFF0000U 00f356: line 3663 define DCMI_DR_BYTE0 0x000000FFU 00f373: line 3664 define DCMI_DR_BYTE1 0x0000FF00U 00f390: line 3665 define DCMI_DR_BYTE2 0x00FF0000U 00f3ad: line 3666 define DCMI_DR_BYTE3 0xFF000000U 00f3ca: line 3674 define DMA_SxCR_CHSEL 0x1E000000U 00f3e8: line 3675 define DMA_SxCR_CHSEL_0 0x02000000U 00f408: line 3676 define DMA_SxCR_CHSEL_1 0x04000000U 00f428: line 3677 define DMA_SxCR_CHSEL_2 0x08000000U 00f448: line 3678 define DMA_SxCR_CHSEL_3 0x10000000U 00f468: line 3679 define DMA_SxCR_MBURST 0x01800000U 00f487: line 3680 define DMA_SxCR_MBURST_0 0x00800000U 00f4a8: line 3681 define DMA_SxCR_MBURST_1 0x01000000U 00f4c9: line 3682 define DMA_SxCR_PBURST 0x00600000U 00f4e8: line 3683 define DMA_SxCR_PBURST_0 0x00200000U 00f509: line 3684 define DMA_SxCR_PBURST_1 0x00400000U 00f52a: line 3685 define DMA_SxCR_CT 0x00080000U 00f545: line 3686 define DMA_SxCR_DBM 0x00040000U 00f561: line 3687 define DMA_SxCR_PL 0x00030000U 00f57c: line 3688 define DMA_SxCR_PL_0 0x00010000U 00f599: line 3689 define DMA_SxCR_PL_1 0x00020000U 00f5b6: line 3690 define DMA_SxCR_PINCOS 0x00008000U 00f5d5: line 3691 define DMA_SxCR_MSIZE 0x00006000U 00f5f3: line 3692 define DMA_SxCR_MSIZE_0 0x00002000U 00f613: line 3693 define DMA_SxCR_MSIZE_1 0x00004000U 00f633: line 3694 define DMA_SxCR_PSIZE 0x00001800U 00f651: line 3695 define DMA_SxCR_PSIZE_0 0x00000800U 00f671: line 3696 define DMA_SxCR_PSIZE_1 0x00001000U 00f691: line 3697 define DMA_SxCR_MINC 0x00000400U 00f6ae: line 3698 define DMA_SxCR_PINC 0x00000200U 00f6cb: line 3699 define DMA_SxCR_CIRC 0x00000100U 00f6e8: line 3700 define DMA_SxCR_DIR 0x000000C0U 00f704: line 3701 define DMA_SxCR_DIR_0 0x00000040U 00f722: line 3702 define DMA_SxCR_DIR_1 0x00000080U 00f740: line 3703 define DMA_SxCR_PFCTRL 0x00000020U 00f75f: line 3704 define DMA_SxCR_TCIE 0x00000010U 00f77c: line 3705 define DMA_SxCR_HTIE 0x00000008U 00f799: line 3706 define DMA_SxCR_TEIE 0x00000004U 00f7b6: line 3707 define DMA_SxCR_DMEIE 0x00000002U 00f7d4: line 3708 define DMA_SxCR_EN 0x00000001U 00f7ef: line 3711 define DMA_SxNDT 0x0000FFFFU 00f808: line 3712 define DMA_SxNDT_0 0x00000001U 00f823: line 3713 define DMA_SxNDT_1 0x00000002U 00f83e: line 3714 define DMA_SxNDT_2 0x00000004U 00f859: line 3715 define DMA_SxNDT_3 0x00000008U 00f874: line 3716 define DMA_SxNDT_4 0x00000010U 00f88f: line 3717 define DMA_SxNDT_5 0x00000020U 00f8aa: line 3718 define DMA_SxNDT_6 0x00000040U 00f8c5: line 3719 define DMA_SxNDT_7 0x00000080U 00f8e0: line 3720 define DMA_SxNDT_8 0x00000100U 00f8fb: line 3721 define DMA_SxNDT_9 0x00000200U 00f916: line 3722 define DMA_SxNDT_10 0x00000400U 00f932: line 3723 define DMA_SxNDT_11 0x00000800U 00f94e: line 3724 define DMA_SxNDT_12 0x00001000U 00f96a: line 3725 define DMA_SxNDT_13 0x00002000U 00f986: line 3726 define DMA_SxNDT_14 0x00004000U 00f9a2: line 3727 define DMA_SxNDT_15 0x00008000U 00f9be: line 3730 define DMA_SxFCR_FEIE 0x00000080U 00f9dc: line 3731 define DMA_SxFCR_FS 0x00000038U 00f9f8: line 3732 define DMA_SxFCR_FS_0 0x00000008U 00fa16: line 3733 define DMA_SxFCR_FS_1 0x00000010U 00fa34: line 3734 define DMA_SxFCR_FS_2 0x00000020U 00fa52: line 3735 define DMA_SxFCR_DMDIS 0x00000004U 00fa71: line 3736 define DMA_SxFCR_FTH 0x00000003U 00fa8e: line 3737 define DMA_SxFCR_FTH_0 0x00000001U 00faad: line 3738 define DMA_SxFCR_FTH_1 0x00000002U 00facc: line 3741 define DMA_LISR_TCIF3 0x08000000U 00faea: line 3742 define DMA_LISR_HTIF3 0x04000000U 00fb08: line 3743 define DMA_LISR_TEIF3 0x02000000U 00fb26: line 3744 define DMA_LISR_DMEIF3 0x01000000U 00fb45: line 3745 define DMA_LISR_FEIF3 0x00400000U 00fb63: line 3746 define DMA_LISR_TCIF2 0x00200000U 00fb81: line 3747 define DMA_LISR_HTIF2 0x00100000U 00fb9f: line 3748 define DMA_LISR_TEIF2 0x00080000U 00fbbd: line 3749 define DMA_LISR_DMEIF2 0x00040000U 00fbdc: line 3750 define DMA_LISR_FEIF2 0x00010000U 00fbfa: line 3751 define DMA_LISR_TCIF1 0x00000800U 00fc18: line 3752 define DMA_LISR_HTIF1 0x00000400U 00fc36: line 3753 define DMA_LISR_TEIF1 0x00000200U 00fc54: line 3754 define DMA_LISR_DMEIF1 0x00000100U 00fc73: line 3755 define DMA_LISR_FEIF1 0x00000040U 00fc91: line 3756 define DMA_LISR_TCIF0 0x00000020U 00fcaf: line 3757 define DMA_LISR_HTIF0 0x00000010U 00fccd: line 3758 define DMA_LISR_TEIF0 0x00000008U 00fceb: line 3759 define DMA_LISR_DMEIF0 0x00000004U 00fd0a: line 3760 define DMA_LISR_FEIF0 0x00000001U 00fd28: line 3763 define DMA_HISR_TCIF7 0x08000000U 00fd46: line 3764 define DMA_HISR_HTIF7 0x04000000U 00fd64: line 3765 define DMA_HISR_TEIF7 0x02000000U 00fd82: line 3766 define DMA_HISR_DMEIF7 0x01000000U 00fda1: line 3767 define DMA_HISR_FEIF7 0x00400000U 00fdbf: line 3768 define DMA_HISR_TCIF6 0x00200000U 00fddd: line 3769 define DMA_HISR_HTIF6 0x00100000U 00fdfb: line 3770 define DMA_HISR_TEIF6 0x00080000U 00fe19: line 3771 define DMA_HISR_DMEIF6 0x00040000U 00fe38: line 3772 define DMA_HISR_FEIF6 0x00010000U 00fe56: line 3773 define DMA_HISR_TCIF5 0x00000800U 00fe74: line 3774 define DMA_HISR_HTIF5 0x00000400U 00fe92: line 3775 define DMA_HISR_TEIF5 0x00000200U 00feb0: line 3776 define DMA_HISR_DMEIF5 0x00000100U 00fecf: line 3777 define DMA_HISR_FEIF5 0x00000040U 00feed: line 3778 define DMA_HISR_TCIF4 0x00000020U 00ff0b: line 3779 define DMA_HISR_HTIF4 0x00000010U 00ff29: line 3780 define DMA_HISR_TEIF4 0x00000008U 00ff47: line 3781 define DMA_HISR_DMEIF4 0x00000004U 00ff66: line 3782 define DMA_HISR_FEIF4 0x00000001U 00ff84: line 3785 define DMA_LIFCR_CTCIF3 0x08000000U 00ffa4: line 3786 define DMA_LIFCR_CHTIF3 0x04000000U 00ffc4: line 3787 define DMA_LIFCR_CTEIF3 0x02000000U 00ffe4: line 3788 define DMA_LIFCR_CDMEIF3 0x01000000U 010005: line 3789 define DMA_LIFCR_CFEIF3 0x00400000U 010025: line 3790 define DMA_LIFCR_CTCIF2 0x00200000U 010045: line 3791 define DMA_LIFCR_CHTIF2 0x00100000U 010065: line 3792 define DMA_LIFCR_CTEIF2 0x00080000U 010085: line 3793 define DMA_LIFCR_CDMEIF2 0x00040000U 0100a6: line 3794 define DMA_LIFCR_CFEIF2 0x00010000U 0100c6: line 3795 define DMA_LIFCR_CTCIF1 0x00000800U 0100e6: line 3796 define DMA_LIFCR_CHTIF1 0x00000400U 010106: line 3797 define DMA_LIFCR_CTEIF1 0x00000200U 010126: line 3798 define DMA_LIFCR_CDMEIF1 0x00000100U 010147: line 3799 define DMA_LIFCR_CFEIF1 0x00000040U 010167: line 3800 define DMA_LIFCR_CTCIF0 0x00000020U 010187: line 3801 define DMA_LIFCR_CHTIF0 0x00000010U 0101a7: line 3802 define DMA_LIFCR_CTEIF0 0x00000008U 0101c7: line 3803 define DMA_LIFCR_CDMEIF0 0x00000004U 0101e8: line 3804 define DMA_LIFCR_CFEIF0 0x00000001U 010208: line 3807 define DMA_HIFCR_CTCIF7 0x08000000U 010228: line 3808 define DMA_HIFCR_CHTIF7 0x04000000U 010248: line 3809 define DMA_HIFCR_CTEIF7 0x02000000U 010268: line 3810 define DMA_HIFCR_CDMEIF7 0x01000000U 010289: line 3811 define DMA_HIFCR_CFEIF7 0x00400000U 0102a9: line 3812 define DMA_HIFCR_CTCIF6 0x00200000U 0102c9: line 3813 define DMA_HIFCR_CHTIF6 0x00100000U 0102e9: line 3814 define DMA_HIFCR_CTEIF6 0x00080000U 010309: line 3815 define DMA_HIFCR_CDMEIF6 0x00040000U 01032a: line 3816 define DMA_HIFCR_CFEIF6 0x00010000U 01034a: line 3817 define DMA_HIFCR_CTCIF5 0x00000800U 01036a: line 3818 define DMA_HIFCR_CHTIF5 0x00000400U 01038a: line 3819 define DMA_HIFCR_CTEIF5 0x00000200U 0103aa: line 3820 define DMA_HIFCR_CDMEIF5 0x00000100U 0103cb: line 3821 define DMA_HIFCR_CFEIF5 0x00000040U 0103eb: line 3822 define DMA_HIFCR_CTCIF4 0x00000020U 01040b: line 3823 define DMA_HIFCR_CHTIF4 0x00000010U 01042b: line 3824 define DMA_HIFCR_CTEIF4 0x00000008U 01044b: line 3825 define DMA_HIFCR_CDMEIF4 0x00000004U 01046c: line 3826 define DMA_HIFCR_CFEIF4 0x00000001U 01048c: line 3836 define DMA2D_CR_START 0x00000001U 0104aa: line 3837 define DMA2D_CR_SUSP 0x00000002U 0104c7: line 3838 define DMA2D_CR_ABORT 0x00000004U 0104e5: line 3839 define DMA2D_CR_TEIE 0x00000100U 010502: line 3840 define DMA2D_CR_TCIE 0x00000200U 01051f: line 3841 define DMA2D_CR_TWIE 0x00000400U 01053c: line 3842 define DMA2D_CR_CAEIE 0x00000800U 01055a: line 3843 define DMA2D_CR_CTCIE 0x00001000U 010578: line 3844 define DMA2D_CR_CEIE 0x00002000U 010595: line 3845 define DMA2D_CR_MODE 0x00030000U 0105b2: line 3846 define DMA2D_CR_MODE_0 0x00010000U 0105d1: line 3847 define DMA2D_CR_MODE_1 0x00020000U 0105f0: line 3851 define DMA2D_ISR_TEIF 0x00000001U 01060e: line 3852 define DMA2D_ISR_TCIF 0x00000002U 01062c: line 3853 define DMA2D_ISR_TWIF 0x00000004U 01064a: line 3854 define DMA2D_ISR_CAEIF 0x00000008U 010669: line 3855 define DMA2D_ISR_CTCIF 0x00000010U 010688: line 3856 define DMA2D_ISR_CEIF 0x00000020U 0106a6: line 3860 define DMA2D_IFCR_CTEIF 0x00000001U 0106c6: line 3861 define DMA2D_IFCR_CTCIF 0x00000002U 0106e6: line 3862 define DMA2D_IFCR_CTWIF 0x00000004U 010706: line 3863 define DMA2D_IFCR_CAECIF 0x00000008U 010727: line 3864 define DMA2D_IFCR_CCTCIF 0x00000010U 010748: line 3865 define DMA2D_IFCR_CCEIF 0x00000020U 010768: line 3868 define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF 01078d: line 3869 define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF 0107b2: line 3870 define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF 0107d7: line 3871 define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF 0107fe: line 3872 define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF 010825: line 3873 define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF 01084a: line 3877 define DMA2D_FGMAR_MA 0xFFFFFFFFU 010868: line 3881 define DMA2D_FGOR_LO 0x00003FFFU 010885: line 3885 define DMA2D_BGMAR_MA 0xFFFFFFFFU 0108a3: line 3889 define DMA2D_BGOR_LO 0x00003FFFU 0108c0: line 3893 define DMA2D_FGPFCCR_CM 0x0000000FU 0108e0: line 3894 define DMA2D_FGPFCCR_CM_0 0x00000001U 010902: line 3895 define DMA2D_FGPFCCR_CM_1 0x00000002U 010924: line 3896 define DMA2D_FGPFCCR_CM_2 0x00000004U 010946: line 3897 define DMA2D_FGPFCCR_CM_3 0x00000008U 010968: line 3898 define DMA2D_FGPFCCR_CCM 0x00000010U 010989: line 3899 define DMA2D_FGPFCCR_START 0x00000020U 0109ac: line 3900 define DMA2D_FGPFCCR_CS 0x0000FF00U 0109cc: line 3901 define DMA2D_FGPFCCR_AM 0x00030000U 0109ec: line 3902 define DMA2D_FGPFCCR_AM_0 0x00010000U 010a0e: line 3903 define DMA2D_FGPFCCR_AM_1 0x00020000U 010a30: line 3904 define DMA2D_FGPFCCR_AI 0x00100000U 010a50: line 3905 define DMA2D_FGPFCCR_RBS 0x00200000U 010a71: line 3906 define DMA2D_FGPFCCR_ALPHA 0xFF000000U 010a94: line 3910 define DMA2D_FGCOLR_BLUE 0x000000FFU 010ab5: line 3911 define DMA2D_FGCOLR_GREEN 0x0000FF00U 010ad7: line 3912 define DMA2D_FGCOLR_RED 0x00FF0000U 010af7: line 3916 define DMA2D_BGPFCCR_CM 0x0000000FU 010b17: line 3917 define DMA2D_BGPFCCR_CM_0 0x00000001U 010b39: line 3918 define DMA2D_BGPFCCR_CM_1 0x00000002U 010b5b: line 3919 define DMA2D_BGPFCCR_CM_2 0x00000004U 010b7d: line 3920 define DMA2D_FGPFCCR_CM_3 0x00000008U 010b9f: line 3921 define DMA2D_BGPFCCR_CCM 0x00000010U 010bc0: line 3922 define DMA2D_BGPFCCR_START 0x00000020U 010be3: line 3923 define DMA2D_BGPFCCR_CS 0x0000FF00U 010c03: line 3924 define DMA2D_BGPFCCR_AM 0x00030000U 010c23: line 3925 define DMA2D_BGPFCCR_AM_0 0x00010000U 010c45: line 3926 define DMA2D_BGPFCCR_AM_1 0x00020000U 010c67: line 3927 define DMA2D_BGPFCCR_AI 0x00100000U 010c87: line 3928 define DMA2D_BGPFCCR_RBS 0x00200000U 010ca8: line 3929 define DMA2D_BGPFCCR_ALPHA 0xFF000000U 010ccb: line 3933 define DMA2D_BGCOLR_BLUE 0x000000FFU 010cec: line 3934 define DMA2D_BGCOLR_GREEN 0x0000FF00U 010d0e: line 3935 define DMA2D_BGCOLR_RED 0x00FF0000U 010d2e: line 3939 define DMA2D_FGCMAR_MA 0xFFFFFFFFU 010d4d: line 3943 define DMA2D_BGCMAR_MA 0xFFFFFFFFU 010d6c: line 3947 define DMA2D_OPFCCR_CM 0x00000007U 010d8b: line 3948 define DMA2D_OPFCCR_CM_0 0x00000001U 010dac: line 3949 define DMA2D_OPFCCR_CM_1 0x00000002U 010dcd: line 3950 define DMA2D_OPFCCR_CM_2 0x00000004U 010dee: line 3951 define DMA2D_OPFCCR_AI 0x00100000U 010e0d: line 3952 define DMA2D_OPFCCR_RBS 0x00200000U 010e2d: line 3958 define DMA2D_OCOLR_BLUE_1 0x000000FFU 010e4f: line 3959 define DMA2D_OCOLR_GREEN_1 0x0000FF00U 010e72: line 3960 define DMA2D_OCOLR_RED_1 0x00FF0000U 010e93: line 3961 define DMA2D_OCOLR_ALPHA_1 0xFF000000U 010eb6: line 3964 define DMA2D_OCOLR_BLUE_2 0x0000001FU 010ed8: line 3965 define DMA2D_OCOLR_GREEN_2 0x000007E0U 010efb: line 3966 define DMA2D_OCOLR_RED_2 0x0000F800U 010f1c: line 3969 define DMA2D_OCOLR_BLUE_3 0x0000001FU 010f3e: line 3970 define DMA2D_OCOLR_GREEN_3 0x000003E0U 010f61: line 3971 define DMA2D_OCOLR_RED_3 0x00007C00U 010f82: line 3972 define DMA2D_OCOLR_ALPHA_3 0x00008000U 010fa5: line 3975 define DMA2D_OCOLR_BLUE_4 0x0000000FU 010fc7: line 3976 define DMA2D_OCOLR_GREEN_4 0x000000F0U 010fea: line 3977 define DMA2D_OCOLR_RED_4 0x00000F00U 01100b: line 3978 define DMA2D_OCOLR_ALPHA_4 0x0000F000U 01102e: line 3982 define DMA2D_OMAR_MA 0xFFFFFFFFU 01104b: line 3986 define DMA2D_OOR_LO 0x00003FFFU 011067: line 3990 define DMA2D_NLR_NL 0x0000FFFFU 011083: line 3991 define DMA2D_NLR_PL 0x3FFF0000U 01109f: line 3995 define DMA2D_LWR_LW 0x0000FFFFU 0110bb: line 3999 define DMA2D_AMTCR_EN 0x00000001U 0110d9: line 4000 define DMA2D_AMTCR_DT 0x0000FF00U 0110f7: line 4013 define EXTI_IMR_MR0 0x00000001U 011113: line 4014 define EXTI_IMR_MR1 0x00000002U 01112f: line 4015 define EXTI_IMR_MR2 0x00000004U 01114b: line 4016 define EXTI_IMR_MR3 0x00000008U 011167: line 4017 define EXTI_IMR_MR4 0x00000010U 011183: line 4018 define EXTI_IMR_MR5 0x00000020U 01119f: line 4019 define EXTI_IMR_MR6 0x00000040U 0111bb: line 4020 define EXTI_IMR_MR7 0x00000080U 0111d7: line 4021 define EXTI_IMR_MR8 0x00000100U 0111f3: line 4022 define EXTI_IMR_MR9 0x00000200U 01120f: line 4023 define EXTI_IMR_MR10 0x00000400U 01122c: line 4024 define EXTI_IMR_MR11 0x00000800U 011249: line 4025 define EXTI_IMR_MR12 0x00001000U 011266: line 4026 define EXTI_IMR_MR13 0x00002000U 011283: line 4027 define EXTI_IMR_MR14 0x00004000U 0112a0: line 4028 define EXTI_IMR_MR15 0x00008000U 0112bd: line 4029 define EXTI_IMR_MR16 0x00010000U 0112da: line 4030 define EXTI_IMR_MR17 0x00020000U 0112f7: line 4031 define EXTI_IMR_MR18 0x00040000U 011314: line 4032 define EXTI_IMR_MR19 0x00080000U 011331: line 4033 define EXTI_IMR_MR20 0x00100000U 01134e: line 4034 define EXTI_IMR_MR21 0x00200000U 01136b: line 4035 define EXTI_IMR_MR22 0x00400000U 011388: line 4036 define EXTI_IMR_MR23 0x00800000U 0113a5: line 4037 define EXTI_IMR_MR24 0x01000000U 0113c2: line 4040 define EXTI_IMR_IM0 EXTI_IMR_MR0 0113df: line 4041 define EXTI_IMR_IM1 EXTI_IMR_MR1 0113fc: line 4042 define EXTI_IMR_IM2 EXTI_IMR_MR2 011419: line 4043 define EXTI_IMR_IM3 EXTI_IMR_MR3 011436: line 4044 define EXTI_IMR_IM4 EXTI_IMR_MR4 011453: line 4045 define EXTI_IMR_IM5 EXTI_IMR_MR5 011470: line 4046 define EXTI_IMR_IM6 EXTI_IMR_MR6 01148d: line 4047 define EXTI_IMR_IM7 EXTI_IMR_MR7 0114aa: line 4048 define EXTI_IMR_IM8 EXTI_IMR_MR8 0114c7: line 4049 define EXTI_IMR_IM9 EXTI_IMR_MR9 0114e4: line 4050 define EXTI_IMR_IM10 EXTI_IMR_MR10 011503: line 4051 define EXTI_IMR_IM11 EXTI_IMR_MR11 011522: line 4052 define EXTI_IMR_IM12 EXTI_IMR_MR12 011541: line 4053 define EXTI_IMR_IM13 EXTI_IMR_MR13 011560: line 4054 define EXTI_IMR_IM14 EXTI_IMR_MR14 01157f: line 4055 define EXTI_IMR_IM15 EXTI_IMR_MR15 01159e: line 4056 define EXTI_IMR_IM16 EXTI_IMR_MR16 0115bd: line 4057 define EXTI_IMR_IM17 EXTI_IMR_MR17 0115dc: line 4058 define EXTI_IMR_IM18 EXTI_IMR_MR18 0115fb: line 4059 define EXTI_IMR_IM19 EXTI_IMR_MR19 01161a: line 4060 define EXTI_IMR_IM20 EXTI_IMR_MR20 011639: line 4061 define EXTI_IMR_IM21 EXTI_IMR_MR21 011658: line 4062 define EXTI_IMR_IM22 EXTI_IMR_MR22 011677: line 4063 define EXTI_IMR_IM23 EXTI_IMR_MR23 011696: line 4064 define EXTI_IMR_IM24 EXTI_IMR_MR24 0116b5: line 4066 define EXTI_IMR_IM 0x01FFFFFFU 0116d0: line 4069 define EXTI_EMR_MR0 0x00000001U 0116ec: line 4070 define EXTI_EMR_MR1 0x00000002U 011708: line 4071 define EXTI_EMR_MR2 0x00000004U 011724: line 4072 define EXTI_EMR_MR3 0x00000008U 011740: line 4073 define EXTI_EMR_MR4 0x00000010U 01175c: line 4074 define EXTI_EMR_MR5 0x00000020U 011778: line 4075 define EXTI_EMR_MR6 0x00000040U 011794: line 4076 define EXTI_EMR_MR7 0x00000080U 0117b0: line 4077 define EXTI_EMR_MR8 0x00000100U 0117cc: line 4078 define EXTI_EMR_MR9 0x00000200U 0117e8: line 4079 define EXTI_EMR_MR10 0x00000400U 011805: line 4080 define EXTI_EMR_MR11 0x00000800U 011822: line 4081 define EXTI_EMR_MR12 0x00001000U 01183f: line 4082 define EXTI_EMR_MR13 0x00002000U 01185c: line 4083 define EXTI_EMR_MR14 0x00004000U 011879: line 4084 define EXTI_EMR_MR15 0x00008000U 011896: line 4085 define EXTI_EMR_MR16 0x00010000U 0118b3: line 4086 define EXTI_EMR_MR17 0x00020000U 0118d0: line 4087 define EXTI_EMR_MR18 0x00040000U 0118ed: line 4088 define EXTI_EMR_MR19 0x00080000U 01190a: line 4089 define EXTI_EMR_MR20 0x00100000U 011927: line 4090 define EXTI_EMR_MR21 0x00200000U 011944: line 4091 define EXTI_EMR_MR22 0x00400000U 011961: line 4092 define EXTI_EMR_MR23 0x00800000U 01197e: line 4093 define EXTI_EMR_MR24 0x01000000U 01199b: line 4096 define EXTI_EMR_EM0 EXTI_EMR_MR0 0119b8: line 4097 define EXTI_EMR_EM1 EXTI_EMR_MR1 0119d5: line 4098 define EXTI_EMR_EM2 EXTI_EMR_MR2 0119f2: line 4099 define EXTI_EMR_EM3 EXTI_EMR_MR3 011a0f: line 4100 define EXTI_EMR_EM4 EXTI_EMR_MR4 011a2c: line 4101 define EXTI_EMR_EM5 EXTI_EMR_MR5 011a49: line 4102 define EXTI_EMR_EM6 EXTI_EMR_MR6 011a66: line 4103 define EXTI_EMR_EM7 EXTI_EMR_MR7 011a83: line 4104 define EXTI_EMR_EM8 EXTI_EMR_MR8 011aa0: line 4105 define EXTI_EMR_EM9 EXTI_EMR_MR9 011abd: line 4106 define EXTI_EMR_EM10 EXTI_EMR_MR10 011adc: line 4107 define EXTI_EMR_EM11 EXTI_EMR_MR11 011afb: line 4108 define EXTI_EMR_EM12 EXTI_EMR_MR12 011b1a: line 4109 define EXTI_EMR_EM13 EXTI_EMR_MR13 011b39: line 4110 define EXTI_EMR_EM14 EXTI_EMR_MR14 011b58: line 4111 define EXTI_EMR_EM15 EXTI_EMR_MR15 011b77: line 4112 define EXTI_EMR_EM16 EXTI_EMR_MR16 011b96: line 4113 define EXTI_EMR_EM17 EXTI_EMR_MR17 011bb5: line 4114 define EXTI_EMR_EM18 EXTI_EMR_MR18 011bd4: line 4115 define EXTI_EMR_EM19 EXTI_EMR_MR19 011bf3: line 4116 define EXTI_EMR_EM20 EXTI_EMR_MR20 011c12: line 4117 define EXTI_EMR_EM21 EXTI_EMR_MR21 011c31: line 4118 define EXTI_EMR_EM22 EXTI_EMR_MR22 011c50: line 4119 define EXTI_EMR_EM23 EXTI_EMR_MR23 011c6f: line 4120 define EXTI_EMR_EM24 EXTI_EMR_MR24 011c8e: line 4124 define EXTI_RTSR_TR0 0x00000001U 011cab: line 4125 define EXTI_RTSR_TR1 0x00000002U 011cc8: line 4126 define EXTI_RTSR_TR2 0x00000004U 011ce5: line 4127 define EXTI_RTSR_TR3 0x00000008U 011d02: line 4128 define EXTI_RTSR_TR4 0x00000010U 011d1f: line 4129 define EXTI_RTSR_TR5 0x00000020U 011d3c: line 4130 define EXTI_RTSR_TR6 0x00000040U 011d59: line 4131 define EXTI_RTSR_TR7 0x00000080U 011d76: line 4132 define EXTI_RTSR_TR8 0x00000100U 011d93: line 4133 define EXTI_RTSR_TR9 0x00000200U 011db0: line 4134 define EXTI_RTSR_TR10 0x00000400U 011dce: line 4135 define EXTI_RTSR_TR11 0x00000800U 011dec: line 4136 define EXTI_RTSR_TR12 0x00001000U 011e0a: line 4137 define EXTI_RTSR_TR13 0x00002000U 011e28: line 4138 define EXTI_RTSR_TR14 0x00004000U 011e46: line 4139 define EXTI_RTSR_TR15 0x00008000U 011e64: line 4140 define EXTI_RTSR_TR16 0x00010000U 011e82: line 4141 define EXTI_RTSR_TR17 0x00020000U 011ea0: line 4142 define EXTI_RTSR_TR18 0x00040000U 011ebe: line 4143 define EXTI_RTSR_TR19 0x00080000U 011edc: line 4144 define EXTI_RTSR_TR20 0x00100000U 011efa: line 4145 define EXTI_RTSR_TR21 0x00200000U 011f18: line 4146 define EXTI_RTSR_TR22 0x00400000U 011f36: line 4147 define EXTI_RTSR_TR23 0x00800000U 011f54: line 4148 define EXTI_RTSR_TR24 0x01000000U 011f72: line 4151 define EXTI_FTSR_TR0 0x00000001U 011f8f: line 4152 define EXTI_FTSR_TR1 0x00000002U 011fac: line 4153 define EXTI_FTSR_TR2 0x00000004U 011fc9: line 4154 define EXTI_FTSR_TR3 0x00000008U 011fe6: line 4155 define EXTI_FTSR_TR4 0x00000010U 012003: line 4156 define EXTI_FTSR_TR5 0x00000020U 012020: line 4157 define EXTI_FTSR_TR6 0x00000040U 01203d: line 4158 define EXTI_FTSR_TR7 0x00000080U 01205a: line 4159 define EXTI_FTSR_TR8 0x00000100U 012077: line 4160 define EXTI_FTSR_TR9 0x00000200U 012094: line 4161 define EXTI_FTSR_TR10 0x00000400U 0120b2: line 4162 define EXTI_FTSR_TR11 0x00000800U 0120d0: line 4163 define EXTI_FTSR_TR12 0x00001000U 0120ee: line 4164 define EXTI_FTSR_TR13 0x00002000U 01210c: line 4165 define EXTI_FTSR_TR14 0x00004000U 01212a: line 4166 define EXTI_FTSR_TR15 0x00008000U 012148: line 4167 define EXTI_FTSR_TR16 0x00010000U 012166: line 4168 define EXTI_FTSR_TR17 0x00020000U 012184: line 4169 define EXTI_FTSR_TR18 0x00040000U 0121a2: line 4170 define EXTI_FTSR_TR19 0x00080000U 0121c0: line 4171 define EXTI_FTSR_TR20 0x00100000U 0121de: line 4172 define EXTI_FTSR_TR21 0x00200000U 0121fc: line 4173 define EXTI_FTSR_TR22 0x00400000U 01221a: line 4174 define EXTI_FTSR_TR23 0x00800000U 012238: line 4175 define EXTI_FTSR_TR24 0x01000000U 012256: line 4178 define EXTI_SWIER_SWIER0 0x00000001U 012277: line 4179 define EXTI_SWIER_SWIER1 0x00000002U 012298: line 4180 define EXTI_SWIER_SWIER2 0x00000004U 0122b9: line 4181 define EXTI_SWIER_SWIER3 0x00000008U 0122da: line 4182 define EXTI_SWIER_SWIER4 0x00000010U 0122fb: line 4183 define EXTI_SWIER_SWIER5 0x00000020U 01231c: line 4184 define EXTI_SWIER_SWIER6 0x00000040U 01233d: line 4185 define EXTI_SWIER_SWIER7 0x00000080U 01235e: line 4186 define EXTI_SWIER_SWIER8 0x00000100U 01237f: line 4187 define EXTI_SWIER_SWIER9 0x00000200U 0123a0: line 4188 define EXTI_SWIER_SWIER10 0x00000400U 0123c2: line 4189 define EXTI_SWIER_SWIER11 0x00000800U 0123e4: line 4190 define EXTI_SWIER_SWIER12 0x00001000U 012406: line 4191 define EXTI_SWIER_SWIER13 0x00002000U 012428: line 4192 define EXTI_SWIER_SWIER14 0x00004000U 01244a: line 4193 define EXTI_SWIER_SWIER15 0x00008000U 01246c: line 4194 define EXTI_SWIER_SWIER16 0x00010000U 01248e: line 4195 define EXTI_SWIER_SWIER17 0x00020000U 0124b0: line 4196 define EXTI_SWIER_SWIER18 0x00040000U 0124d2: line 4197 define EXTI_SWIER_SWIER19 0x00080000U 0124f4: line 4198 define EXTI_SWIER_SWIER20 0x00100000U 012516: line 4199 define EXTI_SWIER_SWIER21 0x00200000U 012538: line 4200 define EXTI_SWIER_SWIER22 0x00400000U 01255a: line 4201 define EXTI_SWIER_SWIER23 0x00800000U 01257c: line 4202 define EXTI_SWIER_SWIER24 0x01000000U 01259e: line 4205 define EXTI_PR_PR0 0x00000001U 0125b9: line 4206 define EXTI_PR_PR1 0x00000002U 0125d4: line 4207 define EXTI_PR_PR2 0x00000004U 0125ef: line 4208 define EXTI_PR_PR3 0x00000008U 01260a: line 4209 define EXTI_PR_PR4 0x00000010U 012625: line 4210 define EXTI_PR_PR5 0x00000020U 012640: line 4211 define EXTI_PR_PR6 0x00000040U 01265b: line 4212 define EXTI_PR_PR7 0x00000080U 012676: line 4213 define EXTI_PR_PR8 0x00000100U 012691: line 4214 define EXTI_PR_PR9 0x00000200U 0126ac: line 4215 define EXTI_PR_PR10 0x00000400U 0126c8: line 4216 define EXTI_PR_PR11 0x00000800U 0126e4: line 4217 define EXTI_PR_PR12 0x00001000U 012700: line 4218 define EXTI_PR_PR13 0x00002000U 01271c: line 4219 define EXTI_PR_PR14 0x00004000U 012738: line 4220 define EXTI_PR_PR15 0x00008000U 012754: line 4221 define EXTI_PR_PR16 0x00010000U 012770: line 4222 define EXTI_PR_PR17 0x00020000U 01278c: line 4223 define EXTI_PR_PR18 0x00040000U 0127a8: line 4224 define EXTI_PR_PR19 0x00080000U 0127c4: line 4225 define EXTI_PR_PR20 0x00100000U 0127e0: line 4226 define EXTI_PR_PR21 0x00200000U 0127fc: line 4227 define EXTI_PR_PR22 0x00400000U 012818: line 4228 define EXTI_PR_PR23 0x00800000U 012834: line 4229 define EXTI_PR_PR24 0x01000000U 012850: line 4239 define FLASH_SECTOR_TOTAL 24 012869: line 4242 define FLASH_ACR_LATENCY 0x0000000FU 01288a: line 4243 define FLASH_ACR_LATENCY_0WS 0x00000000U 0128af: line 4244 define FLASH_ACR_LATENCY_1WS 0x00000001U 0128d4: line 4245 define FLASH_ACR_LATENCY_2WS 0x00000002U 0128f9: line 4246 define FLASH_ACR_LATENCY_3WS 0x00000003U 01291e: line 4247 define FLASH_ACR_LATENCY_4WS 0x00000004U 012943: line 4248 define FLASH_ACR_LATENCY_5WS 0x00000005U 012968: line 4249 define FLASH_ACR_LATENCY_6WS 0x00000006U 01298d: line 4250 define FLASH_ACR_LATENCY_7WS 0x00000007U 0129b2: line 4251 define FLASH_ACR_LATENCY_8WS 0x00000008U 0129d7: line 4252 define FLASH_ACR_LATENCY_9WS 0x00000009U 0129fc: line 4253 define FLASH_ACR_LATENCY_10WS 0x0000000AU 012a22: line 4254 define FLASH_ACR_LATENCY_11WS 0x0000000BU 012a48: line 4255 define FLASH_ACR_LATENCY_12WS 0x0000000CU 012a6e: line 4256 define FLASH_ACR_LATENCY_13WS 0x0000000DU 012a94: line 4257 define FLASH_ACR_LATENCY_14WS 0x0000000EU 012aba: line 4258 define FLASH_ACR_LATENCY_15WS 0x0000000FU 012ae0: line 4259 define FLASH_ACR_PRFTEN 0x00000100U 012b00: line 4260 define FLASH_ACR_ARTEN 0x00000200U 012b1f: line 4261 define FLASH_ACR_ARTRST 0x00000800U 012b3f: line 4264 define FLASH_SR_EOP 0x00000001U 012b5b: line 4265 define FLASH_SR_OPERR 0x00000002U 012b79: line 4266 define FLASH_SR_WRPERR 0x00000010U 012b98: line 4267 define FLASH_SR_PGAERR 0x00000020U 012bb7: line 4268 define FLASH_SR_PGPERR 0x00000040U 012bd6: line 4269 define FLASH_SR_ERSERR 0x00000080U 012bf5: line 4270 define FLASH_SR_BSY 0x00010000U 012c11: line 4273 define FLASH_CR_PG 0x00000001U 012c2c: line 4274 define FLASH_CR_SER 0x00000002U 012c48: line 4275 define FLASH_CR_MER 0x00000004U 012c64: line 4276 define FLASH_CR_MER1 FLASH_CR_MER 012c82: line 4277 define FLASH_CR_SNB 0x000000F8U 012c9e: line 4278 define FLASH_CR_SNB_0 0x00000008U 012cbc: line 4279 define FLASH_CR_SNB_1 0x00000010U 012cda: line 4280 define FLASH_CR_SNB_2 0x00000020U 012cf8: line 4281 define FLASH_CR_SNB_3 0x00000040U 012d16: line 4282 define FLASH_CR_SNB_4 0x00000080U 012d34: line 4283 define FLASH_CR_PSIZE 0x00000300U 012d52: line 4284 define FLASH_CR_PSIZE_0 0x00000100U 012d72: line 4285 define FLASH_CR_PSIZE_1 0x00000200U 012d92: line 4286 define FLASH_CR_MER2 0x00008000U 012daf: line 4287 define FLASH_CR_STRT 0x00010000U 012dcc: line 4288 define FLASH_CR_EOPIE 0x01000000U 012dea: line 4289 define FLASH_CR_ERRIE 0x02000000U 012e08: line 4290 define FLASH_CR_LOCK 0x80000000U 012e25: line 4293 define FLASH_OPTCR_OPTLOCK 0x00000001U 012e48: line 4294 define FLASH_OPTCR_OPTSTRT 0x00000002U 012e6b: line 4295 define FLASH_OPTCR_BOR_LEV 0x0000000CU 012e8e: line 4296 define FLASH_OPTCR_BOR_LEV_0 0x00000004U 012eb3: line 4297 define FLASH_OPTCR_BOR_LEV_1 0x00000008U 012ed8: line 4298 define FLASH_OPTCR_WWDG_SW 0x00000010U 012efb: line 4299 define FLASH_OPTCR_IWDG_SW 0x00000020U 012f1e: line 4300 define FLASH_OPTCR_nRST_STOP 0x00000040U 012f43: line 4301 define FLASH_OPTCR_nRST_STDBY 0x00000080U 012f69: line 4302 define FLASH_OPTCR_RDP 0x0000FF00U 012f88: line 4303 define FLASH_OPTCR_RDP_0 0x00000100U 012fa9: line 4304 define FLASH_OPTCR_RDP_1 0x00000200U 012fca: line 4305 define FLASH_OPTCR_RDP_2 0x00000400U 012feb: line 4306 define FLASH_OPTCR_RDP_3 0x00000800U 01300c: line 4307 define FLASH_OPTCR_RDP_4 0x00001000U 01302d: line 4308 define FLASH_OPTCR_RDP_5 0x00002000U 01304e: line 4309 define FLASH_OPTCR_RDP_6 0x00004000U 01306f: line 4310 define FLASH_OPTCR_RDP_7 0x00008000U 013090: line 4311 define FLASH_OPTCR_nWRP 0x0FFF0000U 0130b0: line 4312 define FLASH_OPTCR_nWRP_0 0x00010000U 0130d2: line 4313 define FLASH_OPTCR_nWRP_1 0x00020000U 0130f4: line 4314 define FLASH_OPTCR_nWRP_2 0x00040000U 013116: line 4315 define FLASH_OPTCR_nWRP_3 0x00080000U 013138: line 4316 define FLASH_OPTCR_nWRP_4 0x00100000U 01315a: line 4317 define FLASH_OPTCR_nWRP_5 0x00200000U 01317c: line 4318 define FLASH_OPTCR_nWRP_6 0x00400000U 01319e: line 4319 define FLASH_OPTCR_nWRP_7 0x00800000U 0131c0: line 4320 define FLASH_OPTCR_nWRP_8 0x01000000U 0131e2: line 4321 define FLASH_OPTCR_nWRP_9 0x02000000U 013204: line 4322 define FLASH_OPTCR_nWRP_10 0x04000000U 013227: line 4323 define FLASH_OPTCR_nWRP_11 0x08000000U 01324a: line 4324 define FLASH_OPTCR_nDBOOT 0x10000000U 01326c: line 4325 define FLASH_OPTCR_nDBANK 0x20000000U 01328e: line 4326 define FLASH_OPTCR_IWDG_STDBY 0x40000000U 0132b4: line 4327 define FLASH_OPTCR_IWDG_STOP 0x80000000U 0132d9: line 4330 define FLASH_OPTCR1_BOOT_ADD0 0x0000FFFFU 0132ff: line 4331 define FLASH_OPTCR1_BOOT_ADD1 0xFFFF0000U 013325: line 4340 define FMC_BCR1_MBKEN 0x00000001U 013343: line 4341 define FMC_BCR1_MUXEN 0x00000002U 013361: line 4342 define FMC_BCR1_MTYP 0x0000000CU 01337e: line 4343 define FMC_BCR1_MTYP_0 0x00000004U 01339d: line 4344 define FMC_BCR1_MTYP_1 0x00000008U 0133bc: line 4345 define FMC_BCR1_MWID 0x00000030U 0133d9: line 4346 define FMC_BCR1_MWID_0 0x00000010U 0133f8: line 4347 define FMC_BCR1_MWID_1 0x00000020U 013417: line 4348 define FMC_BCR1_FACCEN 0x00000040U 013436: line 4349 define FMC_BCR1_BURSTEN 0x00000100U 013456: line 4350 define FMC_BCR1_WAITPOL 0x00000200U 013476: line 4351 define FMC_BCR1_WRAPMOD 0x00000400U 013496: line 4352 define FMC_BCR1_WAITCFG 0x00000800U 0134b6: line 4353 define FMC_BCR1_WREN 0x00001000U 0134d3: line 4354 define FMC_BCR1_WAITEN 0x00002000U 0134f2: line 4355 define FMC_BCR1_EXTMOD 0x00004000U 013511: line 4356 define FMC_BCR1_ASYNCWAIT 0x00008000U 013533: line 4357 define FMC_BCR1_CPSIZE 0x00070000U 013552: line 4358 define FMC_BCR1_CPSIZE_0 0x00010000U 013573: line 4359 define FMC_BCR1_CPSIZE_1 0x00020000U 013594: line 4360 define FMC_BCR1_CPSIZE_2 0x00040000U 0135b5: line 4361 define FMC_BCR1_CBURSTRW 0x00080000U 0135d6: line 4362 define FMC_BCR1_CCLKEN 0x00100000U 0135f5: line 4363 define FMC_BCR1_WFDIS 0x00200000U 013613: line 4366 define FMC_BCR2_MBKEN 0x00000001U 013631: line 4367 define FMC_BCR2_MUXEN 0x00000002U 01364f: line 4368 define FMC_BCR2_MTYP 0x0000000CU 01366c: line 4369 define FMC_BCR2_MTYP_0 0x00000004U 01368b: line 4370 define FMC_BCR2_MTYP_1 0x00000008U 0136aa: line 4371 define FMC_BCR2_MWID 0x00000030U 0136c7: line 4372 define FMC_BCR2_MWID_0 0x00000010U 0136e6: line 4373 define FMC_BCR2_MWID_1 0x00000020U 013705: line 4374 define FMC_BCR2_FACCEN 0x00000040U 013724: line 4375 define FMC_BCR2_BURSTEN 0x00000100U 013744: line 4376 define FMC_BCR2_WAITPOL 0x00000200U 013764: line 4377 define FMC_BCR2_WRAPMOD 0x00000400U 013784: line 4378 define FMC_BCR2_WAITCFG 0x00000800U 0137a4: line 4379 define FMC_BCR2_WREN 0x00001000U 0137c1: line 4380 define FMC_BCR2_WAITEN 0x00002000U 0137e0: line 4381 define FMC_BCR2_EXTMOD 0x00004000U 0137ff: line 4382 define FMC_BCR2_ASYNCWAIT 0x00008000U 013821: line 4383 define FMC_BCR2_CPSIZE 0x00070000U 013840: line 4384 define FMC_BCR2_CPSIZE_0 0x00010000U 013861: line 4385 define FMC_BCR2_CPSIZE_1 0x00020000U 013882: line 4386 define FMC_BCR2_CPSIZE_2 0x00040000U 0138a3: line 4387 define FMC_BCR2_CBURSTRW 0x00080000U 0138c4: line 4390 define FMC_BCR3_MBKEN 0x00000001U 0138e2: line 4391 define FMC_BCR3_MUXEN 0x00000002U 013900: line 4392 define FMC_BCR3_MTYP 0x0000000CU 01391d: line 4393 define FMC_BCR3_MTYP_0 0x00000004U 01393c: line 4394 define FMC_BCR3_MTYP_1 0x00000008U 01395b: line 4395 define FMC_BCR3_MWID 0x00000030U 013978: line 4396 define FMC_BCR3_MWID_0 0x00000010U 013997: line 4397 define FMC_BCR3_MWID_1 0x00000020U 0139b6: line 4398 define FMC_BCR3_FACCEN 0x00000040U 0139d5: line 4399 define FMC_BCR3_BURSTEN 0x00000100U 0139f5: line 4400 define FMC_BCR3_WAITPOL 0x00000200U 013a15: line 4401 define FMC_BCR3_WRAPMOD 0x00000400U 013a35: line 4402 define FMC_BCR3_WAITCFG 0x00000800U 013a55: line 4403 define FMC_BCR3_WREN 0x00001000U 013a72: line 4404 define FMC_BCR3_WAITEN 0x00002000U 013a91: line 4405 define FMC_BCR3_EXTMOD 0x00004000U 013ab0: line 4406 define FMC_BCR3_ASYNCWAIT 0x00008000U 013ad2: line 4407 define FMC_BCR3_CPSIZE 0x00070000U 013af1: line 4408 define FMC_BCR3_CPSIZE_0 0x00010000U 013b12: line 4409 define FMC_BCR3_CPSIZE_1 0x00020000U 013b33: line 4410 define FMC_BCR3_CPSIZE_2 0x00040000U 013b54: line 4411 define FMC_BCR3_CBURSTRW 0x00080000U 013b75: line 4414 define FMC_BCR4_MBKEN 0x00000001U 013b93: line 4415 define FMC_BCR4_MUXEN 0x00000002U 013bb1: line 4416 define FMC_BCR4_MTYP 0x0000000CU 013bce: line 4417 define FMC_BCR4_MTYP_0 0x00000004U 013bed: line 4418 define FMC_BCR4_MTYP_1 0x00000008U 013c0c: line 4419 define FMC_BCR4_MWID 0x00000030U 013c29: line 4420 define FMC_BCR4_MWID_0 0x00000010U 013c48: line 4421 define FMC_BCR4_MWID_1 0x00000020U 013c67: line 4422 define FMC_BCR4_FACCEN 0x00000040U 013c86: line 4423 define FMC_BCR4_BURSTEN 0x00000100U 013ca6: line 4424 define FMC_BCR4_WAITPOL 0x00000200U 013cc6: line 4425 define FMC_BCR4_WRAPMOD 0x00000400U 013ce6: line 4426 define FMC_BCR4_WAITCFG 0x00000800U 013d06: line 4427 define FMC_BCR4_WREN 0x00001000U 013d23: line 4428 define FMC_BCR4_WAITEN 0x00002000U 013d42: line 4429 define FMC_BCR4_EXTMOD 0x00004000U 013d61: line 4430 define FMC_BCR4_ASYNCWAIT 0x00008000U 013d83: line 4431 define FMC_BCR4_CPSIZE 0x00070000U 013da2: line 4432 define FMC_BCR4_CPSIZE_0 0x00010000U 013dc3: line 4433 define FMC_BCR4_CPSIZE_1 0x00020000U 013de4: line 4434 define FMC_BCR4_CPSIZE_2 0x00040000U 013e05: line 4435 define FMC_BCR4_CBURSTRW 0x00080000U 013e26: line 4438 define FMC_BTR1_ADDSET 0x0000000FU 013e45: line 4439 define FMC_BTR1_ADDSET_0 0x00000001U 013e66: line 4440 define FMC_BTR1_ADDSET_1 0x00000002U 013e87: line 4441 define FMC_BTR1_ADDSET_2 0x00000004U 013ea8: line 4442 define FMC_BTR1_ADDSET_3 0x00000008U 013ec9: line 4443 define FMC_BTR1_ADDHLD 0x000000F0U 013ee8: line 4444 define FMC_BTR1_ADDHLD_0 0x00000010U 013f09: line 4445 define FMC_BTR1_ADDHLD_1 0x00000020U 013f2a: line 4446 define FMC_BTR1_ADDHLD_2 0x00000040U 013f4b: line 4447 define FMC_BTR1_ADDHLD_3 0x00000080U 013f6c: line 4448 define FMC_BTR1_DATAST 0x0000FF00U 013f8b: line 4449 define FMC_BTR1_DATAST_0 0x00000100U 013fac: line 4450 define FMC_BTR1_DATAST_1 0x00000200U 013fcd: line 4451 define FMC_BTR1_DATAST_2 0x00000400U 013fee: line 4452 define FMC_BTR1_DATAST_3 0x00000800U 01400f: line 4453 define FMC_BTR1_DATAST_4 0x00001000U 014030: line 4454 define FMC_BTR1_DATAST_5 0x00002000U 014051: line 4455 define FMC_BTR1_DATAST_6 0x00004000U 014072: line 4456 define FMC_BTR1_DATAST_7 0x00008000U 014093: line 4457 define FMC_BTR1_BUSTURN 0x000F0000U 0140b3: line 4458 define FMC_BTR1_BUSTURN_0 0x00010000U 0140d5: line 4459 define FMC_BTR1_BUSTURN_1 0x00020000U 0140f7: line 4460 define FMC_BTR1_BUSTURN_2 0x00040000U 014119: line 4461 define FMC_BTR1_BUSTURN_3 0x00080000U 01413b: line 4462 define FMC_BTR1_CLKDIV 0x00F00000U 01415a: line 4463 define FMC_BTR1_CLKDIV_0 0x00100000U 01417b: line 4464 define FMC_BTR1_CLKDIV_1 0x00200000U 01419c: line 4465 define FMC_BTR1_CLKDIV_2 0x00400000U 0141bd: line 4466 define FMC_BTR1_CLKDIV_3 0x00800000U 0141de: line 4467 define FMC_BTR1_DATLAT 0x0F000000U 0141fd: line 4468 define FMC_BTR1_DATLAT_0 0x01000000U 01421e: line 4469 define FMC_BTR1_DATLAT_1 0x02000000U 01423f: line 4470 define FMC_BTR1_DATLAT_2 0x04000000U 014260: line 4471 define FMC_BTR1_DATLAT_3 0x08000000U 014281: line 4472 define FMC_BTR1_ACCMOD 0x30000000U 0142a0: line 4473 define FMC_BTR1_ACCMOD_0 0x10000000U 0142c1: line 4474 define FMC_BTR1_ACCMOD_1 0x20000000U 0142e2: line 4477 define FMC_BTR2_ADDSET 0x0000000FU 014301: line 4478 define FMC_BTR2_ADDSET_0 0x00000001U 014322: line 4479 define FMC_BTR2_ADDSET_1 0x00000002U 014343: line 4480 define FMC_BTR2_ADDSET_2 0x00000004U 014364: line 4481 define FMC_BTR2_ADDSET_3 0x00000008U 014385: line 4482 define FMC_BTR2_ADDHLD 0x000000F0U 0143a4: line 4483 define FMC_BTR2_ADDHLD_0 0x00000010U 0143c5: line 4484 define FMC_BTR2_ADDHLD_1 0x00000020U 0143e6: line 4485 define FMC_BTR2_ADDHLD_2 0x00000040U 014407: line 4486 define FMC_BTR2_ADDHLD_3 0x00000080U 014428: line 4487 define FMC_BTR2_DATAST 0x0000FF00U 014447: line 4488 define FMC_BTR2_DATAST_0 0x00000100U 014468: line 4489 define FMC_BTR2_DATAST_1 0x00000200U 014489: line 4490 define FMC_BTR2_DATAST_2 0x00000400U 0144aa: line 4491 define FMC_BTR2_DATAST_3 0x00000800U 0144cb: line 4492 define FMC_BTR2_DATAST_4 0x00001000U 0144ec: line 4493 define FMC_BTR2_DATAST_5 0x00002000U 01450d: line 4494 define FMC_BTR2_DATAST_6 0x00004000U 01452e: line 4495 define FMC_BTR2_DATAST_7 0x00008000U 01454f: line 4496 define FMC_BTR2_BUSTURN 0x000F0000U 01456f: line 4497 define FMC_BTR2_BUSTURN_0 0x00010000U 014591: line 4498 define FMC_BTR2_BUSTURN_1 0x00020000U 0145b3: line 4499 define FMC_BTR2_BUSTURN_2 0x00040000U 0145d5: line 4500 define FMC_BTR2_BUSTURN_3 0x00080000U 0145f7: line 4501 define FMC_BTR2_CLKDIV 0x00F00000U 014616: line 4502 define FMC_BTR2_CLKDIV_0 0x00100000U 014637: line 4503 define FMC_BTR2_CLKDIV_1 0x00200000U 014658: line 4504 define FMC_BTR2_CLKDIV_2 0x00400000U 014679: line 4505 define FMC_BTR2_CLKDIV_3 0x00800000U 01469a: line 4506 define FMC_BTR2_DATLAT 0x0F000000U 0146b9: line 4507 define FMC_BTR2_DATLAT_0 0x01000000U 0146da: line 4508 define FMC_BTR2_DATLAT_1 0x02000000U 0146fb: line 4509 define FMC_BTR2_DATLAT_2 0x04000000U 01471c: line 4510 define FMC_BTR2_DATLAT_3 0x08000000U 01473d: line 4511 define FMC_BTR2_ACCMOD 0x30000000U 01475c: line 4512 define FMC_BTR2_ACCMOD_0 0x10000000U 01477d: line 4513 define FMC_BTR2_ACCMOD_1 0x20000000U 01479e: line 4516 define FMC_BTR3_ADDSET 0x0000000FU 0147bd: line 4517 define FMC_BTR3_ADDSET_0 0x00000001U 0147de: line 4518 define FMC_BTR3_ADDSET_1 0x00000002U 0147ff: line 4519 define FMC_BTR3_ADDSET_2 0x00000004U 014820: line 4520 define FMC_BTR3_ADDSET_3 0x00000008U 014841: line 4521 define FMC_BTR3_ADDHLD 0x000000F0U 014860: line 4522 define FMC_BTR3_ADDHLD_0 0x00000010U 014881: line 4523 define FMC_BTR3_ADDHLD_1 0x00000020U 0148a2: line 4524 define FMC_BTR3_ADDHLD_2 0x00000040U 0148c3: line 4525 define FMC_BTR3_ADDHLD_3 0x00000080U 0148e4: line 4526 define FMC_BTR3_DATAST 0x0000FF00U 014903: line 4527 define FMC_BTR3_DATAST_0 0x00000100U 014924: line 4528 define FMC_BTR3_DATAST_1 0x00000200U 014945: line 4529 define FMC_BTR3_DATAST_2 0x00000400U 014966: line 4530 define FMC_BTR3_DATAST_3 0x00000800U 014987: line 4531 define FMC_BTR3_DATAST_4 0x00001000U 0149a8: line 4532 define FMC_BTR3_DATAST_5 0x00002000U 0149c9: line 4533 define FMC_BTR3_DATAST_6 0x00004000U 0149ea: line 4534 define FMC_BTR3_DATAST_7 0x00008000U 014a0b: line 4535 define FMC_BTR3_BUSTURN 0x000F0000U 014a2b: line 4536 define FMC_BTR3_BUSTURN_0 0x00010000U 014a4d: line 4537 define FMC_BTR3_BUSTURN_1 0x00020000U 014a6f: line 4538 define FMC_BTR3_BUSTURN_2 0x00040000U 014a91: line 4539 define FMC_BTR3_BUSTURN_3 0x00080000U 014ab3: line 4540 define FMC_BTR3_CLKDIV 0x00F00000U 014ad2: line 4541 define FMC_BTR3_CLKDIV_0 0x00100000U 014af3: line 4542 define FMC_BTR3_CLKDIV_1 0x00200000U 014b14: line 4543 define FMC_BTR3_CLKDIV_2 0x00400000U 014b35: line 4544 define FMC_BTR3_CLKDIV_3 0x00800000U 014b56: line 4545 define FMC_BTR3_DATLAT 0x0F000000U 014b75: line 4546 define FMC_BTR3_DATLAT_0 0x01000000U 014b96: line 4547 define FMC_BTR3_DATLAT_1 0x02000000U 014bb7: line 4548 define FMC_BTR3_DATLAT_2 0x04000000U 014bd8: line 4549 define FMC_BTR3_DATLAT_3 0x08000000U 014bf9: line 4550 define FMC_BTR3_ACCMOD 0x30000000U 014c18: line 4551 define FMC_BTR3_ACCMOD_0 0x10000000U 014c39: line 4552 define FMC_BTR3_ACCMOD_1 0x20000000U 014c5a: line 4555 define FMC_BTR4_ADDSET 0x0000000FU 014c79: line 4556 define FMC_BTR4_ADDSET_0 0x00000001U 014c9a: line 4557 define FMC_BTR4_ADDSET_1 0x00000002U 014cbb: line 4558 define FMC_BTR4_ADDSET_2 0x00000004U 014cdc: line 4559 define FMC_BTR4_ADDSET_3 0x00000008U 014cfd: line 4560 define FMC_BTR4_ADDHLD 0x000000F0U 014d1c: line 4561 define FMC_BTR4_ADDHLD_0 0x00000010U 014d3d: line 4562 define FMC_BTR4_ADDHLD_1 0x00000020U 014d5e: line 4563 define FMC_BTR4_ADDHLD_2 0x00000040U 014d7f: line 4564 define FMC_BTR4_ADDHLD_3 0x00000080U 014da0: line 4565 define FMC_BTR4_DATAST 0x0000FF00U 014dbf: line 4566 define FMC_BTR4_DATAST_0 0x00000100U 014de0: line 4567 define FMC_BTR4_DATAST_1 0x00000200U 014e01: line 4568 define FMC_BTR4_DATAST_2 0x00000400U 014e22: line 4569 define FMC_BTR4_DATAST_3 0x00000800U 014e43: line 4570 define FMC_BTR4_DATAST_4 0x00001000U 014e64: line 4571 define FMC_BTR4_DATAST_5 0x00002000U 014e85: line 4572 define FMC_BTR4_DATAST_6 0x00004000U 014ea6: line 4573 define FMC_BTR4_DATAST_7 0x00008000U 014ec7: line 4574 define FMC_BTR4_BUSTURN 0x000F0000U 014ee7: line 4575 define FMC_BTR4_BUSTURN_0 0x00010000U 014f09: line 4576 define FMC_BTR4_BUSTURN_1 0x00020000U 014f2b: line 4577 define FMC_BTR4_BUSTURN_2 0x00040000U 014f4d: line 4578 define FMC_BTR4_BUSTURN_3 0x00080000U 014f6f: line 4579 define FMC_BTR4_CLKDIV 0x00F00000U 014f8e: line 4580 define FMC_BTR4_CLKDIV_0 0x00100000U 014faf: line 4581 define FMC_BTR4_CLKDIV_1 0x00200000U 014fd0: line 4582 define FMC_BTR4_CLKDIV_2 0x00400000U 014ff1: line 4583 define FMC_BTR4_CLKDIV_3 0x00800000U 015012: line 4584 define FMC_BTR4_DATLAT 0x0F000000U 015031: line 4585 define FMC_BTR4_DATLAT_0 0x01000000U 015052: line 4586 define FMC_BTR4_DATLAT_1 0x02000000U 015073: line 4587 define FMC_BTR4_DATLAT_2 0x04000000U 015094: line 4588 define FMC_BTR4_DATLAT_3 0x08000000U 0150b5: line 4589 define FMC_BTR4_ACCMOD 0x30000000U 0150d4: line 4590 define FMC_BTR4_ACCMOD_0 0x10000000U 0150f5: line 4591 define FMC_BTR4_ACCMOD_1 0x20000000U 015116: line 4594 define FMC_BWTR1_ADDSET 0x0000000FU 015136: line 4595 define FMC_BWTR1_ADDSET_0 0x00000001U 015158: line 4596 define FMC_BWTR1_ADDSET_1 0x00000002U 01517a: line 4597 define FMC_BWTR1_ADDSET_2 0x00000004U 01519c: line 4598 define FMC_BWTR1_ADDSET_3 0x00000008U 0151be: line 4599 define FMC_BWTR1_ADDHLD 0x000000F0U 0151de: line 4600 define FMC_BWTR1_ADDHLD_0 0x00000010U 015200: line 4601 define FMC_BWTR1_ADDHLD_1 0x00000020U 015222: line 4602 define FMC_BWTR1_ADDHLD_2 0x00000040U 015244: line 4603 define FMC_BWTR1_ADDHLD_3 0x00000080U 015266: line 4604 define FMC_BWTR1_DATAST 0x0000FF00U 015286: line 4605 define FMC_BWTR1_DATAST_0 0x00000100U 0152a8: line 4606 define FMC_BWTR1_DATAST_1 0x00000200U 0152ca: line 4607 define FMC_BWTR1_DATAST_2 0x00000400U 0152ec: line 4608 define FMC_BWTR1_DATAST_3 0x00000800U 01530e: line 4609 define FMC_BWTR1_DATAST_4 0x00001000U 015330: line 4610 define FMC_BWTR1_DATAST_5 0x00002000U 015352: line 4611 define FMC_BWTR1_DATAST_6 0x00004000U 015374: line 4612 define FMC_BWTR1_DATAST_7 0x00008000U 015396: line 4613 define FMC_BWTR1_BUSTURN 0x000F0000U 0153b7: line 4614 define FMC_BWTR1_BUSTURN_0 0x00010000U 0153da: line 4615 define FMC_BWTR1_BUSTURN_1 0x00020000U 0153fd: line 4616 define FMC_BWTR1_BUSTURN_2 0x00040000U 015420: line 4617 define FMC_BWTR1_BUSTURN_3 0x00080000U 015443: line 4618 define FMC_BWTR1_ACCMOD 0x30000000U 015463: line 4619 define FMC_BWTR1_ACCMOD_0 0x10000000U 015485: line 4620 define FMC_BWTR1_ACCMOD_1 0x20000000U 0154a7: line 4623 define FMC_BWTR2_ADDSET 0x0000000FU 0154c7: line 4624 define FMC_BWTR2_ADDSET_0 0x00000001U 0154e9: line 4625 define FMC_BWTR2_ADDSET_1 0x00000002U 01550b: line 4626 define FMC_BWTR2_ADDSET_2 0x00000004U 01552d: line 4627 define FMC_BWTR2_ADDSET_3 0x00000008U 01554f: line 4628 define FMC_BWTR2_ADDHLD 0x000000F0U 01556f: line 4629 define FMC_BWTR2_ADDHLD_0 0x00000010U 015591: line 4630 define FMC_BWTR2_ADDHLD_1 0x00000020U 0155b3: line 4631 define FMC_BWTR2_ADDHLD_2 0x00000040U 0155d5: line 4632 define FMC_BWTR2_ADDHLD_3 0x00000080U 0155f7: line 4633 define FMC_BWTR2_DATAST 0x0000FF00U 015617: line 4634 define FMC_BWTR2_DATAST_0 0x00000100U 015639: line 4635 define FMC_BWTR2_DATAST_1 0x00000200U 01565b: line 4636 define FMC_BWTR2_DATAST_2 0x00000400U 01567d: line 4637 define FMC_BWTR2_DATAST_3 0x00000800U 01569f: line 4638 define FMC_BWTR2_DATAST_4 0x00001000U 0156c1: line 4639 define FMC_BWTR2_DATAST_5 0x00002000U 0156e3: line 4640 define FMC_BWTR2_DATAST_6 0x00004000U 015705: line 4641 define FMC_BWTR2_DATAST_7 0x00008000U 015727: line 4642 define FMC_BWTR2_BUSTURN 0x000F0000U 015748: line 4643 define FMC_BWTR2_BUSTURN_0 0x00010000U 01576b: line 4644 define FMC_BWTR2_BUSTURN_1 0x00020000U 01578e: line 4645 define FMC_BWTR2_BUSTURN_2 0x00040000U 0157b1: line 4646 define FMC_BWTR2_BUSTURN_3 0x00080000U 0157d4: line 4647 define FMC_BWTR2_ACCMOD 0x30000000U 0157f4: line 4648 define FMC_BWTR2_ACCMOD_0 0x10000000U 015816: line 4649 define FMC_BWTR2_ACCMOD_1 0x20000000U 015838: line 4652 define FMC_BWTR3_ADDSET 0x0000000FU 015858: line 4653 define FMC_BWTR3_ADDSET_0 0x00000001U 01587a: line 4654 define FMC_BWTR3_ADDSET_1 0x00000002U 01589c: line 4655 define FMC_BWTR3_ADDSET_2 0x00000004U 0158be: line 4656 define FMC_BWTR3_ADDSET_3 0x00000008U 0158e0: line 4657 define FMC_BWTR3_ADDHLD 0x000000F0U 015900: line 4658 define FMC_BWTR3_ADDHLD_0 0x00000010U 015922: line 4659 define FMC_BWTR3_ADDHLD_1 0x00000020U 015944: line 4660 define FMC_BWTR3_ADDHLD_2 0x00000040U 015966: line 4661 define FMC_BWTR3_ADDHLD_3 0x00000080U 015988: line 4662 define FMC_BWTR3_DATAST 0x0000FF00U 0159a8: line 4663 define FMC_BWTR3_DATAST_0 0x00000100U 0159ca: line 4664 define FMC_BWTR3_DATAST_1 0x00000200U 0159ec: line 4665 define FMC_BWTR3_DATAST_2 0x00000400U 015a0e: line 4666 define FMC_BWTR3_DATAST_3 0x00000800U 015a30: line 4667 define FMC_BWTR3_DATAST_4 0x00001000U 015a52: line 4668 define FMC_BWTR3_DATAST_5 0x00002000U 015a74: line 4669 define FMC_BWTR3_DATAST_6 0x00004000U 015a96: line 4670 define FMC_BWTR3_DATAST_7 0x00008000U 015ab8: line 4671 define FMC_BWTR3_BUSTURN 0x000F0000U 015ad9: line 4672 define FMC_BWTR3_BUSTURN_0 0x00010000U 015afc: line 4673 define FMC_BWTR3_BUSTURN_1 0x00020000U 015b1f: line 4674 define FMC_BWTR3_BUSTURN_2 0x00040000U 015b42: line 4675 define FMC_BWTR3_BUSTURN_3 0x00080000U 015b65: line 4676 define FMC_BWTR3_ACCMOD 0x30000000U 015b85: line 4677 define FMC_BWTR3_ACCMOD_0 0x10000000U 015ba7: line 4678 define FMC_BWTR3_ACCMOD_1 0x20000000U 015bc9: line 4681 define FMC_BWTR4_ADDSET 0x0000000FU 015be9: line 4682 define FMC_BWTR4_ADDSET_0 0x00000001U 015c0b: line 4683 define FMC_BWTR4_ADDSET_1 0x00000002U 015c2d: line 4684 define FMC_BWTR4_ADDSET_2 0x00000004U 015c4f: line 4685 define FMC_BWTR4_ADDSET_3 0x00000008U 015c71: line 4686 define FMC_BWTR4_ADDHLD 0x000000F0U 015c91: line 4687 define FMC_BWTR4_ADDHLD_0 0x00000010U 015cb3: line 4688 define FMC_BWTR4_ADDHLD_1 0x00000020U 015cd5: line 4689 define FMC_BWTR4_ADDHLD_2 0x00000040U 015cf7: line 4690 define FMC_BWTR4_ADDHLD_3 0x00000080U 015d19: line 4691 define FMC_BWTR4_DATAST 0x0000FF00U 015d39: line 4692 define FMC_BWTR4_DATAST_0 0x00000100U 015d5b: line 4693 define FMC_BWTR4_DATAST_1 0x00000200U 015d7d: line 4694 define FMC_BWTR4_DATAST_2 0x00000400U 015d9f: line 4695 define FMC_BWTR4_DATAST_3 0x00000800U 015dc1: line 4696 define FMC_BWTR4_DATAST_4 0x00001000U 015de3: line 4697 define FMC_BWTR4_DATAST_5 0x00002000U 015e05: line 4698 define FMC_BWTR4_DATAST_6 0x00004000U 015e27: line 4699 define FMC_BWTR4_DATAST_7 0x00008000U 015e49: line 4700 define FMC_BWTR4_BUSTURN 0x000F0000U 015e6a: line 4701 define FMC_BWTR4_BUSTURN_0 0x00010000U 015e8d: line 4702 define FMC_BWTR4_BUSTURN_1 0x00020000U 015eb0: line 4703 define FMC_BWTR4_BUSTURN_2 0x00040000U 015ed3: line 4704 define FMC_BWTR4_BUSTURN_3 0x00080000U 015ef6: line 4705 define FMC_BWTR4_ACCMOD 0x30000000U 015f16: line 4706 define FMC_BWTR4_ACCMOD_0 0x10000000U 015f38: line 4707 define FMC_BWTR4_ACCMOD_1 0x20000000U 015f5a: line 4710 define FMC_PCR_PWAITEN 0x00000002U 015f79: line 4711 define FMC_PCR_PBKEN 0x00000004U 015f96: line 4712 define FMC_PCR_PTYP 0x00000008U 015fb2: line 4713 define FMC_PCR_PWID 0x00000030U 015fce: line 4714 define FMC_PCR_PWID_0 0x00000010U 015fec: line 4715 define FMC_PCR_PWID_1 0x00000020U 01600a: line 4716 define FMC_PCR_ECCEN 0x00000040U 016027: line 4717 define FMC_PCR_TCLR 0x00001E00U 016043: line 4718 define FMC_PCR_TCLR_0 0x00000200U 016061: line 4719 define FMC_PCR_TCLR_1 0x00000400U 01607f: line 4720 define FMC_PCR_TCLR_2 0x00000800U 01609d: line 4721 define FMC_PCR_TCLR_3 0x00001000U 0160bb: line 4722 define FMC_PCR_TAR 0x0001E000U 0160d6: line 4723 define FMC_PCR_TAR_0 0x00002000U 0160f3: line 4724 define FMC_PCR_TAR_1 0x00004000U 016110: line 4725 define FMC_PCR_TAR_2 0x00008000U 01612d: line 4726 define FMC_PCR_TAR_3 0x00010000U 01614a: line 4727 define FMC_PCR_ECCPS 0x000E0000U 016167: line 4728 define FMC_PCR_ECCPS_0 0x00020000U 016186: line 4729 define FMC_PCR_ECCPS_1 0x00040000U 0161a5: line 4730 define FMC_PCR_ECCPS_2 0x00080000U 0161c4: line 4733 define FMC_SR_IRS 0x01U 0161d8: line 4734 define FMC_SR_ILS 0x02U 0161ec: line 4735 define FMC_SR_IFS 0x04U 016200: line 4736 define FMC_SR_IREN 0x08U 016215: line 4737 define FMC_SR_ILEN 0x10U 01622a: line 4738 define FMC_SR_IFEN 0x20U 01623f: line 4739 define FMC_SR_FEMPT 0x40U 016255: line 4742 define FMC_PMEM_MEMSET3 0x000000FFU 016275: line 4743 define FMC_PMEM_MEMSET3_0 0x00000001U 016297: line 4744 define FMC_PMEM_MEMSET3_1 0x00000002U 0162b9: line 4745 define FMC_PMEM_MEMSET3_2 0x00000004U 0162db: line 4746 define FMC_PMEM_MEMSET3_3 0x00000008U 0162fd: line 4747 define FMC_PMEM_MEMSET3_4 0x00000010U 01631f: line 4748 define FMC_PMEM_MEMSET3_5 0x00000020U 016341: line 4749 define FMC_PMEM_MEMSET3_6 0x00000040U 016363: line 4750 define FMC_PMEM_MEMSET3_7 0x00000080U 016385: line 4751 define FMC_PMEM_MEMWAIT3 0x0000FF00U 0163a6: line 4752 define FMC_PMEM_MEMWAIT3_0 0x00000100U 0163c9: line 4753 define FMC_PMEM_MEMWAIT3_1 0x00000200U 0163ec: line 4754 define FMC_PMEM_MEMWAIT3_2 0x00000400U 01640f: line 4755 define FMC_PMEM_MEMWAIT3_3 0x00000800U 016432: line 4756 define FMC_PMEM_MEMWAIT3_4 0x00001000U 016455: line 4757 define FMC_PMEM_MEMWAIT3_5 0x00002000U 016478: line 4758 define FMC_PMEM_MEMWAIT3_6 0x00004000U 01649b: line 4759 define FMC_PMEM_MEMWAIT3_7 0x00008000U 0164be: line 4760 define FMC_PMEM_MEMHOLD3 0x00FF0000U 0164df: line 4761 define FMC_PMEM_MEMHOLD3_0 0x00010000U 016502: line 4762 define FMC_PMEM_MEMHOLD3_1 0x00020000U 016525: line 4763 define FMC_PMEM_MEMHOLD3_2 0x00040000U 016548: line 4764 define FMC_PMEM_MEMHOLD3_3 0x00080000U 01656b: line 4765 define FMC_PMEM_MEMHOLD3_4 0x00100000U 01658e: line 4766 define FMC_PMEM_MEMHOLD3_5 0x00200000U 0165b1: line 4767 define FMC_PMEM_MEMHOLD3_6 0x00400000U 0165d4: line 4768 define FMC_PMEM_MEMHOLD3_7 0x00800000U 0165f7: line 4769 define FMC_PMEM_MEMHIZ3 0xFF000000U 016617: line 4770 define FMC_PMEM_MEMHIZ3_0 0x01000000U 016639: line 4771 define FMC_PMEM_MEMHIZ3_1 0x02000000U 01665b: line 4772 define FMC_PMEM_MEMHIZ3_2 0x04000000U 01667d: line 4773 define FMC_PMEM_MEMHIZ3_3 0x08000000U 01669f: line 4774 define FMC_PMEM_MEMHIZ3_4 0x10000000U 0166c1: line 4775 define FMC_PMEM_MEMHIZ3_5 0x20000000U 0166e3: line 4776 define FMC_PMEM_MEMHIZ3_6 0x40000000U 016705: line 4777 define FMC_PMEM_MEMHIZ3_7 0x80000000U 016727: line 4780 define FMC_PATT_ATTSET3 0x000000FFU 016747: line 4781 define FMC_PATT_ATTSET3_0 0x00000001U 016769: line 4782 define FMC_PATT_ATTSET3_1 0x00000002U 01678b: line 4783 define FMC_PATT_ATTSET3_2 0x00000004U 0167ad: line 4784 define FMC_PATT_ATTSET3_3 0x00000008U 0167cf: line 4785 define FMC_PATT_ATTSET3_4 0x00000010U 0167f1: line 4786 define FMC_PATT_ATTSET3_5 0x00000020U 016813: line 4787 define FMC_PATT_ATTSET3_6 0x00000040U 016835: line 4788 define FMC_PATT_ATTSET3_7 0x00000080U 016857: line 4789 define FMC_PATT_ATTWAIT3 0x0000FF00U 016878: line 4790 define FMC_PATT_ATTWAIT3_0 0x00000100U 01689b: line 4791 define FMC_PATT_ATTWAIT3_1 0x00000200U 0168be: line 4792 define FMC_PATT_ATTWAIT3_2 0x00000400U 0168e1: line 4793 define FMC_PATT_ATTWAIT3_3 0x00000800U 016904: line 4794 define FMC_PATT_ATTWAIT3_4 0x00001000U 016927: line 4795 define FMC_PATT_ATTWAIT3_5 0x00002000U 01694a: line 4796 define FMC_PATT_ATTWAIT3_6 0x00004000U 01696d: line 4797 define FMC_PATT_ATTWAIT3_7 0x00008000U 016990: line 4798 define FMC_PATT_ATTHOLD3 0x00FF0000U 0169b1: line 4799 define FMC_PATT_ATTHOLD3_0 0x00010000U 0169d4: line 4800 define FMC_PATT_ATTHOLD3_1 0x00020000U 0169f7: line 4801 define FMC_PATT_ATTHOLD3_2 0x00040000U 016a1a: line 4802 define FMC_PATT_ATTHOLD3_3 0x00080000U 016a3d: line 4803 define FMC_PATT_ATTHOLD3_4 0x00100000U 016a60: line 4804 define FMC_PATT_ATTHOLD3_5 0x00200000U 016a83: line 4805 define FMC_PATT_ATTHOLD3_6 0x00400000U 016aa6: line 4806 define FMC_PATT_ATTHOLD3_7 0x00800000U 016ac9: line 4807 define FMC_PATT_ATTHIZ3 0xFF000000U 016ae9: line 4808 define FMC_PATT_ATTHIZ3_0 0x01000000U 016b0b: line 4809 define FMC_PATT_ATTHIZ3_1 0x02000000U 016b2d: line 4810 define FMC_PATT_ATTHIZ3_2 0x04000000U 016b4f: line 4811 define FMC_PATT_ATTHIZ3_3 0x08000000U 016b71: line 4812 define FMC_PATT_ATTHIZ3_4 0x10000000U 016b93: line 4813 define FMC_PATT_ATTHIZ3_5 0x20000000U 016bb5: line 4814 define FMC_PATT_ATTHIZ3_6 0x40000000U 016bd7: line 4815 define FMC_PATT_ATTHIZ3_7 0x80000000U 016bf9: line 4818 define FMC_ECCR_ECC3 0xFFFFFFFFU 016c16: line 4821 define FMC_SDCR1_NC 0x00000003U 016c32: line 4822 define FMC_SDCR1_NC_0 0x00000001U 016c50: line 4823 define FMC_SDCR1_NC_1 0x00000002U 016c6e: line 4824 define FMC_SDCR1_NR 0x0000000CU 016c8a: line 4825 define FMC_SDCR1_NR_0 0x00000004U 016ca8: line 4826 define FMC_SDCR1_NR_1 0x00000008U 016cc6: line 4827 define FMC_SDCR1_MWID 0x00000030U 016ce4: line 4828 define FMC_SDCR1_MWID_0 0x00000010U 016d04: line 4829 define FMC_SDCR1_MWID_1 0x00000020U 016d24: line 4830 define FMC_SDCR1_NB 0x00000040U 016d40: line 4831 define FMC_SDCR1_CAS 0x00000180U 016d5d: line 4832 define FMC_SDCR1_CAS_0 0x00000080U 016d7c: line 4833 define FMC_SDCR1_CAS_1 0x00000100U 016d9b: line 4834 define FMC_SDCR1_WP 0x00000200U 016db7: line 4835 define FMC_SDCR1_SDCLK 0x00000C00U 016dd6: line 4836 define FMC_SDCR1_SDCLK_0 0x00000400U 016df7: line 4837 define FMC_SDCR1_SDCLK_1 0x00000800U 016e18: line 4838 define FMC_SDCR1_RBURST 0x00001000U 016e38: line 4839 define FMC_SDCR1_RPIPE 0x00006000U 016e57: line 4840 define FMC_SDCR1_RPIPE_0 0x00002000U 016e78: line 4841 define FMC_SDCR1_RPIPE_1 0x00004000U 016e99: line 4844 define FMC_SDCR2_NC 0x00000003U 016eb5: line 4845 define FMC_SDCR2_NC_0 0x00000001U 016ed3: line 4846 define FMC_SDCR2_NC_1 0x00000002U 016ef1: line 4847 define FMC_SDCR2_NR 0x0000000CU 016f0d: line 4848 define FMC_SDCR2_NR_0 0x00000004U 016f2b: line 4849 define FMC_SDCR2_NR_1 0x00000008U 016f49: line 4850 define FMC_SDCR2_MWID 0x00000030U 016f67: line 4851 define FMC_SDCR2_MWID_0 0x00000010U 016f87: line 4852 define FMC_SDCR2_MWID_1 0x00000020U 016fa7: line 4853 define FMC_SDCR2_NB 0x00000040U 016fc3: line 4854 define FMC_SDCR2_CAS 0x00000180U 016fe0: line 4855 define FMC_SDCR2_CAS_0 0x00000080U 016fff: line 4856 define FMC_SDCR2_CAS_1 0x00000100U 01701e: line 4857 define FMC_SDCR2_WP 0x00000200U 01703a: line 4858 define FMC_SDCR2_SDCLK 0x00000C00U 017059: line 4859 define FMC_SDCR2_SDCLK_0 0x00000400U 01707a: line 4860 define FMC_SDCR2_SDCLK_1 0x00000800U 01709b: line 4861 define FMC_SDCR2_RBURST 0x00001000U 0170bb: line 4862 define FMC_SDCR2_RPIPE 0x00006000U 0170da: line 4863 define FMC_SDCR2_RPIPE_0 0x00002000U 0170fb: line 4864 define FMC_SDCR2_RPIPE_1 0x00004000U 01711c: line 4867 define FMC_SDTR1_TMRD 0x0000000FU 01713a: line 4868 define FMC_SDTR1_TMRD_0 0x00000001U 01715a: line 4869 define FMC_SDTR1_TMRD_1 0x00000002U 01717a: line 4870 define FMC_SDTR1_TMRD_2 0x00000004U 01719a: line 4871 define FMC_SDTR1_TMRD_3 0x00000008U 0171ba: line 4872 define FMC_SDTR1_TXSR 0x000000F0U 0171d8: line 4873 define FMC_SDTR1_TXSR_0 0x00000010U 0171f8: line 4874 define FMC_SDTR1_TXSR_1 0x00000020U 017218: line 4875 define FMC_SDTR1_TXSR_2 0x00000040U 017238: line 4876 define FMC_SDTR1_TXSR_3 0x00000080U 017258: line 4877 define FMC_SDTR1_TRAS 0x00000F00U 017276: line 4878 define FMC_SDTR1_TRAS_0 0x00000100U 017296: line 4879 define FMC_SDTR1_TRAS_1 0x00000200U 0172b6: line 4880 define FMC_SDTR1_TRAS_2 0x00000400U 0172d6: line 4881 define FMC_SDTR1_TRAS_3 0x00000800U 0172f6: line 4882 define FMC_SDTR1_TRC 0x0000F000U 017313: line 4883 define FMC_SDTR1_TRC_0 0x00001000U 017332: line 4884 define FMC_SDTR1_TRC_1 0x00002000U 017351: line 4885 define FMC_SDTR1_TRC_2 0x00004000U 017370: line 4886 define FMC_SDTR1_TWR 0x000F0000U 01738d: line 4887 define FMC_SDTR1_TWR_0 0x00010000U 0173ac: line 4888 define FMC_SDTR1_TWR_1 0x00020000U 0173cb: line 4889 define FMC_SDTR1_TWR_2 0x00040000U 0173ea: line 4890 define FMC_SDTR1_TRP 0x00F00000U 017407: line 4891 define FMC_SDTR1_TRP_0 0x00100000U 017426: line 4892 define FMC_SDTR1_TRP_1 0x00200000U 017445: line 4893 define FMC_SDTR1_TRP_2 0x00400000U 017464: line 4894 define FMC_SDTR1_TRCD 0x0F000000U 017482: line 4895 define FMC_SDTR1_TRCD_0 0x01000000U 0174a2: line 4896 define FMC_SDTR1_TRCD_1 0x02000000U 0174c2: line 4897 define FMC_SDTR1_TRCD_2 0x04000000U 0174e2: line 4900 define FMC_SDTR2_TMRD 0x0000000FU 017500: line 4901 define FMC_SDTR2_TMRD_0 0x00000001U 017520: line 4902 define FMC_SDTR2_TMRD_1 0x00000002U 017540: line 4903 define FMC_SDTR2_TMRD_2 0x00000004U 017560: line 4904 define FMC_SDTR2_TMRD_3 0x00000008U 017580: line 4905 define FMC_SDTR2_TXSR 0x000000F0U 01759e: line 4906 define FMC_SDTR2_TXSR_0 0x00000010U 0175be: line 4907 define FMC_SDTR2_TXSR_1 0x00000020U 0175de: line 4908 define FMC_SDTR2_TXSR_2 0x00000040U 0175fe: line 4909 define FMC_SDTR2_TXSR_3 0x00000080U 01761e: line 4910 define FMC_SDTR2_TRAS 0x00000F00U 01763c: line 4911 define FMC_SDTR2_TRAS_0 0x00000100U 01765c: line 4912 define FMC_SDTR2_TRAS_1 0x00000200U 01767c: line 4913 define FMC_SDTR2_TRAS_2 0x00000400U 01769c: line 4914 define FMC_SDTR2_TRAS_3 0x00000800U 0176bc: line 4915 define FMC_SDTR2_TRC 0x0000F000U 0176d9: line 4916 define FMC_SDTR2_TRC_0 0x00001000U 0176f8: line 4917 define FMC_SDTR2_TRC_1 0x00002000U 017717: line 4918 define FMC_SDTR2_TRC_2 0x00004000U 017736: line 4919 define FMC_SDTR2_TWR 0x000F0000U 017753: line 4920 define FMC_SDTR2_TWR_0 0x00010000U 017772: line 4921 define FMC_SDTR2_TWR_1 0x00020000U 017791: line 4922 define FMC_SDTR2_TWR_2 0x00040000U 0177b0: line 4923 define FMC_SDTR2_TRP 0x00F00000U 0177cd: line 4924 define FMC_SDTR2_TRP_0 0x00100000U 0177ec: line 4925 define FMC_SDTR2_TRP_1 0x00200000U 01780b: line 4926 define FMC_SDTR2_TRP_2 0x00400000U 01782a: line 4927 define FMC_SDTR2_TRCD 0x0F000000U 017848: line 4928 define FMC_SDTR2_TRCD_0 0x01000000U 017868: line 4929 define FMC_SDTR2_TRCD_1 0x02000000U 017888: line 4930 define FMC_SDTR2_TRCD_2 0x04000000U 0178a8: line 4933 define FMC_SDCMR_MODE 0x00000007U 0178c6: line 4934 define FMC_SDCMR_MODE_0 0x00000001U 0178e6: line 4935 define FMC_SDCMR_MODE_1 0x00000002U 017906: line 4936 define FMC_SDCMR_MODE_2 0x00000003U 017926: line 4937 define FMC_SDCMR_CTB2 0x00000008U 017944: line 4938 define FMC_SDCMR_CTB1 0x00000010U 017962: line 4939 define FMC_SDCMR_NRFS 0x000001E0U 017980: line 4940 define FMC_SDCMR_NRFS_0 0x00000020U 0179a0: line 4941 define FMC_SDCMR_NRFS_1 0x00000040U 0179c0: line 4942 define FMC_SDCMR_NRFS_2 0x00000080U 0179e0: line 4943 define FMC_SDCMR_NRFS_3 0x00000100U 017a00: line 4944 define FMC_SDCMR_MRD 0x003FFE00U 017a1d: line 4947 define FMC_SDRTR_CRE 0x00000001U 017a3a: line 4948 define FMC_SDRTR_COUNT 0x00003FFEU 017a59: line 4949 define FMC_SDRTR_REIE 0x00004000U 017a77: line 4952 define FMC_SDSR_RE 0x00000001U 017a92: line 4953 define FMC_SDSR_MODES1 0x00000006U 017ab1: line 4954 define FMC_SDSR_MODES1_0 0x00000002U 017ad2: line 4955 define FMC_SDSR_MODES1_1 0x00000004U 017af3: line 4956 define FMC_SDSR_MODES2 0x00000018U 017b12: line 4957 define FMC_SDSR_MODES2_0 0x00000008U 017b33: line 4958 define FMC_SDSR_MODES2_1 0x00000010U 017b54: line 4959 define FMC_SDSR_BUSY 0x00000020U 017b71: line 4967 define GPIO_MODER_MODER0 0x00000003U 017b92: line 4968 define GPIO_MODER_MODER0_0 0x00000001U 017bb5: line 4969 define GPIO_MODER_MODER0_1 0x00000002U 017bd8: line 4970 define GPIO_MODER_MODER1 0x0000000CU 017bf9: line 4971 define GPIO_MODER_MODER1_0 0x00000004U 017c1c: line 4972 define GPIO_MODER_MODER1_1 0x00000008U 017c3f: line 4973 define GPIO_MODER_MODER2 0x00000030U 017c60: line 4974 define GPIO_MODER_MODER2_0 0x00000010U 017c83: line 4975 define GPIO_MODER_MODER2_1 0x00000020U 017ca6: line 4976 define GPIO_MODER_MODER3 0x000000C0U 017cc7: line 4977 define GPIO_MODER_MODER3_0 0x00000040U 017cea: line 4978 define GPIO_MODER_MODER3_1 0x00000080U 017d0d: line 4979 define GPIO_MODER_MODER4 0x00000300U 017d2e: line 4980 define GPIO_MODER_MODER4_0 0x00000100U 017d51: line 4981 define GPIO_MODER_MODER4_1 0x00000200U 017d74: line 4982 define GPIO_MODER_MODER5 0x00000C00U 017d95: line 4983 define GPIO_MODER_MODER5_0 0x00000400U 017db8: line 4984 define GPIO_MODER_MODER5_1 0x00000800U 017ddb: line 4985 define GPIO_MODER_MODER6 0x00003000U 017dfc: line 4986 define GPIO_MODER_MODER6_0 0x00001000U 017e1f: line 4987 define GPIO_MODER_MODER6_1 0x00002000U 017e42: line 4988 define GPIO_MODER_MODER7 0x0000C000U 017e63: line 4989 define GPIO_MODER_MODER7_0 0x00004000U 017e86: line 4990 define GPIO_MODER_MODER7_1 0x00008000U 017ea9: line 4991 define GPIO_MODER_MODER8 0x00030000U 017eca: line 4992 define GPIO_MODER_MODER8_0 0x00010000U 017eed: line 4993 define GPIO_MODER_MODER8_1 0x00020000U 017f10: line 4994 define GPIO_MODER_MODER9 0x000C0000U 017f31: line 4995 define GPIO_MODER_MODER9_0 0x00040000U 017f54: line 4996 define GPIO_MODER_MODER9_1 0x00080000U 017f77: line 4997 define GPIO_MODER_MODER10 0x00300000U 017f99: line 4998 define GPIO_MODER_MODER10_0 0x00100000U 017fbd: line 4999 define GPIO_MODER_MODER10_1 0x00200000U 017fe1: line 5000 define GPIO_MODER_MODER11 0x00C00000U 018003: line 5001 define GPIO_MODER_MODER11_0 0x00400000U 018027: line 5002 define GPIO_MODER_MODER11_1 0x00800000U 01804b: line 5003 define GPIO_MODER_MODER12 0x03000000U 01806d: line 5004 define GPIO_MODER_MODER12_0 0x01000000U 018091: line 5005 define GPIO_MODER_MODER12_1 0x02000000U 0180b5: line 5006 define GPIO_MODER_MODER13 0x0C000000U 0180d7: line 5007 define GPIO_MODER_MODER13_0 0x04000000U 0180fb: line 5008 define GPIO_MODER_MODER13_1 0x08000000U 01811f: line 5009 define GPIO_MODER_MODER14 0x30000000U 018141: line 5010 define GPIO_MODER_MODER14_0 0x10000000U 018165: line 5011 define GPIO_MODER_MODER14_1 0x20000000U 018189: line 5012 define GPIO_MODER_MODER15 0xC0000000U 0181ab: line 5013 define GPIO_MODER_MODER15_0 0x40000000U 0181cf: line 5014 define GPIO_MODER_MODER15_1 0x80000000U 0181f3: line 5017 define GPIO_OTYPER_OT_0 0x00000001U 018213: line 5018 define GPIO_OTYPER_OT_1 0x00000002U 018233: line 5019 define GPIO_OTYPER_OT_2 0x00000004U 018253: line 5020 define GPIO_OTYPER_OT_3 0x00000008U 018273: line 5021 define GPIO_OTYPER_OT_4 0x00000010U 018293: line 5022 define GPIO_OTYPER_OT_5 0x00000020U 0182b3: line 5023 define GPIO_OTYPER_OT_6 0x00000040U 0182d3: line 5024 define GPIO_OTYPER_OT_7 0x00000080U 0182f3: line 5025 define GPIO_OTYPER_OT_8 0x00000100U 018313: line 5026 define GPIO_OTYPER_OT_9 0x00000200U 018333: line 5027 define GPIO_OTYPER_OT_10 0x00000400U 018354: line 5028 define GPIO_OTYPER_OT_11 0x00000800U 018375: line 5029 define GPIO_OTYPER_OT_12 0x00001000U 018396: line 5030 define GPIO_OTYPER_OT_13 0x00002000U 0183b7: line 5031 define GPIO_OTYPER_OT_14 0x00004000U 0183d8: line 5032 define GPIO_OTYPER_OT_15 0x00008000U 0183f9: line 5035 define GPIO_OSPEEDER_OSPEEDR0 0x00000003U 01841f: line 5036 define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U 018447: line 5037 define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U 01846f: line 5038 define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU 018495: line 5039 define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U 0184bd: line 5040 define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U 0184e5: line 5041 define GPIO_OSPEEDER_OSPEEDR2 0x00000030U 01850b: line 5042 define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U 018533: line 5043 define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U 01855b: line 5044 define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U 018581: line 5045 define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U 0185a9: line 5046 define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U 0185d1: line 5047 define GPIO_OSPEEDER_OSPEEDR4 0x00000300U 0185f7: line 5048 define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U 01861f: line 5049 define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U 018647: line 5050 define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U 01866d: line 5051 define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U 018695: line 5052 define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U 0186bd: line 5053 define GPIO_OSPEEDER_OSPEEDR6 0x00003000U 0186e3: line 5054 define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U 01870b: line 5055 define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U 018733: line 5056 define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U 018759: line 5057 define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U 018781: line 5058 define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U 0187a9: line 5059 define GPIO_OSPEEDER_OSPEEDR8 0x00030000U 0187cf: line 5060 define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U 0187f7: line 5061 define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U 01881f: line 5062 define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U 018845: line 5063 define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U 01886d: line 5064 define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U 018895: line 5065 define GPIO_OSPEEDER_OSPEEDR10 0x00300000U 0188bc: line 5066 define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U 0188e5: line 5067 define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U 01890e: line 5068 define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U 018935: line 5069 define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U 01895e: line 5070 define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U 018987: line 5071 define GPIO_OSPEEDER_OSPEEDR12 0x03000000U 0189ae: line 5072 define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U 0189d7: line 5073 define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U 018a00: line 5074 define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U 018a27: line 5075 define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U 018a50: line 5076 define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U 018a79: line 5077 define GPIO_OSPEEDER_OSPEEDR14 0x30000000U 018aa0: line 5078 define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U 018ac9: line 5079 define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U 018af2: line 5080 define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U 018b19: line 5081 define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U 018b42: line 5082 define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U 018b6b: line 5085 define GPIO_PUPDR_PUPDR0 0x00000003U 018b8c: line 5086 define GPIO_PUPDR_PUPDR0_0 0x00000001U 018baf: line 5087 define GPIO_PUPDR_PUPDR0_1 0x00000002U 018bd2: line 5088 define GPIO_PUPDR_PUPDR1 0x0000000CU 018bf3: line 5089 define GPIO_PUPDR_PUPDR1_0 0x00000004U 018c16: line 5090 define GPIO_PUPDR_PUPDR1_1 0x00000008U 018c39: line 5091 define GPIO_PUPDR_PUPDR2 0x00000030U 018c5a: line 5092 define GPIO_PUPDR_PUPDR2_0 0x00000010U 018c7d: line 5093 define GPIO_PUPDR_PUPDR2_1 0x00000020U 018ca0: line 5094 define GPIO_PUPDR_PUPDR3 0x000000C0U 018cc1: line 5095 define GPIO_PUPDR_PUPDR3_0 0x00000040U 018ce4: line 5096 define GPIO_PUPDR_PUPDR3_1 0x00000080U 018d07: line 5097 define GPIO_PUPDR_PUPDR4 0x00000300U 018d28: line 5098 define GPIO_PUPDR_PUPDR4_0 0x00000100U 018d4b: line 5099 define GPIO_PUPDR_PUPDR4_1 0x00000200U 018d6e: line 5100 define GPIO_PUPDR_PUPDR5 0x00000C00U 018d8f: line 5101 define GPIO_PUPDR_PUPDR5_0 0x00000400U 018db2: line 5102 define GPIO_PUPDR_PUPDR5_1 0x00000800U 018dd5: line 5103 define GPIO_PUPDR_PUPDR6 0x00003000U 018df6: line 5104 define GPIO_PUPDR_PUPDR6_0 0x00001000U 018e19: line 5105 define GPIO_PUPDR_PUPDR6_1 0x00002000U 018e3c: line 5106 define GPIO_PUPDR_PUPDR7 0x0000C000U 018e5d: line 5107 define GPIO_PUPDR_PUPDR7_0 0x00004000U 018e80: line 5108 define GPIO_PUPDR_PUPDR7_1 0x00008000U 018ea3: line 5109 define GPIO_PUPDR_PUPDR8 0x00030000U 018ec4: line 5110 define GPIO_PUPDR_PUPDR8_0 0x00010000U 018ee7: line 5111 define GPIO_PUPDR_PUPDR8_1 0x00020000U 018f0a: line 5112 define GPIO_PUPDR_PUPDR9 0x000C0000U 018f2b: line 5113 define GPIO_PUPDR_PUPDR9_0 0x00040000U 018f4e: line 5114 define GPIO_PUPDR_PUPDR9_1 0x00080000U 018f71: line 5115 define GPIO_PUPDR_PUPDR10 0x00300000U 018f93: line 5116 define GPIO_PUPDR_PUPDR10_0 0x00100000U 018fb7: line 5117 define GPIO_PUPDR_PUPDR10_1 0x00200000U 018fdb: line 5118 define GPIO_PUPDR_PUPDR11 0x00C00000U 018ffd: line 5119 define GPIO_PUPDR_PUPDR11_0 0x00400000U 019021: line 5120 define GPIO_PUPDR_PUPDR11_1 0x00800000U 019045: line 5121 define GPIO_PUPDR_PUPDR12 0x03000000U 019067: line 5122 define GPIO_PUPDR_PUPDR12_0 0x01000000U 01908b: line 5123 define GPIO_PUPDR_PUPDR12_1 0x02000000U 0190af: line 5124 define GPIO_PUPDR_PUPDR13 0x0C000000U 0190d1: line 5125 define GPIO_PUPDR_PUPDR13_0 0x04000000U 0190f5: line 5126 define GPIO_PUPDR_PUPDR13_1 0x08000000U 019119: line 5127 define GPIO_PUPDR_PUPDR14 0x30000000U 01913b: line 5128 define GPIO_PUPDR_PUPDR14_0 0x10000000U 01915f: line 5129 define GPIO_PUPDR_PUPDR14_1 0x20000000U 019183: line 5130 define GPIO_PUPDR_PUPDR15 0xC0000000U 0191a5: line 5131 define GPIO_PUPDR_PUPDR15_0 0x40000000U 0191c9: line 5132 define GPIO_PUPDR_PUPDR15_1 0x80000000U 0191ed: line 5135 define GPIO_IDR_IDR_0 0x00000001U 01920b: line 5136 define GPIO_IDR_IDR_1 0x00000002U 019229: line 5137 define GPIO_IDR_IDR_2 0x00000004U 019247: line 5138 define GPIO_IDR_IDR_3 0x00000008U 019265: line 5139 define GPIO_IDR_IDR_4 0x00000010U 019283: line 5140 define GPIO_IDR_IDR_5 0x00000020U 0192a1: line 5141 define GPIO_IDR_IDR_6 0x00000040U 0192bf: line 5142 define GPIO_IDR_IDR_7 0x00000080U 0192dd: line 5143 define GPIO_IDR_IDR_8 0x00000100U 0192fb: line 5144 define GPIO_IDR_IDR_9 0x00000200U 019319: line 5145 define GPIO_IDR_IDR_10 0x00000400U 019338: line 5146 define GPIO_IDR_IDR_11 0x00000800U 019357: line 5147 define GPIO_IDR_IDR_12 0x00001000U 019376: line 5148 define GPIO_IDR_IDR_13 0x00002000U 019395: line 5149 define GPIO_IDR_IDR_14 0x00004000U 0193b4: line 5150 define GPIO_IDR_IDR_15 0x00008000U 0193d3: line 5153 define GPIO_ODR_ODR_0 0x00000001U 0193f1: line 5154 define GPIO_ODR_ODR_1 0x00000002U 01940f: line 5155 define GPIO_ODR_ODR_2 0x00000004U 01942d: line 5156 define GPIO_ODR_ODR_3 0x00000008U 01944b: line 5157 define GPIO_ODR_ODR_4 0x00000010U 019469: line 5158 define GPIO_ODR_ODR_5 0x00000020U 019487: line 5159 define GPIO_ODR_ODR_6 0x00000040U 0194a5: line 5160 define GPIO_ODR_ODR_7 0x00000080U 0194c3: line 5161 define GPIO_ODR_ODR_8 0x00000100U 0194e1: line 5162 define GPIO_ODR_ODR_9 0x00000200U 0194ff: line 5163 define GPIO_ODR_ODR_10 0x00000400U 01951e: line 5164 define GPIO_ODR_ODR_11 0x00000800U 01953d: line 5165 define GPIO_ODR_ODR_12 0x00001000U 01955c: line 5166 define GPIO_ODR_ODR_13 0x00002000U 01957b: line 5167 define GPIO_ODR_ODR_14 0x00004000U 01959a: line 5168 define GPIO_ODR_ODR_15 0x00008000U 0195b9: line 5171 define GPIO_BSRR_BS_0 0x00000001U 0195d7: line 5172 define GPIO_BSRR_BS_1 0x00000002U 0195f5: line 5173 define GPIO_BSRR_BS_2 0x00000004U 019613: line 5174 define GPIO_BSRR_BS_3 0x00000008U 019631: line 5175 define GPIO_BSRR_BS_4 0x00000010U 01964f: line 5176 define GPIO_BSRR_BS_5 0x00000020U 01966d: line 5177 define GPIO_BSRR_BS_6 0x00000040U 01968b: line 5178 define GPIO_BSRR_BS_7 0x00000080U 0196a9: line 5179 define GPIO_BSRR_BS_8 0x00000100U 0196c7: line 5180 define GPIO_BSRR_BS_9 0x00000200U 0196e5: line 5181 define GPIO_BSRR_BS_10 0x00000400U 019704: line 5182 define GPIO_BSRR_BS_11 0x00000800U 019723: line 5183 define GPIO_BSRR_BS_12 0x00001000U 019742: line 5184 define GPIO_BSRR_BS_13 0x00002000U 019761: line 5185 define GPIO_BSRR_BS_14 0x00004000U 019780: line 5186 define GPIO_BSRR_BS_15 0x00008000U 01979f: line 5187 define GPIO_BSRR_BR_0 0x00010000U 0197bd: line 5188 define GPIO_BSRR_BR_1 0x00020000U 0197db: line 5189 define GPIO_BSRR_BR_2 0x00040000U 0197f9: line 5190 define GPIO_BSRR_BR_3 0x00080000U 019817: line 5191 define GPIO_BSRR_BR_4 0x00100000U 019835: line 5192 define GPIO_BSRR_BR_5 0x00200000U 019853: line 5193 define GPIO_BSRR_BR_6 0x00400000U 019871: line 5194 define GPIO_BSRR_BR_7 0x00800000U 01988f: line 5195 define GPIO_BSRR_BR_8 0x01000000U 0198ad: line 5196 define GPIO_BSRR_BR_9 0x02000000U 0198cb: line 5197 define GPIO_BSRR_BR_10 0x04000000U 0198ea: line 5198 define GPIO_BSRR_BR_11 0x08000000U 019909: line 5199 define GPIO_BSRR_BR_12 0x10000000U 019928: line 5200 define GPIO_BSRR_BR_13 0x20000000U 019947: line 5201 define GPIO_BSRR_BR_14 0x40000000U 019966: line 5202 define GPIO_BSRR_BR_15 0x80000000U 019985: line 5205 define GPIO_LCKR_LCK0 0x00000001U 0199a3: line 5206 define GPIO_LCKR_LCK1 0x00000002U 0199c1: line 5207 define GPIO_LCKR_LCK2 0x00000004U 0199df: line 5208 define GPIO_LCKR_LCK3 0x00000008U 0199fd: line 5209 define GPIO_LCKR_LCK4 0x00000010U 019a1b: line 5210 define GPIO_LCKR_LCK5 0x00000020U 019a39: line 5211 define GPIO_LCKR_LCK6 0x00000040U 019a57: line 5212 define GPIO_LCKR_LCK7 0x00000080U 019a75: line 5213 define GPIO_LCKR_LCK8 0x00000100U 019a93: line 5214 define GPIO_LCKR_LCK9 0x00000200U 019ab1: line 5215 define GPIO_LCKR_LCK10 0x00000400U 019ad0: line 5216 define GPIO_LCKR_LCK11 0x00000800U 019aef: line 5217 define GPIO_LCKR_LCK12 0x00001000U 019b0e: line 5218 define GPIO_LCKR_LCK13 0x00002000U 019b2d: line 5219 define GPIO_LCKR_LCK14 0x00004000U 019b4c: line 5220 define GPIO_LCKR_LCK15 0x00008000U 019b6b: line 5221 define GPIO_LCKR_LCKK 0x00010000U 019b89: line 5230 define I2C_CR1_PE 0x00000001U 019ba3: line 5231 define I2C_CR1_TXIE 0x00000002U 019bbf: line 5232 define I2C_CR1_RXIE 0x00000004U 019bdb: line 5233 define I2C_CR1_ADDRIE 0x00000008U 019bf9: line 5234 define I2C_CR1_NACKIE 0x00000010U 019c17: line 5235 define I2C_CR1_STOPIE 0x00000020U 019c35: line 5236 define I2C_CR1_TCIE 0x00000040U 019c51: line 5237 define I2C_CR1_ERRIE 0x00000080U 019c6e: line 5238 define I2C_CR1_DNF 0x00000F00U 019c89: line 5239 define I2C_CR1_ANFOFF 0x00001000U 019ca7: line 5240 define I2C_CR1_TXDMAEN 0x00004000U 019cc6: line 5241 define I2C_CR1_RXDMAEN 0x00008000U 019ce5: line 5242 define I2C_CR1_SBC 0x00010000U 019d00: line 5243 define I2C_CR1_NOSTRETCH 0x00020000U 019d21: line 5244 define I2C_CR1_GCEN 0x00080000U 019d3d: line 5245 define I2C_CR1_SMBHEN 0x00100000U 019d5b: line 5246 define I2C_CR1_SMBDEN 0x00200000U 019d79: line 5247 define I2C_CR1_ALERTEN 0x00400000U 019d98: line 5248 define I2C_CR1_PECEN 0x00800000U 019db5: line 5252 define I2C_CR2_SADD 0x000003FFU 019dd1: line 5253 define I2C_CR2_RD_WRN 0x00000400U 019def: line 5254 define I2C_CR2_ADD10 0x00000800U 019e0c: line 5255 define I2C_CR2_HEAD10R 0x00001000U 019e2b: line 5256 define I2C_CR2_START 0x00002000U 019e48: line 5257 define I2C_CR2_STOP 0x00004000U 019e64: line 5258 define I2C_CR2_NACK 0x00008000U 019e80: line 5259 define I2C_CR2_NBYTES 0x00FF0000U 019e9e: line 5260 define I2C_CR2_RELOAD 0x01000000U 019ebc: line 5261 define I2C_CR2_AUTOEND 0x02000000U 019edb: line 5262 define I2C_CR2_PECBYTE 0x04000000U 019efa: line 5265 define I2C_OAR1_OA1 0x000003FFU 019f16: line 5266 define I2C_OAR1_OA1MODE 0x00000400U 019f36: line 5267 define I2C_OAR1_OA1EN 0x00008000U 019f54: line 5270 define I2C_OAR2_OA2 0x000000FEU 019f70: line 5271 define I2C_OAR2_OA2MSK 0x00000700U 019f8f: line 5272 define I2C_OAR2_OA2NOMASK 0x00000000U 019fb1: line 5273 define I2C_OAR2_OA2MASK01 0x00000100U 019fd3: line 5274 define I2C_OAR2_OA2MASK02 0x00000200U 019ff5: line 5275 define I2C_OAR2_OA2MASK03 0x00000300U 01a017: line 5276 define I2C_OAR2_OA2MASK04 0x00000400U 01a039: line 5277 define I2C_OAR2_OA2MASK05 0x00000500U 01a05b: line 5278 define I2C_OAR2_OA2MASK06 0x00000600U 01a07d: line 5279 define I2C_OAR2_OA2MASK07 0x00000700U 01a09f: line 5280 define I2C_OAR2_OA2EN 0x00008000U 01a0bd: line 5283 define I2C_TIMINGR_SCLL 0x000000FFU 01a0dd: line 5284 define I2C_TIMINGR_SCLH 0x0000FF00U 01a0fd: line 5285 define I2C_TIMINGR_SDADEL 0x000F0000U 01a11f: line 5286 define I2C_TIMINGR_SCLDEL 0x00F00000U 01a141: line 5287 define I2C_TIMINGR_PRESC 0xF0000000U 01a162: line 5290 define I2C_TIMEOUTR_TIMEOUTA 0x00000FFFU 01a187: line 5291 define I2C_TIMEOUTR_TIDLE 0x00001000U 01a1a9: line 5292 define I2C_TIMEOUTR_TIMOUTEN 0x00008000U 01a1ce: line 5293 define I2C_TIMEOUTR_TIMEOUTB 0x0FFF0000U 01a1f3: line 5294 define I2C_TIMEOUTR_TEXTEN 0x80000000U 01a216: line 5297 define I2C_ISR_TXE 0x00000001U 01a231: line 5298 define I2C_ISR_TXIS 0x00000002U 01a24d: line 5299 define I2C_ISR_RXNE 0x00000004U 01a269: line 5300 define I2C_ISR_ADDR 0x00000008U 01a285: line 5301 define I2C_ISR_NACKF 0x00000010U 01a2a2: line 5302 define I2C_ISR_STOPF 0x00000020U 01a2bf: line 5303 define I2C_ISR_TC 0x00000040U 01a2d9: line 5304 define I2C_ISR_TCR 0x00000080U 01a2f4: line 5305 define I2C_ISR_BERR 0x00000100U 01a310: line 5306 define I2C_ISR_ARLO 0x00000200U 01a32c: line 5307 define I2C_ISR_OVR 0x00000400U 01a347: line 5308 define I2C_ISR_PECERR 0x00000800U 01a365: line 5309 define I2C_ISR_TIMEOUT 0x00001000U 01a384: line 5310 define I2C_ISR_ALERT 0x00002000U 01a3a1: line 5311 define I2C_ISR_BUSY 0x00008000U 01a3bd: line 5312 define I2C_ISR_DIR 0x00010000U 01a3d8: line 5313 define I2C_ISR_ADDCODE 0x00FE0000U 01a3f7: line 5316 define I2C_ICR_ADDRCF 0x00000008U 01a415: line 5317 define I2C_ICR_NACKCF 0x00000010U 01a433: line 5318 define I2C_ICR_STOPCF 0x00000020U 01a451: line 5319 define I2C_ICR_BERRCF 0x00000100U 01a46f: line 5320 define I2C_ICR_ARLOCF 0x00000200U 01a48d: line 5321 define I2C_ICR_OVRCF 0x00000400U 01a4aa: line 5322 define I2C_ICR_PECCF 0x00000800U 01a4c7: line 5323 define I2C_ICR_TIMOUTCF 0x00001000U 01a4e7: line 5324 define I2C_ICR_ALERTCF 0x00002000U 01a506: line 5327 define I2C_PECR_PEC 0x000000FFU 01a522: line 5330 define I2C_RXDR_RXDATA 0x000000FFU 01a541: line 5333 define I2C_TXDR_TXDATA 0x000000FFU 01a560: line 5342 define IWDG_KR_KEY 0xFFFFU 01a577: line 5345 define IWDG_PR_PR 0x07U 01a58b: line 5346 define IWDG_PR_PR_0 0x01U 01a5a1: line 5347 define IWDG_PR_PR_1 0x02U 01a5b7: line 5348 define IWDG_PR_PR_2 0x04U 01a5cd: line 5351 define IWDG_RLR_RL 0x0FFFU 01a5e4: line 5354 define IWDG_SR_PVU 0x01U 01a5f9: line 5355 define IWDG_SR_RVU 0x02U 01a60e: line 5356 define IWDG_SR_WVU 0x04U 01a623: line 5359 define IWDG_WINR_WIN 0x0FFFU 01a63c: line 5369 define LTDC_SSCR_VSH 0x000007FFU 01a659: line 5370 define LTDC_SSCR_HSW 0x0FFF0000U 01a676: line 5374 define LTDC_BPCR_AVBP 0x000007FFU 01a694: line 5375 define LTDC_BPCR_AHBP 0x0FFF0000U 01a6b2: line 5379 define LTDC_AWCR_AAH 0x000007FFU 01a6cf: line 5380 define LTDC_AWCR_AAW 0x0FFF0000U 01a6ec: line 5384 define LTDC_TWCR_TOTALH 0x000007FFU 01a70c: line 5385 define LTDC_TWCR_TOTALW 0x0FFF0000U 01a72c: line 5389 define LTDC_GCR_LTDCEN 0x00000001U 01a74b: line 5390 define LTDC_GCR_DBW 0x00000070U 01a767: line 5391 define LTDC_GCR_DGW 0x00000700U 01a783: line 5392 define LTDC_GCR_DRW 0x00007000U 01a79f: line 5393 define LTDC_GCR_DEN 0x00010000U 01a7bb: line 5394 define LTDC_GCR_PCPOL 0x10000000U 01a7d9: line 5395 define LTDC_GCR_DEPOL 0x20000000U 01a7f7: line 5396 define LTDC_GCR_VSPOL 0x40000000U 01a815: line 5397 define LTDC_GCR_HSPOL 0x80000000U 01a833: line 5402 define LTDC_SRCR_IMR 0x00000001U 01a850: line 5403 define LTDC_SRCR_VBR 0x00000002U 01a86d: line 5407 define LTDC_BCCR_BCBLUE 0x000000FFU 01a88d: line 5408 define LTDC_BCCR_BCGREEN 0x0000FF00U 01a8ae: line 5409 define LTDC_BCCR_BCRED 0x00FF0000U 01a8cd: line 5413 define LTDC_IER_LIE 0x00000001U 01a8e9: line 5414 define LTDC_IER_FUIE 0x00000002U 01a906: line 5415 define LTDC_IER_TERRIE 0x00000004U 01a925: line 5416 define LTDC_IER_RRIE 0x00000008U 01a942: line 5420 define LTDC_ISR_LIF 0x00000001U 01a95e: line 5421 define LTDC_ISR_FUIF 0x00000002U 01a97b: line 5422 define LTDC_ISR_TERRIF 0x00000004U 01a99a: line 5423 define LTDC_ISR_RRIF 0x00000008U 01a9b7: line 5427 define LTDC_ICR_CLIF 0x00000001U 01a9d4: line 5428 define LTDC_ICR_CFUIF 0x00000002U 01a9f2: line 5429 define LTDC_ICR_CTERRIF 0x00000004U 01aa12: line 5430 define LTDC_ICR_CRRIF 0x00000008U 01aa30: line 5434 define LTDC_LIPCR_LIPOS 0x000007FFU 01aa50: line 5438 define LTDC_CPSR_CYPOS 0x0000FFFFU 01aa6f: line 5439 define LTDC_CPSR_CXPOS 0xFFFF0000U 01aa8e: line 5443 define LTDC_CDSR_VDES 0x00000001U 01aaac: line 5444 define LTDC_CDSR_HDES 0x00000002U 01aaca: line 5445 define LTDC_CDSR_VSYNCS 0x00000004U 01aaea: line 5446 define LTDC_CDSR_HSYNCS 0x00000008U 01ab0a: line 5450 define LTDC_LxCR_LEN 0x00000001U 01ab27: line 5451 define LTDC_LxCR_COLKEN 0x00000002U 01ab47: line 5452 define LTDC_LxCR_CLUTEN 0x00000010U 01ab67: line 5456 define LTDC_LxWHPCR_WHSTPOS 0x00000FFFU 01ab8b: line 5457 define LTDC_LxWHPCR_WHSPPOS 0xFFFF0000U 01abaf: line 5461 define LTDC_LxWVPCR_WVSTPOS 0x00000FFFU 01abd3: line 5462 define LTDC_LxWVPCR_WVSPPOS 0xFFFF0000U 01abf7: line 5466 define LTDC_LxCKCR_CKBLUE 0x000000FFU 01ac19: line 5467 define LTDC_LxCKCR_CKGREEN 0x0000FF00U 01ac3c: line 5468 define LTDC_LxCKCR_CKRED 0x00FF0000U 01ac5d: line 5472 define LTDC_LxPFCR_PF 0x00000007U 01ac7b: line 5476 define LTDC_LxCACR_CONSTA 0x000000FFU 01ac9d: line 5480 define LTDC_LxDCCR_DCBLUE 0x000000FFU 01acbf: line 5481 define LTDC_LxDCCR_DCGREEN 0x0000FF00U 01ace2: line 5482 define LTDC_LxDCCR_DCRED 0x00FF0000U 01ad03: line 5483 define LTDC_LxDCCR_DCALPHA 0xFF000000U 01ad26: line 5487 define LTDC_LxBFCR_BF2 0x00000007U 01ad45: line 5488 define LTDC_LxBFCR_BF1 0x00000700U 01ad64: line 5492 define LTDC_LxCFBAR_CFBADD 0xFFFFFFFFU 01ad87: line 5496 define LTDC_LxCFBLR_CFBLL 0x00001FFFU 01ada9: line 5497 define LTDC_LxCFBLR_CFBP 0x1FFF0000U 01adca: line 5501 define LTDC_LxCFBLNR_CFBLNBR 0x000007FFU 01adef: line 5505 define LTDC_LxCLUTWR_BLUE 0x000000FFU 01ae11: line 5506 define LTDC_LxCLUTWR_GREEN 0x0000FF00U 01ae34: line 5507 define LTDC_LxCLUTWR_RED 0x00FF0000U 01ae55: line 5508 define LTDC_LxCLUTWR_CLUTADD 0xFF000000U 01ae7a: line 5516 define PWR_CR1_LPDS 0x00000001U 01ae96: line 5517 define PWR_CR1_PDDS 0x00000002U 01aeb2: line 5518 define PWR_CR1_CSBF 0x00000008U 01aece: line 5519 define PWR_CR1_PVDE 0x00000010U 01aeea: line 5520 define PWR_CR1_PLS 0x000000E0U 01af05: line 5521 define PWR_CR1_PLS_0 0x00000020U 01af22: line 5522 define PWR_CR1_PLS_1 0x00000040U 01af3f: line 5523 define PWR_CR1_PLS_2 0x00000080U 01af5c: line 5526 define PWR_CR1_PLS_LEV0 0x00000000U 01af7c: line 5527 define PWR_CR1_PLS_LEV1 0x00000020U 01af9c: line 5528 define PWR_CR1_PLS_LEV2 0x00000040U 01afbc: line 5529 define PWR_CR1_PLS_LEV3 0x00000060U 01afdc: line 5530 define PWR_CR1_PLS_LEV4 0x00000080U 01affc: line 5531 define PWR_CR1_PLS_LEV5 0x000000A0U 01b01c: line 5532 define PWR_CR1_PLS_LEV6 0x000000C0U 01b03c: line 5533 define PWR_CR1_PLS_LEV7 0x000000E0U 01b05c: line 5534 define PWR_CR1_DBP 0x00000100U 01b077: line 5535 define PWR_CR1_FPDS 0x00000200U 01b093: line 5536 define PWR_CR1_LPUDS 0x00000400U 01b0b0: line 5537 define PWR_CR1_MRUDS 0x00000800U 01b0cd: line 5538 define PWR_CR1_ADCDC1 0x00002000U 01b0eb: line 5539 define PWR_CR1_VOS 0x0000C000U 01b106: line 5540 define PWR_CR1_VOS_0 0x00004000U 01b123: line 5541 define PWR_CR1_VOS_1 0x00008000U 01b140: line 5542 define PWR_CR1_ODEN 0x00010000U 01b15c: line 5543 define PWR_CR1_ODSWEN 0x00020000U 01b17a: line 5544 define PWR_CR1_UDEN 0x000C0000U 01b196: line 5545 define PWR_CR1_UDEN_0 0x00040000U 01b1b4: line 5546 define PWR_CR1_UDEN_1 0x00080000U 01b1d2: line 5549 define PWR_CSR1_WUIF 0x00000001U 01b1ef: line 5550 define PWR_CSR1_SBF 0x00000002U 01b20b: line 5551 define PWR_CSR1_PVDO 0x00000004U 01b228: line 5552 define PWR_CSR1_BRR 0x00000008U 01b244: line 5553 define PWR_CSR1_EIWUP 0x00000100U 01b262: line 5554 define PWR_CSR1_BRE 0x00000200U 01b27e: line 5555 define PWR_CSR1_VOSRDY 0x00004000U 01b29d: line 5556 define PWR_CSR1_ODRDY 0x00010000U 01b2bb: line 5557 define PWR_CSR1_ODSWRDY 0x00020000U 01b2db: line 5558 define PWR_CSR1_UDRDY 0x000C0000U 01b2f9: line 5562 define PWR_CR2_CWUPF1 0x00000001U 01b317: line 5563 define PWR_CR2_CWUPF2 0x00000002U 01b335: line 5564 define PWR_CR2_CWUPF3 0x00000004U 01b353: line 5565 define PWR_CR2_CWUPF4 0x00000008U 01b371: line 5566 define PWR_CR2_CWUPF5 0x00000010U 01b38f: line 5567 define PWR_CR2_CWUPF6 0x00000020U 01b3ad: line 5568 define PWR_CR2_WUPP1 0x00000100U 01b3ca: line 5569 define PWR_CR2_WUPP2 0x00000200U 01b3e7: line 5570 define PWR_CR2_WUPP3 0x00000400U 01b404: line 5571 define PWR_CR2_WUPP4 0x00000800U 01b421: line 5572 define PWR_CR2_WUPP5 0x00001000U 01b43e: line 5573 define PWR_CR2_WUPP6 0x00002000U 01b45b: line 5576 define PWR_CSR2_WUPF1 0x00000001U 01b479: line 5577 define PWR_CSR2_WUPF2 0x00000002U 01b497: line 5578 define PWR_CSR2_WUPF3 0x00000004U 01b4b5: line 5579 define PWR_CSR2_WUPF4 0x00000008U 01b4d3: line 5580 define PWR_CSR2_WUPF5 0x00000010U 01b4f1: line 5581 define PWR_CSR2_WUPF6 0x00000020U 01b50f: line 5582 define PWR_CSR2_EWUP1 0x00000100U 01b52d: line 5583 define PWR_CSR2_EWUP2 0x00000200U 01b54b: line 5584 define PWR_CSR2_EWUP3 0x00000400U 01b569: line 5585 define PWR_CSR2_EWUP4 0x00000800U 01b587: line 5586 define PWR_CSR2_EWUP5 0x00001000U 01b5a5: line 5587 define PWR_CSR2_EWUP6 0x00002000U 01b5c3: line 5595 define QUADSPI_CR_EN 0x00000001U 01b5e0: line 5596 define QUADSPI_CR_ABORT 0x00000002U 01b600: line 5597 define QUADSPI_CR_DMAEN 0x00000004U 01b620: line 5598 define QUADSPI_CR_TCEN 0x00000008U 01b63f: line 5599 define QUADSPI_CR_SSHIFT 0x00000010U 01b660: line 5600 define QUADSPI_CR_DFM 0x00000040U 01b67e: line 5601 define QUADSPI_CR_FSEL 0x00000080U 01b69d: line 5602 define QUADSPI_CR_FTHRES 0x00001F00U 01b6be: line 5603 define QUADSPI_CR_FTHRES_0 0x00000100U 01b6e1: line 5604 define QUADSPI_CR_FTHRES_1 0x00000200U 01b704: line 5605 define QUADSPI_CR_FTHRES_2 0x00000400U 01b727: line 5606 define QUADSPI_CR_FTHRES_3 0x00000800U 01b74a: line 5607 define QUADSPI_CR_FTHRES_4 0x00001000U 01b76d: line 5608 define QUADSPI_CR_TEIE 0x00010000U 01b78c: line 5609 define QUADSPI_CR_TCIE 0x00020000U 01b7ab: line 5610 define QUADSPI_CR_FTIE 0x00040000U 01b7ca: line 5611 define QUADSPI_CR_SMIE 0x00080000U 01b7e9: line 5612 define QUADSPI_CR_TOIE 0x00100000U 01b808: line 5613 define QUADSPI_CR_APMS 0x00400000U 01b827: line 5614 define QUADSPI_CR_PMM 0x00800000U 01b845: line 5615 define QUADSPI_CR_PRESCALER 0xFF000000U 01b869: line 5616 define QUADSPI_CR_PRESCALER_0 0x01000000U 01b88f: line 5617 define QUADSPI_CR_PRESCALER_1 0x02000000U 01b8b5: line 5618 define QUADSPI_CR_PRESCALER_2 0x04000000U 01b8db: line 5619 define QUADSPI_CR_PRESCALER_3 0x08000000U 01b901: line 5620 define QUADSPI_CR_PRESCALER_4 0x10000000U 01b927: line 5621 define QUADSPI_CR_PRESCALER_5 0x20000000U 01b94d: line 5622 define QUADSPI_CR_PRESCALER_6 0x40000000U 01b973: line 5623 define QUADSPI_CR_PRESCALER_7 0x80000000U 01b999: line 5626 define QUADSPI_DCR_CKMODE 0x00000001U 01b9bb: line 5627 define QUADSPI_DCR_CSHT 0x00000700U 01b9db: line 5628 define QUADSPI_DCR_CSHT_0 0x00000100U 01b9fd: line 5629 define QUADSPI_DCR_CSHT_1 0x00000200U 01ba1f: line 5630 define QUADSPI_DCR_CSHT_2 0x00000400U 01ba41: line 5631 define QUADSPI_DCR_FSIZE 0x001F0000U 01ba62: line 5632 define QUADSPI_DCR_FSIZE_0 0x00010000U 01ba85: line 5633 define QUADSPI_DCR_FSIZE_1 0x00020000U 01baa8: line 5634 define QUADSPI_DCR_FSIZE_2 0x00040000U 01bacb: line 5635 define QUADSPI_DCR_FSIZE_3 0x00080000U 01baee: line 5636 define QUADSPI_DCR_FSIZE_4 0x00100000U 01bb11: line 5639 define QUADSPI_SR_TEF 0x00000001U 01bb2f: line 5640 define QUADSPI_SR_TCF 0x00000002U 01bb4d: line 5641 define QUADSPI_SR_FTF 0x00000004U 01bb6b: line 5642 define QUADSPI_SR_SMF 0x00000008U 01bb89: line 5643 define QUADSPI_SR_TOF 0x00000010U 01bba7: line 5644 define QUADSPI_SR_BUSY 0x00000020U 01bbc6: line 5645 define QUADSPI_SR_FLEVEL 0x00001F00U 01bbe7: line 5646 define QUADSPI_SR_FLEVEL_0 0x00000100U 01bc0a: line 5647 define QUADSPI_SR_FLEVEL_1 0x00000200U 01bc2d: line 5648 define QUADSPI_SR_FLEVEL_2 0x00000400U 01bc50: line 5649 define QUADSPI_SR_FLEVEL_3 0x00000800U 01bc73: line 5650 define QUADSPI_SR_FLEVEL_4 0x00001000U 01bc96: line 5653 define QUADSPI_FCR_CTEF 0x00000001U 01bcb6: line 5654 define QUADSPI_FCR_CTCF 0x00000002U 01bcd6: line 5655 define QUADSPI_FCR_CSMF 0x00000008U 01bcf6: line 5656 define QUADSPI_FCR_CTOF 0x00000010U 01bd16: line 5659 define QUADSPI_DLR_DL 0xFFFFFFFFU 01bd34: line 5662 define QUADSPI_CCR_INSTRUCTION 0x000000FFU 01bd5b: line 5663 define QUADSPI_CCR_INSTRUCTION_0 0x00000001U 01bd84: line 5664 define QUADSPI_CCR_INSTRUCTION_1 0x00000002U 01bdad: line 5665 define QUADSPI_CCR_INSTRUCTION_2 0x00000004U 01bdd6: line 5666 define QUADSPI_CCR_INSTRUCTION_3 0x00000008U 01bdff: line 5667 define QUADSPI_CCR_INSTRUCTION_4 0x00000010U 01be28: line 5668 define QUADSPI_CCR_INSTRUCTION_5 0x00000020U 01be51: line 5669 define QUADSPI_CCR_INSTRUCTION_6 0x00000040U 01be7a: line 5670 define QUADSPI_CCR_INSTRUCTION_7 0x00000080U 01bea3: line 5671 define QUADSPI_CCR_IMODE 0x00000300U 01bec4: line 5672 define QUADSPI_CCR_IMODE_0 0x00000100U 01bee7: line 5673 define QUADSPI_CCR_IMODE_1 0x00000200U 01bf0a: line 5674 define QUADSPI_CCR_ADMODE 0x00000C00U 01bf2c: line 5675 define QUADSPI_CCR_ADMODE_0 0x00000400U 01bf50: line 5676 define QUADSPI_CCR_ADMODE_1 0x00000800U 01bf74: line 5677 define QUADSPI_CCR_ADSIZE 0x00003000U 01bf96: line 5678 define QUADSPI_CCR_ADSIZE_0 0x00001000U 01bfba: line 5679 define QUADSPI_CCR_ADSIZE_1 0x00002000U 01bfde: line 5680 define QUADSPI_CCR_ABMODE 0x0000C000U 01c000: line 5681 define QUADSPI_CCR_ABMODE_0 0x00004000U 01c024: line 5682 define QUADSPI_CCR_ABMODE_1 0x00008000U 01c048: line 5683 define QUADSPI_CCR_ABSIZE 0x00030000U 01c06a: line 5684 define QUADSPI_CCR_ABSIZE_0 0x00010000U 01c08e: line 5685 define QUADSPI_CCR_ABSIZE_1 0x00020000U 01c0b2: line 5686 define QUADSPI_CCR_DCYC 0x007C0000U 01c0d2: line 5687 define QUADSPI_CCR_DCYC_0 0x00040000U 01c0f4: line 5688 define QUADSPI_CCR_DCYC_1 0x00080000U 01c116: line 5689 define QUADSPI_CCR_DCYC_2 0x00100000U 01c138: line 5690 define QUADSPI_CCR_DCYC_3 0x00200000U 01c15a: line 5691 define QUADSPI_CCR_DCYC_4 0x00400000U 01c17c: line 5692 define QUADSPI_CCR_DMODE 0x03000000U 01c19d: line 5693 define QUADSPI_CCR_DMODE_0 0x01000000U 01c1c0: line 5694 define QUADSPI_CCR_DMODE_1 0x02000000U 01c1e3: line 5695 define QUADSPI_CCR_FMODE 0x0C000000U 01c204: line 5696 define QUADSPI_CCR_FMODE_0 0x04000000U 01c227: line 5697 define QUADSPI_CCR_FMODE_1 0x08000000U 01c24a: line 5698 define QUADSPI_CCR_SIOO 0x10000000U 01c26a: line 5699 define QUADSPI_CCR_DHHC 0x40000000U 01c28a: line 5700 define QUADSPI_CCR_DDRM 0x80000000U 01c2aa: line 5702 define QUADSPI_AR_ADDRESS 0xFFFFFFFFU 01c2cc: line 5705 define QUADSPI_ABR_ALTERNATE 0xFFFFFFFFU 01c2f1: line 5708 define QUADSPI_DR_DATA 0xFFFFFFFFU 01c310: line 5711 define QUADSPI_PSMKR_MASK 0xFFFFFFFFU 01c332: line 5714 define QUADSPI_PSMAR_MATCH 0xFFFFFFFFU 01c355: line 5717 define QUADSPI_PIR_INTERVAL 0x0000FFFFU 01c379: line 5720 define QUADSPI_LPTR_TIMEOUT 0x0000FFFFU 01c39d: line 5728 define RCC_CR_HSION 0x00000001U 01c3b9: line 5729 define RCC_CR_HSIRDY 0x00000002U 01c3d6: line 5730 define RCC_CR_HSITRIM 0x000000F8U 01c3f4: line 5731 define RCC_CR_HSITRIM_0 0x00000008U 01c414: line 5732 define RCC_CR_HSITRIM_1 0x00000010U 01c434: line 5733 define RCC_CR_HSITRIM_2 0x00000020U 01c454: line 5734 define RCC_CR_HSITRIM_3 0x00000040U 01c474: line 5735 define RCC_CR_HSITRIM_4 0x00000080U 01c494: line 5736 define RCC_CR_HSICAL 0x0000FF00U 01c4b1: line 5737 define RCC_CR_HSICAL_0 0x00000100U 01c4d0: line 5738 define RCC_CR_HSICAL_1 0x00000200U 01c4ef: line 5739 define RCC_CR_HSICAL_2 0x00000400U 01c50e: line 5740 define RCC_CR_HSICAL_3 0x00000800U 01c52d: line 5741 define RCC_CR_HSICAL_4 0x00001000U 01c54c: line 5742 define RCC_CR_HSICAL_5 0x00002000U 01c56b: line 5743 define RCC_CR_HSICAL_6 0x00004000U 01c58a: line 5744 define RCC_CR_HSICAL_7 0x00008000U 01c5a9: line 5745 define RCC_CR_HSEON 0x00010000U 01c5c5: line 5746 define RCC_CR_HSERDY 0x00020000U 01c5e2: line 5747 define RCC_CR_HSEBYP 0x00040000U 01c5ff: line 5748 define RCC_CR_CSSON 0x00080000U 01c61b: line 5749 define RCC_CR_PLLON 0x01000000U 01c637: line 5750 define RCC_CR_PLLRDY 0x02000000U 01c654: line 5751 define RCC_CR_PLLI2SON 0x04000000U 01c673: line 5752 define RCC_CR_PLLI2SRDY 0x08000000U 01c693: line 5753 define RCC_CR_PLLSAION 0x10000000U 01c6b2: line 5754 define RCC_CR_PLLSAIRDY 0x20000000U 01c6d2: line 5757 define RCC_PLLCFGR_PLLM 0x0000003FU 01c6f2: line 5758 define RCC_PLLCFGR_PLLM_0 0x00000001U 01c714: line 5759 define RCC_PLLCFGR_PLLM_1 0x00000002U 01c736: line 5760 define RCC_PLLCFGR_PLLM_2 0x00000004U 01c758: line 5761 define RCC_PLLCFGR_PLLM_3 0x00000008U 01c77a: line 5762 define RCC_PLLCFGR_PLLM_4 0x00000010U 01c79c: line 5763 define RCC_PLLCFGR_PLLM_5 0x00000020U 01c7be: line 5764 define RCC_PLLCFGR_PLLN 0x00007FC0U 01c7de: line 5765 define RCC_PLLCFGR_PLLN_0 0x00000040U 01c800: line 5766 define RCC_PLLCFGR_PLLN_1 0x00000080U 01c822: line 5767 define RCC_PLLCFGR_PLLN_2 0x00000100U 01c844: line 5768 define RCC_PLLCFGR_PLLN_3 0x00000200U 01c866: line 5769 define RCC_PLLCFGR_PLLN_4 0x00000400U 01c888: line 5770 define RCC_PLLCFGR_PLLN_5 0x00000800U 01c8aa: line 5771 define RCC_PLLCFGR_PLLN_6 0x00001000U 01c8cc: line 5772 define RCC_PLLCFGR_PLLN_7 0x00002000U 01c8ee: line 5773 define RCC_PLLCFGR_PLLN_8 0x00004000U 01c910: line 5774 define RCC_PLLCFGR_PLLP 0x00030000U 01c930: line 5775 define RCC_PLLCFGR_PLLP_0 0x00010000U 01c952: line 5776 define RCC_PLLCFGR_PLLP_1 0x00020000U 01c974: line 5777 define RCC_PLLCFGR_PLLSRC 0x00400000U 01c996: line 5778 define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U 01c9bc: line 5779 define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U 01c9e2: line 5780 define RCC_PLLCFGR_PLLQ 0x0F000000U 01ca02: line 5781 define RCC_PLLCFGR_PLLQ_0 0x01000000U 01ca24: line 5782 define RCC_PLLCFGR_PLLQ_1 0x02000000U 01ca46: line 5783 define RCC_PLLCFGR_PLLQ_2 0x04000000U 01ca68: line 5784 define RCC_PLLCFGR_PLLQ_3 0x08000000U 01ca8a: line 5786 define RCC_PLLCFGR_PLLR 0x70000000U 01caaa: line 5787 define RCC_PLLCFGR_PLLR_0 0x10000000U 01cacc: line 5788 define RCC_PLLCFGR_PLLR_1 0x20000000U 01caee: line 5789 define RCC_PLLCFGR_PLLR_2 0x40000000U 01cb10: line 5793 define RCC_CFGR_SW 0x00000003U 01cb2b: line 5794 define RCC_CFGR_SW_0 0x00000001U 01cb48: line 5795 define RCC_CFGR_SW_1 0x00000002U 01cb65: line 5796 define RCC_CFGR_SW_HSI 0x00000000U 01cb84: line 5797 define RCC_CFGR_SW_HSE 0x00000001U 01cba3: line 5798 define RCC_CFGR_SW_PLL 0x00000002U 01cbc2: line 5801 define RCC_CFGR_SWS 0x0000000CU 01cbde: line 5802 define RCC_CFGR_SWS_0 0x00000004U 01cbfc: line 5803 define RCC_CFGR_SWS_1 0x00000008U 01cc1a: line 5804 define RCC_CFGR_SWS_HSI 0x00000000U 01cc3a: line 5805 define RCC_CFGR_SWS_HSE 0x00000004U 01cc5a: line 5806 define RCC_CFGR_SWS_PLL 0x00000008U 01cc7a: line 5809 define RCC_CFGR_HPRE 0x000000F0U 01cc97: line 5810 define RCC_CFGR_HPRE_0 0x00000010U 01ccb6: line 5811 define RCC_CFGR_HPRE_1 0x00000020U 01ccd5: line 5812 define RCC_CFGR_HPRE_2 0x00000040U 01ccf4: line 5813 define RCC_CFGR_HPRE_3 0x00000080U 01cd13: line 5815 define RCC_CFGR_HPRE_DIV1 0x00000000U 01cd35: line 5816 define RCC_CFGR_HPRE_DIV2 0x00000080U 01cd57: line 5817 define RCC_CFGR_HPRE_DIV4 0x00000090U 01cd79: line 5818 define RCC_CFGR_HPRE_DIV8 0x000000A0U 01cd9b: line 5819 define RCC_CFGR_HPRE_DIV16 0x000000B0U 01cdbe: line 5820 define RCC_CFGR_HPRE_DIV64 0x000000C0U 01cde1: line 5821 define RCC_CFGR_HPRE_DIV128 0x000000D0U 01ce05: line 5822 define RCC_CFGR_HPRE_DIV256 0x000000E0U 01ce29: line 5823 define RCC_CFGR_HPRE_DIV512 0x000000F0U 01ce4d: line 5826 define RCC_CFGR_PPRE1 0x00001C00U 01ce6b: line 5827 define RCC_CFGR_PPRE1_0 0x00000400U 01ce8b: line 5828 define RCC_CFGR_PPRE1_1 0x00000800U 01ceab: line 5829 define RCC_CFGR_PPRE1_2 0x00001000U 01cecb: line 5831 define RCC_CFGR_PPRE1_DIV1 0x00000000U 01ceee: line 5832 define RCC_CFGR_PPRE1_DIV2 0x00001000U 01cf11: line 5833 define RCC_CFGR_PPRE1_DIV4 0x00001400U 01cf34: line 5834 define RCC_CFGR_PPRE1_DIV8 0x00001800U 01cf57: line 5835 define RCC_CFGR_PPRE1_DIV16 0x00001C00U 01cf7b: line 5838 define RCC_CFGR_PPRE2 0x0000E000U 01cf99: line 5839 define RCC_CFGR_PPRE2_0 0x00002000U 01cfb9: line 5840 define RCC_CFGR_PPRE2_1 0x00004000U 01cfd9: line 5841 define RCC_CFGR_PPRE2_2 0x00008000U 01cff9: line 5843 define RCC_CFGR_PPRE2_DIV1 0x00000000U 01d01c: line 5844 define RCC_CFGR_PPRE2_DIV2 0x00008000U 01d03f: line 5845 define RCC_CFGR_PPRE2_DIV4 0x0000A000U 01d062: line 5846 define RCC_CFGR_PPRE2_DIV8 0x0000C000U 01d085: line 5847 define RCC_CFGR_PPRE2_DIV16 0x0000E000U 01d0a9: line 5850 define RCC_CFGR_RTCPRE 0x001F0000U 01d0c8: line 5851 define RCC_CFGR_RTCPRE_0 0x00010000U 01d0e9: line 5852 define RCC_CFGR_RTCPRE_1 0x00020000U 01d10a: line 5853 define RCC_CFGR_RTCPRE_2 0x00040000U 01d12b: line 5854 define RCC_CFGR_RTCPRE_3 0x00080000U 01d14c: line 5855 define RCC_CFGR_RTCPRE_4 0x00100000U 01d16d: line 5858 define RCC_CFGR_MCO1 0x00600000U 01d18a: line 5859 define RCC_CFGR_MCO1_0 0x00200000U 01d1a9: line 5860 define RCC_CFGR_MCO1_1 0x00400000U 01d1c8: line 5862 define RCC_CFGR_I2SSRC 0x00800000U 01d1e7: line 5864 define RCC_CFGR_MCO1PRE 0x07000000U 01d207: line 5865 define RCC_CFGR_MCO1PRE_0 0x01000000U 01d229: line 5866 define RCC_CFGR_MCO1PRE_1 0x02000000U 01d24b: line 5867 define RCC_CFGR_MCO1PRE_2 0x04000000U 01d26d: line 5869 define RCC_CFGR_MCO2PRE 0x38000000U 01d28d: line 5870 define RCC_CFGR_MCO2PRE_0 0x08000000U 01d2af: line 5871 define RCC_CFGR_MCO2PRE_1 0x10000000U 01d2d1: line 5872 define RCC_CFGR_MCO2PRE_2 0x20000000U 01d2f3: line 5874 define RCC_CFGR_MCO2 0xC0000000U 01d310: line 5875 define RCC_CFGR_MCO2_0 0x40000000U 01d32f: line 5876 define RCC_CFGR_MCO2_1 0x80000000U 01d34e: line 5879 define RCC_CIR_LSIRDYF 0x00000001U 01d36d: line 5880 define RCC_CIR_LSERDYF 0x00000002U 01d38c: line 5881 define RCC_CIR_HSIRDYF 0x00000004U 01d3ab: line 5882 define RCC_CIR_HSERDYF 0x00000008U 01d3ca: line 5883 define RCC_CIR_PLLRDYF 0x00000010U 01d3e9: line 5884 define RCC_CIR_PLLI2SRDYF 0x00000020U 01d40b: line 5885 define RCC_CIR_PLLSAIRDYF 0x00000040U 01d42d: line 5886 define RCC_CIR_CSSF 0x00000080U 01d449: line 5887 define RCC_CIR_LSIRDYIE 0x00000100U 01d469: line 5888 define RCC_CIR_LSERDYIE 0x00000200U 01d489: line 5889 define RCC_CIR_HSIRDYIE 0x00000400U 01d4a9: line 5890 define RCC_CIR_HSERDYIE 0x00000800U 01d4c9: line 5891 define RCC_CIR_PLLRDYIE 0x00001000U 01d4e9: line 5892 define RCC_CIR_PLLI2SRDYIE 0x00002000U 01d50c: line 5893 define RCC_CIR_PLLSAIRDYIE 0x00004000U 01d52f: line 5894 define RCC_CIR_LSIRDYC 0x00010000U 01d54e: line 5895 define RCC_CIR_LSERDYC 0x00020000U 01d56d: line 5896 define RCC_CIR_HSIRDYC 0x00040000U 01d58c: line 5897 define RCC_CIR_HSERDYC 0x00080000U 01d5ab: line 5898 define RCC_CIR_PLLRDYC 0x00100000U 01d5ca: line 5899 define RCC_CIR_PLLI2SRDYC 0x00200000U 01d5ec: line 5900 define RCC_CIR_PLLSAIRDYC 0x00400000U 01d60e: line 5901 define RCC_CIR_CSSC 0x00800000U 01d62a: line 5904 define RCC_AHB1RSTR_GPIOARST 0x00000001U 01d64f: line 5905 define RCC_AHB1RSTR_GPIOBRST 0x00000002U 01d674: line 5906 define RCC_AHB1RSTR_GPIOCRST 0x00000004U 01d699: line 5907 define RCC_AHB1RSTR_GPIODRST 0x00000008U 01d6be: line 5908 define RCC_AHB1RSTR_GPIOERST 0x00000010U 01d6e3: line 5909 define RCC_AHB1RSTR_GPIOFRST 0x00000020U 01d708: line 5910 define RCC_AHB1RSTR_GPIOGRST 0x00000040U 01d72d: line 5911 define RCC_AHB1RSTR_GPIOHRST 0x00000080U 01d752: line 5912 define RCC_AHB1RSTR_GPIOIRST 0x00000100U 01d777: line 5913 define RCC_AHB1RSTR_GPIOJRST 0x00000200U 01d79c: line 5914 define RCC_AHB1RSTR_GPIOKRST 0x00000400U 01d7c1: line 5915 define RCC_AHB1RSTR_CRCRST 0x00001000U 01d7e4: line 5916 define RCC_AHB1RSTR_DMA1RST 0x00200000U 01d808: line 5917 define RCC_AHB1RSTR_DMA2RST 0x00400000U 01d82c: line 5918 define RCC_AHB1RSTR_DMA2DRST 0x00800000U 01d851: line 5919 define RCC_AHB1RSTR_ETHMACRST 0x02000000U 01d877: line 5920 define RCC_AHB1RSTR_OTGHRST 0x20000000U 01d89b: line 5923 define RCC_AHB2RSTR_DCMIRST 0x00000001U 01d8bf: line 5924 define RCC_AHB2RSTR_JPEGRST 0x00000002U 01d8e3: line 5925 define RCC_AHB2RSTR_RNGRST 0x00000040U 01d906: line 5926 define RCC_AHB2RSTR_OTGFSRST 0x00000080U 01d92b: line 5930 define RCC_AHB3RSTR_FMCRST 0x00000001U 01d94e: line 5931 define RCC_AHB3RSTR_QSPIRST 0x00000002U 01d972: line 5934 define RCC_APB1RSTR_TIM2RST 0x00000001U 01d996: line 5935 define RCC_APB1RSTR_TIM3RST 0x00000002U 01d9ba: line 5936 define RCC_APB1RSTR_TIM4RST 0x00000004U 01d9de: line 5937 define RCC_APB1RSTR_TIM5RST 0x00000008U 01da02: line 5938 define RCC_APB1RSTR_TIM6RST 0x00000010U 01da26: line 5939 define RCC_APB1RSTR_TIM7RST 0x00000020U 01da4a: line 5940 define RCC_APB1RSTR_TIM12RST 0x00000040U 01da6f: line 5941 define RCC_APB1RSTR_TIM13RST 0x00000080U 01da94: line 5942 define RCC_APB1RSTR_TIM14RST 0x00000100U 01dab9: line 5943 define RCC_APB1RSTR_LPTIM1RST 0x00000200U 01dadf: line 5944 define RCC_APB1RSTR_WWDGRST 0x00000800U 01db03: line 5945 define RCC_APB1RSTR_CAN3RST 0x00002000U 01db27: line 5946 define RCC_APB1RSTR_SPI2RST 0x00004000U 01db4b: line 5947 define RCC_APB1RSTR_SPI3RST 0x00008000U 01db6f: line 5948 define RCC_APB1RSTR_SPDIFRXRST 0x00010000U 01db96: line 5949 define RCC_APB1RSTR_USART2RST 0x00020000U 01dbbc: line 5950 define RCC_APB1RSTR_USART3RST 0x00040000U 01dbe2: line 5951 define RCC_APB1RSTR_UART4RST 0x00080000U 01dc07: line 5952 define RCC_APB1RSTR_UART5RST 0x00100000U 01dc2c: line 5953 define RCC_APB1RSTR_I2C1RST 0x00200000U 01dc50: line 5954 define RCC_APB1RSTR_I2C2RST 0x00400000U 01dc74: line 5955 define RCC_APB1RSTR_I2C3RST 0x00800000U 01dc98: line 5956 define RCC_APB1RSTR_I2C4RST 0x01000000U 01dcbc: line 5957 define RCC_APB1RSTR_CAN1RST 0x02000000U 01dce0: line 5958 define RCC_APB1RSTR_CAN2RST 0x04000000U 01dd04: line 5959 define RCC_APB1RSTR_CECRST 0x08000000U 01dd27: line 5960 define RCC_APB1RSTR_PWRRST 0x10000000U 01dd4a: line 5961 define RCC_APB1RSTR_DACRST 0x20000000U 01dd6d: line 5962 define RCC_APB1RSTR_UART7RST 0x40000000U 01dd92: line 5963 define RCC_APB1RSTR_UART8RST 0x80000000U 01ddb7: line 5966 define RCC_APB2RSTR_TIM1RST 0x00000001U 01dddb: line 5967 define RCC_APB2RSTR_TIM8RST 0x00000002U 01ddff: line 5968 define RCC_APB2RSTR_USART1RST 0x00000010U 01de25: line 5969 define RCC_APB2RSTR_USART6RST 0x00000020U 01de4b: line 5970 define RCC_APB2RSTR_SDMMC2RST 0x00000080U 01de71: line 5971 define RCC_APB2RSTR_ADCRST 0x00000100U 01de94: line 5972 define RCC_APB2RSTR_SDMMC1RST 0x00000800U 01deba: line 5973 define RCC_APB2RSTR_SPI1RST 0x00001000U 01dede: line 5974 define RCC_APB2RSTR_SPI4RST 0x00002000U 01df02: line 5975 define RCC_APB2RSTR_SYSCFGRST 0x00004000U 01df28: line 5976 define RCC_APB2RSTR_TIM9RST 0x00010000U 01df4c: line 5977 define RCC_APB2RSTR_TIM10RST 0x00020000U 01df71: line 5978 define RCC_APB2RSTR_TIM11RST 0x00040000U 01df96: line 5979 define RCC_APB2RSTR_SPI5RST 0x00100000U 01dfba: line 5980 define RCC_APB2RSTR_SPI6RST 0x00200000U 01dfde: line 5981 define RCC_APB2RSTR_SAI1RST 0x00400000U 01e002: line 5982 define RCC_APB2RSTR_SAI2RST 0x00800000U 01e026: line 5983 define RCC_APB2RSTR_LTDCRST 0x04000000U 01e04a: line 5984 define RCC_APB2RSTR_DFSDM1RST 0x20000000U 01e070: line 5985 define RCC_APB2RSTR_MDIORST 0x40000000U 01e094: line 5988 define RCC_AHB1ENR_GPIOAEN 0x00000001U 01e0b7: line 5989 define RCC_AHB1ENR_GPIOBEN 0x00000002U 01e0da: line 5990 define RCC_AHB1ENR_GPIOCEN 0x00000004U 01e0fd: line 5991 define RCC_AHB1ENR_GPIODEN 0x00000008U 01e120: line 5992 define RCC_AHB1ENR_GPIOEEN 0x00000010U 01e143: line 5993 define RCC_AHB1ENR_GPIOFEN 0x00000020U 01e166: line 5994 define RCC_AHB1ENR_GPIOGEN 0x00000040U 01e189: line 5995 define RCC_AHB1ENR_GPIOHEN 0x00000080U 01e1ac: line 5996 define RCC_AHB1ENR_GPIOIEN 0x00000100U 01e1cf: line 5997 define RCC_AHB1ENR_GPIOJEN 0x00000200U 01e1f2: line 5998 define RCC_AHB1ENR_GPIOKEN 0x00000400U 01e215: line 5999 define RCC_AHB1ENR_CRCEN 0x00001000U 01e236: line 6000 define RCC_AHB1ENR_BKPSRAMEN 0x00040000U 01e25b: line 6001 define RCC_AHB1ENR_DTCMRAMEN 0x00100000U 01e280: line 6002 define RCC_AHB1ENR_DMA1EN 0x00200000U 01e2a2: line 6003 define RCC_AHB1ENR_DMA2EN 0x00400000U 01e2c4: line 6004 define RCC_AHB1ENR_DMA2DEN 0x00800000U 01e2e7: line 6005 define RCC_AHB1ENR_ETHMACEN 0x02000000U 01e30b: line 6006 define RCC_AHB1ENR_ETHMACTXEN 0x04000000U 01e331: line 6007 define RCC_AHB1ENR_ETHMACRXEN 0x08000000U 01e357: line 6008 define RCC_AHB1ENR_ETHMACPTPEN 0x10000000U 01e37e: line 6009 define RCC_AHB1ENR_OTGHSEN 0x20000000U 01e3a1: line 6010 define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U 01e3c8: line 6013 define RCC_AHB2ENR_DCMIEN 0x00000001U 01e3ea: line 6014 define RCC_AHB2ENR_JPEGEN 0x00000002U 01e40c: line 6015 define RCC_AHB2ENR_RNGEN 0x00000040U 01e42d: line 6016 define RCC_AHB2ENR_OTGFSEN 0x00000080U 01e450: line 6019 define RCC_AHB3ENR_FMCEN 0x00000001U 01e471: line 6020 define RCC_AHB3ENR_QSPIEN 0x00000002U 01e493: line 6023 define RCC_APB1ENR_TIM2EN 0x00000001U 01e4b5: line 6024 define RCC_APB1ENR_TIM3EN 0x00000002U 01e4d7: line 6025 define RCC_APB1ENR_TIM4EN 0x00000004U 01e4f9: line 6026 define RCC_APB1ENR_TIM5EN 0x00000008U 01e51b: line 6027 define RCC_APB1ENR_TIM6EN 0x00000010U 01e53d: line 6028 define RCC_APB1ENR_TIM7EN 0x00000020U 01e55f: line 6029 define RCC_APB1ENR_TIM12EN 0x00000040U 01e582: line 6030 define RCC_APB1ENR_TIM13EN 0x00000080U 01e5a5: line 6031 define RCC_APB1ENR_TIM14EN 0x00000100U 01e5c8: line 6032 define RCC_APB1ENR_LPTIM1EN 0x00000200U 01e5ec: line 6033 define RCC_APB1ENR_RTCEN 0x00000400U 01e60d: line 6034 define RCC_APB1ENR_WWDGEN 0x00000800U 01e62f: line 6035 define RCC_APB1ENR_CAN3EN 0x00002000U 01e651: line 6036 define RCC_APB1ENR_SPI2EN 0x00004000U 01e673: line 6037 define RCC_APB1ENR_SPI3EN 0x00008000U 01e695: line 6038 define RCC_APB1ENR_SPDIFRXEN 0x00010000U 01e6ba: line 6039 define RCC_APB1ENR_USART2EN 0x00020000U 01e6de: line 6040 define RCC_APB1ENR_USART3EN 0x00040000U 01e702: line 6041 define RCC_APB1ENR_UART4EN 0x00080000U 01e725: line 6042 define RCC_APB1ENR_UART5EN 0x00100000U 01e748: line 6043 define RCC_APB1ENR_I2C1EN 0x00200000U 01e76a: line 6044 define RCC_APB1ENR_I2C2EN 0x00400000U 01e78c: line 6045 define RCC_APB1ENR_I2C3EN 0x00800000U 01e7ae: line 6046 define RCC_APB1ENR_I2C4EN 0x01000000U 01e7d0: line 6047 define RCC_APB1ENR_CAN1EN 0x02000000U 01e7f2: line 6048 define RCC_APB1ENR_CAN2EN 0x04000000U 01e814: line 6049 define RCC_APB1ENR_CECEN 0x08000000U 01e835: line 6050 define RCC_APB1ENR_PWREN 0x10000000U 01e856: line 6051 define RCC_APB1ENR_DACEN 0x20000000U 01e877: line 6052 define RCC_APB1ENR_UART7EN 0x40000000U 01e89a: line 6053 define RCC_APB1ENR_UART8EN 0x80000000U 01e8bd: line 6056 define RCC_APB2ENR_TIM1EN 0x00000001U 01e8df: line 6057 define RCC_APB2ENR_TIM8EN 0x00000002U 01e901: line 6058 define RCC_APB2ENR_USART1EN 0x00000010U 01e925: line 6059 define RCC_APB2ENR_USART6EN 0x00000020U 01e949: line 6060 define RCC_APB2ENR_SDMMC2EN 0x00000080U 01e96d: line 6061 define RCC_APB2ENR_ADC1EN 0x00000100U 01e98f: line 6062 define RCC_APB2ENR_ADC2EN 0x00000200U 01e9b1: line 6063 define RCC_APB2ENR_ADC3EN 0x00000400U 01e9d3: line 6064 define RCC_APB2ENR_SDMMC1EN 0x00000800U 01e9f7: line 6065 define RCC_APB2ENR_SPI1EN 0x00001000U 01ea19: line 6066 define RCC_APB2ENR_SPI4EN 0x00002000U 01ea3b: line 6067 define RCC_APB2ENR_SYSCFGEN 0x00004000U 01ea5f: line 6068 define RCC_APB2ENR_TIM9EN 0x00010000U 01ea81: line 6069 define RCC_APB2ENR_TIM10EN 0x00020000U 01eaa4: line 6070 define RCC_APB2ENR_TIM11EN 0x00040000U 01eac7: line 6071 define RCC_APB2ENR_SPI5EN 0x00100000U 01eae9: line 6072 define RCC_APB2ENR_SPI6EN 0x00200000U 01eb0b: line 6073 define RCC_APB2ENR_SAI1EN 0x00400000U 01eb2d: line 6074 define RCC_APB2ENR_SAI2EN 0x00800000U 01eb4f: line 6075 define RCC_APB2ENR_LTDCEN 0x04000000U 01eb71: line 6076 define RCC_APB2ENR_DFSDM1EN 0x20000000U 01eb95: line 6077 define RCC_APB2ENR_MDIOEN 0x40000000U 01ebb7: line 6080 define RCC_AHB1LPENR_GPIOALPEN 0x00000001U 01ebde: line 6081 define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U 01ec05: line 6082 define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U 01ec2c: line 6083 define RCC_AHB1LPENR_GPIODLPEN 0x00000008U 01ec53: line 6084 define RCC_AHB1LPENR_GPIOELPEN 0x00000010U 01ec7a: line 6085 define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U 01eca1: line 6086 define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U 01ecc8: line 6087 define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U 01ecef: line 6088 define RCC_AHB1LPENR_GPIOILPEN 0x00000100U 01ed16: line 6089 define RCC_AHB1LPENR_GPIOJLPEN 0x00000200U 01ed3d: line 6090 define RCC_AHB1LPENR_GPIOKLPEN 0x00000400U 01ed64: line 6091 define RCC_AHB1LPENR_CRCLPEN 0x00001000U 01ed89: line 6092 define RCC_AHB1LPENR_AXILPEN 0x00002000U 01edae: line 6093 define RCC_AHB1LPENR_FLITFLPEN 0x00008000U 01edd5: line 6094 define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U 01edfc: line 6095 define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U 01ee23: line 6096 define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U 01ee4c: line 6097 define RCC_AHB1LPENR_DTCMLPEN 0x00100000U 01ee72: line 6098 define RCC_AHB1LPENR_DMA1LPEN 0x00200000U 01ee98: line 6099 define RCC_AHB1LPENR_DMA2LPEN 0x00400000U 01eebe: line 6100 define RCC_AHB1LPENR_DMA2DLPEN 0x00800000U 01eee5: line 6101 define RCC_AHB1LPENR_ETHMACLPEN 0x02000000U 01ef0d: line 6102 define RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U 01ef37: line 6103 define RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U 01ef61: line 6104 define RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U 01ef8c: line 6105 define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U 01efb3: line 6106 define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U 01efde: line 6109 define RCC_AHB2LPENR_DCMILPEN 0x00000001U 01f004: line 6110 define RCC_AHB2LPENR_JPEGLPEN 0x00000002U 01f02a: line 6111 define RCC_AHB2LPENR_RNGLPEN 0x00000040U 01f04f: line 6112 define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U 01f076: line 6115 define RCC_AHB3LPENR_FMCLPEN 0x00000001U 01f09b: line 6116 define RCC_AHB3LPENR_QSPILPEN 0x00000002U 01f0c1: line 6118 define RCC_APB1LPENR_TIM2LPEN 0x00000001U 01f0e7: line 6119 define RCC_APB1LPENR_TIM3LPEN 0x00000002U 01f10d: line 6120 define RCC_APB1LPENR_TIM4LPEN 0x00000004U 01f133: line 6121 define RCC_APB1LPENR_TIM5LPEN 0x00000008U 01f159: line 6122 define RCC_APB1LPENR_TIM6LPEN 0x00000010U 01f17f: line 6123 define RCC_APB1LPENR_TIM7LPEN 0x00000020U 01f1a5: line 6124 define RCC_APB1LPENR_TIM12LPEN 0x00000040U 01f1cc: line 6125 define RCC_APB1LPENR_TIM13LPEN 0x00000080U 01f1f3: line 6126 define RCC_APB1LPENR_TIM14LPEN 0x00000100U 01f21a: line 6127 define RCC_APB1LPENR_LPTIM1LPEN 0x00000200U 01f242: line 6128 define RCC_APB1LPENR_RTCLPEN 0x00000400U 01f267: line 6129 define RCC_APB1LPENR_WWDGLPEN 0x00000800U 01f28d: line 6130 define RCC_APB1LPENR_CAN3LPEN 0x00002000U 01f2b3: line 6131 define RCC_APB1LPENR_SPI2LPEN 0x00004000U 01f2d9: line 6132 define RCC_APB1LPENR_SPI3LPEN 0x00008000U 01f2ff: line 6133 define RCC_APB1LPENR_SPDIFRXLPEN 0x00010000U 01f328: line 6134 define RCC_APB1LPENR_USART2LPEN 0x00020000U 01f350: line 6135 define RCC_APB1LPENR_USART3LPEN 0x00040000U 01f378: line 6136 define RCC_APB1LPENR_UART4LPEN 0x00080000U 01f39f: line 6137 define RCC_APB1LPENR_UART5LPEN 0x00100000U 01f3c6: line 6138 define RCC_APB1LPENR_I2C1LPEN 0x00200000U 01f3ec: line 6139 define RCC_APB1LPENR_I2C2LPEN 0x00400000U 01f412: line 6140 define RCC_APB1LPENR_I2C3LPEN 0x00800000U 01f438: line 6141 define RCC_APB1LPENR_I2C4LPEN 0x01000000U 01f45e: line 6142 define RCC_APB1LPENR_CAN1LPEN 0x02000000U 01f484: line 6143 define RCC_APB1LPENR_CAN2LPEN 0x04000000U 01f4aa: line 6144 define RCC_APB1LPENR_CECLPEN 0x08000000U 01f4cf: line 6145 define RCC_APB1LPENR_PWRLPEN 0x10000000U 01f4f4: line 6146 define RCC_APB1LPENR_DACLPEN 0x20000000U 01f519: line 6147 define RCC_APB1LPENR_UART7LPEN 0x40000000U 01f540: line 6148 define RCC_APB1LPENR_UART8LPEN 0x80000000U 01f567: line 6151 define RCC_APB2LPENR_TIM1LPEN 0x00000001U 01f58d: line 6152 define RCC_APB2LPENR_TIM8LPEN 0x00000002U 01f5b3: line 6153 define RCC_APB2LPENR_USART1LPEN 0x00000010U 01f5db: line 6154 define RCC_APB2LPENR_USART6LPEN 0x00000020U 01f603: line 6155 define RCC_APB2LPENR_SDMMC2LPEN 0x00000080U 01f62b: line 6156 define RCC_APB2LPENR_ADC1LPEN 0x00000100U 01f651: line 6157 define RCC_APB2LPENR_ADC2LPEN 0x00000200U 01f677: line 6158 define RCC_APB2LPENR_ADC3LPEN 0x00000400U 01f69d: line 6159 define RCC_APB2LPENR_SDMMC1LPEN 0x00000800U 01f6c5: line 6160 define RCC_APB2LPENR_SPI1LPEN 0x00001000U 01f6eb: line 6161 define RCC_APB2LPENR_SPI4LPEN 0x00002000U 01f711: line 6162 define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U 01f739: line 6163 define RCC_APB2LPENR_TIM9LPEN 0x00010000U 01f75f: line 6164 define RCC_APB2LPENR_TIM10LPEN 0x00020000U 01f786: line 6165 define RCC_APB2LPENR_TIM11LPEN 0x00040000U 01f7ad: line 6166 define RCC_APB2LPENR_SPI5LPEN 0x00100000U 01f7d3: line 6167 define RCC_APB2LPENR_SPI6LPEN 0x00200000U 01f7f9: line 6168 define RCC_APB2LPENR_SAI1LPEN 0x00400000U 01f81f: line 6169 define RCC_APB2LPENR_SAI2LPEN 0x00800000U 01f845: line 6170 define RCC_APB2LPENR_LTDCLPEN 0x04000000U 01f86b: line 6171 define RCC_APB2LPENR_DFSDM1LPEN 0x20000000U 01f893: line 6172 define RCC_APB2LPENR_MDIOLPEN 0x40000000U 01f8b9: line 6175 define RCC_BDCR_LSEON 0x00000001U 01f8d7: line 6176 define RCC_BDCR_LSERDY 0x00000002U 01f8f6: line 6177 define RCC_BDCR_LSEBYP 0x00000004U 01f915: line 6178 define RCC_BDCR_LSEDRV 0x00000018U 01f934: line 6179 define RCC_BDCR_LSEDRV_0 0x00000008U 01f955: line 6180 define RCC_BDCR_LSEDRV_1 0x00000010U 01f976: line 6181 define RCC_BDCR_RTCSEL 0x00000300U 01f995: line 6182 define RCC_BDCR_RTCSEL_0 0x00000100U 01f9b6: line 6183 define RCC_BDCR_RTCSEL_1 0x00000200U 01f9d7: line 6184 define RCC_BDCR_RTCEN 0x00008000U 01f9f5: line 6185 define RCC_BDCR_BDRST 0x00010000U 01fa13: line 6188 define RCC_CSR_LSION 0x00000001U 01fa30: line 6189 define RCC_CSR_LSIRDY 0x00000002U 01fa4e: line 6190 define RCC_CSR_RMVF 0x01000000U 01fa6a: line 6191 define RCC_CSR_BORRSTF 0x02000000U 01fa89: line 6192 define RCC_CSR_PINRSTF 0x04000000U 01faa8: line 6193 define RCC_CSR_PORRSTF 0x08000000U 01fac7: line 6194 define RCC_CSR_SFTRSTF 0x10000000U 01fae6: line 6195 define RCC_CSR_IWDGRSTF 0x20000000U 01fb06: line 6196 define RCC_CSR_WWDGRSTF 0x40000000U 01fb26: line 6197 define RCC_CSR_LPWRRSTF 0x80000000U 01fb46: line 6200 define RCC_SSCGR_MODPER 0x00001FFFU 01fb66: line 6201 define RCC_SSCGR_INCSTEP 0x0FFFE000U 01fb87: line 6202 define RCC_SSCGR_SPREADSEL 0x40000000U 01fbaa: line 6203 define RCC_SSCGR_SSCGEN 0x80000000U 01fbca: line 6206 define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U 01fbf0: line 6207 define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U 01fc18: line 6208 define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U 01fc40: line 6209 define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U 01fc68: line 6210 define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U 01fc90: line 6211 define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U 01fcb8: line 6212 define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U 01fce0: line 6213 define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U 01fd08: line 6214 define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U 01fd30: line 6215 define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U 01fd58: line 6216 define RCC_PLLI2SCFGR_PLLI2SP 0x00030000U 01fd7e: line 6217 define RCC_PLLI2SCFGR_PLLI2SP_0 0x00010000U 01fda6: line 6218 define RCC_PLLI2SCFGR_PLLI2SP_1 0x00020000U 01fdce: line 6219 define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U 01fdf4: line 6220 define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U 01fe1c: line 6221 define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U 01fe44: line 6222 define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U 01fe6c: line 6223 define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U 01fe94: line 6224 define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U 01feba: line 6225 define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U 01fee2: line 6226 define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U 01ff0a: line 6227 define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U 01ff32: line 6230 define RCC_PLLSAICFGR_PLLSAIN 0x00007FC0U 01ff58: line 6231 define RCC_PLLSAICFGR_PLLSAIN_0 0x00000040U 01ff80: line 6232 define RCC_PLLSAICFGR_PLLSAIN_1 0x00000080U 01ffa8: line 6233 define RCC_PLLSAICFGR_PLLSAIN_2 0x00000100U 01ffd0: line 6234 define RCC_PLLSAICFGR_PLLSAIN_3 0x00000200U 01fff8: line 6235 define RCC_PLLSAICFGR_PLLSAIN_4 0x00000400U 020020: line 6236 define RCC_PLLSAICFGR_PLLSAIN_5 0x00000800U 020048: line 6237 define RCC_PLLSAICFGR_PLLSAIN_6 0x00001000U 020070: line 6238 define RCC_PLLSAICFGR_PLLSAIN_7 0x00002000U 020098: line 6239 define RCC_PLLSAICFGR_PLLSAIN_8 0x00004000U 0200c0: line 6240 define RCC_PLLSAICFGR_PLLSAIP 0x00030000U 0200e6: line 6241 define RCC_PLLSAICFGR_PLLSAIP_0 0x00010000U 02010e: line 6242 define RCC_PLLSAICFGR_PLLSAIP_1 0x00020000U 020136: line 6243 define RCC_PLLSAICFGR_PLLSAIQ 0x0F000000U 02015c: line 6244 define RCC_PLLSAICFGR_PLLSAIQ_0 0x01000000U 020184: line 6245 define RCC_PLLSAICFGR_PLLSAIQ_1 0x02000000U 0201ac: line 6246 define RCC_PLLSAICFGR_PLLSAIQ_2 0x04000000U 0201d4: line 6247 define RCC_PLLSAICFGR_PLLSAIQ_3 0x08000000U 0201fc: line 6248 define RCC_PLLSAICFGR_PLLSAIR 0x70000000U 020222: line 6249 define RCC_PLLSAICFGR_PLLSAIR_0 0x10000000U 02024a: line 6250 define RCC_PLLSAICFGR_PLLSAIR_1 0x20000000U 020272: line 6251 define RCC_PLLSAICFGR_PLLSAIR_2 0x40000000U 02029a: line 6254 define RCC_DCKCFGR1_PLLI2SDIVQ 0x0000001FU 0202c1: line 6255 define RCC_DCKCFGR1_PLLI2SDIVQ_0 0x00000001U 0202ea: line 6256 define RCC_DCKCFGR1_PLLI2SDIVQ_1 0x00000002U 020313: line 6257 define RCC_DCKCFGR1_PLLI2SDIVQ_2 0x00000004U 02033c: line 6258 define RCC_DCKCFGR1_PLLI2SDIVQ_3 0x00000008U 020365: line 6259 define RCC_DCKCFGR1_PLLI2SDIVQ_4 0x00000010U 02038e: line 6261 define RCC_DCKCFGR1_PLLSAIDIVQ 0x00001F00U 0203b5: line 6262 define RCC_DCKCFGR1_PLLSAIDIVQ_0 0x00000100U 0203de: line 6263 define RCC_DCKCFGR1_PLLSAIDIVQ_1 0x00000200U 020407: line 6264 define RCC_DCKCFGR1_PLLSAIDIVQ_2 0x00000400U 020430: line 6265 define RCC_DCKCFGR1_PLLSAIDIVQ_3 0x00000800U 020459: line 6266 define RCC_DCKCFGR1_PLLSAIDIVQ_4 0x00001000U 020482: line 6268 define RCC_DCKCFGR1_PLLSAIDIVR 0x00030000U 0204a9: line 6269 define RCC_DCKCFGR1_PLLSAIDIVR_0 0x00010000U 0204d2: line 6270 define RCC_DCKCFGR1_PLLSAIDIVR_1 0x00020000U 0204fb: line 6272 define RCC_DCKCFGR1_SAI1SEL 0x00300000U 02051f: line 6273 define RCC_DCKCFGR1_SAI1SEL_0 0x00100000U 020545: line 6274 define RCC_DCKCFGR1_SAI1SEL_1 0x00200000U 02056b: line 6276 define RCC_DCKCFGR1_SAI2SEL 0x00C00000U 02058f: line 6277 define RCC_DCKCFGR1_SAI2SEL_0 0x00400000U 0205b5: line 6278 define RCC_DCKCFGR1_SAI2SEL_1 0x00800000U 0205db: line 6280 define RCC_DCKCFGR1_TIMPRE 0x01000000U 0205fe: line 6281 define RCC_DCKCFGR1_DFSDM1SEL 0x02000000U 020624: line 6282 define RCC_DCKCFGR1_ADFSDM1SEL 0x04000000U 02064b: line 6285 define RCC_DCKCFGR2_USART1SEL 0x00000003U 020671: line 6286 define RCC_DCKCFGR2_USART1SEL_0 0x00000001U 020699: line 6287 define RCC_DCKCFGR2_USART1SEL_1 0x00000002U 0206c1: line 6288 define RCC_DCKCFGR2_USART2SEL 0x0000000CU 0206e7: line 6289 define RCC_DCKCFGR2_USART2SEL_0 0x00000004U 02070f: line 6290 define RCC_DCKCFGR2_USART2SEL_1 0x00000008U 020737: line 6291 define RCC_DCKCFGR2_USART3SEL 0x00000030U 02075d: line 6292 define RCC_DCKCFGR2_USART3SEL_0 0x00000010U 020785: line 6293 define RCC_DCKCFGR2_USART3SEL_1 0x00000020U 0207ad: line 6294 define RCC_DCKCFGR2_UART4SEL 0x000000C0U 0207d2: line 6295 define RCC_DCKCFGR2_UART4SEL_0 0x00000040U 0207f9: line 6296 define RCC_DCKCFGR2_UART4SEL_1 0x00000080U 020820: line 6297 define RCC_DCKCFGR2_UART5SEL 0x00000300U 020845: line 6298 define RCC_DCKCFGR2_UART5SEL_0 0x00000100U 02086c: line 6299 define RCC_DCKCFGR2_UART5SEL_1 0x00000200U 020893: line 6300 define RCC_DCKCFGR2_USART6SEL 0x00000C00U 0208b9: line 6301 define RCC_DCKCFGR2_USART6SEL_0 0x00000400U 0208e1: line 6302 define RCC_DCKCFGR2_USART6SEL_1 0x00000800U 020909: line 6303 define RCC_DCKCFGR2_UART7SEL 0x00003000U 02092e: line 6304 define RCC_DCKCFGR2_UART7SEL_0 0x00001000U 020955: line 6305 define RCC_DCKCFGR2_UART7SEL_1 0x00002000U 02097c: line 6306 define RCC_DCKCFGR2_UART8SEL 0x0000C000U 0209a1: line 6307 define RCC_DCKCFGR2_UART8SEL_0 0x00004000U 0209c8: line 6308 define RCC_DCKCFGR2_UART8SEL_1 0x00008000U 0209ef: line 6309 define RCC_DCKCFGR2_I2C1SEL 0x00030000U 020a13: line 6310 define RCC_DCKCFGR2_I2C1SEL_0 0x00010000U 020a39: line 6311 define RCC_DCKCFGR2_I2C1SEL_1 0x00020000U 020a5f: line 6312 define RCC_DCKCFGR2_I2C2SEL 0x000C0000U 020a83: line 6313 define RCC_DCKCFGR2_I2C2SEL_0 0x00040000U 020aa9: line 6314 define RCC_DCKCFGR2_I2C2SEL_1 0x00080000U 020acf: line 6315 define RCC_DCKCFGR2_I2C3SEL 0x00300000U 020af3: line 6316 define RCC_DCKCFGR2_I2C3SEL_0 0x00100000U 020b19: line 6317 define RCC_DCKCFGR2_I2C3SEL_1 0x00200000U 020b3f: line 6318 define RCC_DCKCFGR2_I2C4SEL 0x00C00000U 020b63: line 6319 define RCC_DCKCFGR2_I2C4SEL_0 0x00400000U 020b89: line 6320 define RCC_DCKCFGR2_I2C4SEL_1 0x00800000U 020baf: line 6321 define RCC_DCKCFGR2_LPTIM1SEL 0x03000000U 020bd5: line 6322 define RCC_DCKCFGR2_LPTIM1SEL_0 0x01000000U 020bfd: line 6323 define RCC_DCKCFGR2_LPTIM1SEL_1 0x02000000U 020c25: line 6324 define RCC_DCKCFGR2_CECSEL 0x04000000U 020c48: line 6325 define RCC_DCKCFGR2_CK48MSEL 0x08000000U 020c6d: line 6326 define RCC_DCKCFGR2_SDMMC1SEL 0x10000000U 020c93: line 6327 define RCC_DCKCFGR2_SDMMC2SEL 0x20000000U 020cb9: line 6335 define RNG_CR_RNGEN 0x00000004U 020cd5: line 6336 define RNG_CR_IE 0x00000008U 020cee: line 6339 define RNG_SR_DRDY 0x00000001U 020d09: line 6340 define RNG_SR_CECS 0x00000002U 020d24: line 6341 define RNG_SR_SECS 0x00000004U 020d3f: line 6342 define RNG_SR_CEIS 0x00000020U 020d5a: line 6343 define RNG_SR_SEIS 0x00000040U 020d75: line 6351 define RTC_TR_PM 0x00400000U 020d8e: line 6352 define RTC_TR_HT 0x00300000U 020da7: line 6353 define RTC_TR_HT_0 0x00100000U 020dc2: line 6354 define RTC_TR_HT_1 0x00200000U 020ddd: line 6355 define RTC_TR_HU 0x000F0000U 020df6: line 6356 define RTC_TR_HU_0 0x00010000U 020e11: line 6357 define RTC_TR_HU_1 0x00020000U 020e2c: line 6358 define RTC_TR_HU_2 0x00040000U 020e47: line 6359 define RTC_TR_HU_3 0x00080000U 020e62: line 6360 define RTC_TR_MNT 0x00007000U 020e7c: line 6361 define RTC_TR_MNT_0 0x00001000U 020e98: line 6362 define RTC_TR_MNT_1 0x00002000U 020eb4: line 6363 define RTC_TR_MNT_2 0x00004000U 020ed0: line 6364 define RTC_TR_MNU 0x00000F00U 020eea: line 6365 define RTC_TR_MNU_0 0x00000100U 020f06: line 6366 define RTC_TR_MNU_1 0x00000200U 020f22: line 6367 define RTC_TR_MNU_2 0x00000400U 020f3e: line 6368 define RTC_TR_MNU_3 0x00000800U 020f5a: line 6369 define RTC_TR_ST 0x00000070U 020f73: line 6370 define RTC_TR_ST_0 0x00000010U 020f8e: line 6371 define RTC_TR_ST_1 0x00000020U 020fa9: line 6372 define RTC_TR_ST_2 0x00000040U 020fc4: line 6373 define RTC_TR_SU 0x0000000FU 020fdd: line 6374 define RTC_TR_SU_0 0x00000001U 020ff8: line 6375 define RTC_TR_SU_1 0x00000002U 021013: line 6376 define RTC_TR_SU_2 0x00000004U 02102e: line 6377 define RTC_TR_SU_3 0x00000008U 021049: line 6380 define RTC_DR_YT 0x00F00000U 021062: line 6381 define RTC_DR_YT_0 0x00100000U 02107d: line 6382 define RTC_DR_YT_1 0x00200000U 021098: line 6383 define RTC_DR_YT_2 0x00400000U 0210b3: line 6384 define RTC_DR_YT_3 0x00800000U 0210ce: line 6385 define RTC_DR_YU 0x000F0000U 0210e7: line 6386 define RTC_DR_YU_0 0x00010000U 021102: line 6387 define RTC_DR_YU_1 0x00020000U 02111d: line 6388 define RTC_DR_YU_2 0x00040000U 021138: line 6389 define RTC_DR_YU_3 0x00080000U 021153: line 6390 define RTC_DR_WDU 0x0000E000U 02116d: line 6391 define RTC_DR_WDU_0 0x00002000U 021189: line 6392 define RTC_DR_WDU_1 0x00004000U 0211a5: line 6393 define RTC_DR_WDU_2 0x00008000U 0211c1: line 6394 define RTC_DR_MT 0x00001000U 0211da: line 6395 define RTC_DR_MU 0x00000F00U 0211f3: line 6396 define RTC_DR_MU_0 0x00000100U 02120e: line 6397 define RTC_DR_MU_1 0x00000200U 021229: line 6398 define RTC_DR_MU_2 0x00000400U 021244: line 6399 define RTC_DR_MU_3 0x00000800U 02125f: line 6400 define RTC_DR_DT 0x00000030U 021278: line 6401 define RTC_DR_DT_0 0x00000010U 021293: line 6402 define RTC_DR_DT_1 0x00000020U 0212ae: line 6403 define RTC_DR_DU 0x0000000FU 0212c7: line 6404 define RTC_DR_DU_0 0x00000001U 0212e2: line 6405 define RTC_DR_DU_1 0x00000002U 0212fd: line 6406 define RTC_DR_DU_2 0x00000004U 021318: line 6407 define RTC_DR_DU_3 0x00000008U 021333: line 6410 define RTC_CR_ITSE 0x01000000U 02134e: line 6411 define RTC_CR_COE 0x00800000U 021368: line 6412 define RTC_CR_OSEL 0x00600000U 021383: line 6413 define RTC_CR_OSEL_0 0x00200000U 0213a0: line 6414 define RTC_CR_OSEL_1 0x00400000U 0213bd: line 6415 define RTC_CR_POL 0x00100000U 0213d7: line 6416 define RTC_CR_COSEL 0x00080000U 0213f3: line 6417 define RTC_CR_BKP 0x00040000U 02140d: line 6418 define RTC_CR_SUB1H 0x00020000U 021429: line 6419 define RTC_CR_ADD1H 0x00010000U 021445: line 6420 define RTC_CR_TSIE 0x00008000U 021460: line 6421 define RTC_CR_WUTIE 0x00004000U 02147c: line 6422 define RTC_CR_ALRBIE 0x00002000U 021499: line 6423 define RTC_CR_ALRAIE 0x00001000U 0214b6: line 6424 define RTC_CR_TSE 0x00000800U 0214d0: line 6425 define RTC_CR_WUTE 0x00000400U 0214eb: line 6426 define RTC_CR_ALRBE 0x00000200U 021507: line 6427 define RTC_CR_ALRAE 0x00000100U 021523: line 6428 define RTC_CR_FMT 0x00000040U 02153d: line 6429 define RTC_CR_BYPSHAD 0x00000020U 02155b: line 6430 define RTC_CR_REFCKON 0x00000010U 021579: line 6431 define RTC_CR_TSEDGE 0x00000008U 021596: line 6432 define RTC_CR_WUCKSEL 0x00000007U 0215b4: line 6433 define RTC_CR_WUCKSEL_0 0x00000001U 0215d4: line 6434 define RTC_CR_WUCKSEL_1 0x00000002U 0215f4: line 6435 define RTC_CR_WUCKSEL_2 0x00000004U 021614: line 6438 define RTC_CR_BCK RTC_CR_BKP 02162d: line 6441 define RTC_ISR_ITSF 0x00020000U 021649: line 6442 define RTC_ISR_RECALPF 0x00010000U 021668: line 6443 define RTC_ISR_TAMP3F 0x00008000U 021686: line 6444 define RTC_ISR_TAMP2F 0x00004000U 0216a4: line 6445 define RTC_ISR_TAMP1F 0x00002000U 0216c2: line 6446 define RTC_ISR_TSOVF 0x00001000U 0216df: line 6447 define RTC_ISR_TSF 0x00000800U 0216fa: line 6448 define RTC_ISR_WUTF 0x00000400U 021716: line 6449 define RTC_ISR_ALRBF 0x00000200U 021733: line 6450 define RTC_ISR_ALRAF 0x00000100U 021750: line 6451 define RTC_ISR_INIT 0x00000080U 02176c: line 6452 define RTC_ISR_INITF 0x00000040U 021789: line 6453 define RTC_ISR_RSF 0x00000020U 0217a4: line 6454 define RTC_ISR_INITS 0x00000010U 0217c1: line 6455 define RTC_ISR_SHPF 0x00000008U 0217dd: line 6456 define RTC_ISR_WUTWF 0x00000004U 0217fa: line 6457 define RTC_ISR_ALRBWF 0x00000002U 021818: line 6458 define RTC_ISR_ALRAWF 0x00000001U 021836: line 6461 define RTC_PRER_PREDIV_A 0x007F0000U 021857: line 6462 define RTC_PRER_PREDIV_S 0x00007FFFU 021878: line 6465 define RTC_WUTR_WUT 0x0000FFFFU 021894: line 6468 define RTC_ALRMAR_MSK4 0x80000000U 0218b3: line 6469 define RTC_ALRMAR_WDSEL 0x40000000U 0218d3: line 6470 define RTC_ALRMAR_DT 0x30000000U 0218f0: line 6471 define RTC_ALRMAR_DT_0 0x10000000U 02190f: line 6472 define RTC_ALRMAR_DT_1 0x20000000U 02192e: line 6473 define RTC_ALRMAR_DU 0x0F000000U 02194b: line 6474 define RTC_ALRMAR_DU_0 0x01000000U 02196a: line 6475 define RTC_ALRMAR_DU_1 0x02000000U 021989: line 6476 define RTC_ALRMAR_DU_2 0x04000000U 0219a8: line 6477 define RTC_ALRMAR_DU_3 0x08000000U 0219c7: line 6478 define RTC_ALRMAR_MSK3 0x00800000U 0219e6: line 6479 define RTC_ALRMAR_PM 0x00400000U 021a03: line 6480 define RTC_ALRMAR_HT 0x00300000U 021a20: line 6481 define RTC_ALRMAR_HT_0 0x00100000U 021a3f: line 6482 define RTC_ALRMAR_HT_1 0x00200000U 021a5e: line 6483 define RTC_ALRMAR_HU 0x000F0000U 021a7b: line 6484 define RTC_ALRMAR_HU_0 0x00010000U 021a9a: line 6485 define RTC_ALRMAR_HU_1 0x00020000U 021ab9: line 6486 define RTC_ALRMAR_HU_2 0x00040000U 021ad8: line 6487 define RTC_ALRMAR_HU_3 0x00080000U 021af7: line 6488 define RTC_ALRMAR_MSK2 0x00008000U 021b16: line 6489 define RTC_ALRMAR_MNT 0x00007000U 021b34: line 6490 define RTC_ALRMAR_MNT_0 0x00001000U 021b54: line 6491 define RTC_ALRMAR_MNT_1 0x00002000U 021b74: line 6492 define RTC_ALRMAR_MNT_2 0x00004000U 021b94: line 6493 define RTC_ALRMAR_MNU 0x00000F00U 021bb2: line 6494 define RTC_ALRMAR_MNU_0 0x00000100U 021bd2: line 6495 define RTC_ALRMAR_MNU_1 0x00000200U 021bf2: line 6496 define RTC_ALRMAR_MNU_2 0x00000400U 021c12: line 6497 define RTC_ALRMAR_MNU_3 0x00000800U 021c32: line 6498 define RTC_ALRMAR_MSK1 0x00000080U 021c51: line 6499 define RTC_ALRMAR_ST 0x00000070U 021c6e: line 6500 define RTC_ALRMAR_ST_0 0x00000010U 021c8d: line 6501 define RTC_ALRMAR_ST_1 0x00000020U 021cac: line 6502 define RTC_ALRMAR_ST_2 0x00000040U 021ccb: line 6503 define RTC_ALRMAR_SU 0x0000000FU 021ce8: line 6504 define RTC_ALRMAR_SU_0 0x00000001U 021d07: line 6505 define RTC_ALRMAR_SU_1 0x00000002U 021d26: line 6506 define RTC_ALRMAR_SU_2 0x00000004U 021d45: line 6507 define RTC_ALRMAR_SU_3 0x00000008U 021d64: line 6510 define RTC_ALRMBR_MSK4 0x80000000U 021d83: line 6511 define RTC_ALRMBR_WDSEL 0x40000000U 021da3: line 6512 define RTC_ALRMBR_DT 0x30000000U 021dc0: line 6513 define RTC_ALRMBR_DT_0 0x10000000U 021ddf: line 6514 define RTC_ALRMBR_DT_1 0x20000000U 021dfe: line 6515 define RTC_ALRMBR_DU 0x0F000000U 021e1b: line 6516 define RTC_ALRMBR_DU_0 0x01000000U 021e3a: line 6517 define RTC_ALRMBR_DU_1 0x02000000U 021e59: line 6518 define RTC_ALRMBR_DU_2 0x04000000U 021e78: line 6519 define RTC_ALRMBR_DU_3 0x08000000U 021e97: line 6520 define RTC_ALRMBR_MSK3 0x00800000U 021eb6: line 6521 define RTC_ALRMBR_PM 0x00400000U 021ed3: line 6522 define RTC_ALRMBR_HT 0x00300000U 021ef0: line 6523 define RTC_ALRMBR_HT_0 0x00100000U 021f0f: line 6524 define RTC_ALRMBR_HT_1 0x00200000U 021f2e: line 6525 define RTC_ALRMBR_HU 0x000F0000U 021f4b: line 6526 define RTC_ALRMBR_HU_0 0x00010000U 021f6a: line 6527 define RTC_ALRMBR_HU_1 0x00020000U 021f89: line 6528 define RTC_ALRMBR_HU_2 0x00040000U 021fa8: line 6529 define RTC_ALRMBR_HU_3 0x00080000U 021fc7: line 6530 define RTC_ALRMBR_MSK2 0x00008000U 021fe6: line 6531 define RTC_ALRMBR_MNT 0x00007000U 022004: line 6532 define RTC_ALRMBR_MNT_0 0x00001000U 022024: line 6533 define RTC_ALRMBR_MNT_1 0x00002000U 022044: line 6534 define RTC_ALRMBR_MNT_2 0x00004000U 022064: line 6535 define RTC_ALRMBR_MNU 0x00000F00U 022082: line 6536 define RTC_ALRMBR_MNU_0 0x00000100U 0220a2: line 6537 define RTC_ALRMBR_MNU_1 0x00000200U 0220c2: line 6538 define RTC_ALRMBR_MNU_2 0x00000400U 0220e2: line 6539 define RTC_ALRMBR_MNU_3 0x00000800U 022102: line 6540 define RTC_ALRMBR_MSK1 0x00000080U 022121: line 6541 define RTC_ALRMBR_ST 0x00000070U 02213e: line 6542 define RTC_ALRMBR_ST_0 0x00000010U 02215d: line 6543 define RTC_ALRMBR_ST_1 0x00000020U 02217c: line 6544 define RTC_ALRMBR_ST_2 0x00000040U 02219b: line 6545 define RTC_ALRMBR_SU 0x0000000FU 0221b8: line 6546 define RTC_ALRMBR_SU_0 0x00000001U 0221d7: line 6547 define RTC_ALRMBR_SU_1 0x00000002U 0221f6: line 6548 define RTC_ALRMBR_SU_2 0x00000004U 022215: line 6549 define RTC_ALRMBR_SU_3 0x00000008U 022234: line 6552 define RTC_WPR_KEY 0x000000FFU 02224f: line 6555 define RTC_SSR_SS 0x0000FFFFU 022269: line 6558 define RTC_SHIFTR_SUBFS 0x00007FFFU 022289: line 6559 define RTC_SHIFTR_ADD1S 0x80000000U 0222a9: line 6562 define RTC_TSTR_PM 0x00400000U 0222c4: line 6563 define RTC_TSTR_HT 0x00300000U 0222df: line 6564 define RTC_TSTR_HT_0 0x00100000U 0222fc: line 6565 define RTC_TSTR_HT_1 0x00200000U 022319: line 6566 define RTC_TSTR_HU 0x000F0000U 022334: line 6567 define RTC_TSTR_HU_0 0x00010000U 022351: line 6568 define RTC_TSTR_HU_1 0x00020000U 02236e: line 6569 define RTC_TSTR_HU_2 0x00040000U 02238b: line 6570 define RTC_TSTR_HU_3 0x00080000U 0223a8: line 6571 define RTC_TSTR_MNT 0x00007000U 0223c4: line 6572 define RTC_TSTR_MNT_0 0x00001000U 0223e2: line 6573 define RTC_TSTR_MNT_1 0x00002000U 022400: line 6574 define RTC_TSTR_MNT_2 0x00004000U 02241e: line 6575 define RTC_TSTR_MNU 0x00000F00U 02243a: line 6576 define RTC_TSTR_MNU_0 0x00000100U 022458: line 6577 define RTC_TSTR_MNU_1 0x00000200U 022476: line 6578 define RTC_TSTR_MNU_2 0x00000400U 022494: line 6579 define RTC_TSTR_MNU_3 0x00000800U 0224b2: line 6580 define RTC_TSTR_ST 0x00000070U 0224cd: line 6581 define RTC_TSTR_ST_0 0x00000010U 0224ea: line 6582 define RTC_TSTR_ST_1 0x00000020U 022507: line 6583 define RTC_TSTR_ST_2 0x00000040U 022524: line 6584 define RTC_TSTR_SU 0x0000000FU 02253f: line 6585 define RTC_TSTR_SU_0 0x00000001U 02255c: line 6586 define RTC_TSTR_SU_1 0x00000002U 022579: line 6587 define RTC_TSTR_SU_2 0x00000004U 022596: line 6588 define RTC_TSTR_SU_3 0x00000008U 0225b3: line 6591 define RTC_TSDR_WDU 0x0000E000U 0225cf: line 6592 define RTC_TSDR_WDU_0 0x00002000U 0225ed: line 6593 define RTC_TSDR_WDU_1 0x00004000U 02260b: line 6594 define RTC_TSDR_WDU_2 0x00008000U 022629: line 6595 define RTC_TSDR_MT 0x00001000U 022644: line 6596 define RTC_TSDR_MU 0x00000F00U 02265f: line 6597 define RTC_TSDR_MU_0 0x00000100U 02267c: line 6598 define RTC_TSDR_MU_1 0x00000200U 022699: line 6599 define RTC_TSDR_MU_2 0x00000400U 0226b6: line 6600 define RTC_TSDR_MU_3 0x00000800U 0226d3: line 6601 define RTC_TSDR_DT 0x00000030U 0226ee: line 6602 define RTC_TSDR_DT_0 0x00000010U 02270b: line 6603 define RTC_TSDR_DT_1 0x00000020U 022728: line 6604 define RTC_TSDR_DU 0x0000000FU 022743: line 6605 define RTC_TSDR_DU_0 0x00000001U 022760: line 6606 define RTC_TSDR_DU_1 0x00000002U 02277d: line 6607 define RTC_TSDR_DU_2 0x00000004U 02279a: line 6608 define RTC_TSDR_DU_3 0x00000008U 0227b7: line 6611 define RTC_TSSSR_SS 0x0000FFFFU 0227d3: line 6614 define RTC_CALR_CALP 0x00008000U 0227f0: line 6615 define RTC_CALR_CALW8 0x00004000U 02280e: line 6616 define RTC_CALR_CALW16 0x00002000U 02282d: line 6617 define RTC_CALR_CALM 0x000001FFU 02284a: line 6618 define RTC_CALR_CALM_0 0x00000001U 022869: line 6619 define RTC_CALR_CALM_1 0x00000002U 022888: line 6620 define RTC_CALR_CALM_2 0x00000004U 0228a7: line 6621 define RTC_CALR_CALM_3 0x00000008U 0228c6: line 6622 define RTC_CALR_CALM_4 0x00000010U 0228e5: line 6623 define RTC_CALR_CALM_5 0x00000020U 022904: line 6624 define RTC_CALR_CALM_6 0x00000040U 022923: line 6625 define RTC_CALR_CALM_7 0x00000080U 022942: line 6626 define RTC_CALR_CALM_8 0x00000100U 022961: line 6629 define RTC_TAMPCR_TAMP3MF 0x01000000U 022983: line 6630 define RTC_TAMPCR_TAMP3NOERASE 0x00800000U 0229aa: line 6631 define RTC_TAMPCR_TAMP3IE 0x00400000U 0229cc: line 6632 define RTC_TAMPCR_TAMP2MF 0x00200000U 0229ee: line 6633 define RTC_TAMPCR_TAMP2NOERASE 0x00100000U 022a15: line 6634 define RTC_TAMPCR_TAMP2IE 0x00080000U 022a37: line 6635 define RTC_TAMPCR_TAMP1MF 0x00040000U 022a59: line 6636 define RTC_TAMPCR_TAMP1NOERASE 0x00020000U 022a80: line 6637 define RTC_TAMPCR_TAMP1IE 0x00010000U 022aa2: line 6638 define RTC_TAMPCR_TAMPPUDIS 0x00008000U 022ac6: line 6639 define RTC_TAMPCR_TAMPPRCH 0x00006000U 022ae9: line 6640 define RTC_TAMPCR_TAMPPRCH_0 0x00002000U 022b0e: line 6641 define RTC_TAMPCR_TAMPPRCH_1 0x00004000U 022b33: line 6642 define RTC_TAMPCR_TAMPFLT 0x00001800U 022b55: line 6643 define RTC_TAMPCR_TAMPFLT_0 0x00000800U 022b79: line 6644 define RTC_TAMPCR_TAMPFLT_1 0x00001000U 022b9d: line 6645 define RTC_TAMPCR_TAMPFREQ 0x00000700U 022bc0: line 6646 define RTC_TAMPCR_TAMPFREQ_0 0x00000100U 022be5: line 6647 define RTC_TAMPCR_TAMPFREQ_1 0x00000200U 022c0a: line 6648 define RTC_TAMPCR_TAMPFREQ_2 0x00000400U 022c2f: line 6649 define RTC_TAMPCR_TAMPTS 0x00000080U 022c50: line 6650 define RTC_TAMPCR_TAMP3TRG 0x00000040U 022c73: line 6651 define RTC_TAMPCR_TAMP3E 0x00000020U 022c94: line 6652 define RTC_TAMPCR_TAMP2TRG 0x00000010U 022cb7: line 6653 define RTC_TAMPCR_TAMP2E 0x00000008U 022cd8: line 6654 define RTC_TAMPCR_TAMPIE 0x00000004U 022cf9: line 6655 define RTC_TAMPCR_TAMP1TRG 0x00000002U 022d1c: line 6656 define RTC_TAMPCR_TAMP1E 0x00000001U 022d3d: line 6660 define RTC_ALRMASSR_MASKSS 0x0F000000U 022d60: line 6661 define RTC_ALRMASSR_MASKSS_0 0x01000000U 022d85: line 6662 define RTC_ALRMASSR_MASKSS_1 0x02000000U 022daa: line 6663 define RTC_ALRMASSR_MASKSS_2 0x04000000U 022dcf: line 6664 define RTC_ALRMASSR_MASKSS_3 0x08000000U 022df4: line 6665 define RTC_ALRMASSR_SS 0x00007FFFU 022e13: line 6668 define RTC_ALRMBSSR_MASKSS 0x0F000000U 022e36: line 6669 define RTC_ALRMBSSR_MASKSS_0 0x01000000U 022e5b: line 6670 define RTC_ALRMBSSR_MASKSS_1 0x02000000U 022e80: line 6671 define RTC_ALRMBSSR_MASKSS_2 0x04000000U 022ea5: line 6672 define RTC_ALRMBSSR_MASKSS_3 0x08000000U 022eca: line 6673 define RTC_ALRMBSSR_SS 0x00007FFFU 022ee9: line 6676 define RTC_OR_TSINSEL 0x00000006U 022f07: line 6677 define RTC_OR_TSINSEL_0 0x00000002U 022f27: line 6678 define RTC_OR_TSINSEL_1 0x00000004U 022f47: line 6679 define RTC_OR_ALARMTYPE 0x00000008U 022f67: line 6682 define RTC_BKP0R 0xFFFFFFFFU 022f80: line 6685 define RTC_BKP1R 0xFFFFFFFFU 022f99: line 6688 define RTC_BKP2R 0xFFFFFFFFU 022fb2: line 6691 define RTC_BKP3R 0xFFFFFFFFU 022fcb: line 6694 define RTC_BKP4R 0xFFFFFFFFU 022fe4: line 6697 define RTC_BKP5R 0xFFFFFFFFU 022ffd: line 6700 define RTC_BKP6R 0xFFFFFFFFU 023016: line 6703 define RTC_BKP7R 0xFFFFFFFFU 02302f: line 6706 define RTC_BKP8R 0xFFFFFFFFU 023048: line 6709 define RTC_BKP9R 0xFFFFFFFFU 023061: line 6712 define RTC_BKP10R 0xFFFFFFFFU 02307b: line 6715 define RTC_BKP11R 0xFFFFFFFFU 023095: line 6718 define RTC_BKP12R 0xFFFFFFFFU 0230af: line 6721 define RTC_BKP13R 0xFFFFFFFFU 0230c9: line 6724 define RTC_BKP14R 0xFFFFFFFFU 0230e3: line 6727 define RTC_BKP15R 0xFFFFFFFFU 0230fd: line 6730 define RTC_BKP16R 0xFFFFFFFFU 023117: line 6733 define RTC_BKP17R 0xFFFFFFFFU 023131: line 6736 define RTC_BKP18R 0xFFFFFFFFU 02314b: line 6739 define RTC_BKP19R 0xFFFFFFFFU 023165: line 6742 define RTC_BKP20R 0xFFFFFFFFU 02317f: line 6745 define RTC_BKP21R 0xFFFFFFFFU 023199: line 6748 define RTC_BKP22R 0xFFFFFFFFU 0231b3: line 6751 define RTC_BKP23R 0xFFFFFFFFU 0231cd: line 6754 define RTC_BKP24R 0xFFFFFFFFU 0231e7: line 6757 define RTC_BKP25R 0xFFFFFFFFU 023201: line 6760 define RTC_BKP26R 0xFFFFFFFFU 02321b: line 6763 define RTC_BKP27R 0xFFFFFFFFU 023235: line 6766 define RTC_BKP28R 0xFFFFFFFFU 02324f: line 6769 define RTC_BKP29R 0xFFFFFFFFU 023269: line 6772 define RTC_BKP30R 0xFFFFFFFFU 023283: line 6775 define RTC_BKP31R 0xFFFFFFFFU 02329d: line 6778 define RTC_BKP_NUMBER 0x00000020U 0232bb: line 6787 define SAI_GCR_SYNCIN 0x00000003U 0232d9: line 6788 define SAI_GCR_SYNCIN_0 0x00000001U 0232f9: line 6789 define SAI_GCR_SYNCIN_1 0x00000002U 023319: line 6791 define SAI_GCR_SYNCOUT 0x00000030U 023338: line 6792 define SAI_GCR_SYNCOUT_0 0x00000010U 023359: line 6793 define SAI_GCR_SYNCOUT_1 0x00000020U 02337a: line 6796 define SAI_xCR1_MODE 0x00000003U 023397: line 6797 define SAI_xCR1_MODE_0 0x00000001U 0233b6: line 6798 define SAI_xCR1_MODE_1 0x00000002U 0233d5: line 6800 define SAI_xCR1_PRTCFG 0x0000000CU 0233f4: line 6801 define SAI_xCR1_PRTCFG_0 0x00000004U 023415: line 6802 define SAI_xCR1_PRTCFG_1 0x00000008U 023436: line 6804 define SAI_xCR1_DS 0x000000E0U 023451: line 6805 define SAI_xCR1_DS_0 0x00000020U 02346e: line 6806 define SAI_xCR1_DS_1 0x00000040U 02348b: line 6807 define SAI_xCR1_DS_2 0x00000080U 0234a8: line 6809 define SAI_xCR1_LSBFIRST 0x00000100U 0234c9: line 6810 define SAI_xCR1_CKSTR 0x00000200U 0234e7: line 6812 define SAI_xCR1_SYNCEN 0x00000C00U 023506: line 6813 define SAI_xCR1_SYNCEN_0 0x00000400U 023527: line 6814 define SAI_xCR1_SYNCEN_1 0x00000800U 023548: line 6816 define SAI_xCR1_MONO 0x00001000U 023565: line 6817 define SAI_xCR1_OUTDRIV 0x00002000U 023585: line 6818 define SAI_xCR1_SAIEN 0x00010000U 0235a3: line 6819 define SAI_xCR1_DMAEN 0x00020000U 0235c1: line 6820 define SAI_xCR1_NODIV 0x00080000U 0235df: line 6822 define SAI_xCR1_MCKDIV 0x00F00000U 0235fe: line 6823 define SAI_xCR1_MCKDIV_0 0x00100000U 02361f: line 6824 define SAI_xCR1_MCKDIV_1 0x00200000U 023640: line 6825 define SAI_xCR1_MCKDIV_2 0x00400000U 023661: line 6826 define SAI_xCR1_MCKDIV_3 0x00800000U 023682: line 6829 define SAI_xCR2_FTH 0x00000007U 02369e: line 6830 define SAI_xCR2_FTH_0 0x00000001U 0236bc: line 6831 define SAI_xCR2_FTH_1 0x00000002U 0236da: line 6832 define SAI_xCR2_FTH_2 0x00000004U 0236f8: line 6834 define SAI_xCR2_FFLUSH 0x00000008U 023717: line 6835 define SAI_xCR2_TRIS 0x00000010U 023734: line 6836 define SAI_xCR2_MUTE 0x00000020U 023751: line 6837 define SAI_xCR2_MUTEVAL 0x00000040U 023771: line 6839 define SAI_xCR2_MUTECNT 0x00001F80U 023791: line 6840 define SAI_xCR2_MUTECNT_0 0x00000080U 0237b3: line 6841 define SAI_xCR2_MUTECNT_1 0x00000100U 0237d5: line 6842 define SAI_xCR2_MUTECNT_2 0x00000200U 0237f7: line 6843 define SAI_xCR2_MUTECNT_3 0x00000400U 023819: line 6844 define SAI_xCR2_MUTECNT_4 0x00000800U 02383b: line 6845 define SAI_xCR2_MUTECNT_5 0x00001000U 02385d: line 6847 define SAI_xCR2_CPL 0x00002000U 023879: line 6849 define SAI_xCR2_COMP 0x0000C000U 023896: line 6850 define SAI_xCR2_COMP_0 0x00004000U 0238b5: line 6851 define SAI_xCR2_COMP_1 0x00008000U 0238d4: line 6854 define SAI_xFRCR_FRL 0x000000FFU 0238f1: line 6855 define SAI_xFRCR_FRL_0 0x00000001U 023910: line 6856 define SAI_xFRCR_FRL_1 0x00000002U 02392f: line 6857 define SAI_xFRCR_FRL_2 0x00000004U 02394e: line 6858 define SAI_xFRCR_FRL_3 0x00000008U 02396d: line 6859 define SAI_xFRCR_FRL_4 0x00000010U 02398c: line 6860 define SAI_xFRCR_FRL_5 0x00000020U 0239ab: line 6861 define SAI_xFRCR_FRL_6 0x00000040U 0239ca: line 6862 define SAI_xFRCR_FRL_7 0x00000080U 0239e9: line 6864 define SAI_xFRCR_FSALL 0x00007F00U 023a08: line 6865 define SAI_xFRCR_FSALL_0 0x00000100U 023a29: line 6866 define SAI_xFRCR_FSALL_1 0x00000200U 023a4a: line 6867 define SAI_xFRCR_FSALL_2 0x00000400U 023a6b: line 6868 define SAI_xFRCR_FSALL_3 0x00000800U 023a8c: line 6869 define SAI_xFRCR_FSALL_4 0x00001000U 023aad: line 6870 define SAI_xFRCR_FSALL_5 0x00002000U 023ace: line 6871 define SAI_xFRCR_FSALL_6 0x00004000U 023aef: line 6873 define SAI_xFRCR_FSDEF 0x00010000U 023b0e: line 6874 define SAI_xFRCR_FSPOL 0x00020000U 023b2d: line 6875 define SAI_xFRCR_FSOFF 0x00040000U 023b4c: line 6878 define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL 023b6e: line 6881 define SAI_xSLOTR_FBOFF 0x0000001FU 023b8e: line 6882 define SAI_xSLOTR_FBOFF_0 0x00000001U 023bb0: line 6883 define SAI_xSLOTR_FBOFF_1 0x00000002U 023bd2: line 6884 define SAI_xSLOTR_FBOFF_2 0x00000004U 023bf4: line 6885 define SAI_xSLOTR_FBOFF_3 0x00000008U 023c16: line 6886 define SAI_xSLOTR_FBOFF_4 0x00000010U 023c38: line 6888 define SAI_xSLOTR_SLOTSZ 0x000000C0U 023c59: line 6889 define SAI_xSLOTR_SLOTSZ_0 0x00000040U 023c7c: line 6890 define SAI_xSLOTR_SLOTSZ_1 0x00000080U 023c9f: line 6892 define SAI_xSLOTR_NBSLOT 0x00000F00U 023cc0: line 6893 define SAI_xSLOTR_NBSLOT_0 0x00000100U 023ce3: line 6894 define SAI_xSLOTR_NBSLOT_1 0x00000200U 023d06: line 6895 define SAI_xSLOTR_NBSLOT_2 0x00000400U 023d29: line 6896 define SAI_xSLOTR_NBSLOT_3 0x00000800U 023d4c: line 6898 define SAI_xSLOTR_SLOTEN 0xFFFF0000U 023d6d: line 6901 define SAI_xIMR_OVRUDRIE 0x00000001U 023d8e: line 6902 define SAI_xIMR_MUTEDETIE 0x00000002U 023db0: line 6903 define SAI_xIMR_WCKCFGIE 0x00000004U 023dd1: line 6904 define SAI_xIMR_FREQIE 0x00000008U 023df0: line 6905 define SAI_xIMR_CNRDYIE 0x00000010U 023e10: line 6906 define SAI_xIMR_AFSDETIE 0x00000020U 023e31: line 6907 define SAI_xIMR_LFSDETIE 0x00000040U 023e52: line 6910 define SAI_xSR_OVRUDR 0x00000001U 023e70: line 6911 define SAI_xSR_MUTEDET 0x00000002U 023e8f: line 6912 define SAI_xSR_WCKCFG 0x00000004U 023ead: line 6913 define SAI_xSR_FREQ 0x00000008U 023ec9: line 6914 define SAI_xSR_CNRDY 0x00000010U 023ee6: line 6915 define SAI_xSR_AFSDET 0x00000020U 023f04: line 6916 define SAI_xSR_LFSDET 0x00000040U 023f22: line 6918 define SAI_xSR_FLVL 0x00070000U 023f3e: line 6919 define SAI_xSR_FLVL_0 0x00010000U 023f5c: line 6920 define SAI_xSR_FLVL_1 0x00020000U 023f7a: line 6921 define SAI_xSR_FLVL_2 0x00040000U 023f98: line 6924 define SAI_xCLRFR_COVRUDR 0x00000001U 023fba: line 6925 define SAI_xCLRFR_CMUTEDET 0x00000002U 023fdd: line 6926 define SAI_xCLRFR_CWCKCFG 0x00000004U 023fff: line 6927 define SAI_xCLRFR_CFREQ 0x00000008U 02401f: line 6928 define SAI_xCLRFR_CCNRDY 0x00000010U 024040: line 6929 define SAI_xCLRFR_CAFSDET 0x00000020U 024062: line 6930 define SAI_xCLRFR_CLFSDET 0x00000040U 024084: line 6933 define SAI_xDR_DATA 0xFFFFFFFFU 0240a0: line 6941 define SPDIFRX_CR_SPDIFEN 0x00000003U 0240c2: line 6942 define SPDIFRX_CR_RXDMAEN 0x00000004U 0240e4: line 6943 define SPDIFRX_CR_RXSTEO 0x00000008U 024105: line 6944 define SPDIFRX_CR_DRFMT 0x00000030U 024125: line 6945 define SPDIFRX_CR_PMSK 0x00000040U 024144: line 6946 define SPDIFRX_CR_VMSK 0x00000080U 024163: line 6947 define SPDIFRX_CR_CUMSK 0x00000100U 024183: line 6948 define SPDIFRX_CR_PTMSK 0x00000200U 0241a3: line 6949 define SPDIFRX_CR_CBDMAEN 0x00000400U 0241c5: line 6950 define SPDIFRX_CR_CHSEL 0x00000800U 0241e5: line 6951 define SPDIFRX_CR_NBTR 0x00003000U 024204: line 6952 define SPDIFRX_CR_WFA 0x00004000U 024222: line 6953 define SPDIFRX_CR_INSEL 0x00070000U 024242: line 6956 define SPDIFRX_IMR_RXNEIE 0x00000001U 024264: line 6957 define SPDIFRX_IMR_CSRNEIE 0x00000002U 024287: line 6958 define SPDIFRX_IMR_PERRIE 0x00000004U 0242a9: line 6959 define SPDIFRX_IMR_OVRIE 0x00000008U 0242ca: line 6960 define SPDIFRX_IMR_SBLKIE 0x00000010U 0242ec: line 6961 define SPDIFRX_IMR_SYNCDIE 0x00000020U 02430f: line 6962 define SPDIFRX_IMR_IFEIE 0x00000040U 024330: line 6965 define SPDIFRX_SR_RXNE 0x00000001U 02434f: line 6966 define SPDIFRX_SR_CSRNE 0x00000002U 02436f: line 6967 define SPDIFRX_SR_PERR 0x00000004U 02438e: line 6968 define SPDIFRX_SR_OVR 0x00000008U 0243ac: line 6969 define SPDIFRX_SR_SBD 0x00000010U 0243ca: line 6970 define SPDIFRX_SR_SYNCD 0x00000020U 0243ea: line 6971 define SPDIFRX_SR_FERR 0x00000040U 024409: line 6972 define SPDIFRX_SR_SERR 0x00000080U 024428: line 6973 define SPDIFRX_SR_TERR 0x00000100U 024447: line 6974 define SPDIFRX_SR_WIDTH5 0x7FFF0000U 024468: line 6977 define SPDIFRX_IFCR_PERRCF 0x00000004U 02448b: line 6978 define SPDIFRX_IFCR_OVRCF 0x00000008U 0244ad: line 6979 define SPDIFRX_IFCR_SBDCF 0x00000010U 0244cf: line 6980 define SPDIFRX_IFCR_SYNCDCF 0x00000020U 0244f3: line 6983 define SPDIFRX_DR0_DR 0x00FFFFFFU 024511: line 6984 define SPDIFRX_DR0_PE 0x01000000U 02452f: line 6985 define SPDIFRX_DR0_V 0x02000000U 02454c: line 6986 define SPDIFRX_DR0_U 0x04000000U 024569: line 6987 define SPDIFRX_DR0_C 0x08000000U 024586: line 6988 define SPDIFRX_DR0_PT 0x30000000U 0245a4: line 6991 define SPDIFRX_DR1_DR 0xFFFFFF00U 0245c2: line 6992 define SPDIFRX_DR1_PT 0x00000030U 0245e0: line 6993 define SPDIFRX_DR1_C 0x00000008U 0245fd: line 6994 define SPDIFRX_DR1_U 0x00000004U 02461a: line 6995 define SPDIFRX_DR1_V 0x00000002U 024637: line 6996 define SPDIFRX_DR1_PE 0x00000001U 024655: line 6999 define SPDIFRX_DR1_DRNL1 0xFFFF0000U 024676: line 7000 define SPDIFRX_DR1_DRNL2 0x0000FFFFU 024697: line 7003 define SPDIFRX_CSR_USR 0x0000FFFFU 0246b6: line 7004 define SPDIFRX_CSR_CS 0x00FF0000U 0246d4: line 7005 define SPDIFRX_CSR_SOB 0x01000000U 0246f3: line 7008 define SPDIFRX_DIR_THI 0x000013FFU 024712: line 7009 define SPDIFRX_DIR_TLO 0x1FFF0000U 024731: line 7017 define SDMMC_POWER_PWRCTRL 0x03U 02474e: line 7018 define SDMMC_POWER_PWRCTRL_0 0x01U 02476d: line 7019 define SDMMC_POWER_PWRCTRL_1 0x02U 02478c: line 7022 define SDMMC_CLKCR_CLKDIV 0x00FFU 0247aa: line 7023 define SDMMC_CLKCR_CLKEN 0x0100U 0247c7: line 7024 define SDMMC_CLKCR_PWRSAV 0x0200U 0247e5: line 7025 define SDMMC_CLKCR_BYPASS 0x0400U 024803: line 7027 define SDMMC_CLKCR_WIDBUS 0x1800U 024821: line 7028 define SDMMC_CLKCR_WIDBUS_0 0x0800U 024841: line 7029 define SDMMC_CLKCR_WIDBUS_1 0x1000U 024861: line 7031 define SDMMC_CLKCR_NEGEDGE 0x2000U 024880: line 7032 define SDMMC_CLKCR_HWFC_EN 0x4000U 02489f: line 7035 define SDMMC_ARG_CMDARG 0xFFFFFFFFU 0248bf: line 7038 define SDMMC_CMD_CMDINDEX 0x003FU 0248dd: line 7040 define SDMMC_CMD_WAITRESP 0x00C0U 0248fb: line 7041 define SDMMC_CMD_WAITRESP_0 0x0040U 02491b: line 7042 define SDMMC_CMD_WAITRESP_1 0x0080U 02493b: line 7044 define SDMMC_CMD_WAITINT 0x0100U 024958: line 7045 define SDMMC_CMD_WAITPEND 0x0200U 024976: line 7046 define SDMMC_CMD_CPSMEN 0x0400U 024992: line 7047 define SDMMC_CMD_SDIOSUSPEND 0x0800U 0249b3: line 7050 define SDMMC_RESPCMD_RESPCMD 0x3FU 0249d2: line 7053 define SDMMC_RESP0_CARDSTATUS0 0xFFFFFFFFU 0249f9: line 7056 define SDMMC_RESP1_CARDSTATUS1 0xFFFFFFFFU 024a20: line 7059 define SDMMC_RESP2_CARDSTATUS2 0xFFFFFFFFU 024a47: line 7062 define SDMMC_RESP3_CARDSTATUS3 0xFFFFFFFFU 024a6e: line 7065 define SDMMC_RESP4_CARDSTATUS4 0xFFFFFFFFU 024a95: line 7068 define SDMMC_DTIMER_DATATIME 0xFFFFFFFFU 024aba: line 7071 define SDMMC_DLEN_DATALENGTH 0x01FFFFFFU 024adf: line 7074 define SDMMC_DCTRL_DTEN 0x0001U 024afb: line 7075 define SDMMC_DCTRL_DTDIR 0x0002U 024b18: line 7076 define SDMMC_DCTRL_DTMODE 0x0004U 024b36: line 7077 define SDMMC_DCTRL_DMAEN 0x0008U 024b53: line 7079 define SDMMC_DCTRL_DBLOCKSIZE 0x00F0U 024b75: line 7080 define SDMMC_DCTRL_DBLOCKSIZE_0 0x0010U 024b99: line 7081 define SDMMC_DCTRL_DBLOCKSIZE_1 0x0020U 024bbd: line 7082 define SDMMC_DCTRL_DBLOCKSIZE_2 0x0040U 024be1: line 7083 define SDMMC_DCTRL_DBLOCKSIZE_3 0x0080U 024c05: line 7085 define SDMMC_DCTRL_RWSTART 0x0100U 024c24: line 7086 define SDMMC_DCTRL_RWSTOP 0x0200U 024c42: line 7087 define SDMMC_DCTRL_RWMOD 0x0400U 024c5f: line 7088 define SDMMC_DCTRL_SDIOEN 0x0800U 024c7d: line 7091 define SDMMC_DCOUNT_DATACOUNT 0x01FFFFFFU 024ca3: line 7094 define SDMMC_STA_CCRCFAIL 0x00000001U 024cc5: line 7095 define SDMMC_STA_DCRCFAIL 0x00000002U 024ce7: line 7096 define SDMMC_STA_CTIMEOUT 0x00000004U 024d09: line 7097 define SDMMC_STA_DTIMEOUT 0x00000008U 024d2b: line 7098 define SDMMC_STA_TXUNDERR 0x00000010U 024d4d: line 7099 define SDMMC_STA_RXOVERR 0x00000020U 024d6e: line 7100 define SDMMC_STA_CMDREND 0x00000040U 024d8f: line 7101 define SDMMC_STA_CMDSENT 0x00000080U 024db0: line 7102 define SDMMC_STA_DATAEND 0x00000100U 024dd1: line 7103 define SDMMC_STA_DBCKEND 0x00000400U 024df2: line 7104 define SDMMC_STA_CMDACT 0x00000800U 024e12: line 7105 define SDMMC_STA_TXACT 0x00001000U 024e31: line 7106 define SDMMC_STA_RXACT 0x00002000U 024e50: line 7107 define SDMMC_STA_TXFIFOHE 0x00004000U 024e72: line 7108 define SDMMC_STA_RXFIFOHF 0x00008000U 024e94: line 7109 define SDMMC_STA_TXFIFOF 0x00010000U 024eb5: line 7110 define SDMMC_STA_RXFIFOF 0x00020000U 024ed6: line 7111 define SDMMC_STA_TXFIFOE 0x00040000U 024ef7: line 7112 define SDMMC_STA_RXFIFOE 0x00080000U 024f18: line 7113 define SDMMC_STA_TXDAVL 0x00100000U 024f38: line 7114 define SDMMC_STA_RXDAVL 0x00200000U 024f58: line 7115 define SDMMC_STA_SDIOIT 0x00400000U 024f78: line 7118 define SDMMC_ICR_CCRCFAILC 0x00000001U 024f9b: line 7119 define SDMMC_ICR_DCRCFAILC 0x00000002U 024fbe: line 7120 define SDMMC_ICR_CTIMEOUTC 0x00000004U 024fe1: line 7121 define SDMMC_ICR_DTIMEOUTC 0x00000008U 025004: line 7122 define SDMMC_ICR_TXUNDERRC 0x00000010U 025027: line 7123 define SDMMC_ICR_RXOVERRC 0x00000020U 025049: line 7124 define SDMMC_ICR_CMDRENDC 0x00000040U 02506b: line 7125 define SDMMC_ICR_CMDSENTC 0x00000080U 02508d: line 7126 define SDMMC_ICR_DATAENDC 0x00000100U 0250af: line 7127 define SDMMC_ICR_DBCKENDC 0x00000400U 0250d1: line 7128 define SDMMC_ICR_SDIOITC 0x00400000U 0250f2: line 7131 define SDMMC_MASK_CCRCFAILIE 0x00000001U 025117: line 7132 define SDMMC_MASK_DCRCFAILIE 0x00000002U 02513c: line 7133 define SDMMC_MASK_CTIMEOUTIE 0x00000004U 025161: line 7134 define SDMMC_MASK_DTIMEOUTIE 0x00000008U 025186: line 7135 define SDMMC_MASK_TXUNDERRIE 0x00000010U 0251ab: line 7136 define SDMMC_MASK_RXOVERRIE 0x00000020U 0251cf: line 7137 define SDMMC_MASK_CMDRENDIE 0x00000040U 0251f3: line 7138 define SDMMC_MASK_CMDSENTIE 0x00000080U 025217: line 7139 define SDMMC_MASK_DATAENDIE 0x00000100U 02523b: line 7140 define SDMMC_MASK_DBCKENDIE 0x00000400U 02525f: line 7141 define SDMMC_MASK_CMDACTIE 0x00000800U 025282: line 7142 define SDMMC_MASK_TXACTIE 0x00001000U 0252a4: line 7143 define SDMMC_MASK_RXACTIE 0x00002000U 0252c6: line 7144 define SDMMC_MASK_TXFIFOHEIE 0x00004000U 0252eb: line 7145 define SDMMC_MASK_RXFIFOHFIE 0x00008000U 025310: line 7146 define SDMMC_MASK_TXFIFOFIE 0x00010000U 025334: line 7147 define SDMMC_MASK_RXFIFOFIE 0x00020000U 025358: line 7148 define SDMMC_MASK_TXFIFOEIE 0x00040000U 02537c: line 7149 define SDMMC_MASK_RXFIFOEIE 0x00080000U 0253a0: line 7150 define SDMMC_MASK_TXDAVLIE 0x00100000U 0253c3: line 7151 define SDMMC_MASK_RXDAVLIE 0x00200000U 0253e6: line 7152 define SDMMC_MASK_SDIOITIE 0x00400000U 025409: line 7155 define SDMMC_FIFOCNT_FIFOCOUNT 0x00FFFFFFU 025430: line 7158 define SDMMC_FIFO_FIFODATA 0xFFFFFFFFU 025453: line 7166 define SPI_CR1_CPHA 0x00000001U 02546f: line 7167 define SPI_CR1_CPOL 0x00000002U 02548b: line 7168 define SPI_CR1_MSTR 0x00000004U 0254a7: line 7169 define SPI_CR1_BR 0x00000038U 0254c1: line 7170 define SPI_CR1_BR_0 0x00000008U 0254dd: line 7171 define SPI_CR1_BR_1 0x00000010U 0254f9: line 7172 define SPI_CR1_BR_2 0x00000020U 025515: line 7173 define SPI_CR1_SPE 0x00000040U 025530: line 7174 define SPI_CR1_LSBFIRST 0x00000080U 025550: line 7175 define SPI_CR1_SSI 0x00000100U 02556b: line 7176 define SPI_CR1_SSM 0x00000200U 025586: line 7177 define SPI_CR1_RXONLY 0x00000400U 0255a4: line 7178 define SPI_CR1_CRCL 0x00000800U 0255c0: line 7179 define SPI_CR1_CRCNEXT 0x00001000U 0255df: line 7180 define SPI_CR1_CRCEN 0x00002000U 0255fc: line 7181 define SPI_CR1_BIDIOE 0x00004000U 02561a: line 7182 define SPI_CR1_BIDIMODE 0x00008000U 02563a: line 7185 define SPI_CR2_RXDMAEN 0x00000001U 025659: line 7186 define SPI_CR2_TXDMAEN 0x00000002U 025678: line 7187 define SPI_CR2_SSOE 0x00000004U 025694: line 7188 define SPI_CR2_NSSP 0x00000008U 0256b0: line 7189 define SPI_CR2_FRF 0x00000010U 0256cb: line 7190 define SPI_CR2_ERRIE 0x00000020U 0256e8: line 7191 define SPI_CR2_RXNEIE 0x00000040U 025706: line 7192 define SPI_CR2_TXEIE 0x00000080U 025723: line 7193 define SPI_CR2_DS 0x00000F00U 02573d: line 7194 define SPI_CR2_DS_0 0x00000100U 025759: line 7195 define SPI_CR2_DS_1 0x00000200U 025775: line 7196 define SPI_CR2_DS_2 0x00000400U 025791: line 7197 define SPI_CR2_DS_3 0x00000800U 0257ad: line 7198 define SPI_CR2_FRXTH 0x00001000U 0257ca: line 7199 define SPI_CR2_LDMARX 0x00002000U 0257e8: line 7200 define SPI_CR2_LDMATX 0x00004000U 025806: line 7203 define SPI_SR_RXNE 0x00000001U 025821: line 7204 define SPI_SR_TXE 0x00000002U 02583b: line 7205 define SPI_SR_CHSIDE 0x00000004U 025858: line 7206 define SPI_SR_UDR 0x00000008U 025872: line 7207 define SPI_SR_CRCERR 0x00000010U 02588f: line 7208 define SPI_SR_MODF 0x00000020U 0258aa: line 7209 define SPI_SR_OVR 0x00000040U 0258c4: line 7210 define SPI_SR_BSY 0x00000080U 0258de: line 7211 define SPI_SR_FRE 0x00000100U 0258f8: line 7212 define SPI_SR_FRLVL 0x00000600U 025914: line 7213 define SPI_SR_FRLVL_0 0x00000200U 025932: line 7214 define SPI_SR_FRLVL_1 0x00000400U 025950: line 7215 define SPI_SR_FTLVL 0x00001800U 02596c: line 7216 define SPI_SR_FTLVL_0 0x00000800U 02598a: line 7217 define SPI_SR_FTLVL_1 0x00001000U 0259a8: line 7220 define SPI_DR_DR 0xFFFFU 0259bd: line 7223 define SPI_CRCPR_CRCPOLY 0xFFFFU 0259da: line 7226 define SPI_RXCRCR_RXCRC 0xFFFFU 0259f6: line 7229 define SPI_TXCRCR_TXCRC 0xFFFFU 025a12: line 7232 define SPI_I2SCFGR_CHLEN 0x00000001U 025a33: line 7233 define SPI_I2SCFGR_DATLEN 0x00000006U 025a55: line 7234 define SPI_I2SCFGR_DATLEN_0 0x00000002U 025a79: line 7235 define SPI_I2SCFGR_DATLEN_1 0x00000004U 025a9d: line 7236 define SPI_I2SCFGR_CKPOL 0x00000008U 025abe: line 7237 define SPI_I2SCFGR_I2SSTD 0x00000030U 025ae0: line 7238 define SPI_I2SCFGR_I2SSTD_0 0x00000010U 025b04: line 7239 define SPI_I2SCFGR_I2SSTD_1 0x00000020U 025b28: line 7240 define SPI_I2SCFGR_PCMSYNC 0x00000080U 025b4b: line 7241 define SPI_I2SCFGR_I2SCFG 0x00000300U 025b6d: line 7242 define SPI_I2SCFGR_I2SCFG_0 0x00000100U 025b91: line 7243 define SPI_I2SCFGR_I2SCFG_1 0x00000200U 025bb5: line 7244 define SPI_I2SCFGR_I2SE 0x00000400U 025bd5: line 7245 define SPI_I2SCFGR_I2SMOD 0x00000800U 025bf7: line 7246 define SPI_I2SCFGR_ASTRTEN 0x00001000U 025c1a: line 7249 define SPI_I2SPR_I2SDIV 0x00FFU 025c36: line 7250 define SPI_I2SPR_ODD 0x0100U 025c4f: line 7251 define SPI_I2SPR_MCKOE 0x0200U 025c6a: line 7260 define SYSCFG_MEMRMP_MEM_BOOT 0x00000001U 025c90: line 7262 define SYSCFG_MEMRMP_SWP_FB 0x00000100U 025cb4: line 7264 define SYSCFG_MEMRMP_SWP_FMC 0x00000C00U 025cd9: line 7265 define SYSCFG_MEMRMP_SWP_FMC_0 0x00000400U 025d00: line 7266 define SYSCFG_MEMRMP_SWP_FMC_1 0x00000800U 025d27: line 7269 define SYSCFG_PMC_I2C1_FMP 0x00000001U 025d4a: line 7270 define SYSCFG_PMC_I2C2_FMP 0x00000002U 025d6d: line 7271 define SYSCFG_PMC_I2C3_FMP 0x00000004U 025d90: line 7272 define SYSCFG_PMC_I2C4_FMP 0x00000008U 025db3: line 7273 define SYSCFG_PMC_I2C_PB6_FMP 0x00000010U 025dd9: line 7274 define SYSCFG_PMC_I2C_PB7_FMP 0x00000020U 025dff: line 7275 define SYSCFG_PMC_I2C_PB8_FMP 0x00000040U 025e25: line 7276 define SYSCFG_PMC_I2C_PB9_FMP 0x00000080U 025e4b: line 7278 define SYSCFG_PMC_ADCxDC2 0x00070000U 025e6d: line 7279 define SYSCFG_PMC_ADC1DC2 0x00010000U 025e8f: line 7280 define SYSCFG_PMC_ADC2DC2 0x00020000U 025eb1: line 7281 define SYSCFG_PMC_ADC3DC2 0x00040000U 025ed3: line 7283 define SYSCFG_PMC_MII_RMII_SEL 0x00800000U 025efa: line 7286 define SYSCFG_EXTICR1_EXTI0 0x000FU 025f1a: line 7287 define SYSCFG_EXTICR1_EXTI1 0x00F0U 025f3a: line 7288 define SYSCFG_EXTICR1_EXTI2 0x0F00U 025f5a: line 7289 define SYSCFG_EXTICR1_EXTI3 0xF000U 025f7a: line 7293 define SYSCFG_EXTICR1_EXTI0_PA 0x0000U 025f9d: line 7294 define SYSCFG_EXTICR1_EXTI0_PB 0x0001U 025fc0: line 7295 define SYSCFG_EXTICR1_EXTI0_PC 0x0002U 025fe3: line 7296 define SYSCFG_EXTICR1_EXTI0_PD 0x0003U 026006: line 7297 define SYSCFG_EXTICR1_EXTI0_PE 0x0004U 026029: line 7298 define SYSCFG_EXTICR1_EXTI0_PF 0x0005U 02604c: line 7299 define SYSCFG_EXTICR1_EXTI0_PG 0x0006U 02606f: line 7300 define SYSCFG_EXTICR1_EXTI0_PH 0x0007U 026092: line 7301 define SYSCFG_EXTICR1_EXTI0_PI 0x0008U 0260b5: line 7302 define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U 0260d8: line 7303 define SYSCFG_EXTICR1_EXTI0_PK 0x000AU 0260fb: line 7308 define SYSCFG_EXTICR1_EXTI1_PA 0x0000U 02611e: line 7309 define SYSCFG_EXTICR1_EXTI1_PB 0x0010U 026141: line 7310 define SYSCFG_EXTICR1_EXTI1_PC 0x0020U 026164: line 7311 define SYSCFG_EXTICR1_EXTI1_PD 0x0030U 026187: line 7312 define SYSCFG_EXTICR1_EXTI1_PE 0x0040U 0261aa: line 7313 define SYSCFG_EXTICR1_EXTI1_PF 0x0050U 0261cd: line 7314 define SYSCFG_EXTICR1_EXTI1_PG 0x0060U 0261f0: line 7315 define SYSCFG_EXTICR1_EXTI1_PH 0x0070U 026213: line 7316 define SYSCFG_EXTICR1_EXTI1_PI 0x0080U 026236: line 7317 define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U 026259: line 7318 define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U 02627c: line 7323 define SYSCFG_EXTICR1_EXTI2_PA 0x0000U 02629f: line 7324 define SYSCFG_EXTICR1_EXTI2_PB 0x0100U 0262c2: line 7325 define SYSCFG_EXTICR1_EXTI2_PC 0x0200U 0262e5: line 7326 define SYSCFG_EXTICR1_EXTI2_PD 0x0300U 026308: line 7327 define SYSCFG_EXTICR1_EXTI2_PE 0x0400U 02632b: line 7328 define SYSCFG_EXTICR1_EXTI2_PF 0x0500U 02634e: line 7329 define SYSCFG_EXTICR1_EXTI2_PG 0x0600U 026371: line 7330 define SYSCFG_EXTICR1_EXTI2_PH 0x0700U 026394: line 7331 define SYSCFG_EXTICR1_EXTI2_PI 0x0800U 0263b7: line 7332 define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U 0263da: line 7333 define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U 0263fd: line 7338 define SYSCFG_EXTICR1_EXTI3_PA 0x0000U 026420: line 7339 define SYSCFG_EXTICR1_EXTI3_PB 0x1000U 026443: line 7340 define SYSCFG_EXTICR1_EXTI3_PC 0x2000U 026466: line 7341 define SYSCFG_EXTICR1_EXTI3_PD 0x3000U 026489: line 7342 define SYSCFG_EXTICR1_EXTI3_PE 0x4000U 0264ac: line 7343 define SYSCFG_EXTICR1_EXTI3_PF 0x5000U 0264cf: line 7344 define SYSCFG_EXTICR1_EXTI3_PG 0x6000U 0264f2: line 7345 define SYSCFG_EXTICR1_EXTI3_PH 0x7000U 026515: line 7346 define SYSCFG_EXTICR1_EXTI3_PI 0x8000U 026538: line 7347 define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U 02655b: line 7348 define SYSCFG_EXTICR1_EXTI3_PK 0xA000U 02657e: line 7351 define SYSCFG_EXTICR2_EXTI4 0x000FU 02659e: line 7352 define SYSCFG_EXTICR2_EXTI5 0x00F0U 0265be: line 7353 define SYSCFG_EXTICR2_EXTI6 0x0F00U 0265de: line 7354 define SYSCFG_EXTICR2_EXTI7 0xF000U 0265fe: line 7358 define SYSCFG_EXTICR2_EXTI4_PA 0x0000U 026621: line 7359 define SYSCFG_EXTICR2_EXTI4_PB 0x0001U 026644: line 7360 define SYSCFG_EXTICR2_EXTI4_PC 0x0002U 026667: line 7361 define SYSCFG_EXTICR2_EXTI4_PD 0x0003U 02668a: line 7362 define SYSCFG_EXTICR2_EXTI4_PE 0x0004U 0266ad: line 7363 define SYSCFG_EXTICR2_EXTI4_PF 0x0005U 0266d0: line 7364 define SYSCFG_EXTICR2_EXTI4_PG 0x0006U 0266f3: line 7365 define SYSCFG_EXTICR2_EXTI4_PH 0x0007U 026716: line 7366 define SYSCFG_EXTICR2_EXTI4_PI 0x0008U 026739: line 7367 define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U 02675c: line 7368 define SYSCFG_EXTICR2_EXTI4_PK 0x000AU 02677f: line 7373 define SYSCFG_EXTICR2_EXTI5_PA 0x0000U 0267a2: line 7374 define SYSCFG_EXTICR2_EXTI5_PB 0x0010U 0267c5: line 7375 define SYSCFG_EXTICR2_EXTI5_PC 0x0020U 0267e8: line 7376 define SYSCFG_EXTICR2_EXTI5_PD 0x0030U 02680b: line 7377 define SYSCFG_EXTICR2_EXTI5_PE 0x0040U 02682e: line 7378 define SYSCFG_EXTICR2_EXTI5_PF 0x0050U 026851: line 7379 define SYSCFG_EXTICR2_EXTI5_PG 0x0060U 026874: line 7380 define SYSCFG_EXTICR2_EXTI5_PH 0x0070U 026897: line 7381 define SYSCFG_EXTICR2_EXTI5_PI 0x0080U 0268ba: line 7382 define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U 0268dd: line 7383 define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U 026900: line 7388 define SYSCFG_EXTICR2_EXTI6_PA 0x0000U 026923: line 7389 define SYSCFG_EXTICR2_EXTI6_PB 0x0100U 026946: line 7390 define SYSCFG_EXTICR2_EXTI6_PC 0x0200U 026969: line 7391 define SYSCFG_EXTICR2_EXTI6_PD 0x0300U 02698c: line 7392 define SYSCFG_EXTICR2_EXTI6_PE 0x0400U 0269af: line 7393 define SYSCFG_EXTICR2_EXTI6_PF 0x0500U 0269d2: line 7394 define SYSCFG_EXTICR2_EXTI6_PG 0x0600U 0269f5: line 7395 define SYSCFG_EXTICR2_EXTI6_PH 0x0700U 026a18: line 7396 define SYSCFG_EXTICR2_EXTI6_PI 0x0800U 026a3b: line 7397 define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U 026a5e: line 7398 define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U 026a81: line 7403 define SYSCFG_EXTICR2_EXTI7_PA 0x0000U 026aa4: line 7404 define SYSCFG_EXTICR2_EXTI7_PB 0x1000U 026ac7: line 7405 define SYSCFG_EXTICR2_EXTI7_PC 0x2000U 026aea: line 7406 define SYSCFG_EXTICR2_EXTI7_PD 0x3000U 026b0d: line 7407 define SYSCFG_EXTICR2_EXTI7_PE 0x4000U 026b30: line 7408 define SYSCFG_EXTICR2_EXTI7_PF 0x5000U 026b53: line 7409 define SYSCFG_EXTICR2_EXTI7_PG 0x6000U 026b76: line 7410 define SYSCFG_EXTICR2_EXTI7_PH 0x7000U 026b99: line 7411 define SYSCFG_EXTICR2_EXTI7_PI 0x8000U 026bbc: line 7412 define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U 026bdf: line 7413 define SYSCFG_EXTICR2_EXTI7_PK 0xA000U 026c02: line 7416 define SYSCFG_EXTICR3_EXTI8 0x000FU 026c22: line 7417 define SYSCFG_EXTICR3_EXTI9 0x00F0U 026c42: line 7418 define SYSCFG_EXTICR3_EXTI10 0x0F00U 026c63: line 7419 define SYSCFG_EXTICR3_EXTI11 0xF000U 026c84: line 7424 define SYSCFG_EXTICR3_EXTI8_PA 0x0000U 026ca7: line 7425 define SYSCFG_EXTICR3_EXTI8_PB 0x0001U 026cca: line 7426 define SYSCFG_EXTICR3_EXTI8_PC 0x0002U 026ced: line 7427 define SYSCFG_EXTICR3_EXTI8_PD 0x0003U 026d10: line 7428 define SYSCFG_EXTICR3_EXTI8_PE 0x0004U 026d33: line 7429 define SYSCFG_EXTICR3_EXTI8_PF 0x0005U 026d56: line 7430 define SYSCFG_EXTICR3_EXTI8_PG 0x0006U 026d79: line 7431 define SYSCFG_EXTICR3_EXTI8_PH 0x0007U 026d9c: line 7432 define SYSCFG_EXTICR3_EXTI8_PI 0x0008U 026dbf: line 7433 define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U 026de2: line 7438 define SYSCFG_EXTICR3_EXTI9_PA 0x0000U 026e05: line 7439 define SYSCFG_EXTICR3_EXTI9_PB 0x0010U 026e28: line 7440 define SYSCFG_EXTICR3_EXTI9_PC 0x0020U 026e4b: line 7441 define SYSCFG_EXTICR3_EXTI9_PD 0x0030U 026e6e: line 7442 define SYSCFG_EXTICR3_EXTI9_PE 0x0040U 026e91: line 7443 define SYSCFG_EXTICR3_EXTI9_PF 0x0050U 026eb4: line 7444 define SYSCFG_EXTICR3_EXTI9_PG 0x0060U 026ed7: line 7445 define SYSCFG_EXTICR3_EXTI9_PH 0x0070U 026efa: line 7446 define SYSCFG_EXTICR3_EXTI9_PI 0x0080U 026f1d: line 7447 define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U 026f40: line 7452 define SYSCFG_EXTICR3_EXTI10_PA 0x0000U 026f64: line 7453 define SYSCFG_EXTICR3_EXTI10_PB 0x0100U 026f88: line 7454 define SYSCFG_EXTICR3_EXTI10_PC 0x0200U 026fac: line 7455 define SYSCFG_EXTICR3_EXTI10_PD 0x0300U 026fd0: line 7456 define SYSCFG_EXTICR3_EXTI10_PE 0x0400U 026ff4: line 7457 define SYSCFG_EXTICR3_EXTI10_PF 0x0500U 027018: line 7458 define SYSCFG_EXTICR3_EXTI10_PG 0x0600U 02703c: line 7459 define SYSCFG_EXTICR3_EXTI10_PH 0x0700U 027060: line 7460 define SYSCFG_EXTICR3_EXTI10_PI 0x0800U 027084: line 7461 define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U 0270a8: line 7466 define SYSCFG_EXTICR3_EXTI11_PA 0x0000U 0270cc: line 7467 define SYSCFG_EXTICR3_EXTI11_PB 0x1000U 0270f0: line 7468 define SYSCFG_EXTICR3_EXTI11_PC 0x2000U 027114: line 7469 define SYSCFG_EXTICR3_EXTI11_PD 0x3000U 027138: line 7470 define SYSCFG_EXTICR3_EXTI11_PE 0x4000U 02715c: line 7471 define SYSCFG_EXTICR3_EXTI11_PF 0x5000U 027180: line 7472 define SYSCFG_EXTICR3_EXTI11_PG 0x6000U 0271a4: line 7473 define SYSCFG_EXTICR3_EXTI11_PH 0x7000U 0271c8: line 7474 define SYSCFG_EXTICR3_EXTI11_PI 0x8000U 0271ec: line 7475 define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U 027210: line 7479 define SYSCFG_EXTICR4_EXTI12 0x000FU 027231: line 7480 define SYSCFG_EXTICR4_EXTI13 0x00F0U 027252: line 7481 define SYSCFG_EXTICR4_EXTI14 0x0F00U 027273: line 7482 define SYSCFG_EXTICR4_EXTI15 0xF000U 027294: line 7486 define SYSCFG_EXTICR4_EXTI12_PA 0x0000U 0272b8: line 7487 define SYSCFG_EXTICR4_EXTI12_PB 0x0001U 0272dc: line 7488 define SYSCFG_EXTICR4_EXTI12_PC 0x0002U 027300: line 7489 define SYSCFG_EXTICR4_EXTI12_PD 0x0003U 027324: line 7490 define SYSCFG_EXTICR4_EXTI12_PE 0x0004U 027348: line 7491 define SYSCFG_EXTICR4_EXTI12_PF 0x0005U 02736c: line 7492 define SYSCFG_EXTICR4_EXTI12_PG 0x0006U 027390: line 7493 define SYSCFG_EXTICR4_EXTI12_PH 0x0007U 0273b4: line 7494 define SYSCFG_EXTICR4_EXTI12_PI 0x0008U 0273d8: line 7495 define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U 0273fc: line 7500 define SYSCFG_EXTICR4_EXTI13_PA 0x0000U 027420: line 7501 define SYSCFG_EXTICR4_EXTI13_PB 0x0010U 027444: line 7502 define SYSCFG_EXTICR4_EXTI13_PC 0x0020U 027468: line 7503 define SYSCFG_EXTICR4_EXTI13_PD 0x0030U 02748c: line 7504 define SYSCFG_EXTICR4_EXTI13_PE 0x0040U 0274b0: line 7505 define SYSCFG_EXTICR4_EXTI13_PF 0x0050U 0274d4: line 7506 define SYSCFG_EXTICR4_EXTI13_PG 0x0060U 0274f8: line 7507 define SYSCFG_EXTICR4_EXTI13_PH 0x0070U 02751c: line 7508 define SYSCFG_EXTICR4_EXTI13_PI 0x0080U 027540: line 7509 define SYSCFG_EXTICR4_EXTI13_PJ 0x0090U 027564: line 7514 define SYSCFG_EXTICR4_EXTI14_PA 0x0000U 027588: line 7515 define SYSCFG_EXTICR4_EXTI14_PB 0x0100U 0275ac: line 7516 define SYSCFG_EXTICR4_EXTI14_PC 0x0200U 0275d0: line 7517 define SYSCFG_EXTICR4_EXTI14_PD 0x0300U 0275f4: line 7518 define SYSCFG_EXTICR4_EXTI14_PE 0x0400U 027618: line 7519 define SYSCFG_EXTICR4_EXTI14_PF 0x0500U 02763c: line 7520 define SYSCFG_EXTICR4_EXTI14_PG 0x0600U 027660: line 7521 define SYSCFG_EXTICR4_EXTI14_PH 0x0700U 027684: line 7522 define SYSCFG_EXTICR4_EXTI14_PI 0x0800U 0276a8: line 7523 define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U 0276cc: line 7528 define SYSCFG_EXTICR4_EXTI15_PA 0x0000U 0276f0: line 7529 define SYSCFG_EXTICR4_EXTI15_PB 0x1000U 027714: line 7530 define SYSCFG_EXTICR4_EXTI15_PC 0x2000U 027738: line 7531 define SYSCFG_EXTICR4_EXTI15_PD 0x3000U 02775c: line 7532 define SYSCFG_EXTICR4_EXTI15_PE 0x4000U 027780: line 7533 define SYSCFG_EXTICR4_EXTI15_PF 0x5000U 0277a4: line 7534 define SYSCFG_EXTICR4_EXTI15_PG 0x6000U 0277c8: line 7535 define SYSCFG_EXTICR4_EXTI15_PH 0x7000U 0277ec: line 7536 define SYSCFG_EXTICR4_EXTI15_PI 0x8000U 027810: line 7537 define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U 027834: line 7540 define SYSCFG_CBR_CLL 0x00000001U 027852: line 7541 define SYSCFG_CBR_PVDL 0x00000004U 027871: line 7544 define SYSCFG_CMPCR_CMP_PD 0x00000001U 027894: line 7545 define SYSCFG_CMPCR_READY 0x00000100U 0278b6: line 7553 define TIM_CR1_CEN 0x0001U 0278cd: line 7554 define TIM_CR1_UDIS 0x0002U 0278e5: line 7555 define TIM_CR1_URS 0x0004U 0278fc: line 7556 define TIM_CR1_OPM 0x0008U 027913: line 7557 define TIM_CR1_DIR 0x0010U 02792a: line 7559 define TIM_CR1_CMS 0x0060U 027941: line 7560 define TIM_CR1_CMS_0 0x0020U 02795a: line 7561 define TIM_CR1_CMS_1 0x0040U 027973: line 7563 define TIM_CR1_ARPE 0x0080U 02798b: line 7565 define TIM_CR1_CKD 0x0300U 0279a2: line 7566 define TIM_CR1_CKD_0 0x0100U 0279bb: line 7567 define TIM_CR1_CKD_1 0x0200U 0279d4: line 7568 define TIM_CR1_UIFREMAP 0x0800U 0279f0: line 7571 define TIM_CR2_CCPC 0x00000001U 027a0c: line 7572 define TIM_CR2_CCUS 0x00000004U 027a28: line 7573 define TIM_CR2_CCDS 0x00000008U 027a44: line 7575 define TIM_CR2_OIS5 0x00010000U 027a60: line 7576 define TIM_CR2_OIS6 0x00040000U 027a7c: line 7578 define TIM_CR2_MMS 0x0070U 027a93: line 7579 define TIM_CR2_MMS_0 0x0010U 027aac: line 7580 define TIM_CR2_MMS_1 0x0020U 027ac5: line 7581 define TIM_CR2_MMS_2 0x0040U 027ade: line 7583 define TIM_CR2_MMS2 0x00F00000U 027afa: line 7584 define TIM_CR2_MMS2_0 0x00100000U 027b18: line 7585 define TIM_CR2_MMS2_1 0x00200000U 027b36: line 7586 define TIM_CR2_MMS2_2 0x00400000U 027b54: line 7587 define TIM_CR2_MMS2_3 0x00800000U 027b72: line 7589 define TIM_CR2_TI1S 0x0080U 027b8a: line 7590 define TIM_CR2_OIS1 0x0100U 027ba2: line 7591 define TIM_CR2_OIS1N 0x0200U 027bbb: line 7592 define TIM_CR2_OIS2 0x0400U 027bd3: line 7593 define TIM_CR2_OIS2N 0x0800U 027bec: line 7594 define TIM_CR2_OIS3 0x1000U 027c04: line 7595 define TIM_CR2_OIS3N 0x2000U 027c1d: line 7596 define TIM_CR2_OIS4 0x4000U 027c35: line 7599 define TIM_SMCR_SMS 0x00010007U 027c51: line 7600 define TIM_SMCR_SMS_0 0x00000001U 027c6f: line 7601 define TIM_SMCR_SMS_1 0x00000002U 027c8d: line 7602 define TIM_SMCR_SMS_2 0x00000004U 027cab: line 7603 define TIM_SMCR_SMS_3 0x00010000U 027cc9: line 7604 define TIM_SMCR_OCCS 0x00000008U 027ce6: line 7606 define TIM_SMCR_TS 0x0070U 027cfd: line 7607 define TIM_SMCR_TS_0 0x0010U 027d16: line 7608 define TIM_SMCR_TS_1 0x0020U 027d2f: line 7609 define TIM_SMCR_TS_2 0x0040U 027d48: line 7611 define TIM_SMCR_MSM 0x0080U 027d60: line 7613 define TIM_SMCR_ETF 0x0F00U 027d78: line 7614 define TIM_SMCR_ETF_0 0x0100U 027d92: line 7615 define TIM_SMCR_ETF_1 0x0200U 027dac: line 7616 define TIM_SMCR_ETF_2 0x0400U 027dc6: line 7617 define TIM_SMCR_ETF_3 0x0800U 027de0: line 7619 define TIM_SMCR_ETPS 0x3000U 027df9: line 7620 define TIM_SMCR_ETPS_0 0x1000U 027e14: line 7621 define TIM_SMCR_ETPS_1 0x2000U 027e2f: line 7623 define TIM_SMCR_ECE 0x4000U 027e47: line 7624 define TIM_SMCR_ETP 0x8000U 027e5f: line 7627 define TIM_DIER_UIE 0x0001U 027e77: line 7628 define TIM_DIER_CC1IE 0x0002U 027e91: line 7629 define TIM_DIER_CC2IE 0x0004U 027eab: line 7630 define TIM_DIER_CC3IE 0x0008U 027ec5: line 7631 define TIM_DIER_CC4IE 0x0010U 027edf: line 7632 define TIM_DIER_COMIE 0x0020U 027ef9: line 7633 define TIM_DIER_TIE 0x0040U 027f11: line 7634 define TIM_DIER_BIE 0x0080U 027f29: line 7635 define TIM_DIER_UDE 0x0100U 027f41: line 7636 define TIM_DIER_CC1DE 0x0200U 027f5b: line 7637 define TIM_DIER_CC2DE 0x0400U 027f75: line 7638 define TIM_DIER_CC3DE 0x0800U 027f8f: line 7639 define TIM_DIER_CC4DE 0x1000U 027fa9: line 7640 define TIM_DIER_COMDE 0x2000U 027fc3: line 7641 define TIM_DIER_TDE 0x4000U 027fdb: line 7644 define TIM_SR_UIF 0x0001U 027ff1: line 7645 define TIM_SR_CC1IF 0x0002U 028009: line 7646 define TIM_SR_CC2IF 0x0004U 028021: line 7647 define TIM_SR_CC3IF 0x0008U 028039: line 7648 define TIM_SR_CC4IF 0x0010U 028051: line 7649 define TIM_SR_COMIF 0x0020U 028069: line 7650 define TIM_SR_TIF 0x0040U 02807f: line 7651 define TIM_SR_BIF 0x0080U 028095: line 7652 define TIM_SR_B2IF 0x0100U 0280ac: line 7653 define TIM_SR_CC1OF 0x0200U 0280c4: line 7654 define TIM_SR_CC2OF 0x0400U 0280dc: line 7655 define TIM_SR_CC3OF 0x0800U 0280f4: line 7656 define TIM_SR_CC4OF 0x1000U 02810c: line 7659 define TIM_EGR_UG 0x00000001U 028126: line 7660 define TIM_EGR_CC1G 0x00000002U 028142: line 7661 define TIM_EGR_CC2G 0x00000004U 02815e: line 7662 define TIM_EGR_CC3G 0x00000008U 02817a: line 7663 define TIM_EGR_CC4G 0x00000010U 028196: line 7664 define TIM_EGR_COMG 0x00000020U 0281b2: line 7665 define TIM_EGR_TG 0x00000040U 0281cc: line 7666 define TIM_EGR_BG 0x00000080U 0281e6: line 7667 define TIM_EGR_B2G 0x00000100U 028201: line 7670 define TIM_CCMR1_CC1S 0x00000003U 02821f: line 7671 define TIM_CCMR1_CC1S_0 0x00000001U 02823f: line 7672 define TIM_CCMR1_CC1S_1 0x00000002U 02825f: line 7674 define TIM_CCMR1_OC1FE 0x00000004U 02827e: line 7675 define TIM_CCMR1_OC1PE 0x00000008U 02829d: line 7677 define TIM_CCMR1_OC1M 0x00010070U 0282bb: line 7678 define TIM_CCMR1_OC1M_0 0x00000010U 0282db: line 7679 define TIM_CCMR1_OC1M_1 0x00000020U 0282fb: line 7680 define TIM_CCMR1_OC1M_2 0x00000040U 02831b: line 7681 define TIM_CCMR1_OC1M_3 0x00010000U 02833b: line 7683 define TIM_CCMR1_OC1CE 0x00000080U 02835a: line 7685 define TIM_CCMR1_CC2S 0x00000300U 028378: line 7686 define TIM_CCMR1_CC2S_0 0x00000100U 028398: line 7687 define TIM_CCMR1_CC2S_1 0x00000200U 0283b8: line 7689 define TIM_CCMR1_OC2FE 0x00000400U 0283d7: line 7690 define TIM_CCMR1_OC2PE 0x00000800U 0283f6: line 7692 define TIM_CCMR1_OC2M 0x01007000U 028414: line 7693 define TIM_CCMR1_OC2M_0 0x00001000U 028434: line 7694 define TIM_CCMR1_OC2M_1 0x00002000U 028454: line 7695 define TIM_CCMR1_OC2M_2 0x00004000U 028474: line 7696 define TIM_CCMR1_OC2M_3 0x01000000U 028494: line 7698 define TIM_CCMR1_OC2CE 0x00008000U 0284b3: line 7702 define TIM_CCMR1_IC1PSC 0x000CU 0284cf: line 7703 define TIM_CCMR1_IC1PSC_0 0x0004U 0284ed: line 7704 define TIM_CCMR1_IC1PSC_1 0x0008U 02850b: line 7706 define TIM_CCMR1_IC1F 0x00F0U 028525: line 7707 define TIM_CCMR1_IC1F_0 0x0010U 028541: line 7708 define TIM_CCMR1_IC1F_1 0x0020U 02855d: line 7709 define TIM_CCMR1_IC1F_2 0x0040U 028579: line 7710 define TIM_CCMR1_IC1F_3 0x0080U 028595: line 7712 define TIM_CCMR1_IC2PSC 0x0C00U 0285b1: line 7713 define TIM_CCMR1_IC2PSC_0 0x0400U 0285cf: line 7714 define TIM_CCMR1_IC2PSC_1 0x0800U 0285ed: line 7716 define TIM_CCMR1_IC2F 0xF000U 028607: line 7717 define TIM_CCMR1_IC2F_0 0x1000U 028623: line 7718 define TIM_CCMR1_IC2F_1 0x2000U 02863f: line 7719 define TIM_CCMR1_IC2F_2 0x4000U 02865b: line 7720 define TIM_CCMR1_IC2F_3 0x8000U 028677: line 7723 define TIM_CCMR2_CC3S 0x00000003U 028695: line 7724 define TIM_CCMR2_CC3S_0 0x00000001U 0286b5: line 7725 define TIM_CCMR2_CC3S_1 0x00000002U 0286d5: line 7727 define TIM_CCMR2_OC3FE 0x00000004U 0286f4: line 7728 define TIM_CCMR2_OC3PE 0x00000008U 028713: line 7730 define TIM_CCMR2_OC3M 0x00010070U 028731: line 7731 define TIM_CCMR2_OC3M_0 0x00000010U 028751: line 7732 define TIM_CCMR2_OC3M_1 0x00000020U 028771: line 7733 define TIM_CCMR2_OC3M_2 0x00000040U 028791: line 7734 define TIM_CCMR2_OC3M_3 0x00010000U 0287b1: line 7738 define TIM_CCMR2_OC3CE 0x00000080U 0287d0: line 7740 define TIM_CCMR2_CC4S 0x00000300U 0287ee: line 7741 define TIM_CCMR2_CC4S_0 0x00000100U 02880e: line 7742 define TIM_CCMR2_CC4S_1 0x00000200U 02882e: line 7744 define TIM_CCMR2_OC4FE 0x00000400U 02884d: line 7745 define TIM_CCMR2_OC4PE 0x00000800U 02886c: line 7747 define TIM_CCMR2_OC4M 0x01007000U 02888a: line 7748 define TIM_CCMR2_OC4M_0 0x00001000U 0288aa: line 7749 define TIM_CCMR2_OC4M_1 0x00002000U 0288ca: line 7750 define TIM_CCMR2_OC4M_2 0x00004000U 0288ea: line 7751 define TIM_CCMR2_OC4M_3 0x01000000U 02890a: line 7753 define TIM_CCMR2_OC4CE 0x8000U 028925: line 7757 define TIM_CCMR2_IC3PSC 0x000CU 028941: line 7758 define TIM_CCMR2_IC3PSC_0 0x0004U 02895f: line 7759 define TIM_CCMR2_IC3PSC_1 0x0008U 02897d: line 7761 define TIM_CCMR2_IC3F 0x00F0U 028997: line 7762 define TIM_CCMR2_IC3F_0 0x0010U 0289b3: line 7763 define TIM_CCMR2_IC3F_1 0x0020U 0289cf: line 7764 define TIM_CCMR2_IC3F_2 0x0040U 0289eb: line 7765 define TIM_CCMR2_IC3F_3 0x0080U 028a07: line 7767 define TIM_CCMR2_IC4PSC 0x0C00U 028a23: line 7768 define TIM_CCMR2_IC4PSC_0 0x0400U 028a41: line 7769 define TIM_CCMR2_IC4PSC_1 0x0800U 028a5f: line 7771 define TIM_CCMR2_IC4F 0xF000U 028a79: line 7772 define TIM_CCMR2_IC4F_0 0x1000U 028a95: line 7773 define TIM_CCMR2_IC4F_1 0x2000U 028ab1: line 7774 define TIM_CCMR2_IC4F_2 0x4000U 028acd: line 7775 define TIM_CCMR2_IC4F_3 0x8000U 028ae9: line 7778 define TIM_CCER_CC1E 0x00000001U 028b06: line 7779 define TIM_CCER_CC1P 0x00000002U 028b23: line 7780 define TIM_CCER_CC1NE 0x00000004U 028b41: line 7781 define TIM_CCER_CC1NP 0x00000008U 028b5f: line 7782 define TIM_CCER_CC2E 0x00000010U 028b7c: line 7783 define TIM_CCER_CC2P 0x00000020U 028b99: line 7784 define TIM_CCER_CC2NE 0x00000040U 028bb7: line 7785 define TIM_CCER_CC2NP 0x00000080U 028bd5: line 7786 define TIM_CCER_CC3E 0x00000100U 028bf2: line 7787 define TIM_CCER_CC3P 0x00000200U 028c0f: line 7788 define TIM_CCER_CC3NE 0x00000400U 028c2d: line 7789 define TIM_CCER_CC3NP 0x00000800U 028c4b: line 7790 define TIM_CCER_CC4E 0x00001000U 028c68: line 7791 define TIM_CCER_CC4P 0x00002000U 028c85: line 7792 define TIM_CCER_CC4NP 0x00008000U 028ca3: line 7793 define TIM_CCER_CC5E 0x00010000U 028cc0: line 7794 define TIM_CCER_CC5P 0x00020000U 028cdd: line 7795 define TIM_CCER_CC6E 0x00100000U 028cfa: line 7796 define TIM_CCER_CC6P 0x00200000U 028d17: line 7800 define TIM_CNT_CNT 0xFFFFU 028d2e: line 7803 define TIM_PSC_PSC 0xFFFFU 028d45: line 7806 define TIM_ARR_ARR 0xFFFFU 028d5c: line 7809 define TIM_RCR_REP ((uint8_t)0xFFU) 028d7c: line 7812 define TIM_CCR1_CCR1 0xFFFFU 028d95: line 7815 define TIM_CCR2_CCR2 0xFFFFU 028dae: line 7818 define TIM_CCR3_CCR3 0xFFFFU 028dc7: line 7821 define TIM_CCR4_CCR4 0xFFFFU 028de0: line 7824 define TIM_BDTR_DTG 0x000000FFU 028dfc: line 7825 define TIM_BDTR_DTG_0 0x00000001U 028e1a: line 7826 define TIM_BDTR_DTG_1 0x00000002U 028e38: line 7827 define TIM_BDTR_DTG_2 0x00000004U 028e56: line 7828 define TIM_BDTR_DTG_3 0x00000008U 028e74: line 7829 define TIM_BDTR_DTG_4 0x00000010U 028e92: line 7830 define TIM_BDTR_DTG_5 0x00000020U 028eb0: line 7831 define TIM_BDTR_DTG_6 0x00000040U 028ece: line 7832 define TIM_BDTR_DTG_7 0x00000080U 028eec: line 7834 define TIM_BDTR_LOCK 0x00000300U 028f09: line 7835 define TIM_BDTR_LOCK_0 0x00000100U 028f28: line 7836 define TIM_BDTR_LOCK_1 0x00000200U 028f47: line 7838 define TIM_BDTR_OSSI 0x00000400U 028f64: line 7839 define TIM_BDTR_OSSR 0x00000800U 028f81: line 7840 define TIM_BDTR_BKE 0x00001000U 028f9d: line 7841 define TIM_BDTR_BKP 0x00002000U 028fb9: line 7842 define TIM_BDTR_AOE 0x00004000U 028fd5: line 7843 define TIM_BDTR_MOE 0x00008000U 028ff1: line 7844 define TIM_BDTR_BKF 0x000F0000U 02900d: line 7845 define TIM_BDTR_BK2F 0x00F00000U 02902a: line 7846 define TIM_BDTR_BK2E 0x01000000U 029047: line 7847 define TIM_BDTR_BK2P 0x02000000U 029064: line 7850 define TIM_DCR_DBA 0x001FU 02907b: line 7851 define TIM_DCR_DBA_0 0x0001U 029094: line 7852 define TIM_DCR_DBA_1 0x0002U 0290ad: line 7853 define TIM_DCR_DBA_2 0x0004U 0290c6: line 7854 define TIM_DCR_DBA_3 0x0008U 0290df: line 7855 define TIM_DCR_DBA_4 0x0010U 0290f8: line 7857 define TIM_DCR_DBL 0x1F00U 02910f: line 7858 define TIM_DCR_DBL_0 0x0100U 029128: line 7859 define TIM_DCR_DBL_1 0x0200U 029141: line 7860 define TIM_DCR_DBL_2 0x0400U 02915a: line 7861 define TIM_DCR_DBL_3 0x0800U 029173: line 7862 define TIM_DCR_DBL_4 0x1000U 02918c: line 7865 define TIM_DMAR_DMAB 0xFFFFU 0291a5: line 7868 define TIM_OR_TI4_RMP 0x00C0U 0291bf: line 7869 define TIM_OR_TI4_RMP_0 0x0040U 0291db: line 7870 define TIM_OR_TI4_RMP_1 0x0080U 0291f7: line 7871 define TIM_OR_ITR1_RMP 0x0C00U 029212: line 7872 define TIM_OR_ITR1_RMP_0 0x0400U 02922f: line 7873 define TIM_OR_ITR1_RMP_1 0x0800U 02924c: line 7876 define TIM_CCMR3_OC5FE 0x00000004U 02926b: line 7877 define TIM_CCMR3_OC5PE 0x00000008U 02928a: line 7879 define TIM_CCMR3_OC5M 0x00010070U 0292a8: line 7880 define TIM_CCMR3_OC5M_0 0x00000010U 0292c8: line 7881 define TIM_CCMR3_OC5M_1 0x00000020U 0292e8: line 7882 define TIM_CCMR3_OC5M_2 0x00000040U 029308: line 7883 define TIM_CCMR3_OC5M_3 0x00010000U 029328: line 7885 define TIM_CCMR3_OC5CE 0x00000080U 029347: line 7887 define TIM_CCMR3_OC6FE 0x00000400U 029366: line 7888 define TIM_CCMR3_OC6PE 0x00000800U 029385: line 7890 define TIM_CCMR3_OC6M 0x01007000U 0293a3: line 7891 define TIM_CCMR3_OC6M_0 0x00001000U 0293c3: line 7892 define TIM_CCMR3_OC6M_1 0x00002000U 0293e3: line 7893 define TIM_CCMR3_OC6M_2 0x00004000U 029403: line 7894 define TIM_CCMR3_OC6M_3 0x01000000U 029423: line 7896 define TIM_CCMR3_OC6CE 0x00008000U 029442: line 7899 define TIM_CCR5_CCR5 0xFFFFFFFFU 02945f: line 7900 define TIM_CCR5_GC5C1 0x20000000U 02947d: line 7901 define TIM_CCR5_GC5C2 0x40000000U 02949b: line 7902 define TIM_CCR5_GC5C3 0x80000000U 0294b9: line 7905 define TIM_CCR6_CCR6 ((uint16_t)0xFFFFU) 0294de: line 7908 define TIM1_AF1_BKINE 0x00000001U 0294fc: line 7909 define TIM1_AF1_BKDF1BKE 0x00000100U 02951d: line 7912 define TIM1_AF2_BK2INE 0x00000001U 02953c: line 7913 define TIM1_AF2_BK2DF1BKE 0x00000100U 02955e: line 7916 define TIM8_AF1_BKINE 0x00000001U 02957c: line 7917 define TIM8_AF1_BKDF1BKE 0x00000100U 02959d: line 7920 define TIM8_AF2_BK2INE 0x00000001U 0295bc: line 7921 define TIM8_AF2_BK2DF1BKE 0x00000100U 0295de: line 7929 define LPTIM_ISR_CMPM 0x00000001U 0295fc: line 7930 define LPTIM_ISR_ARRM 0x00000002U 02961a: line 7931 define LPTIM_ISR_EXTTRIG 0x00000004U 02963b: line 7932 define LPTIM_ISR_CMPOK 0x00000008U 02965a: line 7933 define LPTIM_ISR_ARROK 0x00000010U 029679: line 7934 define LPTIM_ISR_UP 0x00000020U 029695: line 7935 define LPTIM_ISR_DOWN 0x00000040U 0296b3: line 7938 define LPTIM_ICR_CMPMCF 0x00000001U 0296d3: line 7939 define LPTIM_ICR_ARRMCF 0x00000002U 0296f3: line 7940 define LPTIM_ICR_EXTTRIGCF 0x00000004U 029716: line 7941 define LPTIM_ICR_CMPOKCF 0x00000008U 029737: line 7942 define LPTIM_ICR_ARROKCF 0x00000010U 029758: line 7943 define LPTIM_ICR_UPCF 0x00000020U 029776: line 7944 define LPTIM_ICR_DOWNCF 0x00000040U 029796: line 7947 define LPTIM_IER_CMPMIE 0x00000001U 0297b6: line 7948 define LPTIM_IER_ARRMIE 0x00000002U 0297d6: line 7949 define LPTIM_IER_EXTTRIGIE 0x00000004U 0297f9: line 7950 define LPTIM_IER_CMPOKIE 0x00000008U 02981a: line 7951 define LPTIM_IER_ARROKIE 0x00000010U 02983b: line 7952 define LPTIM_IER_UPIE 0x00000020U 029859: line 7953 define LPTIM_IER_DOWNIE 0x00000040U 029879: line 7956 define LPTIM_CFGR_CKSEL 0x00000001U 029899: line 7958 define LPTIM_CFGR_CKPOL 0x00000006U 0298b9: line 7959 define LPTIM_CFGR_CKPOL_0 0x00000002U 0298db: line 7960 define LPTIM_CFGR_CKPOL_1 0x00000004U 0298fd: line 7962 define LPTIM_CFGR_CKFLT 0x00000018U 02991d: line 7963 define LPTIM_CFGR_CKFLT_0 0x00000008U 02993f: line 7964 define LPTIM_CFGR_CKFLT_1 0x00000010U 029961: line 7966 define LPTIM_CFGR_TRGFLT 0x000000C0U 029982: line 7967 define LPTIM_CFGR_TRGFLT_0 0x00000040U 0299a5: line 7968 define LPTIM_CFGR_TRGFLT_1 0x00000080U 0299c8: line 7970 define LPTIM_CFGR_PRESC 0x00000E00U 0299e8: line 7971 define LPTIM_CFGR_PRESC_0 0x00000200U 029a0a: line 7972 define LPTIM_CFGR_PRESC_1 0x00000400U 029a2c: line 7973 define LPTIM_CFGR_PRESC_2 0x00000800U 029a4e: line 7975 define LPTIM_CFGR_TRIGSEL 0x0000E000U 029a70: line 7976 define LPTIM_CFGR_TRIGSEL_0 0x00002000U 029a94: line 7977 define LPTIM_CFGR_TRIGSEL_1 0x00004000U 029ab8: line 7978 define LPTIM_CFGR_TRIGSEL_2 0x00008000U 029adc: line 7980 define LPTIM_CFGR_TRIGEN 0x00060000U 029afd: line 7981 define LPTIM_CFGR_TRIGEN_0 0x00020000U 029b20: line 7982 define LPTIM_CFGR_TRIGEN_1 0x00040000U 029b43: line 7984 define LPTIM_CFGR_TIMOUT 0x00080000U 029b64: line 7985 define LPTIM_CFGR_WAVE 0x00100000U 029b83: line 7986 define LPTIM_CFGR_WAVPOL 0x00200000U 029ba4: line 7987 define LPTIM_CFGR_PRELOAD 0x00400000U 029bc6: line 7988 define LPTIM_CFGR_COUNTMODE 0x00800000U 029bea: line 7989 define LPTIM_CFGR_ENC 0x01000000U 029c08: line 7992 define LPTIM_CR_ENABLE 0x00000001U 029c27: line 7993 define LPTIM_CR_SNGSTRT 0x00000002U 029c47: line 7994 define LPTIM_CR_CNTSTRT 0x00000004U 029c67: line 7997 define LPTIM_CMP_CMP 0x0000FFFFU 029c84: line 8000 define LPTIM_ARR_ARR 0x0000FFFFU 029ca1: line 8003 define LPTIM_CNT_CNT 0x0000FFFFU 029cbe: line 8010 define USART_CR1_UE 0x00000001U 029cda: line 8011 define USART_CR1_RE 0x00000004U 029cf6: line 8012 define USART_CR1_TE 0x00000008U 029d12: line 8013 define USART_CR1_IDLEIE 0x00000010U 029d32: line 8014 define USART_CR1_RXNEIE 0x00000020U 029d52: line 8015 define USART_CR1_TCIE 0x00000040U 029d70: line 8016 define USART_CR1_TXEIE 0x00000080U 029d8f: line 8017 define USART_CR1_PEIE 0x00000100U 029dad: line 8018 define USART_CR1_PS 0x00000200U 029dc9: line 8019 define USART_CR1_PCE 0x00000400U 029de6: line 8020 define USART_CR1_WAKE 0x00000800U 029e04: line 8021 define USART_CR1_M 0x10001000U 029e1f: line 8022 define USART_CR1_M_0 0x00001000U 029e3c: line 8023 define USART_CR1_MME 0x00002000U 029e59: line 8024 define USART_CR1_CMIE 0x00004000U 029e77: line 8025 define USART_CR1_OVER8 0x00008000U 029e96: line 8026 define USART_CR1_DEDT 0x001F0000U 029eb4: line 8027 define USART_CR1_DEDT_0 0x00010000U 029ed4: line 8028 define USART_CR1_DEDT_1 0x00020000U 029ef4: line 8029 define USART_CR1_DEDT_2 0x00040000U 029f14: line 8030 define USART_CR1_DEDT_3 0x00080000U 029f34: line 8031 define USART_CR1_DEDT_4 0x00100000U 029f54: line 8032 define USART_CR1_DEAT 0x03E00000U 029f72: line 8033 define USART_CR1_DEAT_0 0x00200000U 029f92: line 8034 define USART_CR1_DEAT_1 0x00400000U 029fb2: line 8035 define USART_CR1_DEAT_2 0x00800000U 029fd2: line 8036 define USART_CR1_DEAT_3 0x01000000U 029ff2: line 8037 define USART_CR1_DEAT_4 0x02000000U 02a012: line 8038 define USART_CR1_RTOIE 0x04000000U 02a031: line 8039 define USART_CR1_EOBIE 0x08000000U 02a050: line 8040 define USART_CR1_M_1 0x10000000U 02a06d: line 8043 define USART_CR2_ADDM7 0x00000010U 02a08c: line 8044 define USART_CR2_LBDL 0x00000020U 02a0aa: line 8045 define USART_CR2_LBDIE 0x00000040U 02a0c9: line 8046 define USART_CR2_LBCL 0x00000100U 02a0e7: line 8047 define USART_CR2_CPHA 0x00000200U 02a105: line 8048 define USART_CR2_CPOL 0x00000400U 02a123: line 8049 define USART_CR2_CLKEN 0x00000800U 02a142: line 8050 define USART_CR2_STOP 0x00003000U 02a160: line 8051 define USART_CR2_STOP_0 0x00001000U 02a180: line 8052 define USART_CR2_STOP_1 0x00002000U 02a1a0: line 8053 define USART_CR2_LINEN 0x00004000U 02a1bf: line 8054 define USART_CR2_SWAP 0x00008000U 02a1dd: line 8055 define USART_CR2_RXINV 0x00010000U 02a1fc: line 8056 define USART_CR2_TXINV 0x00020000U 02a21b: line 8057 define USART_CR2_DATAINV 0x00040000U 02a23c: line 8058 define USART_CR2_MSBFIRST 0x00080000U 02a25e: line 8059 define USART_CR2_ABREN 0x00100000U 02a27d: line 8060 define USART_CR2_ABRMODE 0x00600000U 02a29e: line 8061 define USART_CR2_ABRMODE_0 0x00200000U 02a2c1: line 8062 define USART_CR2_ABRMODE_1 0x00400000U 02a2e4: line 8063 define USART_CR2_RTOEN 0x00800000U 02a303: line 8064 define USART_CR2_ADD 0xFF000000U 02a320: line 8067 define USART_CR3_EIE 0x00000001U 02a33d: line 8068 define USART_CR3_IREN 0x00000002U 02a35b: line 8069 define USART_CR3_IRLP 0x00000004U 02a379: line 8070 define USART_CR3_HDSEL 0x00000008U 02a398: line 8071 define USART_CR3_NACK 0x00000010U 02a3b6: line 8072 define USART_CR3_SCEN 0x00000020U 02a3d4: line 8073 define USART_CR3_DMAR 0x00000040U 02a3f2: line 8074 define USART_CR3_DMAT 0x00000080U 02a410: line 8075 define USART_CR3_RTSE 0x00000100U 02a42e: line 8076 define USART_CR3_CTSE 0x00000200U 02a44c: line 8077 define USART_CR3_CTSIE 0x00000400U 02a46b: line 8078 define USART_CR3_ONEBIT 0x00000800U 02a48b: line 8079 define USART_CR3_OVRDIS 0x00001000U 02a4ab: line 8080 define USART_CR3_DDRE 0x00002000U 02a4c9: line 8081 define USART_CR3_DEM 0x00004000U 02a4e6: line 8082 define USART_CR3_DEP 0x00008000U 02a503: line 8083 define USART_CR3_SCARCNT 0x000E0000U 02a524: line 8084 define USART_CR3_SCARCNT_0 0x00020000U 02a547: line 8085 define USART_CR3_SCARCNT_1 0x00040000U 02a56a: line 8086 define USART_CR3_SCARCNT_2 0x00080000U 02a58d: line 8090 define USART_BRR_DIV_FRACTION 0x000FU 02a5af: line 8091 define USART_BRR_DIV_MANTISSA 0xFFF0U 02a5d1: line 8094 define USART_GTPR_PSC 0x00FFU 02a5eb: line 8095 define USART_GTPR_GT 0xFF00U 02a604: line 8099 define USART_RTOR_RTO 0x00FFFFFFU 02a622: line 8100 define USART_RTOR_BLEN 0xFF000000U 02a641: line 8103 define USART_RQR_ABRRQ 0x0001U 02a65c: line 8104 define USART_RQR_SBKRQ 0x0002U 02a677: line 8105 define USART_RQR_MMRQ 0x0004U 02a691: line 8106 define USART_RQR_RXFRQ 0x0008U 02a6ac: line 8107 define USART_RQR_TXFRQ 0x0010U 02a6c7: line 8110 define USART_ISR_PE 0x00000001U 02a6e3: line 8111 define USART_ISR_FE 0x00000002U 02a6ff: line 8112 define USART_ISR_NE 0x00000004U 02a71b: line 8113 define USART_ISR_ORE 0x00000008U 02a738: line 8114 define USART_ISR_IDLE 0x00000010U 02a756: line 8115 define USART_ISR_RXNE 0x00000020U 02a774: line 8116 define USART_ISR_TC 0x00000040U 02a790: line 8117 define USART_ISR_TXE 0x00000080U 02a7ad: line 8118 define USART_ISR_LBDF 0x00000100U 02a7cb: line 8119 define USART_ISR_CTSIF 0x00000200U 02a7ea: line 8120 define USART_ISR_CTS 0x00000400U 02a807: line 8121 define USART_ISR_RTOF 0x00000800U 02a825: line 8122 define USART_ISR_EOBF 0x00001000U 02a843: line 8123 define USART_ISR_ABRE 0x00004000U 02a861: line 8124 define USART_ISR_ABRF 0x00008000U 02a87f: line 8125 define USART_ISR_BUSY 0x00010000U 02a89d: line 8126 define USART_ISR_CMF 0x00020000U 02a8ba: line 8127 define USART_ISR_SBKF 0x00040000U 02a8d8: line 8128 define USART_ISR_RWU 0x00080000U 02a8f5: line 8129 define USART_ISR_WUF 0x00100000U 02a912: line 8130 define USART_ISR_TEACK 0x00200000U 02a931: line 8131 define USART_ISR_REACK 0x00400000U 02a950: line 8135 define USART_ICR_PECF 0x00000001U 02a96e: line 8136 define USART_ICR_FECF 0x00000002U 02a98c: line 8137 define USART_ICR_NCF 0x00000004U 02a9a9: line 8138 define USART_ICR_ORECF 0x00000008U 02a9c8: line 8139 define USART_ICR_IDLECF 0x00000010U 02a9e8: line 8140 define USART_ICR_TCCF 0x00000040U 02aa06: line 8141 define USART_ICR_LBDCF 0x00000100U 02aa25: line 8142 define USART_ICR_CTSCF 0x00000200U 02aa44: line 8143 define USART_ICR_RTOCF 0x00000800U 02aa63: line 8144 define USART_ICR_EOBCF 0x00001000U 02aa82: line 8145 define USART_ICR_CMCF 0x00020000U 02aaa0: line 8146 define USART_ICR_WUCF 0x00100000U 02aabe: line 8149 define USART_RDR_RDR 0x01FFU 02aad7: line 8152 define USART_TDR_TDR 0x01FFU 02aaf0: line 8160 define WWDG_CR_T 0x7FU 02ab03: line 8161 define WWDG_CR_T_0 0x01U 02ab18: line 8162 define WWDG_CR_T_1 0x02U 02ab2d: line 8163 define WWDG_CR_T_2 0x04U 02ab42: line 8164 define WWDG_CR_T_3 0x08U 02ab57: line 8165 define WWDG_CR_T_4 0x10U 02ab6c: line 8166 define WWDG_CR_T_5 0x20U 02ab81: line 8167 define WWDG_CR_T_6 0x40U 02ab96: line 8170 define WWDG_CR_WDGA 0x80U 02abac: line 8173 define WWDG_CFR_W 0x007FU 02abc2: line 8174 define WWDG_CFR_W_0 0x0001U 02abda: line 8175 define WWDG_CFR_W_1 0x0002U 02abf2: line 8176 define WWDG_CFR_W_2 0x0004U 02ac0a: line 8177 define WWDG_CFR_W_3 0x0008U 02ac22: line 8178 define WWDG_CFR_W_4 0x0010U 02ac3a: line 8179 define WWDG_CFR_W_5 0x0020U 02ac52: line 8180 define WWDG_CFR_W_6 0x0040U 02ac6a: line 8183 define WWDG_CFR_WDGTB 0x0180U 02ac84: line 8184 define WWDG_CFR_WDGTB_0 0x0080U 02aca0: line 8185 define WWDG_CFR_WDGTB_1 0x0100U 02acbc: line 8188 define WWDG_CFR_EWI 0x0200U 02acd4: line 8191 define WWDG_SR_EWIF 0x01U 02acea: line 8199 define DBGMCU_IDCODE_DEV_ID 0x00000FFFU 02ad0e: line 8200 define DBGMCU_IDCODE_REV_ID 0xFFFF0000U 02ad32: line 8203 define DBGMCU_CR_DBG_SLEEP 0x00000001U 02ad55: line 8204 define DBGMCU_CR_DBG_STOP 0x00000002U 02ad77: line 8205 define DBGMCU_CR_DBG_STANDBY 0x00000004U 02ad9c: line 8206 define DBGMCU_CR_TRACE_IOEN 0x00000020U 02adc0: line 8208 define DBGMCU_CR_TRACE_MODE 0x000000C0U 02ade4: line 8209 define DBGMCU_CR_TRACE_MODE_0 0x00000040U 02ae0a: line 8210 define DBGMCU_CR_TRACE_MODE_1 0x00000080U 02ae30: line 8213 define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U 02ae5c: line 8214 define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U 02ae88: line 8215 define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U 02aeb4: line 8216 define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U 02aee0: line 8217 define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U 02af0c: line 8218 define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U 02af38: line 8219 define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U 02af65: line 8220 define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U 02af92: line 8221 define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U 02afbf: line 8222 define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U 02afea: line 8223 define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U 02b016: line 8224 define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U 02b042: line 8225 define DBGMCU_APB1_FZ_DBG_CAN3_STOP 0x00002000U 02b06e: line 8226 define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U 02b0a3: line 8227 define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U 02b0d8: line 8228 define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U 02b10d: line 8229 define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U 02b139: line 8230 define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U 02b165: line 8233 define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U 02b191: line 8234 define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U 02b1bd: line 8235 define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U 02b1e9: line 8236 define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U 02b216: line 8237 define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U 02b243: line 8245 define ETH_MACCR_WD 0x00800000U 02b25f: line 8246 define ETH_MACCR_JD 0x00400000U 02b27b: line 8247 define ETH_MACCR_IFG 0x000E0000U 02b298: line 8248 define ETH_MACCR_IFG_96Bit 0x00000000U 02b2bb: line 8249 define ETH_MACCR_IFG_88Bit 0x00020000U 02b2de: line 8250 define ETH_MACCR_IFG_80Bit 0x00040000U 02b301: line 8251 define ETH_MACCR_IFG_72Bit 0x00060000U 02b324: line 8252 define ETH_MACCR_IFG_64Bit 0x00080000U 02b347: line 8253 define ETH_MACCR_IFG_56Bit 0x000A0000U 02b36a: line 8254 define ETH_MACCR_IFG_48Bit 0x000C0000U 02b38d: line 8255 define ETH_MACCR_IFG_40Bit 0x000E0000U 02b3b0: line 8256 define ETH_MACCR_CSD 0x00010000U 02b3cd: line 8257 define ETH_MACCR_FES 0x00004000U 02b3ea: line 8258 define ETH_MACCR_ROD 0x00002000U 02b407: line 8259 define ETH_MACCR_LM 0x00001000U 02b423: line 8260 define ETH_MACCR_DM 0x00000800U 02b43f: line 8261 define ETH_MACCR_IPCO 0x00000400U 02b45d: line 8262 define ETH_MACCR_RD 0x00000200U 02b479: line 8263 define ETH_MACCR_APCS 0x00000080U 02b497: line 8264 define ETH_MACCR_BL 0x00000060U 02b4b3: line 8266 define ETH_MACCR_BL_10 0x00000000U 02b4d2: line 8267 define ETH_MACCR_BL_8 0x00000020U 02b4f0: line 8268 define ETH_MACCR_BL_4 0x00000040U 02b50e: line 8269 define ETH_MACCR_BL_1 0x00000060U 02b52c: line 8270 define ETH_MACCR_DC 0x00000010U 02b548: line 8271 define ETH_MACCR_TE 0x00000008U 02b564: line 8272 define ETH_MACCR_RE 0x00000004U 02b580: line 8275 define ETH_MACFFR_RA 0x80000000U 02b59d: line 8276 define ETH_MACFFR_HPF 0x00000400U 02b5bb: line 8277 define ETH_MACFFR_SAF 0x00000200U 02b5d9: line 8278 define ETH_MACFFR_SAIF 0x00000100U 02b5f8: line 8279 define ETH_MACFFR_PCF 0x000000C0U 02b616: line 8280 define ETH_MACFFR_PCF_BlockAll 0x00000040U 02b63d: line 8281 define ETH_MACFFR_PCF_ForwardAll 0x00000080U 02b666: line 8282 define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U 02b69c: line 8283 define ETH_MACFFR_BFD 0x00000020U 02b6ba: line 8284 define ETH_MACFFR_PAM 0x00000010U 02b6d8: line 8285 define ETH_MACFFR_DAIF 0x00000008U 02b6f7: line 8286 define ETH_MACFFR_HM 0x00000004U 02b714: line 8287 define ETH_MACFFR_HU 0x00000002U 02b731: line 8288 define ETH_MACFFR_PM 0x00000001U 02b74e: line 8291 define ETH_MACHTHR_HTH 0xFFFFFFFFU 02b76d: line 8294 define ETH_MACHTLR_HTL 0xFFFFFFFFU 02b78c: line 8297 define ETH_MACMIIAR_PA 0x0000F800U 02b7ab: line 8298 define ETH_MACMIIAR_MR 0x000007C0U 02b7ca: line 8299 define ETH_MACMIIAR_CR 0x0000001CU 02b7e9: line 8300 define ETH_MACMIIAR_CR_Div42 0x00000000U 02b80e: line 8301 define ETH_MACMIIAR_CR_Div62 0x00000004U 02b833: line 8302 define ETH_MACMIIAR_CR_Div16 0x00000008U 02b858: line 8303 define ETH_MACMIIAR_CR_Div26 0x0000000CU 02b87d: line 8304 define ETH_MACMIIAR_CR_Div102 0x00000010U 02b8a3: line 8305 define ETH_MACMIIAR_MW 0x00000002U 02b8c2: line 8306 define ETH_MACMIIAR_MB 0x00000001U 02b8e1: line 8309 define ETH_MACMIIDR_MD 0x0000FFFFU 02b900: line 8312 define ETH_MACFCR_PT 0xFFFF0000U 02b91d: line 8313 define ETH_MACFCR_ZQPD 0x00000080U 02b93c: line 8314 define ETH_MACFCR_PLT 0x00000030U 02b95a: line 8315 define ETH_MACFCR_PLT_Minus4 0x00000000U 02b97f: line 8316 define ETH_MACFCR_PLT_Minus28 0x00000010U 02b9a5: line 8317 define ETH_MACFCR_PLT_Minus144 0x00000020U 02b9cc: line 8318 define ETH_MACFCR_PLT_Minus256 0x00000030U 02b9f3: line 8319 define ETH_MACFCR_UPFD 0x00000008U 02ba12: line 8320 define ETH_MACFCR_RFCE 0x00000004U 02ba31: line 8321 define ETH_MACFCR_TFCE 0x00000002U 02ba50: line 8322 define ETH_MACFCR_FCBBPA 0x00000001U 02ba71: line 8325 define ETH_MACVLANTR_VLANTC 0x00010000U 02ba95: line 8326 define ETH_MACVLANTR_VLANTI 0x0000FFFFU 02bab9: line 8329 define ETH_MACRWUFFR_D 0xFFFFFFFFU 02bad8: line 8343 define ETH_MACPMTCSR_WFFRPR 0x80000000U 02bafc: line 8344 define ETH_MACPMTCSR_GU 0x00000200U 02bb1c: line 8345 define ETH_MACPMTCSR_WFR 0x00000040U 02bb3d: line 8346 define ETH_MACPMTCSR_MPR 0x00000020U 02bb5e: line 8347 define ETH_MACPMTCSR_WFE 0x00000004U 02bb7f: line 8348 define ETH_MACPMTCSR_MPE 0x00000002U 02bba0: line 8349 define ETH_MACPMTCSR_PD 0x00000001U 02bbc0: line 8352 define ETH_MACSR_TSTS 0x00000200U 02bbde: line 8353 define ETH_MACSR_MMCTS 0x00000040U 02bbfd: line 8354 define ETH_MACSR_MMMCRS 0x00000020U 02bc1d: line 8355 define ETH_MACSR_MMCS 0x00000010U 02bc3b: line 8356 define ETH_MACSR_PMTS 0x00000008U 02bc59: line 8359 define ETH_MACIMR_TSTIM 0x00000200U 02bc79: line 8360 define ETH_MACIMR_PMTIM 0x00000008U 02bc99: line 8363 define ETH_MACA0HR_MACA0H 0x0000FFFFU 02bcbb: line 8366 define ETH_MACA0LR_MACA0L 0xFFFFFFFFU 02bcdd: line 8369 define ETH_MACA1HR_AE 0x80000000U 02bcfb: line 8370 define ETH_MACA1HR_SA 0x40000000U 02bd19: line 8371 define ETH_MACA1HR_MBC 0x3F000000U 02bd38: line 8372 define ETH_MACA1HR_MBC_HBits15_8 0x20000000U 02bd61: line 8373 define ETH_MACA1HR_MBC_HBits7_0 0x10000000U 02bd89: line 8374 define ETH_MACA1HR_MBC_LBits31_24 0x08000000U 02bdb3: line 8375 define ETH_MACA1HR_MBC_LBits23_16 0x04000000U 02bddd: line 8376 define ETH_MACA1HR_MBC_LBits15_8 0x02000000U 02be06: line 8377 define ETH_MACA1HR_MBC_LBits7_0 0x01000000U 02be2e: line 8378 define ETH_MACA1HR_MACA1H 0x0000FFFFU 02be50: line 8381 define ETH_MACA1LR_MACA1L 0xFFFFFFFFU 02be72: line 8384 define ETH_MACA2HR_AE 0x80000000U 02be90: line 8385 define ETH_MACA2HR_SA 0x40000000U 02beae: line 8386 define ETH_MACA2HR_MBC 0x3F000000U 02becd: line 8387 define ETH_MACA2HR_MBC_HBits15_8 0x20000000U 02bef6: line 8388 define ETH_MACA2HR_MBC_HBits7_0 0x10000000U 02bf1e: line 8389 define ETH_MACA2HR_MBC_LBits31_24 0x08000000U 02bf48: line 8390 define ETH_MACA2HR_MBC_LBits23_16 0x04000000U 02bf72: line 8391 define ETH_MACA2HR_MBC_LBits15_8 0x02000000U 02bf9b: line 8392 define ETH_MACA2HR_MBC_LBits7_0 0x01000000U 02bfc3: line 8393 define ETH_MACA2HR_MACA2H 0x0000FFFFU 02bfe5: line 8396 define ETH_MACA2LR_MACA2L 0xFFFFFFFFU 02c007: line 8399 define ETH_MACA3HR_AE 0x80000000U 02c025: line 8400 define ETH_MACA3HR_SA 0x40000000U 02c043: line 8401 define ETH_MACA3HR_MBC 0x3F000000U 02c062: line 8402 define ETH_MACA3HR_MBC_HBits15_8 0x20000000U 02c08b: line 8403 define ETH_MACA3HR_MBC_HBits7_0 0x10000000U 02c0b3: line 8404 define ETH_MACA3HR_MBC_LBits31_24 0x08000000U 02c0dd: line 8405 define ETH_MACA3HR_MBC_LBits23_16 0x04000000U 02c107: line 8406 define ETH_MACA3HR_MBC_LBits15_8 0x02000000U 02c130: line 8407 define ETH_MACA3HR_MBC_LBits7_0 0x01000000U 02c158: line 8408 define ETH_MACA3HR_MACA3H 0x0000FFFFU 02c17a: line 8411 define ETH_MACA3LR_MACA3L 0xFFFFFFFFU 02c19c: line 8418 define ETH_MMCCR_MCFHP 0x00000020U 02c1bb: line 8419 define ETH_MMCCR_MCP 0x00000010U 02c1d8: line 8420 define ETH_MMCCR_MCF 0x00000008U 02c1f5: line 8421 define ETH_MMCCR_ROR 0x00000004U 02c212: line 8422 define ETH_MMCCR_CSR 0x00000002U 02c22f: line 8423 define ETH_MMCCR_CR 0x00000001U 02c24b: line 8426 define ETH_MMCRIR_RGUFS 0x00020000U 02c26b: line 8427 define ETH_MMCRIR_RFAES 0x00000040U 02c28b: line 8428 define ETH_MMCRIR_RFCES 0x00000020U 02c2ab: line 8431 define ETH_MMCTIR_TGFS 0x00200000U 02c2ca: line 8432 define ETH_MMCTIR_TGFMSCS 0x00008000U 02c2ec: line 8433 define ETH_MMCTIR_TGFSCS 0x00004000U 02c30d: line 8436 define ETH_MMCRIMR_RGUFM 0x00020000U 02c32e: line 8437 define ETH_MMCRIMR_RFAEM 0x00000040U 02c34f: line 8438 define ETH_MMCRIMR_RFCEM 0x00000020U 02c370: line 8441 define ETH_MMCTIMR_TGFM 0x00200000U 02c390: line 8442 define ETH_MMCTIMR_TGFMSCM 0x00008000U 02c3b3: line 8443 define ETH_MMCTIMR_TGFSCM 0x00004000U 02c3d5: line 8446 define ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU 02c3fa: line 8449 define ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU 02c421: line 8452 define ETH_MMCTGFCR_TGFC 0xFFFFFFFFU 02c442: line 8455 define ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU 02c465: line 8458 define ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU 02c488: line 8461 define ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU 02c4ab: line 8468 define ETH_PTPTSCR_TSCNT 0x00030000U 02c4cc: line 8469 define ETH_PTPTSSR_TSSMRME 0x00008000U 02c4ef: line 8470 define ETH_PTPTSSR_TSSEME 0x00004000U 02c511: line 8471 define ETH_PTPTSSR_TSSIPV4FE 0x00002000U 02c536: line 8472 define ETH_PTPTSSR_TSSIPV6FE 0x00001000U 02c55b: line 8473 define ETH_PTPTSSR_TSSPTPOEFE 0x00000800U 02c581: line 8474 define ETH_PTPTSSR_TSPTPPSV2E 0x00000400U 02c5a7: line 8475 define ETH_PTPTSSR_TSSSR 0x00000200U 02c5c8: line 8476 define ETH_PTPTSSR_TSSARFE 0x00000100U 02c5eb: line 8478 define ETH_PTPTSCR_TSARU 0x00000020U 02c60c: line 8479 define ETH_PTPTSCR_TSITE 0x00000010U 02c62d: line 8480 define ETH_PTPTSCR_TSSTU 0x00000008U 02c64e: line 8481 define ETH_PTPTSCR_TSSTI 0x00000004U 02c66f: line 8482 define ETH_PTPTSCR_TSFCU 0x00000002U 02c690: line 8483 define ETH_PTPTSCR_TSE 0x00000001U 02c6af: line 8486 define ETH_PTPSSIR_STSSI 0x000000FFU 02c6d0: line 8489 define ETH_PTPTSHR_STS 0xFFFFFFFFU 02c6ef: line 8492 define ETH_PTPTSLR_STPNS 0x80000000U 02c710: line 8493 define ETH_PTPTSLR_STSS 0x7FFFFFFFU 02c730: line 8496 define ETH_PTPTSHUR_TSUS 0xFFFFFFFFU 02c751: line 8499 define ETH_PTPTSLUR_TSUPNS 0x80000000U 02c774: line 8500 define ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU 02c796: line 8503 define ETH_PTPTSAR_TSA 0xFFFFFFFFU 02c7b5: line 8506 define ETH_PTPTTHR_TTSH 0xFFFFFFFFU 02c7d5: line 8509 define ETH_PTPTTLR_TTSL 0xFFFFFFFFU 02c7f5: line 8512 define ETH_PTPTSSR_TSTTR 0x00000020U 02c816: line 8513 define ETH_PTPTSSR_TSSO 0x00000010U 02c836: line 8520 define ETH_DMABMR_AAB 0x02000000U 02c854: line 8521 define ETH_DMABMR_FPM 0x01000000U 02c872: line 8522 define ETH_DMABMR_USP 0x00800000U 02c890: line 8523 define ETH_DMABMR_RDP 0x007E0000U 02c8ae: line 8524 define ETH_DMABMR_RDP_1Beat 0x00020000U 02c8d2: line 8525 define ETH_DMABMR_RDP_2Beat 0x00040000U 02c8f6: line 8526 define ETH_DMABMR_RDP_4Beat 0x00080000U 02c91a: line 8527 define ETH_DMABMR_RDP_8Beat 0x00100000U 02c93e: line 8528 define ETH_DMABMR_RDP_16Beat 0x00200000U 02c963: line 8529 define ETH_DMABMR_RDP_32Beat 0x00400000U 02c988: line 8530 define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U 02c9b2: line 8531 define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U 02c9dc: line 8532 define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U 02ca07: line 8533 define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U 02ca32: line 8534 define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U 02ca5d: line 8535 define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U 02ca89: line 8536 define ETH_DMABMR_FB 0x00010000U 02caa6: line 8537 define ETH_DMABMR_RTPR 0x0000C000U 02cac5: line 8538 define ETH_DMABMR_RTPR_1_1 0x00000000U 02cae8: line 8539 define ETH_DMABMR_RTPR_2_1 0x00004000U 02cb0b: line 8540 define ETH_DMABMR_RTPR_3_1 0x00008000U 02cb2e: line 8541 define ETH_DMABMR_RTPR_4_1 0x0000C000U 02cb51: line 8542 define ETH_DMABMR_PBL 0x00003F00U 02cb6f: line 8543 define ETH_DMABMR_PBL_1Beat 0x00000100U 02cb93: line 8544 define ETH_DMABMR_PBL_2Beat 0x00000200U 02cbb7: line 8545 define ETH_DMABMR_PBL_4Beat 0x00000400U 02cbdb: line 8546 define ETH_DMABMR_PBL_8Beat 0x00000800U 02cbff: line 8547 define ETH_DMABMR_PBL_16Beat 0x00001000U 02cc24: line 8548 define ETH_DMABMR_PBL_32Beat 0x00002000U 02cc49: line 8549 define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U 02cc73: line 8550 define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U 02cc9d: line 8551 define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U 02ccc8: line 8552 define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U 02ccf3: line 8553 define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U 02cd1e: line 8554 define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U 02cd4a: line 8555 define ETH_DMABMR_EDE 0x00000080U 02cd68: line 8556 define ETH_DMABMR_DSL 0x0000007CU 02cd86: line 8557 define ETH_DMABMR_DA 0x00000002U 02cda3: line 8558 define ETH_DMABMR_SR 0x00000001U 02cdc0: line 8561 define ETH_DMATPDR_TPD 0xFFFFFFFFU 02cddf: line 8564 define ETH_DMARPDR_RPD 0xFFFFFFFFU 02cdfe: line 8567 define ETH_DMARDLAR_SRL 0xFFFFFFFFU 02ce1e: line 8570 define ETH_DMATDLAR_STL 0xFFFFFFFFU 02ce3e: line 8573 define ETH_DMASR_TSTS 0x20000000U 02ce5c: line 8574 define ETH_DMASR_PMTS 0x10000000U 02ce7a: line 8575 define ETH_DMASR_MMCS 0x08000000U 02ce98: line 8576 define ETH_DMASR_EBS 0x03800000U 02ceb5: line 8578 define ETH_DMASR_EBS_DescAccess 0x02000000U 02cedd: line 8579 define ETH_DMASR_EBS_ReadTransf 0x01000000U 02cf05: line 8580 define ETH_DMASR_EBS_DataTransfTx 0x00800000U 02cf2f: line 8581 define ETH_DMASR_TPS 0x00700000U 02cf4c: line 8582 define ETH_DMASR_TPS_Stopped 0x00000000U 02cf71: line 8583 define ETH_DMASR_TPS_Fetching 0x00100000U 02cf97: line 8584 define ETH_DMASR_TPS_Waiting 0x00200000U 02cfbc: line 8585 define ETH_DMASR_TPS_Reading 0x00300000U 02cfe1: line 8586 define ETH_DMASR_TPS_Suspended 0x00600000U 02d008: line 8587 define ETH_DMASR_TPS_Closing 0x00700000U 02d02d: line 8588 define ETH_DMASR_RPS 0x000E0000U 02d04a: line 8589 define ETH_DMASR_RPS_Stopped 0x00000000U 02d06f: line 8590 define ETH_DMASR_RPS_Fetching 0x00020000U 02d095: line 8591 define ETH_DMASR_RPS_Waiting 0x00060000U 02d0ba: line 8592 define ETH_DMASR_RPS_Suspended 0x00080000U 02d0e1: line 8593 define ETH_DMASR_RPS_Closing 0x000A0000U 02d106: line 8594 define ETH_DMASR_RPS_Queuing 0x000E0000U 02d12b: line 8595 define ETH_DMASR_NIS 0x00010000U 02d148: line 8596 define ETH_DMASR_AIS 0x00008000U 02d165: line 8597 define ETH_DMASR_ERS 0x00004000U 02d182: line 8598 define ETH_DMASR_FBES 0x00002000U 02d1a0: line 8599 define ETH_DMASR_ETS 0x00000400U 02d1bd: line 8600 define ETH_DMASR_RWTS 0x00000200U 02d1db: line 8601 define ETH_DMASR_RPSS 0x00000100U 02d1f9: line 8602 define ETH_DMASR_RBUS 0x00000080U 02d217: line 8603 define ETH_DMASR_RS 0x00000040U 02d233: line 8604 define ETH_DMASR_TUS 0x00000020U 02d250: line 8605 define ETH_DMASR_ROS 0x00000010U 02d26d: line 8606 define ETH_DMASR_TJTS 0x00000008U 02d28b: line 8607 define ETH_DMASR_TBUS 0x00000004U 02d2a9: line 8608 define ETH_DMASR_TPSS 0x00000002U 02d2c7: line 8609 define ETH_DMASR_TS 0x00000001U 02d2e3: line 8612 define ETH_DMAOMR_DTCEFD 0x04000000U 02d304: line 8613 define ETH_DMAOMR_RSF 0x02000000U 02d322: line 8614 define ETH_DMAOMR_DFRF 0x01000000U 02d341: line 8615 define ETH_DMAOMR_TSF 0x00200000U 02d35f: line 8616 define ETH_DMAOMR_FTF 0x00100000U 02d37d: line 8617 define ETH_DMAOMR_TTC 0x0001C000U 02d39b: line 8618 define ETH_DMAOMR_TTC_64Bytes 0x00000000U 02d3c1: line 8619 define ETH_DMAOMR_TTC_128Bytes 0x00004000U 02d3e8: line 8620 define ETH_DMAOMR_TTC_192Bytes 0x00008000U 02d40f: line 8621 define ETH_DMAOMR_TTC_256Bytes 0x0000C000U 02d436: line 8622 define ETH_DMAOMR_TTC_40Bytes 0x00010000U 02d45c: line 8623 define ETH_DMAOMR_TTC_32Bytes 0x00014000U 02d482: line 8624 define ETH_DMAOMR_TTC_24Bytes 0x00018000U 02d4a8: line 8625 define ETH_DMAOMR_TTC_16Bytes 0x0001C000U 02d4ce: line 8626 define ETH_DMAOMR_ST 0x00002000U 02d4eb: line 8627 define ETH_DMAOMR_FEF 0x00000080U 02d509: line 8628 define ETH_DMAOMR_FUGF 0x00000040U 02d528: line 8629 define ETH_DMAOMR_RTC 0x00000018U 02d546: line 8630 define ETH_DMAOMR_RTC_64Bytes 0x00000000U 02d56c: line 8631 define ETH_DMAOMR_RTC_32Bytes 0x00000008U 02d592: line 8632 define ETH_DMAOMR_RTC_96Bytes 0x00000010U 02d5b8: line 8633 define ETH_DMAOMR_RTC_128Bytes 0x00000018U 02d5df: line 8634 define ETH_DMAOMR_OSF 0x00000004U 02d5fd: line 8635 define ETH_DMAOMR_SR 0x00000002U 02d61a: line 8638 define ETH_DMAIER_NISE 0x00010000U 02d639: line 8639 define ETH_DMAIER_AISE 0x00008000U 02d658: line 8640 define ETH_DMAIER_ERIE 0x00004000U 02d677: line 8641 define ETH_DMAIER_FBEIE 0x00002000U 02d697: line 8642 define ETH_DMAIER_ETIE 0x00000400U 02d6b6: line 8643 define ETH_DMAIER_RWTIE 0x00000200U 02d6d6: line 8644 define ETH_DMAIER_RPSIE 0x00000100U 02d6f6: line 8645 define ETH_DMAIER_RBUIE 0x00000080U 02d716: line 8646 define ETH_DMAIER_RIE 0x00000040U 02d734: line 8647 define ETH_DMAIER_TUIE 0x00000020U 02d753: line 8648 define ETH_DMAIER_ROIE 0x00000010U 02d772: line 8649 define ETH_DMAIER_TJTIE 0x00000008U 02d792: line 8650 define ETH_DMAIER_TBUIE 0x00000004U 02d7b2: line 8651 define ETH_DMAIER_TPSIE 0x00000002U 02d7d2: line 8652 define ETH_DMAIER_TIE 0x00000001U 02d7f0: line 8655 define ETH_DMAMFBOCR_OFOC 0x10000000U 02d812: line 8656 define ETH_DMAMFBOCR_MFA 0x0FFE0000U 02d833: line 8657 define ETH_DMAMFBOCR_OMFC 0x00010000U 02d855: line 8658 define ETH_DMAMFBOCR_MFC 0x0000FFFFU 02d876: line 8661 define ETH_DMACHTDR_HTDAP 0xFFFFFFFFU 02d898: line 8664 define ETH_DMACHRDR_HRDAP 0xFFFFFFFFU 02d8ba: line 8667 define ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU 02d8dd: line 8670 define ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU 02d900: line 8678 define USB_OTG_GOTGCTL_SRQSCS 0x00000001U 02d926: line 8679 define USB_OTG_GOTGCTL_SRQ 0x00000002U 02d949: line 8680 define USB_OTG_GOTGCTL_VBVALOEN 0x00000004U 02d971: line 8681 define USB_OTG_GOTGCTL_VBVALOVAL 0x00000008U 02d99a: line 8682 define USB_OTG_GOTGCTL_AVALOEN 0x00000010U 02d9c1: line 8683 define USB_OTG_GOTGCTL_AVALOVAL 0x00000020U 02d9e9: line 8684 define USB_OTG_GOTGCTL_BVALOEN 0x00000040U 02da10: line 8685 define USB_OTG_GOTGCTL_BVALOVAL 0x00000080U 02da38: line 8686 define USB_OTG_GOTGCTL_HNGSCS 0x00000100U 02da5e: line 8687 define USB_OTG_GOTGCTL_HNPRQ 0x00000200U 02da83: line 8688 define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U 02daaa: line 8689 define USB_OTG_GOTGCTL_DHNPEN 0x00000800U 02dad0: line 8690 define USB_OTG_GOTGCTL_EHEN 0x00001000U 02daf4: line 8691 define USB_OTG_GOTGCTL_CIDSTS 0x00010000U 02db1a: line 8692 define USB_OTG_GOTGCTL_DBCT 0x00020000U 02db3e: line 8693 define USB_OTG_GOTGCTL_ASVLD 0x00040000U 02db63: line 8694 define USB_OTG_GOTGCTL_BSESVLD 0x00080000U 02db8a: line 8695 define USB_OTG_GOTGCTL_OTGVER 0x00100000U 02dbb0: line 8698 define USB_OTG_HCFG_FSLSPCS 0x00000003U 02dbd4: line 8699 define USB_OTG_HCFG_FSLSPCS_0 0x00000001U 02dbfa: line 8700 define USB_OTG_HCFG_FSLSPCS_1 0x00000002U 02dc20: line 8701 define USB_OTG_HCFG_FSLSS 0x00000004U 02dc42: line 8704 define USB_OTG_DCFG_DSPD 0x00000003U 02dc63: line 8705 define USB_OTG_DCFG_DSPD_0 0x00000001U 02dc86: line 8706 define USB_OTG_DCFG_DSPD_1 0x00000002U 02dca9: line 8707 define USB_OTG_DCFG_NZLSOHSK 0x00000004U 02dcce: line 8709 define USB_OTG_DCFG_DAD 0x000007F0U 02dcee: line 8710 define USB_OTG_DCFG_DAD_0 0x00000010U 02dd10: line 8711 define USB_OTG_DCFG_DAD_1 0x00000020U 02dd32: line 8712 define USB_OTG_DCFG_DAD_2 0x00000040U 02dd54: line 8713 define USB_OTG_DCFG_DAD_3 0x00000080U 02dd76: line 8714 define USB_OTG_DCFG_DAD_4 0x00000100U 02dd98: line 8715 define USB_OTG_DCFG_DAD_5 0x00000200U 02ddba: line 8716 define USB_OTG_DCFG_DAD_6 0x00000400U 02dddc: line 8718 define USB_OTG_DCFG_PFIVL 0x00001800U 02ddfe: line 8719 define USB_OTG_DCFG_PFIVL_0 0x00000800U 02de22: line 8720 define USB_OTG_DCFG_PFIVL_1 0x00001000U 02de46: line 8722 define USB_OTG_DCFG_PERSCHIVL 0x03000000U 02de6c: line 8723 define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U 02de94: line 8724 define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U 02debc: line 8727 define USB_OTG_PCGCR_STPPCLK 0x00000001U 02dee1: line 8728 define USB_OTG_PCGCR_GATEHCLK 0x00000002U 02df07: line 8729 define USB_OTG_PCGCR_PHYSUSP 0x00000010U 02df2c: line 8732 define USB_OTG_GOTGINT_SEDET 0x00000004U 02df51: line 8733 define USB_OTG_GOTGINT_SRSSCHG 0x00000100U 02df78: line 8734 define USB_OTG_GOTGINT_HNSSCHG 0x00000200U 02df9f: line 8735 define USB_OTG_GOTGINT_HNGDET 0x00020000U 02dfc5: line 8736 define USB_OTG_GOTGINT_ADTOCHG 0x00040000U 02dfec: line 8737 define USB_OTG_GOTGINT_DBCDNE 0x00080000U 02e012: line 8738 define USB_OTG_GOTGINT_IDCHNG 0x00100000U 02e038: line 8741 define USB_OTG_DCTL_RWUSIG 0x00000001U 02e05b: line 8742 define USB_OTG_DCTL_SDIS 0x00000002U 02e07c: line 8743 define USB_OTG_DCTL_GINSTS 0x00000004U 02e09f: line 8744 define USB_OTG_DCTL_GONSTS 0x00000008U 02e0c2: line 8746 define USB_OTG_DCTL_TCTL 0x00000070U 02e0e3: line 8747 define USB_OTG_DCTL_TCTL_0 0x00000010U 02e106: line 8748 define USB_OTG_DCTL_TCTL_1 0x00000020U 02e129: line 8749 define USB_OTG_DCTL_TCTL_2 0x00000040U 02e14c: line 8750 define USB_OTG_DCTL_SGINAK 0x00000080U 02e16f: line 8751 define USB_OTG_DCTL_CGINAK 0x00000100U 02e192: line 8752 define USB_OTG_DCTL_SGONAK 0x00000200U 02e1b5: line 8753 define USB_OTG_DCTL_CGONAK 0x00000400U 02e1d8: line 8754 define USB_OTG_DCTL_POPRGDNE 0x00000800U 02e1fd: line 8757 define USB_OTG_HFIR_FRIVL 0x0000FFFFU 02e21f: line 8760 define USB_OTG_HFNUM_FRNUM 0x0000FFFFU 02e242: line 8761 define USB_OTG_HFNUM_FTREM 0xFFFF0000U 02e265: line 8764 define USB_OTG_DSTS_SUSPSTS 0x00000001U 02e289: line 8766 define USB_OTG_DSTS_ENUMSPD 0x00000006U 02e2ad: line 8767 define USB_OTG_DSTS_ENUMSPD_0 0x00000002U 02e2d3: line 8768 define USB_OTG_DSTS_ENUMSPD_1 0x00000004U 02e2f9: line 8769 define USB_OTG_DSTS_EERR 0x00000008U 02e31a: line 8770 define USB_OTG_DSTS_FNSOF 0x003FFF00U 02e33c: line 8773 define USB_OTG_GAHBCFG_GINT 0x00000001U 02e360: line 8774 define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU 02e387: line 8775 define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U 02e3b0: line 8776 define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U 02e3d9: line 8777 define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U 02e402: line 8778 define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U 02e42b: line 8779 define USB_OTG_GAHBCFG_DMAEN 0x00000020U 02e450: line 8780 define USB_OTG_GAHBCFG_TXFELVL 0x00000080U 02e477: line 8781 define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U 02e49f: line 8784 define USB_OTG_GUSBCFG_TOCAL 0x00000007U 02e4c4: line 8785 define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U 02e4eb: line 8786 define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U 02e512: line 8787 define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U 02e539: line 8788 define USB_OTG_GUSBCFG_PHYSEL 0x00000040U 02e55f: line 8789 define USB_OTG_GUSBCFG_SRPCAP 0x00000100U 02e585: line 8790 define USB_OTG_GUSBCFG_HNPCAP 0x00000200U 02e5ab: line 8791 define USB_OTG_GUSBCFG_TRDT 0x00003C00U 02e5cf: line 8792 define USB_OTG_GUSBCFG_TRDT_0 0x00000400U 02e5f5: line 8793 define USB_OTG_GUSBCFG_TRDT_1 0x00000800U 02e61b: line 8794 define USB_OTG_GUSBCFG_TRDT_2 0x00001000U 02e641: line 8795 define USB_OTG_GUSBCFG_TRDT_3 0x00002000U 02e667: line 8796 define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U 02e68e: line 8797 define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U 02e6b6: line 8798 define USB_OTG_GUSBCFG_ULPIAR 0x00040000U 02e6dc: line 8799 define USB_OTG_GUSBCFG_ULPICSM 0x00080000U 02e703: line 8800 define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U 02e72d: line 8801 define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U 02e757: line 8802 define USB_OTG_GUSBCFG_TSDPS 0x00400000U 02e77c: line 8803 define USB_OTG_GUSBCFG_PCCI 0x00800000U 02e7a0: line 8804 define USB_OTG_GUSBCFG_PTCI 0x01000000U 02e7c4: line 8805 define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U 02e7eb: line 8806 define USB_OTG_GUSBCFG_FHMOD 0x20000000U 02e810: line 8807 define USB_OTG_GUSBCFG_FDMOD 0x40000000U 02e835: line 8808 define USB_OTG_GUSBCFG_CTXPKT 0x80000000U 02e85b: line 8811 define USB_OTG_GRSTCTL_CSRST 0x00000001U 02e880: line 8812 define USB_OTG_GRSTCTL_HSRST 0x00000002U 02e8a5: line 8813 define USB_OTG_GRSTCTL_FCRST 0x00000004U 02e8ca: line 8814 define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U 02e8f1: line 8815 define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U 02e918: line 8816 define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U 02e93e: line 8817 define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U 02e966: line 8818 define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U 02e98e: line 8819 define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U 02e9b6: line 8820 define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U 02e9de: line 8821 define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U 02ea06: line 8822 define USB_OTG_GRSTCTL_DMAREQ 0x40000000U 02ea2c: line 8823 define USB_OTG_GRSTCTL_AHBIDL 0x80000000U 02ea52: line 8826 define USB_OTG_DIEPMSK_XFRCM 0x00000001U 02ea77: line 8827 define USB_OTG_DIEPMSK_EPDM 0x00000002U 02ea9b: line 8828 define USB_OTG_DIEPMSK_TOM 0x00000008U 02eabe: line 8829 define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U 02eae7: line 8830 define USB_OTG_DIEPMSK_INEPNMM 0x00000020U 02eb0e: line 8831 define USB_OTG_DIEPMSK_INEPNEM 0x00000040U 02eb35: line 8832 define USB_OTG_DIEPMSK_TXFURM 0x00000100U 02eb5b: line 8833 define USB_OTG_DIEPMSK_BIM 0x00000200U 02eb7e: line 8836 define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU 02eba6: line 8837 define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U 02ebcd: line 8838 define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U 02ebf6: line 8839 define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U 02ec1f: line 8840 define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U 02ec48: line 8841 define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U 02ec71: line 8842 define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U 02ec9a: line 8843 define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U 02ecc3: line 8844 define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U 02ecec: line 8845 define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U 02ed15: line 8847 define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U 02ed3c: line 8848 define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U 02ed65: line 8849 define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U 02ed8e: line 8850 define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U 02edb7: line 8851 define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U 02ede0: line 8852 define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U 02ee09: line 8853 define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U 02ee32: line 8854 define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U 02ee5b: line 8855 define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U 02ee84: line 8858 define USB_OTG_HAINT_HAINT 0x0000FFFFU 02eea7: line 8861 define USB_OTG_DOEPMSK_XFRCM 0x00000001U 02eecc: line 8862 define USB_OTG_DOEPMSK_EPDM 0x00000002U 02eef0: line 8863 define USB_OTG_DOEPMSK_STUPM 0x00000008U 02ef15: line 8864 define USB_OTG_DOEPMSK_OTEPDM 0x00000010U 02ef3b: line 8865 define USB_OTG_DOEPMSK_OTEPSPRM 0x00000020U 02ef63: line 8866 define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U 02ef8a: line 8867 define USB_OTG_DOEPMSK_OPEM 0x00000100U 02efae: line 8868 define USB_OTG_DOEPMSK_BOIM 0x00000200U 02efd2: line 8871 define USB_OTG_GINTSTS_CMOD 0x00000001U 02eff6: line 8872 define USB_OTG_GINTSTS_MMIS 0x00000002U 02f01a: line 8873 define USB_OTG_GINTSTS_OTGINT 0x00000004U 02f040: line 8874 define USB_OTG_GINTSTS_SOF 0x00000008U 02f063: line 8875 define USB_OTG_GINTSTS_RXFLVL 0x00000010U 02f089: line 8876 define USB_OTG_GINTSTS_NPTXFE 0x00000020U 02f0af: line 8877 define USB_OTG_GINTSTS_GINAKEFF 0x00000040U 02f0d7: line 8878 define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U 02f101: line 8879 define USB_OTG_GINTSTS_ESUSP 0x00000400U 02f126: line 8880 define USB_OTG_GINTSTS_USBSUSP 0x00000800U 02f14d: line 8881 define USB_OTG_GINTSTS_USBRST 0x00001000U 02f173: line 8882 define USB_OTG_GINTSTS_ENUMDNE 0x00002000U 02f19a: line 8883 define USB_OTG_GINTSTS_ISOODRP 0x00004000U 02f1c1: line 8884 define USB_OTG_GINTSTS_EOPF 0x00008000U 02f1e5: line 8885 define USB_OTG_GINTSTS_IEPINT 0x00040000U 02f20b: line 8886 define USB_OTG_GINTSTS_OEPINT 0x00080000U 02f231: line 8887 define USB_OTG_GINTSTS_IISOIXFR 0x00100000U 02f259: line 8888 define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U 02f28a: line 8889 define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U 02f2b3: line 8890 define USB_OTG_GINTSTS_RSTDET 0x00800000U 02f2d9: line 8891 define USB_OTG_GINTSTS_HPRTINT 0x01000000U 02f300: line 8892 define USB_OTG_GINTSTS_HCINT 0x02000000U 02f325: line 8893 define USB_OTG_GINTSTS_PTXFE 0x04000000U 02f34a: line 8894 define USB_OTG_GINTSTS_LPMINT 0x08000000U 02f370: line 8895 define USB_OTG_GINTSTS_CIDSCHG 0x10000000U 02f397: line 8896 define USB_OTG_GINTSTS_DISCINT 0x20000000U 02f3be: line 8897 define USB_OTG_GINTSTS_SRQINT 0x40000000U 02f3e4: line 8898 define USB_OTG_GINTSTS_WKUINT 0x80000000U 02f40a: line 8901 define USB_OTG_GINTMSK_MMISM 0x00000002U 02f42f: line 8902 define USB_OTG_GINTMSK_OTGINT 0x00000004U 02f455: line 8903 define USB_OTG_GINTMSK_SOFM 0x00000008U 02f479: line 8904 define USB_OTG_GINTMSK_RXFLVLM 0x00000010U 02f4a0: line 8905 define USB_OTG_GINTMSK_NPTXFEM 0x00000020U 02f4c7: line 8906 define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U 02f4f0: line 8907 define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U 02f519: line 8908 define USB_OTG_GINTMSK_ESUSPM 0x00000400U 02f53f: line 8909 define USB_OTG_GINTMSK_USBSUSPM 0x00000800U 02f567: line 8910 define USB_OTG_GINTMSK_USBRST 0x00001000U 02f58d: line 8911 define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U 02f5b5: line 8912 define USB_OTG_GINTMSK_ISOODRPM 0x00004000U 02f5dd: line 8913 define USB_OTG_GINTMSK_EOPFM 0x00008000U 02f602: line 8914 define USB_OTG_GINTMSK_EPMISM 0x00020000U 02f628: line 8915 define USB_OTG_GINTMSK_IEPINT 0x00040000U 02f64e: line 8916 define USB_OTG_GINTMSK_OEPINT 0x00080000U 02f674: line 8917 define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U 02f69d: line 8918 define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U 02f6cc: line 8919 define USB_OTG_GINTMSK_FSUSPM 0x00400000U 02f6f2: line 8920 define USB_OTG_GINTMSK_RSTDEM 0x00800000U 02f718: line 8921 define USB_OTG_GINTMSK_PRTIM 0x01000000U 02f73d: line 8922 define USB_OTG_GINTMSK_HCIM 0x02000000U 02f761: line 8923 define USB_OTG_GINTMSK_PTXFEM 0x04000000U 02f787: line 8924 define USB_OTG_GINTMSK_LPMINTM 0x08000000U 02f7ae: line 8925 define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U 02f7d6: line 8926 define USB_OTG_GINTMSK_DISCINT 0x20000000U 02f7fd: line 8927 define USB_OTG_GINTMSK_SRQIM 0x40000000U 02f822: line 8928 define USB_OTG_GINTMSK_WUIM 0x80000000U 02f846: line 8931 define USB_OTG_DAINT_IEPINT 0x0000FFFFU 02f86a: line 8932 define USB_OTG_DAINT_OEPINT 0xFFFF0000U 02f88e: line 8935 define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU 02f8b5: line 8938 define USB_OTG_GRXSTSP_EPNUM 0x0000000FU 02f8da: line 8939 define USB_OTG_GRXSTSP_BCNT 0x00007FF0U 02f8fe: line 8940 define USB_OTG_GRXSTSP_DPID 0x00018000U 02f922: line 8941 define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U 02f948: line 8944 define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU 02f96d: line 8945 define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U 02f992: line 8949 define USB_OTG_CHNUM 0x0000000FU 02f9af: line 8950 define USB_OTG_CHNUM_0 0x00000001U 02f9ce: line 8951 define USB_OTG_CHNUM_1 0x00000002U 02f9ed: line 8952 define USB_OTG_CHNUM_2 0x00000004U 02fa0c: line 8953 define USB_OTG_CHNUM_3 0x00000008U 02fa2b: line 8954 define USB_OTG_BCNT 0x00007FF0U 02fa47: line 8956 define USB_OTG_DPID 0x00018000U 02fa63: line 8957 define USB_OTG_DPID_0 0x00008000U 02fa81: line 8958 define USB_OTG_DPID_1 0x00010000U 02fa9f: line 8960 define USB_OTG_PKTSTS 0x001E0000U 02fabd: line 8961 define USB_OTG_PKTSTS_0 0x00020000U 02fadd: line 8962 define USB_OTG_PKTSTS_1 0x00040000U 02fafd: line 8963 define USB_OTG_PKTSTS_2 0x00080000U 02fb1d: line 8964 define USB_OTG_PKTSTS_3 0x00100000U 02fb3d: line 8966 define USB_OTG_EPNUM 0x0000000FU 02fb5a: line 8967 define USB_OTG_EPNUM_0 0x00000001U 02fb79: line 8968 define USB_OTG_EPNUM_1 0x00000002U 02fb98: line 8969 define USB_OTG_EPNUM_2 0x00000004U 02fbb7: line 8970 define USB_OTG_EPNUM_3 0x00000008U 02fbd6: line 8972 define USB_OTG_FRMNUM 0x01E00000U 02fbf4: line 8973 define USB_OTG_FRMNUM_0 0x00200000U 02fc14: line 8974 define USB_OTG_FRMNUM_1 0x00400000U 02fc34: line 8975 define USB_OTG_FRMNUM_2 0x00800000U 02fc54: line 8976 define USB_OTG_FRMNUM_3 0x01000000U 02fc74: line 8980 define USB_OTG_CHNUM 0x0000000FU 02fc91: line 8981 define USB_OTG_CHNUM_0 0x00000001U 02fcb0: line 8982 define USB_OTG_CHNUM_1 0x00000002U 02fccf: line 8983 define USB_OTG_CHNUM_2 0x00000004U 02fcee: line 8984 define USB_OTG_CHNUM_3 0x00000008U 02fd0d: line 8985 define USB_OTG_BCNT 0x00007FF0U 02fd29: line 8987 define USB_OTG_DPID 0x00018000U 02fd45: line 8988 define USB_OTG_DPID_0 0x00008000U 02fd63: line 8989 define USB_OTG_DPID_1 0x00010000U 02fd81: line 8991 define USB_OTG_PKTSTS 0x001E0000U 02fd9f: line 8992 define USB_OTG_PKTSTS_0 0x00020000U 02fdbf: line 8993 define USB_OTG_PKTSTS_1 0x00040000U 02fddf: line 8994 define USB_OTG_PKTSTS_2 0x00080000U 02fdff: line 8995 define USB_OTG_PKTSTS_3 0x00100000U 02fe1f: line 8997 define USB_OTG_EPNUM 0x0000000FU 02fe3c: line 8998 define USB_OTG_EPNUM_0 0x00000001U 02fe5b: line 8999 define USB_OTG_EPNUM_1 0x00000002U 02fe7a: line 9000 define USB_OTG_EPNUM_2 0x00000004U 02fe99: line 9001 define USB_OTG_EPNUM_3 0x00000008U 02feb8: line 9003 define USB_OTG_FRMNUM 0x01E00000U 02fed6: line 9004 define USB_OTG_FRMNUM_0 0x00200000U 02fef6: line 9005 define USB_OTG_FRMNUM_1 0x00400000U 02ff16: line 9006 define USB_OTG_FRMNUM_2 0x00800000U 02ff36: line 9007 define USB_OTG_FRMNUM_3 0x01000000U 02ff56: line 9010 define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU 02ff7a: line 9013 define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU 02ffa1: line 9016 define USB_OTG_NPTXFSA 0x0000FFFFU 02ffc0: line 9017 define USB_OTG_NPTXFD 0xFFFF0000U 02ffde: line 9018 define USB_OTG_TX0FSA 0x0000FFFFU 02fffc: line 9019 define USB_OTG_TX0FD 0xFFFF0000U 030019: line 9022 define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU 030042: line 9025 define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU 03006b: line 9027 define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U 030094: line 9028 define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U 0300bf: line 9029 define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U 0300ea: line 9030 define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U 030115: line 9031 define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U 030140: line 9032 define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U 03016b: line 9033 define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U 030196: line 9034 define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U 0301c1: line 9035 define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U 0301ec: line 9037 define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U 030215: line 9038 define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U 030240: line 9039 define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U 03026b: line 9040 define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U 030296: line 9041 define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U 0302c1: line 9042 define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U 0302ec: line 9043 define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U 030317: line 9044 define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U 030342: line 9047 define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U 03036d: line 9048 define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U 030395: line 9050 define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU 0303bd: line 9051 define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U 0303e7: line 9052 define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U 030411: line 9053 define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U 03043b: line 9054 define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U 030465: line 9055 define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U 03048f: line 9056 define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U 0304b9: line 9057 define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U 0304e3: line 9058 define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U 03050d: line 9059 define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U 030537: line 9060 define USB_OTG_DTHRCTL_RXTHREN 0x00010000U 03055e: line 9062 define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U 030586: line 9063 define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U 0305b0: line 9064 define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U 0305da: line 9065 define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U 030604: line 9066 define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U 03062e: line 9067 define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U 030658: line 9068 define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U 030682: line 9069 define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U 0306ac: line 9070 define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U 0306d6: line 9071 define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U 030700: line 9072 define USB_OTG_DTHRCTL_ARPEN 0x08000000U 030725: line 9075 define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU 030751: line 9078 define USB_OTG_DEACHINT_IEP1INT 0x00000002U 030779: line 9079 define USB_OTG_DEACHINT_OEP1INT 0x00020000U 0307a1: line 9082 define USB_OTG_GCCFG_PWRDWN 0x00010000U 0307c5: line 9083 define USB_OTG_GCCFG_VBDEN 0x00200000U 0307e8: line 9086 define USB_OTG_GPWRDN_ADPMEN 0x00000001U 03080d: line 9087 define USB_OTG_GPWRDN_ADPIF 0x00800000U 030831: line 9090 define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U 03085d: line 9091 define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U 030889: line 9094 define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU 0308af: line 9097 define USB_OTG_GLPMCFG_LPMEN 0x00000001U 0308d4: line 9098 define USB_OTG_GLPMCFG_LPMACK 0x00000002U 0308fa: line 9099 define USB_OTG_GLPMCFG_BESL 0x0000003CU 03091e: line 9100 define USB_OTG_GLPMCFG_REMWAKE 0x00000040U 030945: line 9101 define USB_OTG_GLPMCFG_L1SSEN 0x00000080U 03096b: line 9102 define USB_OTG_GLPMCFG_BESLTHRS 0x00000F00U 030993: line 9103 define USB_OTG_GLPMCFG_L1DSEN 0x00001000U 0309b9: line 9104 define USB_OTG_GLPMCFG_LPMRSP 0x00006000U 0309df: line 9105 define USB_OTG_GLPMCFG_SLPSTS 0x00008000U 030a05: line 9106 define USB_OTG_GLPMCFG_L1RSMOK 0x00010000U 030a2c: line 9107 define USB_OTG_GLPMCFG_LPMCHIDX 0x001E0000U 030a54: line 9108 define USB_OTG_GLPMCFG_LPMRCNT 0x00E00000U 030a7b: line 9109 define USB_OTG_GLPMCFG_SNDLPM 0x01000000U 030aa1: line 9110 define USB_OTG_GLPMCFG_LPMRCNTSTS 0x0E000000U 030acb: line 9111 define USB_OTG_GLPMCFG_ENBESL 0x10000000U 030af1: line 9114 define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U 030b1b: line 9115 define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U 030b44: line 9116 define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U 030b6c: line 9117 define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U 030b9a: line 9118 define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U 030bc6: line 9119 define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U 030bf2: line 9120 define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U 030c1d: line 9121 define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U 030c45: line 9122 define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U 030c6e: line 9125 define USB_OTG_HPRT_PCSTS 0x00000001U 030c90: line 9126 define USB_OTG_HPRT_PCDET 0x00000002U 030cb2: line 9127 define USB_OTG_HPRT_PENA 0x00000004U 030cd3: line 9128 define USB_OTG_HPRT_PENCHNG 0x00000008U 030cf7: line 9129 define USB_OTG_HPRT_POCA 0x00000010U 030d18: line 9130 define USB_OTG_HPRT_POCCHNG 0x00000020U 030d3c: line 9131 define USB_OTG_HPRT_PRES 0x00000040U 030d5d: line 9132 define USB_OTG_HPRT_PSUSP 0x00000080U 030d7f: line 9133 define USB_OTG_HPRT_PRST 0x00000100U 030da0: line 9135 define USB_OTG_HPRT_PLSTS 0x00000C00U 030dc2: line 9136 define USB_OTG_HPRT_PLSTS_0 0x00000400U 030de6: line 9137 define USB_OTG_HPRT_PLSTS_1 0x00000800U 030e0a: line 9138 define USB_OTG_HPRT_PPWR 0x00001000U 030e2b: line 9140 define USB_OTG_HPRT_PTCTL 0x0001E000U 030e4d: line 9141 define USB_OTG_HPRT_PTCTL_0 0x00002000U 030e71: line 9142 define USB_OTG_HPRT_PTCTL_1 0x00004000U 030e95: line 9143 define USB_OTG_HPRT_PTCTL_2 0x00008000U 030eb9: line 9144 define USB_OTG_HPRT_PTCTL_3 0x00010000U 030edd: line 9146 define USB_OTG_HPRT_PSPD 0x00060000U 030efe: line 9147 define USB_OTG_HPRT_PSPD_0 0x00020000U 030f21: line 9148 define USB_OTG_HPRT_PSPD_1 0x00040000U 030f44: line 9151 define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U 030f6e: line 9152 define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U 030f97: line 9153 define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U 030fbf: line 9154 define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U 030fed: line 9155 define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U 031019: line 9156 define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U 031045: line 9157 define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U 031070: line 9158 define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U 031098: line 9159 define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U 0310c2: line 9160 define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U 0310eb: line 9161 define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U 031115: line 9164 define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU 03113b: line 9165 define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U 031161: line 9168 define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU 031186: line 9169 define USB_OTG_DIEPCTL_USBAEP 0x00008000U 0311ac: line 9170 define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U 0311d6: line 9171 define USB_OTG_DIEPCTL_NAKSTS 0x00020000U 0311fc: line 9173 define USB_OTG_DIEPCTL_EPTYP 0x000C0000U 031221: line 9174 define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U 031248: line 9175 define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U 03126f: line 9176 define USB_OTG_DIEPCTL_STALL 0x00200000U 031294: line 9178 define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U 0312ba: line 9179 define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U 0312e2: line 9180 define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U 03130a: line 9181 define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U 031332: line 9182 define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U 03135a: line 9183 define USB_OTG_DIEPCTL_CNAK 0x04000000U 03137e: line 9184 define USB_OTG_DIEPCTL_SNAK 0x08000000U 0313a2: line 9185 define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U 0313d0: line 9186 define USB_OTG_DIEPCTL_SODDFRM 0x20000000U 0313f7: line 9187 define USB_OTG_DIEPCTL_EPDIS 0x40000000U 03141c: line 9188 define USB_OTG_DIEPCTL_EPENA 0x80000000U 031441: line 9191 define USB_OTG_HCCHAR_MPSIZ 0x000007FFU 031465: line 9193 define USB_OTG_HCCHAR_EPNUM 0x00007800U 031489: line 9194 define USB_OTG_HCCHAR_EPNUM_0 0x00000800U 0314af: line 9195 define USB_OTG_HCCHAR_EPNUM_1 0x00001000U 0314d5: line 9196 define USB_OTG_HCCHAR_EPNUM_2 0x00002000U 0314fb: line 9197 define USB_OTG_HCCHAR_EPNUM_3 0x00004000U 031521: line 9198 define USB_OTG_HCCHAR_EPDIR 0x00008000U 031545: line 9199 define USB_OTG_HCCHAR_LSDEV 0x00020000U 031569: line 9201 define USB_OTG_HCCHAR_EPTYP 0x000C0000U 03158d: line 9202 define USB_OTG_HCCHAR_EPTYP_0 0x00040000U 0315b3: line 9203 define USB_OTG_HCCHAR_EPTYP_1 0x00080000U 0315d9: line 9205 define USB_OTG_HCCHAR_MC 0x00300000U 0315fa: line 9206 define USB_OTG_HCCHAR_MC_0 0x00100000U 03161d: line 9207 define USB_OTG_HCCHAR_MC_1 0x00200000U 031640: line 9209 define USB_OTG_HCCHAR_DAD 0x1FC00000U 031662: line 9210 define USB_OTG_HCCHAR_DAD_0 0x00400000U 031686: line 9211 define USB_OTG_HCCHAR_DAD_1 0x00800000U 0316aa: line 9212 define USB_OTG_HCCHAR_DAD_2 0x01000000U 0316ce: line 9213 define USB_OTG_HCCHAR_DAD_3 0x02000000U 0316f2: line 9214 define USB_OTG_HCCHAR_DAD_4 0x04000000U 031716: line 9215 define USB_OTG_HCCHAR_DAD_5 0x08000000U 03173a: line 9216 define USB_OTG_HCCHAR_DAD_6 0x10000000U 03175e: line 9217 define USB_OTG_HCCHAR_ODDFRM 0x20000000U 031783: line 9218 define USB_OTG_HCCHAR_CHDIS 0x40000000U 0317a7: line 9219 define USB_OTG_HCCHAR_CHENA 0x80000000U 0317cb: line 9223 define USB_OTG_HCSPLT_PRTADDR 0x0000007FU 0317f1: line 9224 define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U 031819: line 9225 define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U 031841: line 9226 define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U 031869: line 9227 define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U 031891: line 9228 define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U 0318b9: line 9229 define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U 0318e1: line 9230 define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U 031909: line 9232 define USB_OTG_HCSPLT_HUBADDR 0x00003F80U 03192f: line 9233 define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U 031957: line 9234 define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U 03197f: line 9235 define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U 0319a7: line 9236 define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U 0319cf: line 9237 define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U 0319f7: line 9238 define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U 031a1f: line 9239 define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U 031a47: line 9241 define USB_OTG_HCSPLT_XACTPOS 0x0000C000U 031a6d: line 9242 define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U 031a95: line 9243 define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U 031abd: line 9244 define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U 031ae5: line 9245 define USB_OTG_HCSPLT_SPLITEN 0x80000000U 031b0b: line 9248 define USB_OTG_HCINT_XFRC 0x00000001U 031b2d: line 9249 define USB_OTG_HCINT_CHH 0x00000002U 031b4e: line 9250 define USB_OTG_HCINT_AHBERR 0x00000004U 031b72: line 9251 define USB_OTG_HCINT_STALL 0x00000008U 031b95: line 9252 define USB_OTG_HCINT_NAK 0x00000010U 031bb6: line 9253 define USB_OTG_HCINT_ACK 0x00000020U 031bd7: line 9254 define USB_OTG_HCINT_NYET 0x00000040U 031bf9: line 9255 define USB_OTG_HCINT_TXERR 0x00000080U 031c1c: line 9256 define USB_OTG_HCINT_BBERR 0x00000100U 031c3f: line 9257 define USB_OTG_HCINT_FRMOR 0x00000200U 031c62: line 9258 define USB_OTG_HCINT_DTERR 0x00000400U 031c85: line 9261 define USB_OTG_DIEPINT_XFRC 0x00000001U 031ca9: line 9262 define USB_OTG_DIEPINT_EPDISD 0x00000002U 031ccf: line 9263 define USB_OTG_DIEPINT_TOC 0x00000008U 031cf2: line 9264 define USB_OTG_DIEPINT_ITTXFE 0x00000010U 031d18: line 9265 define USB_OTG_DIEPINT_INEPNE 0x00000040U 031d3e: line 9266 define USB_OTG_DIEPINT_TXFE 0x00000080U 031d62: line 9267 define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U 031d8c: line 9268 define USB_OTG_DIEPINT_BNA 0x00000200U 031daf: line 9269 define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U 031dd8: line 9270 define USB_OTG_DIEPINT_BERR 0x00001000U 031dfc: line 9271 define USB_OTG_DIEPINT_NAK 0x00002000U 031e1f: line 9274 define USB_OTG_HCINTMSK_XFRCM 0x00000001U 031e45: line 9275 define USB_OTG_HCINTMSK_CHHM 0x00000002U 031e6a: line 9276 define USB_OTG_HCINTMSK_AHBERR 0x00000004U 031e91: line 9277 define USB_OTG_HCINTMSK_STALLM 0x00000008U 031eb8: line 9278 define USB_OTG_HCINTMSK_NAKM 0x00000010U 031edd: line 9279 define USB_OTG_HCINTMSK_ACKM 0x00000020U 031f02: line 9280 define USB_OTG_HCINTMSK_NYET 0x00000040U 031f27: line 9281 define USB_OTG_HCINTMSK_TXERRM 0x00000080U 031f4e: line 9282 define USB_OTG_HCINTMSK_BBERRM 0x00000100U 031f75: line 9283 define USB_OTG_HCINTMSK_FRMORM 0x00000200U 031f9c: line 9284 define USB_OTG_HCINTMSK_DTERRM 0x00000400U 031fc3: line 9288 define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU 031fea: line 9289 define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U 032011: line 9290 define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U 032038: line 9292 define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU 03205d: line 9293 define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U 032082: line 9294 define USB_OTG_HCTSIZ_DOPING 0x80000000U 0320a7: line 9295 define USB_OTG_HCTSIZ_DPID 0x60000000U 0320ca: line 9296 define USB_OTG_HCTSIZ_DPID_0 0x20000000U 0320ef: line 9297 define USB_OTG_HCTSIZ_DPID_1 0x40000000U 032114: line 9300 define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU 03213b: line 9303 define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU 032160: line 9306 define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU 032189: line 9309 define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU 0321b1: line 9310 define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U 0321d9: line 9313 define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU 0321fe: line 9314 define USB_OTG_DOEPCTL_USBAEP 0x00008000U 032224: line 9315 define USB_OTG_DOEPCTL_NAKSTS 0x00020000U 03224a: line 9316 define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U 032278: line 9317 define USB_OTG_DOEPCTL_SODDFRM 0x20000000U 03229f: line 9318 define USB_OTG_DOEPCTL_EPTYP 0x000C0000U 0322c4: line 9319 define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U 0322eb: line 9320 define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U 032312: line 9321 define USB_OTG_DOEPCTL_SNPM 0x00100000U 032336: line 9322 define USB_OTG_DOEPCTL_STALL 0x00200000U 03235b: line 9323 define USB_OTG_DOEPCTL_CNAK 0x04000000U 03237f: line 9324 define USB_OTG_DOEPCTL_SNAK 0x08000000U 0323a3: line 9325 define USB_OTG_DOEPCTL_EPDIS 0x40000000U 0323c8: line 9326 define USB_OTG_DOEPCTL_EPENA 0x80000000U 0323ed: line 9329 define USB_OTG_DOEPINT_XFRC 0x00000001U 032411: line 9330 define USB_OTG_DOEPINT_EPDISD 0x00000002U 032437: line 9331 define USB_OTG_DOEPINT_STUP 0x00000008U 03245b: line 9332 define USB_OTG_DOEPINT_OTEPDIS 0x00000010U 032482: line 9333 define USB_OTG_DOEPINT_OTEPSPR 0x00000020U 0324a9: line 9334 define USB_OTG_DOEPINT_B2BSTUP 0x00000040U 0324d0: line 9335 define USB_OTG_DOEPINT_NYET 0x00004000U 0324f4: line 9338 define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU 03251b: line 9339 define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U 032542: line 9341 define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U 03256a: line 9342 define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U 032594: line 9343 define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U 0325be: line 9346 define USB_OTG_PCGCCTL_STOPCLK 0x00000001U 0325e5: line 9347 define USB_OTG_PCGCCTL_GATECLK 0x00000002U 03260c: line 9348 define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U 032633: line 9357 define JPEG_CONFR0_START 0x00000001U 032654: line 9360 define JPEG_CONFR1_NF 0x00000003U 032672: line 9361 define JPEG_CONFR1_NF_0 0x00000001U 032692: line 9362 define JPEG_CONFR1_NF_1 0x00000002U 0326b2: line 9363 define JPEG_CONFR1_RE 0x00000004U 0326d0: line 9364 define JPEG_CONFR1_DE 0x00000008U 0326ee: line 9365 define JPEG_CONFR1_COLORSPACE 0x00000030U 032714: line 9366 define JPEG_CONFR1_COLORSPACE_0 0x00000010U 03273c: line 9367 define JPEG_CONFR1_COLORSPACE_1 0x00000020U 032764: line 9368 define JPEG_CONFR1_NS 0x000000C0U 032782: line 9369 define JPEG_CONFR1_NS_0 0x00000040U 0327a2: line 9370 define JPEG_CONFR1_NS_1 0x00000080U 0327c2: line 9371 define JPEG_CONFR1_HDR 0x00000100U 0327e1: line 9372 define JPEG_CONFR1_YSIZE 0xFFFF0000U 032802: line 9375 define JPEG_CONFR2_NMCU 0x03FFFFFFU 032822: line 9378 define JPEG_CONFR3_NRST 0x0000FFFFU 032842: line 9379 define JPEG_CONFR3_XSIZE 0xFFFF0000U 032863: line 9382 define JPEG_CONFR4_HD 0x00000001U 032881: line 9383 define JPEG_CONFR4_HA 0x00000002U 03289f: line 9384 define JPEG_CONFR4_QT 0x0000000CU 0328bd: line 9385 define JPEG_CONFR4_QT_0 0x00000004U 0328dd: line 9386 define JPEG_CONFR4_QT_1 0x00000008U 0328fd: line 9387 define JPEG_CONFR4_NB 0x000000F0U 03291b: line 9388 define JPEG_CONFR4_NB_0 0x00000010U 03293b: line 9389 define JPEG_CONFR4_NB_1 0x00000020U 03295b: line 9390 define JPEG_CONFR4_NB_2 0x00000040U 03297b: line 9391 define JPEG_CONFR4_NB_3 0x00000080U 03299b: line 9392 define JPEG_CONFR4_VSF 0x00000F00U 0329ba: line 9393 define JPEG_CONFR4_VSF_0 0x00000100U 0329db: line 9394 define JPEG_CONFR4_VSF_1 0x00000200U 0329fc: line 9395 define JPEG_CONFR4_VSF_2 0x00000400U 032a1d: line 9396 define JPEG_CONFR4_VSF_3 0x00000800U 032a3e: line 9397 define JPEG_CONFR4_HSF 0x0000F000U 032a5d: line 9398 define JPEG_CONFR4_HSF_0 0x00001000U 032a7e: line 9399 define JPEG_CONFR4_HSF_1 0x00002000U 032a9f: line 9400 define JPEG_CONFR4_HSF_2 0x00004000U 032ac0: line 9401 define JPEG_CONFR4_HSF_3 0x00008000U 032ae1: line 9404 define JPEG_CONFR5_HD 0x00000001U 032aff: line 9405 define JPEG_CONFR5_HA 0x00000002U 032b1d: line 9406 define JPEG_CONFR5_QT 0x0000000CU 032b3b: line 9407 define JPEG_CONFR5_QT_0 0x00000004U 032b5b: line 9408 define JPEG_CONFR5_QT_1 0x00000008U 032b7b: line 9409 define JPEG_CONFR5_NB 0x000000F0U 032b99: line 9410 define JPEG_CONFR5_NB_0 0x00000010U 032bb9: line 9411 define JPEG_CONFR5_NB_1 0x00000020U 032bd9: line 9412 define JPEG_CONFR5_NB_2 0x00000040U 032bf9: line 9413 define JPEG_CONFR5_NB_3 0x00000080U 032c19: line 9414 define JPEG_CONFR5_VSF 0x00000F00U 032c38: line 9415 define JPEG_CONFR5_VSF_0 0x00000100U 032c59: line 9416 define JPEG_CONFR5_VSF_1 0x00000200U 032c7a: line 9417 define JPEG_CONFR5_VSF_2 0x00000400U 032c9b: line 9418 define JPEG_CONFR5_VSF_3 0x00000800U 032cbc: line 9419 define JPEG_CONFR5_HSF 0x0000F000U 032cdb: line 9420 define JPEG_CONFR5_HSF_0 0x00001000U 032cfc: line 9421 define JPEG_CONFR5_HSF_1 0x00002000U 032d1d: line 9422 define JPEG_CONFR5_HSF_2 0x00004000U 032d3e: line 9423 define JPEG_CONFR5_HSF_3 0x00008000U 032d5f: line 9426 define JPEG_CONFR6_HD 0x00000001U 032d7d: line 9427 define JPEG_CONFR6_HA 0x00000002U 032d9b: line 9428 define JPEG_CONFR6_QT 0x0000000CU 032db9: line 9429 define JPEG_CONFR6_QT_0 0x00000004U 032dd9: line 9430 define JPEG_CONFR6_QT_1 0x00000008U 032df9: line 9431 define JPEG_CONFR6_NB 0x000000F0U 032e17: line 9432 define JPEG_CONFR6_NB_0 0x00000010U 032e37: line 9433 define JPEG_CONFR6_NB_1 0x00000020U 032e57: line 9434 define JPEG_CONFR6_NB_2 0x00000040U 032e77: line 9435 define JPEG_CONFR6_NB_3 0x00000080U 032e97: line 9436 define JPEG_CONFR6_VSF 0x00000F00U 032eb6: line 9437 define JPEG_CONFR6_VSF_0 0x00000100U 032ed7: line 9438 define JPEG_CONFR6_VSF_1 0x00000200U 032ef8: line 9439 define JPEG_CONFR6_VSF_2 0x00000400U 032f19: line 9440 define JPEG_CONFR6_VSF_3 0x00000800U 032f3a: line 9441 define JPEG_CONFR6_HSF 0x0000F000U 032f59: line 9442 define JPEG_CONFR6_HSF_0 0x00001000U 032f7a: line 9443 define JPEG_CONFR6_HSF_1 0x00002000U 032f9b: line 9444 define JPEG_CONFR6_HSF_2 0x00004000U 032fbc: line 9445 define JPEG_CONFR6_HSF_3 0x00008000U 032fdd: line 9448 define JPEG_CONFR7_HD 0x00000001U 032ffb: line 9449 define JPEG_CONFR7_HA 0x00000002U 033019: line 9450 define JPEG_CONFR7_QT 0x0000000CU 033037: line 9451 define JPEG_CONFR7_QT_0 0x00000004U 033057: line 9452 define JPEG_CONFR7_QT_1 0x00000008U 033077: line 9453 define JPEG_CONFR7_NB 0x000000F0U 033095: line 9454 define JPEG_CONFR7_NB_0 0x00000010U 0330b5: line 9455 define JPEG_CONFR7_NB_1 0x00000020U 0330d5: line 9456 define JPEG_CONFR7_NB_2 0x00000040U 0330f5: line 9457 define JPEG_CONFR7_NB_3 0x00000080U 033115: line 9458 define JPEG_CONFR7_VSF 0x00000F00U 033134: line 9459 define JPEG_CONFR7_VSF_0 0x00000100U 033155: line 9460 define JPEG_CONFR7_VSF_1 0x00000200U 033176: line 9461 define JPEG_CONFR7_VSF_2 0x00000400U 033197: line 9462 define JPEG_CONFR7_VSF_3 0x00000800U 0331b8: line 9463 define JPEG_CONFR7_HSF 0x0000F000U 0331d7: line 9464 define JPEG_CONFR7_HSF_0 0x00001000U 0331f8: line 9465 define JPEG_CONFR7_HSF_1 0x00002000U 033219: line 9466 define JPEG_CONFR7_HSF_2 0x00004000U 03323a: line 9467 define JPEG_CONFR7_HSF_3 0x00008000U 03325b: line 9470 define JPEG_CR_JCEN 0x00000001U 033277: line 9471 define JPEG_CR_IFTIE 0x00000002U 033294: line 9472 define JPEG_CR_IFNFIE 0x00000004U 0332b2: line 9473 define JPEG_CR_OFTIE 0x00000008U 0332cf: line 9474 define JPEG_CR_OFNEIE 0x00000010U 0332ed: line 9475 define JPEG_CR_EOCIE 0x00000020U 03330a: line 9476 define JPEG_CR_HPDIE 0x00000040U 033327: line 9477 define JPEG_CR_IDMAEN 0x00000800U 033345: line 9478 define JPEG_CR_ODMAEN 0x00001000U 033363: line 9479 define JPEG_CR_IFF 0x00002000U 03337e: line 9480 define JPEG_CR_OFF 0x00004000U 033399: line 9483 define JPEG_SR_IFTF 0x00000002U 0333b5: line 9484 define JPEG_SR_IFNFF 0x00000004U 0333d2: line 9485 define JPEG_SR_OFTF 0x00000008U 0333ee: line 9486 define JPEG_SR_OFNEF 0x000000010U 03340c: line 9487 define JPEG_SR_EOCF 0x000000020U 033429: line 9488 define JPEG_SR_HPDF 0x000000040U 033446: line 9489 define JPEG_SR_COF 0x000000080U 033462: line 9492 define JPEG_CFR_CEOCF 0x00000020U 033480: line 9493 define JPEG_CFR_CHPDF 0x00000040U 03349e: line 9496 define JPEG_DIR_DATAIN 0xFFFFFFFFU 0334bd: line 9499 define JPEG_DOR_DATAOUT 0xFFFFFFFFU 0334dd: line 9507 define MDIOS_CR_EN 0x00000001U 0334f8: line 9508 define MDIOS_CR_WRIE 0x00000002U 033515: line 9509 define MDIOS_CR_RDIE 0x00000004U 033532: line 9510 define MDIOS_CR_EIE 0x00000008U 03354e: line 9511 define MDIOS_CR_DPC 0x00000080U 03356a: line 9512 define MDIOS_CR_PORT_ADDRESS 0x00001F00U 03358f: line 9513 define MDIOS_CR_PORT_ADDRESS_0 0x00000100U 0335b6: line 9514 define MDIOS_CR_PORT_ADDRESS_1 0x00000200U 0335dd: line 9515 define MDIOS_CR_PORT_ADDRESS_2 0x00000400U 033604: line 9516 define MDIOS_CR_PORT_ADDRESS_3 0x00000800U 03362b: line 9517 define MDIOS_CR_PORT_ADDRESS_4 0x00001000U 033652: line 9520 define MDIOS_WRFR_WRF 0xFFFFFFFFU 033670: line 9523 define MDIOS_CWRFR_CWRF 0xFFFFFFFFU 033690: line 9526 define MDIOS_RDFR_RDF 0xFFFFFFFFU 0336ae: line 9529 define MDIOS_CRDFR_CRDF 0xFFFFFFFFU 0336ce: line 9532 define MDIOS_SR_PERF 0x00000001U 0336eb: line 9533 define MDIOS_SR_SERF 0x00000002U 033708: line 9534 define MDIOS_SR_TERF 0x00000004U 033725: line 9537 define MDIOS_CLRFR_CPERF 0x00000001U 033746: line 9538 define MDIOS_CLRFR_CSERF 0x00000002U 033767: line 9539 define MDIOS_CLRFR_CTERF 0x00000004U 033788: line 9554 define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || ((__INSTANCE__) == ADC2) || ((__INSTANCE__) == ADC3)) 033800: line 9559 define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || ((__INSTANCE__) == CAN2) || ((__INSTANCE__) == CAN3)) 033878: line 9563 define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC) 0338b5: line 9566 define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC) 0338f2: line 9569 define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI) 033931: line 9572 define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || ((INSTANCE) == DFSDM1_Filter1) || ((INSTANCE) == DFSDM1_Filter2) || ((INSTANCE) == DFSDM1_Filter3)) 0339e2: line 9577 define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || ((INSTANCE) == DFSDM1_Channel1) || ((INSTANCE) == DFSDM1_Channel2) || ((INSTANCE) == DFSDM1_Channel3) || ((INSTANCE) == DFSDM1_Channel4) || ((INSTANCE) == DFSDM1_Channel5) || ((INSTANCE) == DFSDM1_Channel6) || ((INSTANCE) == DFSDM1_Channel7)) 033b24: line 9587 define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D) 033b65: line 9590 define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || ((__INSTANCE__) == DMA1_Stream1) || ((__INSTANCE__) == DMA1_Stream2) || ((__INSTANCE__) == DMA1_Stream3) || ((__INSTANCE__) == DMA1_Stream4) || ((__INSTANCE__) == DMA1_Stream5) || ((__INSTANCE__) == DMA1_Stream6) || ((__INSTANCE__) == DMA1_Stream7) || ((__INSTANCE__) == DMA2_Stream0) || ((__INSTANCE__) == DMA2_Stream1) || ((__INSTANCE__) == DMA2_Stream2) || ((__INSTANCE__) == DMA2_Stream3) || ((__INSTANCE__) == DMA2_Stream4) || ((__INSTANCE__) == DMA2_Stream5) || ((__INSTANCE__) == DMA2_Stream6) || ((__INSTANCE__) == DMA2_Stream7)) 033dd0: line 9608 define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || ((__INSTANCE__) == GPIOB) || ((__INSTANCE__) == GPIOC) || ((__INSTANCE__) == GPIOD) || ((__INSTANCE__) == GPIOE) || ((__INSTANCE__) == GPIOF) || ((__INSTANCE__) == GPIOG) || ((__INSTANCE__) == GPIOH) || ((__INSTANCE__) == GPIOI) || ((__INSTANCE__) == GPIOJ) || ((__INSTANCE__) == GPIOK)) 033f34: line 9620 define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || ((__INSTANCE__) == GPIOB) || ((__INSTANCE__) == GPIOC) || ((__INSTANCE__) == GPIOD) || ((__INSTANCE__) == GPIOE) || ((__INSTANCE__) == GPIOF) || ((__INSTANCE__) == GPIOG) || ((__INSTANCE__) == GPIOH) || ((__INSTANCE__) == GPIOI) || ((__INSTANCE__) == GPIOJ) || ((__INSTANCE__) == GPIOK)) 034097: line 9633 define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC) 0340d4: line 9636 define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI) 034116: line 9640 define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || ((__INSTANCE__) == I2C2) || ((__INSTANCE__) == I2C3) || ((__INSTANCE__) == I2C4)) 0341aa: line 9646 define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || ((__INSTANCE__) == SPI2) || ((__INSTANCE__) == SPI3)) 034222: line 9651 define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1) 034260: line 9654 define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC) 03429f: line 9657 define IS_MDIOS_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == MDIOS) 0342e0: line 9660 define IS_JPEG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == JPEG) 03431f: line 9664 define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG) 03435c: line 9667 define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC) 034399: line 9670 define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || ((__PERIPH__) == SAI1_Block_B) || ((__PERIPH__) == SAI2_Block_A) || ((__PERIPH__) == SAI2_Block_B)) 034443: line 9675 define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE 03446e: line 9678 define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SDMMC1) || ((__INSTANCE__) == SDMMC2)) 0344d0: line 9682 define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX) 034515: line 9685 define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || ((__INSTANCE__) == SPI2) || ((__INSTANCE__) == SPI3) || ((__INSTANCE__) == SPI4) || ((__INSTANCE__) == SPI5) || ((__INSTANCE__) == SPI6)) 0345e1: line 9693 define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || ((__INSTANCE__) == TIM2) || ((__INSTANCE__) == TIM3) || ((__INSTANCE__) == TIM4) || ((__INSTANCE__) == TIM5) || ((__INSTANCE__) == TIM6) || ((__INSTANCE__) == TIM7) || ((__INSTANCE__) == TIM8) || ((__INSTANCE__) == TIM9) || ((__INSTANCE__) == TIM10) || ((__INSTANCE__) == TIM11) || ((__INSTANCE__) == TIM12) || ((__INSTANCE__) == TIM13) || ((__INSTANCE__) == TIM14)) 03478e: line 9709 define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || ((__INSTANCE__) == TIM2) || ((__INSTANCE__) == TIM3) || ((__INSTANCE__) == TIM4) || ((__INSTANCE__) == TIM5) || ((__INSTANCE__) == TIM8) || ((__INSTANCE__) == TIM9) || ((__INSTANCE__) == TIM10) || ((__INSTANCE__) == TIM11) || ((__INSTANCE__) == TIM12) || ((__INSTANCE__) == TIM13) || ((__INSTANCE__) == TIM14)) 034907: line 9723 define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || ((__INSTANCE__) == TIM2) || ((__INSTANCE__) == TIM3) || ((__INSTANCE__) == TIM4) || ((__INSTANCE__) == TIM5) || ((__INSTANCE__) == TIM8) || ((__INSTANCE__) == TIM9) || ((__INSTANCE__) == TIM12)) 034a0c: line 9733 define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || ((__INSTANCE__) == TIM2) || ((__INSTANCE__) == TIM3) || ((__INSTANCE__) == TIM4) || ((__INSTANCE__) == TIM5) || ((__INSTANCE__) == TIM8)) 034ad8: line 9741 define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || ((__INSTANCE__) == TIM2) || ((__INSTANCE__) == TIM3) || ((__INSTANCE__) == TIM4) || ((__INSTANCE__) == TIM5) || ((__INSTANCE__) == TIM8)) 034ba4: line 9749 define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || ((__INSTANCE__) == TIM8)) 034c0e: line 9754 define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || ((__INSTANCE__) == TIM2) || ((__INSTANCE__) == TIM3) || ((__INSTANCE__) == TIM4) || ((__INSTANCE__) == TIM8)) 034cc7: line 9762 define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || ((__INSTANCE__) == TIM2) || ((__INSTANCE__) == TIM3) || ((__INSTANCE__) == TIM4) || ((__INSTANCE__) == TIM5) || ((__INSTANCE__) == TIM8)) 034d9f: line 9771 define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || ((__INSTANCE__) == TIM2) || ((__INSTANCE__) == TIM3) || ((__INSTANCE__) == TIM4) || ((__INSTANCE__) == TIM5) || ((__INSTANCE__) == TIM8)) 034e78: line 9779 define IS_TIM_CC5_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || ((__INSTANCE__) == TIM8) ) 034ed5: line 9784 define IS_TIM_CC6_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || ((__INSTANCE__) == TIM8)) 034f31: line 9790 define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || ((__INSTANCE__) == TIM8)) 034f92: line 9794 define IS_TIM_BREAK_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || ((__INSTANCE__) == TIM8)) 034ff0: line 9799 define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || ((__INSTANCE__) == TIM2) || ((__INSTANCE__) == TIM3) || ((__INSTANCE__) == TIM4) || ((__INSTANCE__) == TIM5) || ((__INSTANCE__) == TIM8)) 0350bc: line 9807 define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || ((__INSTANCE__) == TIM2) || ((__INSTANCE__) == TIM3) || ((__INSTANCE__) == TIM4) || ((__INSTANCE__) == TIM5) || ((__INSTANCE__) == TIM6) || ((__INSTANCE__) == TIM7) || ((__INSTANCE__) == TIM8)) 0351c0: line 9817 define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || ((__INSTANCE__) == TIM2) || ((__INSTANCE__) == TIM3) || ((__INSTANCE__) == TIM4) || ((__INSTANCE__) == TIM5) || ((__INSTANCE__) == TIM8)) 03528f: line 9825 define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || ((__INSTANCE__) == TIM2) || ((__INSTANCE__) == TIM3) || ((__INSTANCE__) == TIM4) || ((__INSTANCE__) == TIM5) || ((__INSTANCE__) == TIM8)) 03535d: line 9833 define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || ((__INSTANCE__) == TIM2) || ((__INSTANCE__) == TIM3) || ((__INSTANCE__) == TIM4) || ((__INSTANCE__) == TIM5) || ((__INSTANCE__) == TIM8)) 03542e: line 9841 define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || ((__INSTANCE__) == TIM2) || ((__INSTANCE__) == TIM3) || ((__INSTANCE__) == TIM4) || ((__INSTANCE__) == TIM5) || ((__INSTANCE__) == TIM6) || ((__INSTANCE__) == TIM7) || ((__INSTANCE__) == TIM8) || ((__INSTANCE__) == TIM13) || ((__INSTANCE__) == TIM14)) 03556f: line 9853 define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || ((__INSTANCE__) == TIM2) || ((__INSTANCE__) == TIM3) || ((__INSTANCE__) == TIM4) || ((__INSTANCE__) == TIM5) || ((__INSTANCE__) == TIM8) || ((__INSTANCE__) == TIM9) || ((__INSTANCE__) == TIM12)) 035676: line 9863 define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || ((__INSTANCE__) == TIM5)) 0356da: line 9867 define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || ((__INSTANCE__) == TIM2) || ((__INSTANCE__) == TIM3) || ((__INSTANCE__) == TIM4) || ((__INSTANCE__) == TIM5) || ((__INSTANCE__) == TIM8)) 0357a6: line 9875 define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || ((__INSTANCE__) == TIM5) || ((__INSTANCE__) == TIM11)) 035821: line 9880 define IS_TIM_CCX_INSTANCE(__INSTANCE__,__CHANNEL__) ((((__INSTANCE__) == TIM1) && (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2) || ((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4))) || (((__INSTANCE__) == TIM2) && (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2) || ((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4))) || (((__INSTANCE__) == TIM3) && (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2) || ((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4))) || (((__INSTANCE__) == TIM4) && (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2) || ((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4))) || (((__INSTANCE__) == TIM5) && (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2) || ((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4))) || (((__INSTANCE__) == TIM8) && (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2) || ((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4))) || (((__INSTANCE__) == TIM9) && (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2))) || (((__INSTANCE__) == TIM10) && (((__CHANNEL__) == TIM_CHANNEL_1))) || (((__INSTANCE__) == TIM11) && (((__CHANNEL__) == TIM_CHANNEL_1))) || (((__INSTANCE__) == TIM12) && (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2))) || (((__INSTANCE__) == TIM13) && (((__CHANNEL__) == TIM_CHANNEL_1))) || (((__INSTANCE__) == TIM14) && (((__CHANNEL__) == TIM_CHANNEL_1)))) 035e56: line 9938 define IS_TIM_CCXN_INSTANCE(__INSTANCE__,__CHANNEL__) ((((__INSTANCE__) == TIM1) && (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2) || ((__CHANNEL__) == TIM_CHANNEL_3))) || (((__INSTANCE__) == TIM8) && (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2) || ((__CHANNEL__) == TIM_CHANNEL_3)))) 035f9f: line 9950 define IS_TIM_TRGO2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || ((__INSTANCE__) == TIM8) ) 035ffe: line 9955 define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || ((__INSTANCE__) == TIM2) || ((__INSTANCE__) == TIM3) || ((__INSTANCE__) == TIM4) || ((__INSTANCE__) == TIM5) || ((__INSTANCE__) == TIM6) || ((__INSTANCE__) == TIM7) || ((__INSTANCE__) == TIM8)) 036106: line 9966 define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || ((__INSTANCE__) == USART2) || ((__INSTANCE__) == USART3) || ((__INSTANCE__) == USART6)) 0361a0: line 9972 define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || ((__INSTANCE__) == USART2) || ((__INSTANCE__) == USART3) || ((__INSTANCE__) == UART4) || ((__INSTANCE__) == UART5) || ((__INSTANCE__) == USART6) || ((__INSTANCE__) == UART7) || ((__INSTANCE__) == UART8)) 0362ad: line 9982 define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || ((__INSTANCE__) == USART2) || ((__INSTANCE__) == USART3) || ((__INSTANCE__) == UART4) || ((__INSTANCE__) == UART5) || ((__INSTANCE__) == USART6) || ((__INSTANCE__) == UART7) || ((__INSTANCE__) == UART8)) 0363c8: line 9992 define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || ((__INSTANCE__) == USART2) || ((__INSTANCE__) == USART3) || ((__INSTANCE__) == UART4) || ((__INSTANCE__) == UART5) || ((__INSTANCE__) == USART6) || ((__INSTANCE__) == UART7) || ((__INSTANCE__) == UART8)) 0364dc: line 10002 define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || ((__INSTANCE__) == USART2) || ((__INSTANCE__) == USART3) || ((__INSTANCE__) == USART6)) 03657a: line 10008 define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || ((__INSTANCE__) == USART2) || ((__INSTANCE__) == USART3) || ((__INSTANCE__) == UART4) || ((__INSTANCE__) == UART5) || ((__INSTANCE__) == USART6) || ((__INSTANCE__) == UART7) || ((__INSTANCE__) == UART8)) 036687: line 10018 define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG) 0366c6: line 10021 define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG) 036705: line 10033 define HASH_RNG_IRQn RNG_IRQn 03671f: line 10036 define HASH_RNG_IRQHandler RNG_IRQHandler 036745: end include 036746: end of translation unit ** Section #56 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 236 bytes 000000: Header: length 232 (not including this field) version 3 prologue length 223 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\CMSIS\Device\ST\STM32F7xx\Include\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 43 4d 53 49 53 5c 44 65 76 69 63 65 5c 53 54 5c 53 54 4d 33 32 46 37 78 78 5c 49 6e 63 6c 75 64 65 5c 00 00004e: directory "..\..\Libraries\CMSIS\Include\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 43 4d 53 49 53 5c 49 6e 63 6c 75 64 65 5c 00 00006d: directory "D:\Program Files (x86)\Keil_v5\ARM\ARMCC\Bin\..\include\": 44 3a 5c 50 72 6f 67 72 61 6d 20 46 69 6c 65 73 20 28 78 38 36 29 5c 4b 65 69 6c 5f 76 35 5c 41 52 4d 5c 41 52 4d 43 43 5c 42 69 6e 5c 2e 2e 5c 69 6e 63 6c 75 64 65 5c 00 0000a6: directory "" : 00 0000a7: file "stm32f767xx.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 36 37 78 78 2e 68 00 01 00 00 0000b8: file "core_cm7.h": dir 2 time 0x0 length 0: 63 6f 72 65 5f 63 6d 37 2e 68 00 02 00 00 0000c6: file "system_stm32f7xx.h": dir 1 time 0x0 length 0: 73 79 73 74 65 6d 5f 73 74 6d 33 32 66 37 78 78 2e 68 00 01 00 00 0000dc: file "stdint.h": dir 3 time 0x0 length 0: 73 74 64 69 6e 74 2e 68 00 03 00 00 0000e8: file "" : 00 0000e9: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\CMSIS\Device\ST\STM32F7xx\Include\stm32f767xx.h:1.0 ** Section #57 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 13724 bytes 000000: Header: size 0x3598 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\CMSIS\Device\ST\STM32F7xx\Include\stm32f767xx.h 00004c: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000093: DW_AT_language DW_LANG_C89 000095: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010c: DW_AT_macro_info 0x0 000110: DW_AT_stmt_list 0x0 000114: 19 = 0x4 (DW_TAG_enumeration_type) 000115: DW_AT_sibling 0x86c 000117: DW_AT_byte_size 0x1 000118: 21 = 0x28 (DW_TAG_enumerator) 000119: DW_AT_name NonMaskableInt_IRQn 00012d: DW_AT_const_value -0xe 00012e: 21 = 0x28 (DW_TAG_enumerator) 00012f: DW_AT_name MemoryManagement_IRQn 000145: DW_AT_const_value -0xc 000146: 21 = 0x28 (DW_TAG_enumerator) 000147: DW_AT_name BusFault_IRQn 000155: DW_AT_const_value -0xb 000156: 21 = 0x28 (DW_TAG_enumerator) 000157: DW_AT_name UsageFault_IRQn 000167: DW_AT_const_value -0xa 000168: 21 = 0x28 (DW_TAG_enumerator) 000169: DW_AT_name SVCall_IRQn 000175: DW_AT_const_value -0x5 000176: 21 = 0x28 (DW_TAG_enumerator) 000177: DW_AT_name DebugMonitor_IRQn 000189: DW_AT_const_value -0x4 00018a: 21 = 0x28 (DW_TAG_enumerator) 00018b: DW_AT_name PendSV_IRQn 000197: DW_AT_const_value -0x2 000198: 21 = 0x28 (DW_TAG_enumerator) 000199: DW_AT_name SysTick_IRQn 0001a6: DW_AT_const_value -0x1 0001a7: 21 = 0x28 (DW_TAG_enumerator) 0001a8: DW_AT_name WWDG_IRQn 0001b2: DW_AT_const_value 0x0 0001b3: 21 = 0x28 (DW_TAG_enumerator) 0001b4: DW_AT_name PVD_IRQn 0001bd: DW_AT_const_value 0x1 0001be: 21 = 0x28 (DW_TAG_enumerator) 0001bf: DW_AT_name TAMP_STAMP_IRQn 0001cf: DW_AT_const_value 0x2 0001d0: 21 = 0x28 (DW_TAG_enumerator) 0001d1: DW_AT_name RTC_WKUP_IRQn 0001df: DW_AT_const_value 0x3 0001e0: 21 = 0x28 (DW_TAG_enumerator) 0001e1: DW_AT_name FLASH_IRQn 0001ec: DW_AT_const_value 0x4 0001ed: 21 = 0x28 (DW_TAG_enumerator) 0001ee: DW_AT_name RCC_IRQn 0001f7: DW_AT_const_value 0x5 0001f8: 21 = 0x28 (DW_TAG_enumerator) 0001f9: DW_AT_name EXTI0_IRQn 000204: DW_AT_const_value 0x6 000205: 21 = 0x28 (DW_TAG_enumerator) 000206: DW_AT_name EXTI1_IRQn 000211: DW_AT_const_value 0x7 000212: 21 = 0x28 (DW_TAG_enumerator) 000213: DW_AT_name EXTI2_IRQn 00021e: DW_AT_const_value 0x8 00021f: 21 = 0x28 (DW_TAG_enumerator) 000220: DW_AT_name EXTI3_IRQn 00022b: DW_AT_const_value 0x9 00022c: 21 = 0x28 (DW_TAG_enumerator) 00022d: DW_AT_name EXTI4_IRQn 000238: DW_AT_const_value 0xa 000239: 21 = 0x28 (DW_TAG_enumerator) 00023a: DW_AT_name DMA1_Stream0_IRQn 00024c: DW_AT_const_value 0xb 00024d: 21 = 0x28 (DW_TAG_enumerator) 00024e: DW_AT_name DMA1_Stream1_IRQn 000260: DW_AT_const_value 0xc 000261: 21 = 0x28 (DW_TAG_enumerator) 000262: DW_AT_name DMA1_Stream2_IRQn 000274: DW_AT_const_value 0xd 000275: 21 = 0x28 (DW_TAG_enumerator) 000276: DW_AT_name DMA1_Stream3_IRQn 000288: DW_AT_const_value 0xe 000289: 21 = 0x28 (DW_TAG_enumerator) 00028a: DW_AT_name DMA1_Stream4_IRQn 00029c: DW_AT_const_value 0xf 00029d: 21 = 0x28 (DW_TAG_enumerator) 00029e: DW_AT_name DMA1_Stream5_IRQn 0002b0: DW_AT_const_value 0x10 0002b1: 21 = 0x28 (DW_TAG_enumerator) 0002b2: DW_AT_name DMA1_Stream6_IRQn 0002c4: DW_AT_const_value 0x11 0002c5: 21 = 0x28 (DW_TAG_enumerator) 0002c6: DW_AT_name ADC_IRQn 0002cf: DW_AT_const_value 0x12 0002d0: 21 = 0x28 (DW_TAG_enumerator) 0002d1: DW_AT_name CAN1_TX_IRQn 0002de: DW_AT_const_value 0x13 0002df: 21 = 0x28 (DW_TAG_enumerator) 0002e0: DW_AT_name CAN1_RX0_IRQn 0002ee: DW_AT_const_value 0x14 0002ef: 21 = 0x28 (DW_TAG_enumerator) 0002f0: DW_AT_name CAN1_RX1_IRQn 0002fe: DW_AT_const_value 0x15 0002ff: 21 = 0x28 (DW_TAG_enumerator) 000300: DW_AT_name CAN1_SCE_IRQn 00030e: DW_AT_const_value 0x16 00030f: 21 = 0x28 (DW_TAG_enumerator) 000310: DW_AT_name EXTI9_5_IRQn 00031d: DW_AT_const_value 0x17 00031e: 21 = 0x28 (DW_TAG_enumerator) 00031f: DW_AT_name TIM1_BRK_TIM9_IRQn 000332: DW_AT_const_value 0x18 000333: 21 = 0x28 (DW_TAG_enumerator) 000334: DW_AT_name TIM1_UP_TIM10_IRQn 000347: DW_AT_const_value 0x19 000348: 21 = 0x28 (DW_TAG_enumerator) 000349: DW_AT_name TIM1_TRG_COM_TIM11_IRQn 000361: DW_AT_const_value 0x1a 000362: 21 = 0x28 (DW_TAG_enumerator) 000363: DW_AT_name TIM1_CC_IRQn 000370: DW_AT_const_value 0x1b 000371: 21 = 0x28 (DW_TAG_enumerator) 000372: DW_AT_name TIM2_IRQn 00037c: DW_AT_const_value 0x1c 00037d: 21 = 0x28 (DW_TAG_enumerator) 00037e: DW_AT_name TIM3_IRQn 000388: DW_AT_const_value 0x1d 000389: 21 = 0x28 (DW_TAG_enumerator) 00038a: DW_AT_name TIM4_IRQn 000394: DW_AT_const_value 0x1e 000395: 21 = 0x28 (DW_TAG_enumerator) 000396: DW_AT_name I2C1_EV_IRQn 0003a3: DW_AT_const_value 0x1f 0003a4: 21 = 0x28 (DW_TAG_enumerator) 0003a5: DW_AT_name I2C1_ER_IRQn 0003b2: DW_AT_const_value 0x20 0003b3: 21 = 0x28 (DW_TAG_enumerator) 0003b4: DW_AT_name I2C2_EV_IRQn 0003c1: DW_AT_const_value 0x21 0003c2: 21 = 0x28 (DW_TAG_enumerator) 0003c3: DW_AT_name I2C2_ER_IRQn 0003d0: DW_AT_const_value 0x22 0003d1: 21 = 0x28 (DW_TAG_enumerator) 0003d2: DW_AT_name SPI1_IRQn 0003dc: DW_AT_const_value 0x23 0003dd: 21 = 0x28 (DW_TAG_enumerator) 0003de: DW_AT_name SPI2_IRQn 0003e8: DW_AT_const_value 0x24 0003e9: 21 = 0x28 (DW_TAG_enumerator) 0003ea: DW_AT_name USART1_IRQn 0003f6: DW_AT_const_value 0x25 0003f7: 21 = 0x28 (DW_TAG_enumerator) 0003f8: DW_AT_name USART2_IRQn 000404: DW_AT_const_value 0x26 000405: 21 = 0x28 (DW_TAG_enumerator) 000406: DW_AT_name USART3_IRQn 000412: DW_AT_const_value 0x27 000413: 21 = 0x28 (DW_TAG_enumerator) 000414: DW_AT_name EXTI15_10_IRQn 000423: DW_AT_const_value 0x28 000424: 21 = 0x28 (DW_TAG_enumerator) 000425: DW_AT_name RTC_Alarm_IRQn 000434: DW_AT_const_value 0x29 000435: 21 = 0x28 (DW_TAG_enumerator) 000436: DW_AT_name OTG_FS_WKUP_IRQn 000447: DW_AT_const_value 0x2a 000448: 21 = 0x28 (DW_TAG_enumerator) 000449: DW_AT_name TIM8_BRK_TIM12_IRQn 00045d: DW_AT_const_value 0x2b 00045e: 21 = 0x28 (DW_TAG_enumerator) 00045f: DW_AT_name TIM8_UP_TIM13_IRQn 000472: DW_AT_const_value 0x2c 000473: 21 = 0x28 (DW_TAG_enumerator) 000474: DW_AT_name TIM8_TRG_COM_TIM14_IRQn 00048c: DW_AT_const_value 0x2d 00048d: 21 = 0x28 (DW_TAG_enumerator) 00048e: DW_AT_name TIM8_CC_IRQn 00049b: DW_AT_const_value 0x2e 00049c: 21 = 0x28 (DW_TAG_enumerator) 00049d: DW_AT_name DMA1_Stream7_IRQn 0004af: DW_AT_const_value 0x2f 0004b0: 21 = 0x28 (DW_TAG_enumerator) 0004b1: DW_AT_name FMC_IRQn 0004ba: DW_AT_const_value 0x30 0004bb: 21 = 0x28 (DW_TAG_enumerator) 0004bc: DW_AT_name SDMMC1_IRQn 0004c8: DW_AT_const_value 0x31 0004c9: 21 = 0x28 (DW_TAG_enumerator) 0004ca: DW_AT_name TIM5_IRQn 0004d4: DW_AT_const_value 0x32 0004d5: 21 = 0x28 (DW_TAG_enumerator) 0004d6: DW_AT_name SPI3_IRQn 0004e0: DW_AT_const_value 0x33 0004e1: 21 = 0x28 (DW_TAG_enumerator) 0004e2: DW_AT_name UART4_IRQn 0004ed: DW_AT_const_value 0x34 0004ee: 21 = 0x28 (DW_TAG_enumerator) 0004ef: DW_AT_name UART5_IRQn 0004fa: DW_AT_const_value 0x35 0004fb: 21 = 0x28 (DW_TAG_enumerator) 0004fc: DW_AT_name TIM6_DAC_IRQn 00050a: DW_AT_const_value 0x36 00050b: 21 = 0x28 (DW_TAG_enumerator) 00050c: DW_AT_name TIM7_IRQn 000516: DW_AT_const_value 0x37 000517: 21 = 0x28 (DW_TAG_enumerator) 000518: DW_AT_name DMA2_Stream0_IRQn 00052a: DW_AT_const_value 0x38 00052b: 21 = 0x28 (DW_TAG_enumerator) 00052c: DW_AT_name DMA2_Stream1_IRQn 00053e: DW_AT_const_value 0x39 00053f: 21 = 0x28 (DW_TAG_enumerator) 000540: DW_AT_name DMA2_Stream2_IRQn 000552: DW_AT_const_value 0x3a 000553: 21 = 0x28 (DW_TAG_enumerator) 000554: DW_AT_name DMA2_Stream3_IRQn 000566: DW_AT_const_value 0x3b 000567: 21 = 0x28 (DW_TAG_enumerator) 000568: DW_AT_name DMA2_Stream4_IRQn 00057a: DW_AT_const_value 0x3c 00057b: 21 = 0x28 (DW_TAG_enumerator) 00057c: DW_AT_name ETH_IRQn 000585: DW_AT_const_value 0x3d 000586: 21 = 0x28 (DW_TAG_enumerator) 000587: DW_AT_name ETH_WKUP_IRQn 000595: DW_AT_const_value 0x3e 000596: 21 = 0x28 (DW_TAG_enumerator) 000597: DW_AT_name CAN2_TX_IRQn 0005a4: DW_AT_const_value 0x3f 0005a5: 21 = 0x28 (DW_TAG_enumerator) 0005a6: DW_AT_name CAN2_RX0_IRQn 0005b4: DW_AT_const_value 0x40 0005b6: 21 = 0x28 (DW_TAG_enumerator) 0005b7: DW_AT_name CAN2_RX1_IRQn 0005c5: DW_AT_const_value 0x41 0005c7: 21 = 0x28 (DW_TAG_enumerator) 0005c8: DW_AT_name CAN2_SCE_IRQn 0005d6: DW_AT_const_value 0x42 0005d8: 21 = 0x28 (DW_TAG_enumerator) 0005d9: DW_AT_name OTG_FS_IRQn 0005e5: DW_AT_const_value 0x43 0005e7: 21 = 0x28 (DW_TAG_enumerator) 0005e8: DW_AT_name DMA2_Stream5_IRQn 0005fa: DW_AT_const_value 0x44 0005fc: 21 = 0x28 (DW_TAG_enumerator) 0005fd: DW_AT_name DMA2_Stream6_IRQn 00060f: DW_AT_const_value 0x45 000611: 21 = 0x28 (DW_TAG_enumerator) 000612: DW_AT_name DMA2_Stream7_IRQn 000624: DW_AT_const_value 0x46 000626: 21 = 0x28 (DW_TAG_enumerator) 000627: DW_AT_name USART6_IRQn 000633: DW_AT_const_value 0x47 000635: 21 = 0x28 (DW_TAG_enumerator) 000636: DW_AT_name I2C3_EV_IRQn 000643: DW_AT_const_value 0x48 000645: 21 = 0x28 (DW_TAG_enumerator) 000646: DW_AT_name I2C3_ER_IRQn 000653: DW_AT_const_value 0x49 000655: 21 = 0x28 (DW_TAG_enumerator) 000656: DW_AT_name OTG_HS_EP1_OUT_IRQn 00066a: DW_AT_const_value 0x4a 00066c: 21 = 0x28 (DW_TAG_enumerator) 00066d: DW_AT_name OTG_HS_EP1_IN_IRQn 000680: DW_AT_const_value 0x4b 000682: 21 = 0x28 (DW_TAG_enumerator) 000683: DW_AT_name OTG_HS_WKUP_IRQn 000694: DW_AT_const_value 0x4c 000696: 21 = 0x28 (DW_TAG_enumerator) 000697: DW_AT_name OTG_HS_IRQn 0006a3: DW_AT_const_value 0x4d 0006a5: 21 = 0x28 (DW_TAG_enumerator) 0006a6: DW_AT_name DCMI_IRQn 0006b0: DW_AT_const_value 0x4e 0006b2: 21 = 0x28 (DW_TAG_enumerator) 0006b3: DW_AT_name RNG_IRQn 0006bc: DW_AT_const_value 0x50 0006be: 21 = 0x28 (DW_TAG_enumerator) 0006bf: DW_AT_name FPU_IRQn 0006c8: DW_AT_const_value 0x51 0006ca: 21 = 0x28 (DW_TAG_enumerator) 0006cb: DW_AT_name UART7_IRQn 0006d6: DW_AT_const_value 0x52 0006d8: 21 = 0x28 (DW_TAG_enumerator) 0006d9: DW_AT_name UART8_IRQn 0006e4: DW_AT_const_value 0x53 0006e6: 21 = 0x28 (DW_TAG_enumerator) 0006e7: DW_AT_name SPI4_IRQn 0006f1: DW_AT_const_value 0x54 0006f3: 21 = 0x28 (DW_TAG_enumerator) 0006f4: DW_AT_name SPI5_IRQn 0006fe: DW_AT_const_value 0x55 000700: 21 = 0x28 (DW_TAG_enumerator) 000701: DW_AT_name SPI6_IRQn 00070b: DW_AT_const_value 0x56 00070d: 21 = 0x28 (DW_TAG_enumerator) 00070e: DW_AT_name SAI1_IRQn 000718: DW_AT_const_value 0x57 00071a: 21 = 0x28 (DW_TAG_enumerator) 00071b: DW_AT_name LTDC_IRQn 000725: DW_AT_const_value 0x58 000727: 21 = 0x28 (DW_TAG_enumerator) 000728: DW_AT_name LTDC_ER_IRQn 000735: DW_AT_const_value 0x59 000737: 21 = 0x28 (DW_TAG_enumerator) 000738: DW_AT_name DMA2D_IRQn 000743: DW_AT_const_value 0x5a 000745: 21 = 0x28 (DW_TAG_enumerator) 000746: DW_AT_name SAI2_IRQn 000750: DW_AT_const_value 0x5b 000752: 21 = 0x28 (DW_TAG_enumerator) 000753: DW_AT_name QUADSPI_IRQn 000760: DW_AT_const_value 0x5c 000762: 21 = 0x28 (DW_TAG_enumerator) 000763: DW_AT_name LPTIM1_IRQn 00076f: DW_AT_const_value 0x5d 000771: 21 = 0x28 (DW_TAG_enumerator) 000772: DW_AT_name CEC_IRQn 00077b: DW_AT_const_value 0x5e 00077d: 21 = 0x28 (DW_TAG_enumerator) 00077e: DW_AT_name I2C4_EV_IRQn 00078b: DW_AT_const_value 0x5f 00078d: 21 = 0x28 (DW_TAG_enumerator) 00078e: DW_AT_name I2C4_ER_IRQn 00079b: DW_AT_const_value 0x60 00079d: 21 = 0x28 (DW_TAG_enumerator) 00079e: DW_AT_name SPDIF_RX_IRQn 0007ac: DW_AT_const_value 0x61 0007ae: 21 = 0x28 (DW_TAG_enumerator) 0007af: DW_AT_name DFSDM1_FLT0_IRQn 0007c0: DW_AT_const_value 0x63 0007c2: 21 = 0x28 (DW_TAG_enumerator) 0007c3: DW_AT_name DFSDM1_FLT1_IRQn 0007d4: DW_AT_const_value 0x64 0007d6: 21 = 0x28 (DW_TAG_enumerator) 0007d7: DW_AT_name DFSDM1_FLT2_IRQn 0007e8: DW_AT_const_value 0x65 0007ea: 21 = 0x28 (DW_TAG_enumerator) 0007eb: DW_AT_name DFSDM1_FLT3_IRQn 0007fc: DW_AT_const_value 0x66 0007fe: 21 = 0x28 (DW_TAG_enumerator) 0007ff: DW_AT_name SDMMC2_IRQn 00080b: DW_AT_const_value 0x67 00080d: 21 = 0x28 (DW_TAG_enumerator) 00080e: DW_AT_name CAN3_TX_IRQn 00081b: DW_AT_const_value 0x68 00081d: 21 = 0x28 (DW_TAG_enumerator) 00081e: DW_AT_name CAN3_RX0_IRQn 00082c: DW_AT_const_value 0x69 00082e: 21 = 0x28 (DW_TAG_enumerator) 00082f: DW_AT_name CAN3_RX1_IRQn 00083d: DW_AT_const_value 0x6a 00083f: 21 = 0x28 (DW_TAG_enumerator) 000840: DW_AT_name CAN3_SCE_IRQn 00084e: DW_AT_const_value 0x6b 000850: 21 = 0x28 (DW_TAG_enumerator) 000851: DW_AT_name JPEG_IRQn 00085b: DW_AT_const_value 0x6c 00085d: 21 = 0x28 (DW_TAG_enumerator) 00085e: DW_AT_name MDIOS_IRQn 000869: DW_AT_const_value 0x6d 00086b: 0 null 00086c: 80 = 0x16 (DW_TAG_typedef) 00086d: DW_AT_name IRQn_Type 000877: DW_AT_type indirect DW_FORM_ref2 0x114 00087a: DW_AT_decl_file 0x1 00087b: DW_AT_decl_line 0xbb 00087d: DW_AT_decl_column 0x3 00087e: 42 = 0x13 (DW_TAG_structure_type) 00087f: DW_AT_sibling 0x971 000881: DW_AT_byte_size 0x50 000882: 30 = 0xd (DW_TAG_member) 000883: DW_AT_name SR 000886: DW_AT_type indirect DW_FORM_ref2 0x971 000889: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00088c: 30 = 0xd (DW_TAG_member) 00088d: DW_AT_name CR1 000891: DW_AT_type indirect DW_FORM_ref2 0x971 000894: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000897: 30 = 0xd (DW_TAG_member) 000898: DW_AT_name CR2 00089c: DW_AT_type indirect DW_FORM_ref2 0x971 00089f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0008a2: 30 = 0xd (DW_TAG_member) 0008a3: DW_AT_name SMPR1 0008a9: DW_AT_type indirect DW_FORM_ref2 0x971 0008ac: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0008af: 30 = 0xd (DW_TAG_member) 0008b0: DW_AT_name SMPR2 0008b6: DW_AT_type indirect DW_FORM_ref2 0x971 0008b9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 0008bc: 30 = 0xd (DW_TAG_member) 0008bd: DW_AT_name JOFR1 0008c3: DW_AT_type indirect DW_FORM_ref2 0x971 0008c6: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 0008c9: 30 = 0xd (DW_TAG_member) 0008ca: DW_AT_name JOFR2 0008d0: DW_AT_type indirect DW_FORM_ref2 0x971 0008d3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 0008d6: 30 = 0xd (DW_TAG_member) 0008d7: DW_AT_name JOFR3 0008dd: DW_AT_type indirect DW_FORM_ref2 0x971 0008e0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 0008e3: 30 = 0xd (DW_TAG_member) 0008e4: DW_AT_name JOFR4 0008ea: DW_AT_type indirect DW_FORM_ref2 0x971 0008ed: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 0008f0: 30 = 0xd (DW_TAG_member) 0008f1: DW_AT_name HTR 0008f5: DW_AT_type indirect DW_FORM_ref2 0x971 0008f8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 0008fb: 30 = 0xd (DW_TAG_member) 0008fc: DW_AT_name LTR 000900: DW_AT_type indirect DW_FORM_ref2 0x971 000903: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 000906: 30 = 0xd (DW_TAG_member) 000907: DW_AT_name SQR1 00090c: DW_AT_type indirect DW_FORM_ref2 0x971 00090f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 000912: 30 = 0xd (DW_TAG_member) 000913: DW_AT_name SQR2 000918: DW_AT_type indirect DW_FORM_ref2 0x971 00091b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 00091e: 30 = 0xd (DW_TAG_member) 00091f: DW_AT_name SQR3 000924: DW_AT_type indirect DW_FORM_ref2 0x971 000927: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 00092a: 30 = 0xd (DW_TAG_member) 00092b: DW_AT_name JSQR 000930: DW_AT_type indirect DW_FORM_ref2 0x971 000933: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 000936: 30 = 0xd (DW_TAG_member) 000937: DW_AT_name JDR1 00093c: DW_AT_type indirect DW_FORM_ref2 0x971 00093f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 60 } 000942: 30 = 0xd (DW_TAG_member) 000943: DW_AT_name JDR2 000948: DW_AT_type indirect DW_FORM_ref2 0x971 00094b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 64 } 00094e: 30 = 0xd (DW_TAG_member) 00094f: DW_AT_name JDR3 000954: DW_AT_type indirect DW_FORM_ref2 0x971 000957: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 68 } 00095a: 30 = 0xd (DW_TAG_member) 00095b: DW_AT_name JDR4 000960: DW_AT_type indirect DW_FORM_ref2 0x971 000963: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 72 } 000966: 30 = 0xd (DW_TAG_member) 000967: DW_AT_name DR 00096a: DW_AT_type indirect DW_FORM_ref2 0x971 00096d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 76 } 000970: 0 null 000971: 116 = 0x35 (DW_TAG_volatile_type) 000972: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000977: 80 = 0x16 (DW_TAG_typedef) 000978: DW_AT_name ADC_TypeDef 000984: DW_AT_type indirect DW_FORM_ref2 0x87e 000987: DW_AT_decl_file 0x1 000988: DW_AT_decl_line 0xef 00098a: DW_AT_decl_column 0x3 00098b: 42 = 0x13 (DW_TAG_structure_type) 00098c: DW_AT_sibling 0x9b1 00098e: DW_AT_byte_size 0xc 00098f: 30 = 0xd (DW_TAG_member) 000990: DW_AT_name CSR 000994: DW_AT_type indirect DW_FORM_ref2 0x971 000997: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00099a: 30 = 0xd (DW_TAG_member) 00099b: DW_AT_name CCR 00099f: DW_AT_type indirect DW_FORM_ref2 0x971 0009a2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0009a5: 30 = 0xd (DW_TAG_member) 0009a6: DW_AT_name CDR 0009aa: DW_AT_type indirect DW_FORM_ref2 0x971 0009ad: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0009b0: 0 null 0009b1: 80 = 0x16 (DW_TAG_typedef) 0009b2: DW_AT_name ADC_Common_TypeDef 0009c5: DW_AT_type indirect DW_FORM_ref2 0x98b 0009c8: DW_AT_decl_file 0x1 0009c9: DW_AT_decl_line 0xf7 0009cb: DW_AT_decl_column 0x3 0009cc: 42 = 0x13 (DW_TAG_structure_type) 0009cd: DW_AT_sibling 0xa00 0009cf: DW_AT_byte_size 0x10 0009d0: 30 = 0xd (DW_TAG_member) 0009d1: DW_AT_name TIR 0009d5: DW_AT_type indirect DW_FORM_ref2 0x971 0009d8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0009db: 30 = 0xd (DW_TAG_member) 0009dc: DW_AT_name TDTR 0009e1: DW_AT_type indirect DW_FORM_ref2 0x971 0009e4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0009e7: 30 = 0xd (DW_TAG_member) 0009e8: DW_AT_name TDLR 0009ed: DW_AT_type indirect DW_FORM_ref2 0x971 0009f0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0009f3: 30 = 0xd (DW_TAG_member) 0009f4: DW_AT_name TDHR 0009f9: DW_AT_type indirect DW_FORM_ref2 0x971 0009fc: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0009ff: 0 null 000a00: 80 = 0x16 (DW_TAG_typedef) 000a01: DW_AT_name CAN_TxMailBox_TypeDef 000a17: DW_AT_type indirect DW_FORM_ref2 0x9cc 000a1a: DW_AT_decl_file 0x1 000a1b: DW_AT_decl_line 0x104 000a1d: DW_AT_decl_column 0x3 000a1e: 42 = 0x13 (DW_TAG_structure_type) 000a1f: DW_AT_sibling 0xa52 000a21: DW_AT_byte_size 0x10 000a22: 30 = 0xd (DW_TAG_member) 000a23: DW_AT_name RIR 000a27: DW_AT_type indirect DW_FORM_ref2 0x971 000a2a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000a2d: 30 = 0xd (DW_TAG_member) 000a2e: DW_AT_name RDTR 000a33: DW_AT_type indirect DW_FORM_ref2 0x971 000a36: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000a39: 30 = 0xd (DW_TAG_member) 000a3a: DW_AT_name RDLR 000a3f: DW_AT_type indirect DW_FORM_ref2 0x971 000a42: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000a45: 30 = 0xd (DW_TAG_member) 000a46: DW_AT_name RDHR 000a4b: DW_AT_type indirect DW_FORM_ref2 0x971 000a4e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000a51: 0 null 000a52: 80 = 0x16 (DW_TAG_typedef) 000a53: DW_AT_name CAN_FIFOMailBox_TypeDef 000a6b: DW_AT_type indirect DW_FORM_ref2 0xa1e 000a6e: DW_AT_decl_file 0x1 000a6f: DW_AT_decl_line 0x110 000a71: DW_AT_decl_column 0x3 000a72: 42 = 0x13 (DW_TAG_structure_type) 000a73: DW_AT_sibling 0xa8d 000a75: DW_AT_byte_size 0x8 000a76: 30 = 0xd (DW_TAG_member) 000a77: DW_AT_name FR1 000a7b: DW_AT_type indirect DW_FORM_ref2 0x971 000a7e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000a81: 30 = 0xd (DW_TAG_member) 000a82: DW_AT_name FR2 000a86: DW_AT_type indirect DW_FORM_ref2 0x971 000a89: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000a8c: 0 null 000a8d: 80 = 0x16 (DW_TAG_typedef) 000a8e: DW_AT_name CAN_FilterRegister_TypeDef 000aa9: DW_AT_type indirect DW_FORM_ref2 0xa72 000aac: DW_AT_decl_file 0x1 000aad: DW_AT_decl_line 0x11a 000aaf: DW_AT_decl_column 0x3 000ab0: 42 = 0x13 (DW_TAG_structure_type) 000ab1: DW_AT_sibling 0xc3e 000ab3: DW_AT_byte_size 0x320 000ab5: 30 = 0xd (DW_TAG_member) 000ab6: DW_AT_name MCR 000aba: DW_AT_type indirect DW_FORM_ref2 0x971 000abd: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000ac0: 30 = 0xd (DW_TAG_member) 000ac1: DW_AT_name MSR 000ac5: DW_AT_type indirect DW_FORM_ref2 0x971 000ac8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000acb: 30 = 0xd (DW_TAG_member) 000acc: DW_AT_name TSR 000ad0: DW_AT_type indirect DW_FORM_ref2 0x971 000ad3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000ad6: 30 = 0xd (DW_TAG_member) 000ad7: DW_AT_name RF0R 000adc: DW_AT_type indirect DW_FORM_ref2 0x971 000adf: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000ae2: 30 = 0xd (DW_TAG_member) 000ae3: DW_AT_name RF1R 000ae8: DW_AT_type indirect DW_FORM_ref2 0x971 000aeb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000aee: 30 = 0xd (DW_TAG_member) 000aef: DW_AT_name IER 000af3: DW_AT_type indirect DW_FORM_ref2 0x971 000af6: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 000af9: 30 = 0xd (DW_TAG_member) 000afa: DW_AT_name ESR 000afe: DW_AT_type indirect DW_FORM_ref2 0x971 000b01: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 000b04: 30 = 0xd (DW_TAG_member) 000b05: DW_AT_name BTR 000b09: DW_AT_type indirect DW_FORM_ref2 0x971 000b0c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 000b0f: 3 = 0x1 (DW_TAG_array_type) 000b10: DW_AT_sibling 0xb1a 000b12: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000b17: 1 = 0x21 (DW_TAG_subrange_type) 000b18: DW_AT_upper_bound 0x57 000b19: 0 null 000b1a: 30 = 0xd (DW_TAG_member) 000b1b: DW_AT_name RESERVED0 000b25: DW_AT_type indirect DW_FORM_ref2 0xb0f 000b28: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 000b2b: 3 = 0x1 (DW_TAG_array_type) 000b2c: DW_AT_sibling 0xb34 000b2e: DW_AT_type indirect DW_FORM_ref2 0xa00 000b31: 1 = 0x21 (DW_TAG_subrange_type) 000b32: DW_AT_upper_bound 0x2 000b33: 0 null 000b34: 30 = 0xd (DW_TAG_member) 000b35: DW_AT_name sTxMailBox 000b40: DW_AT_type indirect DW_FORM_ref2 0xb2b 000b43: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 384 } 000b47: 3 = 0x1 (DW_TAG_array_type) 000b48: DW_AT_sibling 0xb50 000b4a: DW_AT_type indirect DW_FORM_ref2 0xa52 000b4d: 1 = 0x21 (DW_TAG_subrange_type) 000b4e: DW_AT_upper_bound 0x1 000b4f: 0 null 000b50: 30 = 0xd (DW_TAG_member) 000b51: DW_AT_name sFIFOMailBox 000b5e: DW_AT_type indirect DW_FORM_ref2 0xb47 000b61: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 432 } 000b65: 3 = 0x1 (DW_TAG_array_type) 000b66: DW_AT_sibling 0xb70 000b68: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000b6d: 1 = 0x21 (DW_TAG_subrange_type) 000b6e: DW_AT_upper_bound 0xb 000b6f: 0 null 000b70: 30 = 0xd (DW_TAG_member) 000b71: DW_AT_name RESERVED1 000b7b: DW_AT_type indirect DW_FORM_ref2 0xb65 000b7e: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 464 } 000b82: 30 = 0xd (DW_TAG_member) 000b83: DW_AT_name FMR 000b87: DW_AT_type indirect DW_FORM_ref2 0x971 000b8a: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 512 } 000b8e: 30 = 0xd (DW_TAG_member) 000b8f: DW_AT_name FM1R 000b94: DW_AT_type indirect DW_FORM_ref2 0x971 000b97: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 516 } 000b9b: 30 = 0xd (DW_TAG_member) 000b9c: DW_AT_name RESERVED2 000ba6: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000bab: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 520 } 000baf: 30 = 0xd (DW_TAG_member) 000bb0: DW_AT_name FS1R 000bb5: DW_AT_type indirect DW_FORM_ref2 0x971 000bb8: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 524 } 000bbc: 30 = 0xd (DW_TAG_member) 000bbd: DW_AT_name RESERVED3 000bc7: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000bcc: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 528 } 000bd0: 30 = 0xd (DW_TAG_member) 000bd1: DW_AT_name FFA1R 000bd7: DW_AT_type indirect DW_FORM_ref2 0x971 000bda: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 532 } 000bde: 30 = 0xd (DW_TAG_member) 000bdf: DW_AT_name RESERVED4 000be9: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000bee: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 536 } 000bf2: 30 = 0xd (DW_TAG_member) 000bf3: DW_AT_name FA1R 000bf8: DW_AT_type indirect DW_FORM_ref2 0x971 000bfb: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 540 } 000bff: 3 = 0x1 (DW_TAG_array_type) 000c00: DW_AT_sibling 0xc0a 000c02: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000c07: 1 = 0x21 (DW_TAG_subrange_type) 000c08: DW_AT_upper_bound 0x7 000c09: 0 null 000c0a: 30 = 0xd (DW_TAG_member) 000c0b: DW_AT_name RESERVED5 000c15: DW_AT_type indirect DW_FORM_ref2 0xbff 000c18: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 544 } 000c1c: 3 = 0x1 (DW_TAG_array_type) 000c1d: DW_AT_sibling 0xc25 000c1f: DW_AT_type indirect DW_FORM_ref2 0xa8d 000c22: 1 = 0x21 (DW_TAG_subrange_type) 000c23: DW_AT_upper_bound 0x1b 000c24: 0 null 000c25: 30 = 0xd (DW_TAG_member) 000c26: DW_AT_name sFilterRegister 000c36: DW_AT_type indirect DW_FORM_ref2 0xc1c 000c39: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 576 } 000c3d: 0 null 000c3e: 80 = 0x16 (DW_TAG_typedef) 000c3f: DW_AT_name CAN_TypeDef 000c4b: DW_AT_type indirect DW_FORM_ref2 0xab0 000c4e: DW_AT_decl_file 0x1 000c4f: DW_AT_decl_line 0x138 000c51: DW_AT_decl_column 0x3 000c52: 42 = 0x13 (DW_TAG_structure_type) 000c53: DW_AT_sibling 0xc9b 000c55: DW_AT_byte_size 0x18 000c56: 30 = 0xd (DW_TAG_member) 000c57: DW_AT_name CR 000c5a: DW_AT_type indirect DW_FORM_ref2 0x971 000c5d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000c60: 30 = 0xd (DW_TAG_member) 000c61: DW_AT_name CFGR 000c66: DW_AT_type indirect DW_FORM_ref2 0x971 000c69: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000c6c: 30 = 0xd (DW_TAG_member) 000c6d: DW_AT_name TXDR 000c72: DW_AT_type indirect DW_FORM_ref2 0x971 000c75: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000c78: 30 = 0xd (DW_TAG_member) 000c79: DW_AT_name RXDR 000c7e: DW_AT_type indirect DW_FORM_ref2 0x971 000c81: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000c84: 30 = 0xd (DW_TAG_member) 000c85: DW_AT_name ISR 000c89: DW_AT_type indirect DW_FORM_ref2 0x971 000c8c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000c8f: 30 = 0xd (DW_TAG_member) 000c90: DW_AT_name IER 000c94: DW_AT_type indirect DW_FORM_ref2 0x971 000c97: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 000c9a: 0 null 000c9b: 80 = 0x16 (DW_TAG_typedef) 000c9c: DW_AT_name CEC_TypeDef 000ca8: DW_AT_type indirect DW_FORM_ref2 0xc52 000cab: DW_AT_decl_file 0x1 000cac: DW_AT_decl_line 0x146 000cae: DW_AT_decl_column 0x2 000caf: 42 = 0x13 (DW_TAG_structure_type) 000cb0: DW_AT_sibling 0xd23 000cb2: DW_AT_byte_size 0x18 000cb3: 30 = 0xd (DW_TAG_member) 000cb4: DW_AT_name DR 000cb7: DW_AT_type indirect DW_FORM_ref2 0x971 000cba: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000cbd: 30 = 0xd (DW_TAG_member) 000cbe: DW_AT_name IDR 000cc2: DW_AT_type indirect DW_FORM_ref2 0xd23 000cc5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000cc8: 30 = 0xd (DW_TAG_member) 000cc9: DW_AT_name RESERVED0 000cd3: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000cd8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 5 } 000cdb: 30 = 0xd (DW_TAG_member) 000cdc: DW_AT_name RESERVED1 000ce6: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000ceb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 6 } 000cee: 30 = 0xd (DW_TAG_member) 000cef: DW_AT_name CR 000cf2: DW_AT_type indirect DW_FORM_ref2 0x971 000cf5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000cf8: 30 = 0xd (DW_TAG_member) 000cf9: DW_AT_name RESERVED2 000d03: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000d08: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000d0b: 30 = 0xd (DW_TAG_member) 000d0c: DW_AT_name INIT 000d11: DW_AT_type indirect DW_FORM_ref2 0x971 000d14: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000d17: 30 = 0xd (DW_TAG_member) 000d18: DW_AT_name POL 000d1c: DW_AT_type indirect DW_FORM_ref2 0x971 000d1f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 000d22: 0 null 000d23: 116 = 0x35 (DW_TAG_volatile_type) 000d24: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000d29: 80 = 0x16 (DW_TAG_typedef) 000d2a: DW_AT_name CRC_TypeDef 000d36: DW_AT_type indirect DW_FORM_ref2 0xcaf 000d39: DW_AT_decl_file 0x1 000d3a: DW_AT_decl_line 0x156 000d3c: DW_AT_decl_column 0x3 000d3d: 42 = 0x13 (DW_TAG_structure_type) 000d3e: DW_AT_sibling 0xe01 000d40: DW_AT_byte_size 0x38 000d41: 30 = 0xd (DW_TAG_member) 000d42: DW_AT_name CR 000d45: DW_AT_type indirect DW_FORM_ref2 0x971 000d48: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000d4b: 30 = 0xd (DW_TAG_member) 000d4c: DW_AT_name SWTRIGR 000d54: DW_AT_type indirect DW_FORM_ref2 0x971 000d57: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000d5a: 30 = 0xd (DW_TAG_member) 000d5b: DW_AT_name DHR12R1 000d63: DW_AT_type indirect DW_FORM_ref2 0x971 000d66: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000d69: 30 = 0xd (DW_TAG_member) 000d6a: DW_AT_name DHR12L1 000d72: DW_AT_type indirect DW_FORM_ref2 0x971 000d75: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000d78: 30 = 0xd (DW_TAG_member) 000d79: DW_AT_name DHR8R1 000d80: DW_AT_type indirect DW_FORM_ref2 0x971 000d83: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000d86: 30 = 0xd (DW_TAG_member) 000d87: DW_AT_name DHR12R2 000d8f: DW_AT_type indirect DW_FORM_ref2 0x971 000d92: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 000d95: 30 = 0xd (DW_TAG_member) 000d96: DW_AT_name DHR12L2 000d9e: DW_AT_type indirect DW_FORM_ref2 0x971 000da1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 000da4: 30 = 0xd (DW_TAG_member) 000da5: DW_AT_name DHR8R2 000dac: DW_AT_type indirect DW_FORM_ref2 0x971 000daf: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 000db2: 30 = 0xd (DW_TAG_member) 000db3: DW_AT_name DHR12RD 000dbb: DW_AT_type indirect DW_FORM_ref2 0x971 000dbe: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 000dc1: 30 = 0xd (DW_TAG_member) 000dc2: DW_AT_name DHR12LD 000dca: DW_AT_type indirect DW_FORM_ref2 0x971 000dcd: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 000dd0: 30 = 0xd (DW_TAG_member) 000dd1: DW_AT_name DHR8RD 000dd8: DW_AT_type indirect DW_FORM_ref2 0x971 000ddb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 000dde: 30 = 0xd (DW_TAG_member) 000ddf: DW_AT_name DOR1 000de4: DW_AT_type indirect DW_FORM_ref2 0x971 000de7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 000dea: 30 = 0xd (DW_TAG_member) 000deb: DW_AT_name DOR2 000df0: DW_AT_type indirect DW_FORM_ref2 0x971 000df3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 000df6: 30 = 0xd (DW_TAG_member) 000df7: DW_AT_name SR 000dfa: DW_AT_type indirect DW_FORM_ref2 0x971 000dfd: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 000e00: 0 null 000e01: 80 = 0x16 (DW_TAG_typedef) 000e02: DW_AT_name DAC_TypeDef 000e0e: DW_AT_type indirect DW_FORM_ref2 0xd3d 000e11: DW_AT_decl_file 0x1 000e12: DW_AT_decl_line 0x16c 000e14: DW_AT_decl_column 0x3 000e15: 42 = 0x13 (DW_TAG_structure_type) 000e16: DW_AT_sibling 0xf03 000e18: DW_AT_byte_size 0x3c 000e19: 30 = 0xd (DW_TAG_member) 000e1a: DW_AT_name FLTCR1 000e21: DW_AT_type indirect DW_FORM_ref2 0x971 000e24: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000e27: 30 = 0xd (DW_TAG_member) 000e28: DW_AT_name FLTCR2 000e2f: DW_AT_type indirect DW_FORM_ref2 0x971 000e32: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000e35: 30 = 0xd (DW_TAG_member) 000e36: DW_AT_name FLTISR 000e3d: DW_AT_type indirect DW_FORM_ref2 0x971 000e40: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000e43: 30 = 0xd (DW_TAG_member) 000e44: DW_AT_name FLTICR 000e4b: DW_AT_type indirect DW_FORM_ref2 0x971 000e4e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000e51: 30 = 0xd (DW_TAG_member) 000e52: DW_AT_name FLTJCHGR 000e5b: DW_AT_type indirect DW_FORM_ref2 0x971 000e5e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000e61: 30 = 0xd (DW_TAG_member) 000e62: DW_AT_name FLTFCR 000e69: DW_AT_type indirect DW_FORM_ref2 0x971 000e6c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 000e6f: 30 = 0xd (DW_TAG_member) 000e70: DW_AT_name FLTJDATAR 000e7a: DW_AT_type indirect DW_FORM_ref2 0x971 000e7d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 000e80: 30 = 0xd (DW_TAG_member) 000e81: DW_AT_name FLTRDATAR 000e8b: DW_AT_type indirect DW_FORM_ref2 0x971 000e8e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 000e91: 30 = 0xd (DW_TAG_member) 000e92: DW_AT_name FLTAWHTR 000e9b: DW_AT_type indirect DW_FORM_ref2 0x971 000e9e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 000ea1: 30 = 0xd (DW_TAG_member) 000ea2: DW_AT_name FLTAWLTR 000eab: DW_AT_type indirect DW_FORM_ref2 0x971 000eae: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 000eb1: 30 = 0xd (DW_TAG_member) 000eb2: DW_AT_name FLTAWSR 000eba: DW_AT_type indirect DW_FORM_ref2 0x971 000ebd: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 000ec0: 30 = 0xd (DW_TAG_member) 000ec1: DW_AT_name FLTAWCFR 000eca: DW_AT_type indirect DW_FORM_ref2 0x971 000ecd: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 000ed0: 30 = 0xd (DW_TAG_member) 000ed1: DW_AT_name FLTEXMAX 000eda: DW_AT_type indirect DW_FORM_ref2 0x971 000edd: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 000ee0: 30 = 0xd (DW_TAG_member) 000ee1: DW_AT_name FLTEXMIN 000eea: DW_AT_type indirect DW_FORM_ref2 0x971 000eed: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 000ef0: 30 = 0xd (DW_TAG_member) 000ef1: DW_AT_name FLTCNVTIMR 000efc: DW_AT_type indirect DW_FORM_ref2 0x971 000eff: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 000f02: 0 null 000f03: 80 = 0x16 (DW_TAG_typedef) 000f04: DW_AT_name DFSDM_Filter_TypeDef 000f19: DW_AT_type indirect DW_FORM_ref2 0xe15 000f1c: DW_AT_decl_file 0x1 000f1d: DW_AT_decl_line 0x182 000f1f: DW_AT_decl_column 0x3 000f20: 42 = 0x13 (DW_TAG_structure_type) 000f21: DW_AT_sibling 0xf73 000f23: DW_AT_byte_size 0x14 000f24: 30 = 0xd (DW_TAG_member) 000f25: DW_AT_name CHCFGR1 000f2d: DW_AT_type indirect DW_FORM_ref2 0x971 000f30: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000f33: 30 = 0xd (DW_TAG_member) 000f34: DW_AT_name CHCFGR2 000f3c: DW_AT_type indirect DW_FORM_ref2 0x971 000f3f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000f42: 30 = 0xd (DW_TAG_member) 000f43: DW_AT_name CHAWSCDR 000f4c: DW_AT_type indirect DW_FORM_ref2 0x971 000f4f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000f52: 30 = 0xd (DW_TAG_member) 000f53: DW_AT_name CHWDATAR 000f5c: DW_AT_type indirect DW_FORM_ref2 0x971 000f5f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000f62: 30 = 0xd (DW_TAG_member) 000f63: DW_AT_name CHDATINR 000f6c: DW_AT_type indirect DW_FORM_ref2 0x971 000f6f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000f72: 0 null 000f73: 80 = 0x16 (DW_TAG_typedef) 000f74: DW_AT_name DFSDM_Channel_TypeDef 000f8a: DW_AT_type indirect DW_FORM_ref2 0xf20 000f8d: DW_AT_decl_file 0x1 000f8e: DW_AT_decl_line 0x18f 000f90: DW_AT_decl_column 0x3 000f91: 42 = 0x13 (DW_TAG_structure_type) 000f92: DW_AT_sibling 0xfca 000f94: DW_AT_byte_size 0x10 000f95: 30 = 0xd (DW_TAG_member) 000f96: DW_AT_name IDCODE 000f9d: DW_AT_type indirect DW_FORM_ref2 0x971 000fa0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000fa3: 30 = 0xd (DW_TAG_member) 000fa4: DW_AT_name CR 000fa7: DW_AT_type indirect DW_FORM_ref2 0x971 000faa: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000fad: 30 = 0xd (DW_TAG_member) 000fae: DW_AT_name APB1FZ 000fb5: DW_AT_type indirect DW_FORM_ref2 0x971 000fb8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000fbb: 30 = 0xd (DW_TAG_member) 000fbc: DW_AT_name APB2FZ 000fc3: DW_AT_type indirect DW_FORM_ref2 0x971 000fc6: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000fc9: 0 null 000fca: 80 = 0x16 (DW_TAG_typedef) 000fcb: DW_AT_name DBGMCU_TypeDef 000fda: DW_AT_type indirect DW_FORM_ref2 0xf91 000fdd: DW_AT_decl_file 0x1 000fde: DW_AT_decl_line 0x19b 000fe0: DW_AT_decl_column 0x2 000fe1: 42 = 0x13 (DW_TAG_structure_type) 000fe2: DW_AT_sibling 0x1068 000fe4: DW_AT_byte_size 0x2c 000fe5: 30 = 0xd (DW_TAG_member) 000fe6: DW_AT_name CR 000fe9: DW_AT_type indirect DW_FORM_ref2 0x971 000fec: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000fef: 30 = 0xd (DW_TAG_member) 000ff0: DW_AT_name SR 000ff3: DW_AT_type indirect DW_FORM_ref2 0x971 000ff6: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000ff9: 30 = 0xd (DW_TAG_member) 000ffa: DW_AT_name RISR 000fff: DW_AT_type indirect DW_FORM_ref2 0x971 001002: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 001005: 30 = 0xd (DW_TAG_member) 001006: DW_AT_name IER 00100a: DW_AT_type indirect DW_FORM_ref2 0x971 00100d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 001010: 30 = 0xd (DW_TAG_member) 001011: DW_AT_name MISR 001016: DW_AT_type indirect DW_FORM_ref2 0x971 001019: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 00101c: 30 = 0xd (DW_TAG_member) 00101d: DW_AT_name ICR 001021: DW_AT_type indirect DW_FORM_ref2 0x971 001024: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 001027: 30 = 0xd (DW_TAG_member) 001028: DW_AT_name ESCR 00102d: DW_AT_type indirect DW_FORM_ref2 0x971 001030: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 001033: 30 = 0xd (DW_TAG_member) 001034: DW_AT_name ESUR 001039: DW_AT_type indirect DW_FORM_ref2 0x971 00103c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 00103f: 30 = 0xd (DW_TAG_member) 001040: DW_AT_name CWSTRTR 001048: DW_AT_type indirect DW_FORM_ref2 0x971 00104b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 00104e: 30 = 0xd (DW_TAG_member) 00104f: DW_AT_name CWSIZER 001057: DW_AT_type indirect DW_FORM_ref2 0x971 00105a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 00105d: 30 = 0xd (DW_TAG_member) 00105e: DW_AT_name DR 001061: DW_AT_type indirect DW_FORM_ref2 0x971 001064: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 001067: 0 null 001068: 80 = 0x16 (DW_TAG_typedef) 001069: DW_AT_name DCMI_TypeDef 001076: DW_AT_type indirect DW_FORM_ref2 0xfe1 001079: DW_AT_decl_file 0x1 00107a: DW_AT_decl_line 0x1ae 00107c: DW_AT_decl_column 0x3 00107d: 42 = 0x13 (DW_TAG_structure_type) 00107e: DW_AT_sibling 0x10c6 001080: DW_AT_byte_size 0x18 001081: 30 = 0xd (DW_TAG_member) 001082: DW_AT_name CR 001085: DW_AT_type indirect DW_FORM_ref2 0x971 001088: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00108b: 30 = 0xd (DW_TAG_member) 00108c: DW_AT_name NDTR 001091: DW_AT_type indirect DW_FORM_ref2 0x971 001094: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 001097: 30 = 0xd (DW_TAG_member) 001098: DW_AT_name PAR 00109c: DW_AT_type indirect DW_FORM_ref2 0x971 00109f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0010a2: 30 = 0xd (DW_TAG_member) 0010a3: DW_AT_name M0AR 0010a8: DW_AT_type indirect DW_FORM_ref2 0x971 0010ab: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0010ae: 30 = 0xd (DW_TAG_member) 0010af: DW_AT_name M1AR 0010b4: DW_AT_type indirect DW_FORM_ref2 0x971 0010b7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 0010ba: 30 = 0xd (DW_TAG_member) 0010bb: DW_AT_name FCR 0010bf: DW_AT_type indirect DW_FORM_ref2 0x971 0010c2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 0010c5: 0 null 0010c6: 80 = 0x16 (DW_TAG_typedef) 0010c7: DW_AT_name DMA_Stream_TypeDef 0010da: DW_AT_type indirect DW_FORM_ref2 0x107d 0010dd: DW_AT_decl_file 0x1 0010de: DW_AT_decl_line 0x1bc 0010e0: DW_AT_decl_column 0x3 0010e1: 42 = 0x13 (DW_TAG_structure_type) 0010e2: DW_AT_sibling 0x1118 0010e4: DW_AT_byte_size 0x10 0010e5: 30 = 0xd (DW_TAG_member) 0010e6: DW_AT_name LISR 0010eb: DW_AT_type indirect DW_FORM_ref2 0x971 0010ee: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0010f1: 30 = 0xd (DW_TAG_member) 0010f2: DW_AT_name HISR 0010f7: DW_AT_type indirect DW_FORM_ref2 0x971 0010fa: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0010fd: 30 = 0xd (DW_TAG_member) 0010fe: DW_AT_name LIFCR 001104: DW_AT_type indirect DW_FORM_ref2 0x971 001107: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 00110a: 30 = 0xd (DW_TAG_member) 00110b: DW_AT_name HIFCR 001111: DW_AT_type indirect DW_FORM_ref2 0x971 001114: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 001117: 0 null 001118: 80 = 0x16 (DW_TAG_typedef) 001119: DW_AT_name DMA_TypeDef 001125: DW_AT_type indirect DW_FORM_ref2 0x10e1 001128: DW_AT_decl_file 0x1 001129: DW_AT_decl_line 0x1c4 00112b: DW_AT_decl_column 0x3 00112c: 42 = 0x13 (DW_TAG_structure_type) 00112d: DW_AT_sibling 0x127e 00112f: DW_AT_byte_size 0xc00 001131: 30 = 0xd (DW_TAG_member) 001132: DW_AT_name CR 001135: DW_AT_type indirect DW_FORM_ref2 0x971 001138: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00113b: 30 = 0xd (DW_TAG_member) 00113c: DW_AT_name ISR 001140: DW_AT_type indirect DW_FORM_ref2 0x971 001143: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 001146: 30 = 0xd (DW_TAG_member) 001147: DW_AT_name IFCR 00114c: DW_AT_type indirect DW_FORM_ref2 0x971 00114f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 001152: 30 = 0xd (DW_TAG_member) 001153: DW_AT_name FGMAR 001159: DW_AT_type indirect DW_FORM_ref2 0x971 00115c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00115f: 30 = 0xd (DW_TAG_member) 001160: DW_AT_name FGOR 001165: DW_AT_type indirect DW_FORM_ref2 0x971 001168: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 00116b: 30 = 0xd (DW_TAG_member) 00116c: DW_AT_name BGMAR 001172: DW_AT_type indirect DW_FORM_ref2 0x971 001175: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 001178: 30 = 0xd (DW_TAG_member) 001179: DW_AT_name BGOR 00117e: DW_AT_type indirect DW_FORM_ref2 0x971 001181: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 001184: 30 = 0xd (DW_TAG_member) 001185: DW_AT_name FGPFCCR 00118d: DW_AT_type indirect DW_FORM_ref2 0x971 001190: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 001193: 30 = 0xd (DW_TAG_member) 001194: DW_AT_name FGCOLR 00119b: DW_AT_type indirect DW_FORM_ref2 0x971 00119e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 0011a1: 30 = 0xd (DW_TAG_member) 0011a2: DW_AT_name BGPFCCR 0011aa: DW_AT_type indirect DW_FORM_ref2 0x971 0011ad: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 0011b0: 30 = 0xd (DW_TAG_member) 0011b1: DW_AT_name BGCOLR 0011b8: DW_AT_type indirect DW_FORM_ref2 0x971 0011bb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 0011be: 30 = 0xd (DW_TAG_member) 0011bf: DW_AT_name FGCMAR 0011c6: DW_AT_type indirect DW_FORM_ref2 0x971 0011c9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 0011cc: 30 = 0xd (DW_TAG_member) 0011cd: DW_AT_name BGCMAR 0011d4: DW_AT_type indirect DW_FORM_ref2 0x971 0011d7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 0011da: 30 = 0xd (DW_TAG_member) 0011db: DW_AT_name OPFCCR 0011e2: DW_AT_type indirect DW_FORM_ref2 0x971 0011e5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 0011e8: 30 = 0xd (DW_TAG_member) 0011e9: DW_AT_name OCOLR 0011ef: DW_AT_type indirect DW_FORM_ref2 0x971 0011f2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 0011f5: 30 = 0xd (DW_TAG_member) 0011f6: DW_AT_name OMAR 0011fb: DW_AT_type indirect DW_FORM_ref2 0x971 0011fe: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 60 } 001201: 30 = 0xd (DW_TAG_member) 001202: DW_AT_name OOR 001206: DW_AT_type indirect DW_FORM_ref2 0x971 001209: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 64 } 00120c: 30 = 0xd (DW_TAG_member) 00120d: DW_AT_name NLR 001211: DW_AT_type indirect DW_FORM_ref2 0x971 001214: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 68 } 001217: 30 = 0xd (DW_TAG_member) 001218: DW_AT_name LWR 00121c: DW_AT_type indirect DW_FORM_ref2 0x971 00121f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 72 } 001222: 30 = 0xd (DW_TAG_member) 001223: DW_AT_name AMTCR 001229: DW_AT_type indirect DW_FORM_ref2 0x971 00122c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 76 } 00122f: 3 = 0x1 (DW_TAG_array_type) 001230: DW_AT_sibling 0x123b 001232: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001237: 1 = 0x21 (DW_TAG_subrange_type) 001238: DW_AT_upper_bound 0xeb 00123a: 0 null 00123b: 30 = 0xd (DW_TAG_member) 00123c: DW_AT_name RESERVED 001245: DW_AT_type indirect DW_FORM_ref2 0x122f 001248: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 80 } 00124b: 3 = 0x1 (DW_TAG_array_type) 00124c: DW_AT_sibling 0x1255 00124e: DW_AT_type indirect DW_FORM_ref2 0x971 001251: 1 = 0x21 (DW_TAG_subrange_type) 001252: DW_AT_upper_bound 0xff 001254: 0 null 001255: 30 = 0xd (DW_TAG_member) 001256: DW_AT_name FGCLUT 00125d: DW_AT_type indirect DW_FORM_ref2 0x124b 001260: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 1024 } 001264: 3 = 0x1 (DW_TAG_array_type) 001265: DW_AT_sibling 0x126e 001267: DW_AT_type indirect DW_FORM_ref2 0x971 00126a: 1 = 0x21 (DW_TAG_subrange_type) 00126b: DW_AT_upper_bound 0xff 00126d: 0 null 00126e: 30 = 0xd (DW_TAG_member) 00126f: DW_AT_name BGCLUT 001276: DW_AT_type indirect DW_FORM_ref2 0x1264 001279: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 2048 } 00127d: 0 null 00127e: 80 = 0x16 (DW_TAG_typedef) 00127f: DW_AT_name DMA2D_TypeDef 00128d: DW_AT_type indirect DW_FORM_ref2 0x112c 001290: DW_AT_decl_file 0x1 001291: DW_AT_decl_line 0x1e3 001293: DW_AT_decl_column 0x3 001294: 42 = 0x13 (DW_TAG_structure_type) 001295: DW_AT_sibling 0x173d 001297: DW_AT_byte_size 0x1058 001299: 30 = 0xd (DW_TAG_member) 00129a: DW_AT_name MACCR 0012a0: DW_AT_type indirect DW_FORM_ref2 0x971 0012a3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0012a6: 30 = 0xd (DW_TAG_member) 0012a7: DW_AT_name MACFFR 0012ae: DW_AT_type indirect DW_FORM_ref2 0x971 0012b1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0012b4: 30 = 0xd (DW_TAG_member) 0012b5: DW_AT_name MACHTHR 0012bd: DW_AT_type indirect DW_FORM_ref2 0x971 0012c0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0012c3: 30 = 0xd (DW_TAG_member) 0012c4: DW_AT_name MACHTLR 0012cc: DW_AT_type indirect DW_FORM_ref2 0x971 0012cf: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0012d2: 30 = 0xd (DW_TAG_member) 0012d3: DW_AT_name MACMIIAR 0012dc: DW_AT_type indirect DW_FORM_ref2 0x971 0012df: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 0012e2: 30 = 0xd (DW_TAG_member) 0012e3: DW_AT_name MACMIIDR 0012ec: DW_AT_type indirect DW_FORM_ref2 0x971 0012ef: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 0012f2: 30 = 0xd (DW_TAG_member) 0012f3: DW_AT_name MACFCR 0012fa: DW_AT_type indirect DW_FORM_ref2 0x971 0012fd: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 001300: 30 = 0xd (DW_TAG_member) 001301: DW_AT_name MACVLANTR 00130b: DW_AT_type indirect DW_FORM_ref2 0x971 00130e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 001311: 3 = 0x1 (DW_TAG_array_type) 001312: DW_AT_sibling 0x131c 001314: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001319: 1 = 0x21 (DW_TAG_subrange_type) 00131a: DW_AT_upper_bound 0x1 00131b: 0 null 00131c: 30 = 0xd (DW_TAG_member) 00131d: DW_AT_name RESERVED0 001327: DW_AT_type indirect DW_FORM_ref2 0x1311 00132a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 00132d: 30 = 0xd (DW_TAG_member) 00132e: DW_AT_name MACRWUFFR 001338: DW_AT_type indirect DW_FORM_ref2 0x971 00133b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 00133e: 30 = 0xd (DW_TAG_member) 00133f: DW_AT_name MACPMTCSR 001349: DW_AT_type indirect DW_FORM_ref2 0x971 00134c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 00134f: 3 = 0x1 (DW_TAG_array_type) 001350: DW_AT_sibling 0x135a 001352: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001357: 1 = 0x21 (DW_TAG_subrange_type) 001358: DW_AT_upper_bound 0x1 001359: 0 null 00135a: 30 = 0xd (DW_TAG_member) 00135b: DW_AT_name RESERVED1 001365: DW_AT_type indirect DW_FORM_ref2 0x134f 001368: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 00136b: 30 = 0xd (DW_TAG_member) 00136c: DW_AT_name MACSR 001372: DW_AT_type indirect DW_FORM_ref2 0x971 001375: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 001378: 30 = 0xd (DW_TAG_member) 001379: DW_AT_name MACIMR 001380: DW_AT_type indirect DW_FORM_ref2 0x971 001383: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 60 } 001386: 30 = 0xd (DW_TAG_member) 001387: DW_AT_name MACA0HR 00138f: DW_AT_type indirect DW_FORM_ref2 0x971 001392: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 64 } 001395: 30 = 0xd (DW_TAG_member) 001396: DW_AT_name MACA0LR 00139e: DW_AT_type indirect DW_FORM_ref2 0x971 0013a1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 68 } 0013a4: 30 = 0xd (DW_TAG_member) 0013a5: DW_AT_name MACA1HR 0013ad: DW_AT_type indirect DW_FORM_ref2 0x971 0013b0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 72 } 0013b3: 30 = 0xd (DW_TAG_member) 0013b4: DW_AT_name MACA1LR 0013bc: DW_AT_type indirect DW_FORM_ref2 0x971 0013bf: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 76 } 0013c2: 30 = 0xd (DW_TAG_member) 0013c3: DW_AT_name MACA2HR 0013cb: DW_AT_type indirect DW_FORM_ref2 0x971 0013ce: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 80 } 0013d1: 30 = 0xd (DW_TAG_member) 0013d2: DW_AT_name MACA2LR 0013da: DW_AT_type indirect DW_FORM_ref2 0x971 0013dd: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 84 } 0013e0: 30 = 0xd (DW_TAG_member) 0013e1: DW_AT_name MACA3HR 0013e9: DW_AT_type indirect DW_FORM_ref2 0x971 0013ec: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 88 } 0013ef: 30 = 0xd (DW_TAG_member) 0013f0: DW_AT_name MACA3LR 0013f8: DW_AT_type indirect DW_FORM_ref2 0x971 0013fb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 92 } 0013fe: 3 = 0x1 (DW_TAG_array_type) 0013ff: DW_AT_sibling 0x1409 001401: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001406: 1 = 0x21 (DW_TAG_subrange_type) 001407: DW_AT_upper_bound 0x27 001408: 0 null 001409: 30 = 0xd (DW_TAG_member) 00140a: DW_AT_name RESERVED2 001414: DW_AT_type indirect DW_FORM_ref2 0x13fe 001417: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 96 } 00141a: 30 = 0xd (DW_TAG_member) 00141b: DW_AT_name MMCCR 001421: DW_AT_type indirect DW_FORM_ref2 0x971 001424: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 256 } 001428: 30 = 0xd (DW_TAG_member) 001429: DW_AT_name MMCRIR 001430: DW_AT_type indirect DW_FORM_ref2 0x971 001433: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 260 } 001437: 30 = 0xd (DW_TAG_member) 001438: DW_AT_name MMCTIR 00143f: DW_AT_type indirect DW_FORM_ref2 0x971 001442: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 264 } 001446: 30 = 0xd (DW_TAG_member) 001447: DW_AT_name MMCRIMR 00144f: DW_AT_type indirect DW_FORM_ref2 0x971 001452: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 268 } 001456: 30 = 0xd (DW_TAG_member) 001457: DW_AT_name MMCTIMR 00145f: DW_AT_type indirect DW_FORM_ref2 0x971 001462: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 272 } 001466: 3 = 0x1 (DW_TAG_array_type) 001467: DW_AT_sibling 0x1471 001469: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00146e: 1 = 0x21 (DW_TAG_subrange_type) 00146f: DW_AT_upper_bound 0xd 001470: 0 null 001471: 30 = 0xd (DW_TAG_member) 001472: DW_AT_name RESERVED3 00147c: DW_AT_type indirect DW_FORM_ref2 0x1466 00147f: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 276 } 001483: 30 = 0xd (DW_TAG_member) 001484: DW_AT_name MMCTGFSCCR 00148f: DW_AT_type indirect DW_FORM_ref2 0x971 001492: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 332 } 001496: 30 = 0xd (DW_TAG_member) 001497: DW_AT_name MMCTGFMSCCR 0014a3: DW_AT_type indirect DW_FORM_ref2 0x971 0014a6: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 336 } 0014aa: 3 = 0x1 (DW_TAG_array_type) 0014ab: DW_AT_sibling 0x14b5 0014ad: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0014b2: 1 = 0x21 (DW_TAG_subrange_type) 0014b3: DW_AT_upper_bound 0x4 0014b4: 0 null 0014b5: 30 = 0xd (DW_TAG_member) 0014b6: DW_AT_name RESERVED4 0014c0: DW_AT_type indirect DW_FORM_ref2 0x14aa 0014c3: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 340 } 0014c7: 30 = 0xd (DW_TAG_member) 0014c8: DW_AT_name MMCTGFCR 0014d1: DW_AT_type indirect DW_FORM_ref2 0x971 0014d4: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 360 } 0014d8: 3 = 0x1 (DW_TAG_array_type) 0014d9: DW_AT_sibling 0x14e3 0014db: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0014e0: 1 = 0x21 (DW_TAG_subrange_type) 0014e1: DW_AT_upper_bound 0x9 0014e2: 0 null 0014e3: 30 = 0xd (DW_TAG_member) 0014e4: DW_AT_name RESERVED5 0014ee: DW_AT_type indirect DW_FORM_ref2 0x14d8 0014f1: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 364 } 0014f5: 30 = 0xd (DW_TAG_member) 0014f6: DW_AT_name MMCRFCECR 001500: DW_AT_type indirect DW_FORM_ref2 0x971 001503: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 404 } 001507: 30 = 0xd (DW_TAG_member) 001508: DW_AT_name MMCRFAECR 001512: DW_AT_type indirect DW_FORM_ref2 0x971 001515: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 408 } 001519: 3 = 0x1 (DW_TAG_array_type) 00151a: DW_AT_sibling 0x1524 00151c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001521: 1 = 0x21 (DW_TAG_subrange_type) 001522: DW_AT_upper_bound 0x9 001523: 0 null 001524: 30 = 0xd (DW_TAG_member) 001525: DW_AT_name RESERVED6 00152f: DW_AT_type indirect DW_FORM_ref2 0x1519 001532: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 412 } 001536: 30 = 0xd (DW_TAG_member) 001537: DW_AT_name MMCRGUFCR 001541: DW_AT_type indirect DW_FORM_ref2 0x971 001544: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 452 } 001548: 3 = 0x1 (DW_TAG_array_type) 001549: DW_AT_sibling 0x1554 00154b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001550: 1 = 0x21 (DW_TAG_subrange_type) 001551: DW_AT_upper_bound 0x14d 001553: 0 null 001554: 30 = 0xd (DW_TAG_member) 001555: DW_AT_name RESERVED7 00155f: DW_AT_type indirect DW_FORM_ref2 0x1548 001562: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 456 } 001566: 30 = 0xd (DW_TAG_member) 001567: DW_AT_name PTPTSCR 00156f: DW_AT_type indirect DW_FORM_ref2 0x971 001572: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 1792 } 001576: 30 = 0xd (DW_TAG_member) 001577: DW_AT_name PTPSSIR 00157f: DW_AT_type indirect DW_FORM_ref2 0x971 001582: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 1796 } 001586: 30 = 0xd (DW_TAG_member) 001587: DW_AT_name PTPTSHR 00158f: DW_AT_type indirect DW_FORM_ref2 0x971 001592: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 1800 } 001596: 30 = 0xd (DW_TAG_member) 001597: DW_AT_name PTPTSLR 00159f: DW_AT_type indirect DW_FORM_ref2 0x971 0015a2: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 1804 } 0015a6: 30 = 0xd (DW_TAG_member) 0015a7: DW_AT_name PTPTSHUR 0015b0: DW_AT_type indirect DW_FORM_ref2 0x971 0015b3: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 1808 } 0015b7: 30 = 0xd (DW_TAG_member) 0015b8: DW_AT_name PTPTSLUR 0015c1: DW_AT_type indirect DW_FORM_ref2 0x971 0015c4: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 1812 } 0015c8: 30 = 0xd (DW_TAG_member) 0015c9: DW_AT_name PTPTSAR 0015d1: DW_AT_type indirect DW_FORM_ref2 0x971 0015d4: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 1816 } 0015d8: 30 = 0xd (DW_TAG_member) 0015d9: DW_AT_name PTPTTHR 0015e1: DW_AT_type indirect DW_FORM_ref2 0x971 0015e4: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 1820 } 0015e8: 30 = 0xd (DW_TAG_member) 0015e9: DW_AT_name PTPTTLR 0015f1: DW_AT_type indirect DW_FORM_ref2 0x971 0015f4: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 1824 } 0015f8: 30 = 0xd (DW_TAG_member) 0015f9: DW_AT_name RESERVED8 001603: DW_AT_type indirect DW_FORM_ref2 0x971 001606: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 1828 } 00160a: 30 = 0xd (DW_TAG_member) 00160b: DW_AT_name PTPTSSR 001613: DW_AT_type indirect DW_FORM_ref2 0x971 001616: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 1832 } 00161a: 3 = 0x1 (DW_TAG_array_type) 00161b: DW_AT_sibling 0x1626 00161d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001622: 1 = 0x21 (DW_TAG_subrange_type) 001623: DW_AT_upper_bound 0x234 001625: 0 null 001626: 30 = 0xd (DW_TAG_member) 001627: DW_AT_name RESERVED9 001631: DW_AT_type indirect DW_FORM_ref2 0x161a 001634: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 1836 } 001638: 30 = 0xd (DW_TAG_member) 001639: DW_AT_name DMABMR 001640: DW_AT_type indirect DW_FORM_ref2 0x971 001643: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4096 } 001647: 30 = 0xd (DW_TAG_member) 001648: DW_AT_name DMATPDR 001650: DW_AT_type indirect DW_FORM_ref2 0x971 001653: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4100 } 001657: 30 = 0xd (DW_TAG_member) 001658: DW_AT_name DMARPDR 001660: DW_AT_type indirect DW_FORM_ref2 0x971 001663: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4104 } 001667: 30 = 0xd (DW_TAG_member) 001668: DW_AT_name DMARDLAR 001671: DW_AT_type indirect DW_FORM_ref2 0x971 001674: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4108 } 001678: 30 = 0xd (DW_TAG_member) 001679: DW_AT_name DMATDLAR 001682: DW_AT_type indirect DW_FORM_ref2 0x971 001685: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4112 } 001689: 30 = 0xd (DW_TAG_member) 00168a: DW_AT_name DMASR 001690: DW_AT_type indirect DW_FORM_ref2 0x971 001693: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4116 } 001697: 30 = 0xd (DW_TAG_member) 001698: DW_AT_name DMAOMR 00169f: DW_AT_type indirect DW_FORM_ref2 0x971 0016a2: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4120 } 0016a6: 30 = 0xd (DW_TAG_member) 0016a7: DW_AT_name DMAIER 0016ae: DW_AT_type indirect DW_FORM_ref2 0x971 0016b1: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4124 } 0016b5: 30 = 0xd (DW_TAG_member) 0016b6: DW_AT_name DMAMFBOCR 0016c0: DW_AT_type indirect DW_FORM_ref2 0x971 0016c3: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4128 } 0016c7: 30 = 0xd (DW_TAG_member) 0016c8: DW_AT_name DMARSWTR 0016d1: DW_AT_type indirect DW_FORM_ref2 0x971 0016d4: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4132 } 0016d8: 3 = 0x1 (DW_TAG_array_type) 0016d9: DW_AT_sibling 0x16e3 0016db: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0016e0: 1 = 0x21 (DW_TAG_subrange_type) 0016e1: DW_AT_upper_bound 0x7 0016e2: 0 null 0016e3: 30 = 0xd (DW_TAG_member) 0016e4: DW_AT_name RESERVED10 0016ef: DW_AT_type indirect DW_FORM_ref2 0x16d8 0016f2: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4136 } 0016f6: 30 = 0xd (DW_TAG_member) 0016f7: DW_AT_name DMACHTDR 001700: DW_AT_type indirect DW_FORM_ref2 0x971 001703: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4168 } 001707: 30 = 0xd (DW_TAG_member) 001708: DW_AT_name DMACHRDR 001711: DW_AT_type indirect DW_FORM_ref2 0x971 001714: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4172 } 001718: 30 = 0xd (DW_TAG_member) 001719: DW_AT_name DMACHTBAR 001723: DW_AT_type indirect DW_FORM_ref2 0x971 001726: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4176 } 00172a: 30 = 0xd (DW_TAG_member) 00172b: DW_AT_name DMACHRBAR 001735: DW_AT_type indirect DW_FORM_ref2 0x971 001738: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 4180 } 00173c: 0 null 00173d: 80 = 0x16 (DW_TAG_typedef) 00173e: DW_AT_name ETH_TypeDef 00174a: DW_AT_type indirect DW_FORM_ref2 0x1294 00174d: DW_AT_decl_file 0x1 00174e: DW_AT_decl_line 0x22e 001750: DW_AT_decl_column 0x3 001751: 42 = 0x13 (DW_TAG_structure_type) 001752: DW_AT_sibling 0x179b 001754: DW_AT_byte_size 0x18 001755: 30 = 0xd (DW_TAG_member) 001756: DW_AT_name IMR 00175a: DW_AT_type indirect DW_FORM_ref2 0x971 00175d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 001760: 30 = 0xd (DW_TAG_member) 001761: DW_AT_name EMR 001765: DW_AT_type indirect DW_FORM_ref2 0x971 001768: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00176b: 30 = 0xd (DW_TAG_member) 00176c: DW_AT_name RTSR 001771: DW_AT_type indirect DW_FORM_ref2 0x971 001774: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 001777: 30 = 0xd (DW_TAG_member) 001778: DW_AT_name FTSR 00177d: DW_AT_type indirect DW_FORM_ref2 0x971 001780: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 001783: 30 = 0xd (DW_TAG_member) 001784: DW_AT_name SWIER 00178a: DW_AT_type indirect DW_FORM_ref2 0x971 00178d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 001790: 30 = 0xd (DW_TAG_member) 001791: DW_AT_name PR 001794: DW_AT_type indirect DW_FORM_ref2 0x971 001797: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 00179a: 0 null 00179b: 80 = 0x16 (DW_TAG_typedef) 00179c: DW_AT_name EXTI_TypeDef 0017a9: DW_AT_type indirect DW_FORM_ref2 0x1751 0017ac: DW_AT_decl_file 0x1 0017ad: DW_AT_decl_line 0x23c 0017af: DW_AT_decl_column 0x3 0017b0: 42 = 0x13 (DW_TAG_structure_type) 0017b1: DW_AT_sibling 0x180a 0017b3: DW_AT_byte_size 0x1c 0017b4: 30 = 0xd (DW_TAG_member) 0017b5: DW_AT_name ACR 0017b9: DW_AT_type indirect DW_FORM_ref2 0x971 0017bc: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0017bf: 30 = 0xd (DW_TAG_member) 0017c0: DW_AT_name KEYR 0017c5: DW_AT_type indirect DW_FORM_ref2 0x971 0017c8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0017cb: 30 = 0xd (DW_TAG_member) 0017cc: DW_AT_name OPTKEYR 0017d4: DW_AT_type indirect DW_FORM_ref2 0x971 0017d7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0017da: 30 = 0xd (DW_TAG_member) 0017db: DW_AT_name SR 0017de: DW_AT_type indirect DW_FORM_ref2 0x971 0017e1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0017e4: 30 = 0xd (DW_TAG_member) 0017e5: DW_AT_name CR 0017e8: DW_AT_type indirect DW_FORM_ref2 0x971 0017eb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 0017ee: 30 = 0xd (DW_TAG_member) 0017ef: DW_AT_name OPTCR 0017f5: DW_AT_type indirect DW_FORM_ref2 0x971 0017f8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 0017fb: 30 = 0xd (DW_TAG_member) 0017fc: DW_AT_name OPTCR1 001803: DW_AT_type indirect DW_FORM_ref2 0x971 001806: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 001809: 0 null 00180a: 80 = 0x16 (DW_TAG_typedef) 00180b: DW_AT_name FLASH_TypeDef 001819: DW_AT_type indirect DW_FORM_ref2 0x17b0 00181c: DW_AT_decl_file 0x1 00181d: DW_AT_decl_line 0x24b 00181f: DW_AT_decl_column 0x3 001820: 42 = 0x13 (DW_TAG_structure_type) 001821: DW_AT_sibling 0x183a 001823: DW_AT_byte_size 0x20 001824: 3 = 0x1 (DW_TAG_array_type) 001825: DW_AT_sibling 0x182d 001827: DW_AT_type indirect DW_FORM_ref2 0x971 00182a: 1 = 0x21 (DW_TAG_subrange_type) 00182b: DW_AT_upper_bound 0x7 00182c: 0 null 00182d: 30 = 0xd (DW_TAG_member) 00182e: DW_AT_name BTCR 001833: DW_AT_type indirect DW_FORM_ref2 0x1824 001836: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 001839: 0 null 00183a: 80 = 0x16 (DW_TAG_typedef) 00183b: DW_AT_name FMC_Bank1_TypeDef 00184d: DW_AT_type indirect DW_FORM_ref2 0x1820 001850: DW_AT_decl_file 0x1 001851: DW_AT_decl_line 0x256 001853: DW_AT_decl_column 0x3 001854: 42 = 0x13 (DW_TAG_structure_type) 001855: DW_AT_sibling 0x186e 001857: DW_AT_byte_size 0x1c 001858: 3 = 0x1 (DW_TAG_array_type) 001859: DW_AT_sibling 0x1861 00185b: DW_AT_type indirect DW_FORM_ref2 0x971 00185e: 1 = 0x21 (DW_TAG_subrange_type) 00185f: DW_AT_upper_bound 0x6 001860: 0 null 001861: 30 = 0xd (DW_TAG_member) 001862: DW_AT_name BWTR 001867: DW_AT_type indirect DW_FORM_ref2 0x1858 00186a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00186d: 0 null 00186e: 80 = 0x16 (DW_TAG_typedef) 00186f: DW_AT_name FMC_Bank1E_TypeDef 001882: DW_AT_type indirect DW_FORM_ref2 0x1854 001885: DW_AT_decl_file 0x1 001886: DW_AT_decl_line 0x25f 001888: DW_AT_decl_column 0x3 001889: 42 = 0x13 (DW_TAG_structure_type) 00188a: DW_AT_sibling 0x18da 00188c: DW_AT_byte_size 0x18 00188d: 30 = 0xd (DW_TAG_member) 00188e: DW_AT_name PCR 001892: DW_AT_type indirect DW_FORM_ref2 0x971 001895: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 001898: 30 = 0xd (DW_TAG_member) 001899: DW_AT_name SR 00189c: DW_AT_type indirect DW_FORM_ref2 0x971 00189f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0018a2: 30 = 0xd (DW_TAG_member) 0018a3: DW_AT_name PMEM 0018a8: DW_AT_type indirect DW_FORM_ref2 0x971 0018ab: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0018ae: 30 = 0xd (DW_TAG_member) 0018af: DW_AT_name PATT 0018b4: DW_AT_type indirect DW_FORM_ref2 0x971 0018b7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0018ba: 30 = 0xd (DW_TAG_member) 0018bb: DW_AT_name RESERVED0 0018c5: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0018ca: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 0018cd: 30 = 0xd (DW_TAG_member) 0018ce: DW_AT_name ECCR 0018d3: DW_AT_type indirect DW_FORM_ref2 0x971 0018d6: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 0018d9: 0 null 0018da: 80 = 0x16 (DW_TAG_typedef) 0018db: DW_AT_name FMC_Bank3_TypeDef 0018ed: DW_AT_type indirect DW_FORM_ref2 0x1889 0018f0: DW_AT_decl_file 0x1 0018f1: DW_AT_decl_line 0x26d 0018f3: DW_AT_decl_column 0x3 0018f4: 42 = 0x13 (DW_TAG_structure_type) 0018f5: DW_AT_sibling 0x1949 0018f7: DW_AT_byte_size 0x1c 0018f8: 3 = 0x1 (DW_TAG_array_type) 0018f9: DW_AT_sibling 0x1901 0018fb: DW_AT_type indirect DW_FORM_ref2 0x971 0018fe: 1 = 0x21 (DW_TAG_subrange_type) 0018ff: DW_AT_upper_bound 0x1 001900: 0 null 001901: 30 = 0xd (DW_TAG_member) 001902: DW_AT_name SDCR 001907: DW_AT_type indirect DW_FORM_ref2 0x18f8 00190a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00190d: 3 = 0x1 (DW_TAG_array_type) 00190e: DW_AT_sibling 0x1916 001910: DW_AT_type indirect DW_FORM_ref2 0x971 001913: 1 = 0x21 (DW_TAG_subrange_type) 001914: DW_AT_upper_bound 0x1 001915: 0 null 001916: 30 = 0xd (DW_TAG_member) 001917: DW_AT_name SDTR 00191c: DW_AT_type indirect DW_FORM_ref2 0x190d 00191f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 001922: 30 = 0xd (DW_TAG_member) 001923: DW_AT_name SDCMR 001929: DW_AT_type indirect DW_FORM_ref2 0x971 00192c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 00192f: 30 = 0xd (DW_TAG_member) 001930: DW_AT_name SDRTR 001936: DW_AT_type indirect DW_FORM_ref2 0x971 001939: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 00193c: 30 = 0xd (DW_TAG_member) 00193d: DW_AT_name SDSR 001942: DW_AT_type indirect DW_FORM_ref2 0x971 001945: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 001948: 0 null 001949: 80 = 0x16 (DW_TAG_typedef) 00194a: DW_AT_name FMC_Bank5_6_TypeDef 00195e: DW_AT_type indirect DW_FORM_ref2 0x18f4 001961: DW_AT_decl_file 0x1 001962: DW_AT_decl_line 0x27a 001964: DW_AT_decl_column 0x3 001965: 42 = 0x13 (DW_TAG_structure_type) 001966: DW_AT_sibling 0x19e3 001968: DW_AT_byte_size 0x28 001969: 30 = 0xd (DW_TAG_member) 00196a: DW_AT_name MODER 001970: DW_AT_type indirect DW_FORM_ref2 0x971 001973: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 001976: 30 = 0xd (DW_TAG_member) 001977: DW_AT_name OTYPER 00197e: DW_AT_type indirect DW_FORM_ref2 0x971 001981: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 001984: 30 = 0xd (DW_TAG_member) 001985: DW_AT_name OSPEEDR 00198d: DW_AT_type indirect DW_FORM_ref2 0x971 001990: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 001993: 30 = 0xd (DW_TAG_member) 001994: DW_AT_name PUPDR 00199a: DW_AT_type indirect DW_FORM_ref2 0x971 00199d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0019a0: 30 = 0xd (DW_TAG_member) 0019a1: DW_AT_name IDR 0019a5: DW_AT_type indirect DW_FORM_ref2 0x971 0019a8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 0019ab: 30 = 0xd (DW_TAG_member) 0019ac: DW_AT_name ODR 0019b0: DW_AT_type indirect DW_FORM_ref2 0x971 0019b3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 0019b6: 30 = 0xd (DW_TAG_member) 0019b7: DW_AT_name BSRR 0019bc: DW_AT_type indirect DW_FORM_ref2 0x971 0019bf: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 0019c2: 30 = 0xd (DW_TAG_member) 0019c3: DW_AT_name LCKR 0019c8: DW_AT_type indirect DW_FORM_ref2 0x971 0019cb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 0019ce: 3 = 0x1 (DW_TAG_array_type) 0019cf: DW_AT_sibling 0x19d7 0019d1: DW_AT_type indirect DW_FORM_ref2 0x971 0019d4: 1 = 0x21 (DW_TAG_subrange_type) 0019d5: DW_AT_upper_bound 0x1 0019d6: 0 null 0019d7: 30 = 0xd (DW_TAG_member) 0019d8: DW_AT_name AFR 0019dc: DW_AT_type indirect DW_FORM_ref2 0x19ce 0019df: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 0019e2: 0 null 0019e3: 80 = 0x16 (DW_TAG_typedef) 0019e4: DW_AT_name GPIO_TypeDef 0019f1: DW_AT_type indirect DW_FORM_ref2 0x1965 0019f4: DW_AT_decl_file 0x1 0019f5: DW_AT_decl_line 0x28c 0019f7: DW_AT_decl_column 0x3 0019f8: 42 = 0x13 (DW_TAG_structure_type) 0019f9: DW_AT_sibling 0x1a57 0019fb: DW_AT_byte_size 0x24 0019fc: 30 = 0xd (DW_TAG_member) 0019fd: DW_AT_name MEMRMP 001a04: DW_AT_type indirect DW_FORM_ref2 0x971 001a07: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 001a0a: 30 = 0xd (DW_TAG_member) 001a0b: DW_AT_name PMC 001a0f: DW_AT_type indirect DW_FORM_ref2 0x971 001a12: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 001a15: 3 = 0x1 (DW_TAG_array_type) 001a16: DW_AT_sibling 0x1a1e 001a18: DW_AT_type indirect DW_FORM_ref2 0x971 001a1b: 1 = 0x21 (DW_TAG_subrange_type) 001a1c: DW_AT_upper_bound 0x3 001a1d: 0 null 001a1e: 30 = 0xd (DW_TAG_member) 001a1f: DW_AT_name EXTICR 001a26: DW_AT_type indirect DW_FORM_ref2 0x1a15 001a29: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 001a2c: 30 = 0xd (DW_TAG_member) 001a2d: DW_AT_name RESERVED 001a36: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001a3b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 001a3e: 30 = 0xd (DW_TAG_member) 001a3f: DW_AT_name CBR 001a43: DW_AT_type indirect DW_FORM_ref2 0x971 001a46: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 001a49: 30 = 0xd (DW_TAG_member) 001a4a: DW_AT_name CMPCR 001a50: DW_AT_type indirect DW_FORM_ref2 0x971 001a53: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 001a56: 0 null 001a57: 80 = 0x16 (DW_TAG_typedef) 001a58: DW_AT_name SYSCFG_TypeDef 001a67: DW_AT_type indirect DW_FORM_ref2 0x19f8 001a6a: DW_AT_decl_file 0x1 001a6b: DW_AT_decl_line 0x29a 001a6d: DW_AT_decl_column 0x3 001a6e: 42 = 0x13 (DW_TAG_structure_type) 001a6f: DW_AT_sibling 0x1afa 001a71: DW_AT_byte_size 0x2c 001a72: 30 = 0xd (DW_TAG_member) 001a73: DW_AT_name CR1 001a77: DW_AT_type indirect DW_FORM_ref2 0x971 001a7a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 001a7d: 30 = 0xd (DW_TAG_member) 001a7e: DW_AT_name CR2 001a82: DW_AT_type indirect DW_FORM_ref2 0x971 001a85: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 001a88: 30 = 0xd (DW_TAG_member) 001a89: DW_AT_name OAR1 001a8e: DW_AT_type indirect DW_FORM_ref2 0x971 001a91: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 001a94: 30 = 0xd (DW_TAG_member) 001a95: DW_AT_name OAR2 001a9a: DW_AT_type indirect DW_FORM_ref2 0x971 001a9d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 001aa0: 30 = 0xd (DW_TAG_member) 001aa1: DW_AT_name TIMINGR 001aa9: DW_AT_type indirect DW_FORM_ref2 0x971 001aac: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 001aaf: 30 = 0xd (DW_TAG_member) 001ab0: DW_AT_name TIMEOUTR 001ab9: DW_AT_type indirect DW_FORM_ref2 0x971 001abc: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 001abf: 30 = 0xd (DW_TAG_member) 001ac0: DW_AT_name ISR 001ac4: DW_AT_type indirect DW_FORM_ref2 0x971 001ac7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 001aca: 30 = 0xd (DW_TAG_member) 001acb: DW_AT_name ICR 001acf: DW_AT_type indirect DW_FORM_ref2 0x971 001ad2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 001ad5: 30 = 0xd (DW_TAG_member) 001ad6: DW_AT_name PECR 001adb: DW_AT_type indirect DW_FORM_ref2 0x971 001ade: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 001ae1: 30 = 0xd (DW_TAG_member) 001ae2: DW_AT_name RXDR 001ae7: DW_AT_type indirect DW_FORM_ref2 0x971 001aea: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 001aed: 30 = 0xd (DW_TAG_member) 001aee: DW_AT_name TXDR 001af3: DW_AT_type indirect DW_FORM_ref2 0x971 001af6: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 001af9: 0 null 001afa: 80 = 0x16 (DW_TAG_typedef) 001afb: DW_AT_name I2C_TypeDef 001b07: DW_AT_type indirect DW_FORM_ref2 0x1a6e 001b0a: DW_AT_decl_file 0x1 001b0b: DW_AT_decl_line 0x2ad 001b0d: DW_AT_decl_column 0x3 001b0e: 42 = 0x13 (DW_TAG_structure_type) 001b0f: DW_AT_sibling 0x1b48 001b11: DW_AT_byte_size 0x14 001b12: 30 = 0xd (DW_TAG_member) 001b13: DW_AT_name KR 001b16: DW_AT_type indirect DW_FORM_ref2 0x971 001b19: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 001b1c: 30 = 0xd (DW_TAG_member) 001b1d: DW_AT_name PR 001b20: DW_AT_type indirect DW_FORM_ref2 0x971 001b23: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 001b26: 30 = 0xd (DW_TAG_member) 001b27: DW_AT_name RLR 001b2b: DW_AT_type indirect DW_FORM_ref2 0x971 001b2e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 001b31: 30 = 0xd (DW_TAG_member) 001b32: DW_AT_name SR 001b35: DW_AT_type indirect DW_FORM_ref2 0x971 001b38: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 001b3b: 30 = 0xd (DW_TAG_member) 001b3c: DW_AT_name WINR 001b41: DW_AT_type indirect DW_FORM_ref2 0x971 001b44: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 001b47: 0 null 001b48: 80 = 0x16 (DW_TAG_typedef) 001b49: DW_AT_name IWDG_TypeDef 001b56: DW_AT_type indirect DW_FORM_ref2 0x1b0e 001b59: DW_AT_decl_file 0x1 001b5a: DW_AT_decl_line 0x2ba 001b5c: DW_AT_decl_column 0x3 001b5d: 42 = 0x13 (DW_TAG_structure_type) 001b5e: DW_AT_sibling 0x1c6b 001b60: DW_AT_byte_size 0x4c 001b61: 3 = 0x1 (DW_TAG_array_type) 001b62: DW_AT_sibling 0x1b6c 001b64: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001b69: 1 = 0x21 (DW_TAG_subrange_type) 001b6a: DW_AT_upper_bound 0x1 001b6b: 0 null 001b6c: 30 = 0xd (DW_TAG_member) 001b6d: DW_AT_name RESERVED0 001b77: DW_AT_type indirect DW_FORM_ref2 0x1b61 001b7a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 001b7d: 30 = 0xd (DW_TAG_member) 001b7e: DW_AT_name SSCR 001b83: DW_AT_type indirect DW_FORM_ref2 0x971 001b86: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 001b89: 30 = 0xd (DW_TAG_member) 001b8a: DW_AT_name BPCR 001b8f: DW_AT_type indirect DW_FORM_ref2 0x971 001b92: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 001b95: 30 = 0xd (DW_TAG_member) 001b96: DW_AT_name AWCR 001b9b: DW_AT_type indirect DW_FORM_ref2 0x971 001b9e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 001ba1: 30 = 0xd (DW_TAG_member) 001ba2: DW_AT_name TWCR 001ba7: DW_AT_type indirect DW_FORM_ref2 0x971 001baa: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 001bad: 30 = 0xd (DW_TAG_member) 001bae: DW_AT_name GCR 001bb2: DW_AT_type indirect DW_FORM_ref2 0x971 001bb5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 001bb8: 3 = 0x1 (DW_TAG_array_type) 001bb9: DW_AT_sibling 0x1bc3 001bbb: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001bc0: 1 = 0x21 (DW_TAG_subrange_type) 001bc1: DW_AT_upper_bound 0x1 001bc2: 0 null 001bc3: 30 = 0xd (DW_TAG_member) 001bc4: DW_AT_name RESERVED1 001bce: DW_AT_type indirect DW_FORM_ref2 0x1bb8 001bd1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 001bd4: 30 = 0xd (DW_TAG_member) 001bd5: DW_AT_name SRCR 001bda: DW_AT_type indirect DW_FORM_ref2 0x971 001bdd: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 001be0: 3 = 0x1 (DW_TAG_array_type) 001be1: DW_AT_sibling 0x1beb 001be3: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001be8: 1 = 0x21 (DW_TAG_subrange_type) 001be9: DW_AT_upper_bound 0x0 001bea: 0 null 001beb: 30 = 0xd (DW_TAG_member) 001bec: DW_AT_name RESERVED2 001bf6: DW_AT_type indirect DW_FORM_ref2 0x1be0 001bf9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 001bfc: 30 = 0xd (DW_TAG_member) 001bfd: DW_AT_name BCCR 001c02: DW_AT_type indirect DW_FORM_ref2 0x971 001c05: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 001c08: 3 = 0x1 (DW_TAG_array_type) 001c09: DW_AT_sibling 0x1c13 001c0b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001c10: 1 = 0x21 (DW_TAG_subrange_type) 001c11: DW_AT_upper_bound 0x0 001c12: 0 null 001c13: 30 = 0xd (DW_TAG_member) 001c14: DW_AT_name RESERVED3 001c1e: DW_AT_type indirect DW_FORM_ref2 0x1c08 001c21: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 001c24: 30 = 0xd (DW_TAG_member) 001c25: DW_AT_name IER 001c29: DW_AT_type indirect DW_FORM_ref2 0x971 001c2c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 001c2f: 30 = 0xd (DW_TAG_member) 001c30: DW_AT_name ISR 001c34: DW_AT_type indirect DW_FORM_ref2 0x971 001c37: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 001c3a: 30 = 0xd (DW_TAG_member) 001c3b: DW_AT_name ICR 001c3f: DW_AT_type indirect DW_FORM_ref2 0x971 001c42: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 60 } 001c45: 30 = 0xd (DW_TAG_member) 001c46: DW_AT_name LIPCR 001c4c: DW_AT_type indirect DW_FORM_ref2 0x971 001c4f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 64 } 001c52: 30 = 0xd (DW_TAG_member) 001c53: DW_AT_name CPSR 001c58: DW_AT_type indirect DW_FORM_ref2 0x971 001c5b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 68 } 001c5e: 30 = 0xd (DW_TAG_member) 001c5f: DW_AT_name CDSR 001c64: DW_AT_type indirect DW_FORM_ref2 0x971 001c67: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 72 } 001c6a: 0 null 001c6b: 80 = 0x16 (DW_TAG_typedef) 001c6c: DW_AT_name LTDC_TypeDef 001c79: DW_AT_type indirect DW_FORM_ref2 0x1b5d 001c7c: DW_AT_decl_file 0x1 001c7d: DW_AT_decl_line 0x2d4 001c7f: DW_AT_decl_column 0x3 001c80: 42 = 0x13 (DW_TAG_structure_type) 001c81: DW_AT_sibling 0x1d53 001c83: DW_AT_byte_size 0x44 001c84: 30 = 0xd (DW_TAG_member) 001c85: DW_AT_name CR 001c88: DW_AT_type indirect DW_FORM_ref2 0x971 001c8b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 001c8e: 30 = 0xd (DW_TAG_member) 001c8f: DW_AT_name WHPCR 001c95: DW_AT_type indirect DW_FORM_ref2 0x971 001c98: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 001c9b: 30 = 0xd (DW_TAG_member) 001c9c: DW_AT_name WVPCR 001ca2: DW_AT_type indirect DW_FORM_ref2 0x971 001ca5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 001ca8: 30 = 0xd (DW_TAG_member) 001ca9: DW_AT_name CKCR 001cae: DW_AT_type indirect DW_FORM_ref2 0x971 001cb1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 001cb4: 30 = 0xd (DW_TAG_member) 001cb5: DW_AT_name PFCR 001cba: DW_AT_type indirect DW_FORM_ref2 0x971 001cbd: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 001cc0: 30 = 0xd (DW_TAG_member) 001cc1: DW_AT_name CACR 001cc6: DW_AT_type indirect DW_FORM_ref2 0x971 001cc9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 001ccc: 30 = 0xd (DW_TAG_member) 001ccd: DW_AT_name DCCR 001cd2: DW_AT_type indirect DW_FORM_ref2 0x971 001cd5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 001cd8: 30 = 0xd (DW_TAG_member) 001cd9: DW_AT_name BFCR 001cde: DW_AT_type indirect DW_FORM_ref2 0x971 001ce1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 001ce4: 3 = 0x1 (DW_TAG_array_type) 001ce5: DW_AT_sibling 0x1cef 001ce7: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001cec: 1 = 0x21 (DW_TAG_subrange_type) 001ced: DW_AT_upper_bound 0x1 001cee: 0 null 001cef: 30 = 0xd (DW_TAG_member) 001cf0: DW_AT_name RESERVED0 001cfa: DW_AT_type indirect DW_FORM_ref2 0x1ce4 001cfd: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 001d00: 30 = 0xd (DW_TAG_member) 001d01: DW_AT_name CFBAR 001d07: DW_AT_type indirect DW_FORM_ref2 0x971 001d0a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 001d0d: 30 = 0xd (DW_TAG_member) 001d0e: DW_AT_name CFBLR 001d14: DW_AT_type indirect DW_FORM_ref2 0x971 001d17: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 001d1a: 30 = 0xd (DW_TAG_member) 001d1b: DW_AT_name CFBLNR 001d22: DW_AT_type indirect DW_FORM_ref2 0x971 001d25: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 001d28: 3 = 0x1 (DW_TAG_array_type) 001d29: DW_AT_sibling 0x1d33 001d2b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001d30: 1 = 0x21 (DW_TAG_subrange_type) 001d31: DW_AT_upper_bound 0x2 001d32: 0 null 001d33: 30 = 0xd (DW_TAG_member) 001d34: DW_AT_name RESERVED1 001d3e: DW_AT_type indirect DW_FORM_ref2 0x1d28 001d41: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 001d44: 30 = 0xd (DW_TAG_member) 001d45: DW_AT_name CLUTWR 001d4c: DW_AT_type indirect DW_FORM_ref2 0x971 001d4f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 64 } 001d52: 0 null 001d53: 80 = 0x16 (DW_TAG_typedef) 001d54: DW_AT_name LTDC_Layer_TypeDef 001d67: DW_AT_type indirect DW_FORM_ref2 0x1c80 001d6a: DW_AT_decl_file 0x1 001d6b: DW_AT_decl_line 0x2eb 001d6d: DW_AT_decl_column 0x3 001d6e: 42 = 0x13 (DW_TAG_structure_type) 001d6f: DW_AT_sibling 0x1da1 001d71: DW_AT_byte_size 0x10 001d72: 30 = 0xd (DW_TAG_member) 001d73: DW_AT_name CR1 001d77: DW_AT_type indirect DW_FORM_ref2 0x971 001d7a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 001d7d: 30 = 0xd (DW_TAG_member) 001d7e: DW_AT_name CSR1 001d83: DW_AT_type indirect DW_FORM_ref2 0x971 001d86: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 001d89: 30 = 0xd (DW_TAG_member) 001d8a: DW_AT_name CR2 001d8e: DW_AT_type indirect DW_FORM_ref2 0x971 001d91: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 001d94: 30 = 0xd (DW_TAG_member) 001d95: DW_AT_name CSR2 001d9a: DW_AT_type indirect DW_FORM_ref2 0x971 001d9d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 001da0: 0 null 001da1: 80 = 0x16 (DW_TAG_typedef) 001da2: DW_AT_name PWR_TypeDef 001dae: DW_AT_type indirect DW_FORM_ref2 0x1d6e 001db1: DW_AT_decl_file 0x1 001db2: DW_AT_decl_line 0x2f7 001db4: DW_AT_decl_column 0x3 001db5: 42 = 0x13 (DW_TAG_structure_type) 001db6: DW_AT_sibling 0x1ff1 001db8: DW_AT_byte_size 0x94 001dba: 30 = 0xd (DW_TAG_member) 001dbb: DW_AT_name CR 001dbe: DW_AT_type indirect DW_FORM_ref2 0x971 001dc1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 001dc4: 30 = 0xd (DW_TAG_member) 001dc5: DW_AT_name PLLCFGR 001dcd: DW_AT_type indirect DW_FORM_ref2 0x971 001dd0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 001dd3: 30 = 0xd (DW_TAG_member) 001dd4: DW_AT_name CFGR 001dd9: DW_AT_type indirect DW_FORM_ref2 0x971 001ddc: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 001ddf: 30 = 0xd (DW_TAG_member) 001de0: DW_AT_name CIR 001de4: DW_AT_type indirect DW_FORM_ref2 0x971 001de7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 001dea: 30 = 0xd (DW_TAG_member) 001deb: DW_AT_name AHB1RSTR 001df4: DW_AT_type indirect DW_FORM_ref2 0x971 001df7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 001dfa: 30 = 0xd (DW_TAG_member) 001dfb: DW_AT_name AHB2RSTR 001e04: DW_AT_type indirect DW_FORM_ref2 0x971 001e07: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 001e0a: 30 = 0xd (DW_TAG_member) 001e0b: DW_AT_name AHB3RSTR 001e14: DW_AT_type indirect DW_FORM_ref2 0x971 001e17: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 001e1a: 30 = 0xd (DW_TAG_member) 001e1b: DW_AT_name RESERVED0 001e25: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001e2a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 001e2d: 30 = 0xd (DW_TAG_member) 001e2e: DW_AT_name APB1RSTR 001e37: DW_AT_type indirect DW_FORM_ref2 0x971 001e3a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 001e3d: 30 = 0xd (DW_TAG_member) 001e3e: DW_AT_name APB2RSTR 001e47: DW_AT_type indirect DW_FORM_ref2 0x971 001e4a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 001e4d: 3 = 0x1 (DW_TAG_array_type) 001e4e: DW_AT_sibling 0x1e58 001e50: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001e55: 1 = 0x21 (DW_TAG_subrange_type) 001e56: DW_AT_upper_bound 0x1 001e57: 0 null 001e58: 30 = 0xd (DW_TAG_member) 001e59: DW_AT_name RESERVED1 001e63: DW_AT_type indirect DW_FORM_ref2 0x1e4d 001e66: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 001e69: 30 = 0xd (DW_TAG_member) 001e6a: DW_AT_name AHB1ENR 001e72: DW_AT_type indirect DW_FORM_ref2 0x971 001e75: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 001e78: 30 = 0xd (DW_TAG_member) 001e79: DW_AT_name AHB2ENR 001e81: DW_AT_type indirect DW_FORM_ref2 0x971 001e84: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 001e87: 30 = 0xd (DW_TAG_member) 001e88: DW_AT_name AHB3ENR 001e90: DW_AT_type indirect DW_FORM_ref2 0x971 001e93: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 001e96: 30 = 0xd (DW_TAG_member) 001e97: DW_AT_name RESERVED2 001ea1: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001ea6: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 60 } 001ea9: 30 = 0xd (DW_TAG_member) 001eaa: DW_AT_name APB1ENR 001eb2: DW_AT_type indirect DW_FORM_ref2 0x971 001eb5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 64 } 001eb8: 30 = 0xd (DW_TAG_member) 001eb9: DW_AT_name APB2ENR 001ec1: DW_AT_type indirect DW_FORM_ref2 0x971 001ec4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 68 } 001ec7: 3 = 0x1 (DW_TAG_array_type) 001ec8: DW_AT_sibling 0x1ed2 001eca: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001ecf: 1 = 0x21 (DW_TAG_subrange_type) 001ed0: DW_AT_upper_bound 0x1 001ed1: 0 null 001ed2: 30 = 0xd (DW_TAG_member) 001ed3: DW_AT_name RESERVED3 001edd: DW_AT_type indirect DW_FORM_ref2 0x1ec7 001ee0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 72 } 001ee3: 30 = 0xd (DW_TAG_member) 001ee4: DW_AT_name AHB1LPENR 001eee: DW_AT_type indirect DW_FORM_ref2 0x971 001ef1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 80 } 001ef4: 30 = 0xd (DW_TAG_member) 001ef5: DW_AT_name AHB2LPENR 001eff: DW_AT_type indirect DW_FORM_ref2 0x971 001f02: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 84 } 001f05: 30 = 0xd (DW_TAG_member) 001f06: DW_AT_name AHB3LPENR 001f10: DW_AT_type indirect DW_FORM_ref2 0x971 001f13: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 88 } 001f16: 30 = 0xd (DW_TAG_member) 001f17: DW_AT_name RESERVED4 001f21: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001f26: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 92 } 001f29: 30 = 0xd (DW_TAG_member) 001f2a: DW_AT_name APB1LPENR 001f34: DW_AT_type indirect DW_FORM_ref2 0x971 001f37: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 96 } 001f3a: 30 = 0xd (DW_TAG_member) 001f3b: DW_AT_name APB2LPENR 001f45: DW_AT_type indirect DW_FORM_ref2 0x971 001f48: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 100 } 001f4b: 3 = 0x1 (DW_TAG_array_type) 001f4c: DW_AT_sibling 0x1f56 001f4e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001f53: 1 = 0x21 (DW_TAG_subrange_type) 001f54: DW_AT_upper_bound 0x1 001f55: 0 null 001f56: 30 = 0xd (DW_TAG_member) 001f57: DW_AT_name RESERVED5 001f61: DW_AT_type indirect DW_FORM_ref2 0x1f4b 001f64: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 104 } 001f67: 30 = 0xd (DW_TAG_member) 001f68: DW_AT_name BDCR 001f6d: DW_AT_type indirect DW_FORM_ref2 0x971 001f70: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 112 } 001f73: 30 = 0xd (DW_TAG_member) 001f74: DW_AT_name CSR 001f78: DW_AT_type indirect DW_FORM_ref2 0x971 001f7b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 116 } 001f7e: 3 = 0x1 (DW_TAG_array_type) 001f7f: DW_AT_sibling 0x1f89 001f81: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 001f86: 1 = 0x21 (DW_TAG_subrange_type) 001f87: DW_AT_upper_bound 0x1 001f88: 0 null 001f89: 30 = 0xd (DW_TAG_member) 001f8a: DW_AT_name RESERVED6 001f94: DW_AT_type indirect DW_FORM_ref2 0x1f7e 001f97: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 120 } 001f9a: 30 = 0xd (DW_TAG_member) 001f9b: DW_AT_name SSCGR 001fa1: DW_AT_type indirect DW_FORM_ref2 0x971 001fa4: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 128 } 001fa8: 30 = 0xd (DW_TAG_member) 001fa9: DW_AT_name PLLI2SCFGR 001fb4: DW_AT_type indirect DW_FORM_ref2 0x971 001fb7: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 132 } 001fbb: 30 = 0xd (DW_TAG_member) 001fbc: DW_AT_name PLLSAICFGR 001fc7: DW_AT_type indirect DW_FORM_ref2 0x971 001fca: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 136 } 001fce: 30 = 0xd (DW_TAG_member) 001fcf: DW_AT_name DCKCFGR1 001fd8: DW_AT_type indirect DW_FORM_ref2 0x971 001fdb: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 140 } 001fdf: 30 = 0xd (DW_TAG_member) 001fe0: DW_AT_name DCKCFGR2 001fe9: DW_AT_type indirect DW_FORM_ref2 0x971 001fec: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 144 } 001ff0: 0 null 001ff1: 80 = 0x16 (DW_TAG_typedef) 001ff2: DW_AT_name RCC_TypeDef 001ffe: DW_AT_type indirect DW_FORM_ref2 0x1db5 002001: DW_AT_decl_file 0x1 002002: DW_AT_decl_line 0x322 002004: DW_AT_decl_column 0x3 002005: 42 = 0x13 (DW_TAG_structure_type) 002006: DW_AT_sibling 0x22d1 002008: DW_AT_byte_size 0xd0 00200a: 30 = 0xd (DW_TAG_member) 00200b: DW_AT_name TR 00200e: DW_AT_type indirect DW_FORM_ref2 0x971 002011: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 002014: 30 = 0xd (DW_TAG_member) 002015: DW_AT_name DR 002018: DW_AT_type indirect DW_FORM_ref2 0x971 00201b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00201e: 30 = 0xd (DW_TAG_member) 00201f: DW_AT_name CR 002022: DW_AT_type indirect DW_FORM_ref2 0x971 002025: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 002028: 30 = 0xd (DW_TAG_member) 002029: DW_AT_name ISR 00202d: DW_AT_type indirect DW_FORM_ref2 0x971 002030: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 002033: 30 = 0xd (DW_TAG_member) 002034: DW_AT_name PRER 002039: DW_AT_type indirect DW_FORM_ref2 0x971 00203c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 00203f: 30 = 0xd (DW_TAG_member) 002040: DW_AT_name WUTR 002045: DW_AT_type indirect DW_FORM_ref2 0x971 002048: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 00204b: 30 = 0xd (DW_TAG_member) 00204c: DW_AT_name reserved 002055: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00205a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 00205d: 30 = 0xd (DW_TAG_member) 00205e: DW_AT_name ALRMAR 002065: DW_AT_type indirect DW_FORM_ref2 0x971 002068: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 00206b: 30 = 0xd (DW_TAG_member) 00206c: DW_AT_name ALRMBR 002073: DW_AT_type indirect DW_FORM_ref2 0x971 002076: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 002079: 30 = 0xd (DW_TAG_member) 00207a: DW_AT_name WPR 00207e: DW_AT_type indirect DW_FORM_ref2 0x971 002081: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 002084: 30 = 0xd (DW_TAG_member) 002085: DW_AT_name SSR 002089: DW_AT_type indirect DW_FORM_ref2 0x971 00208c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 00208f: 30 = 0xd (DW_TAG_member) 002090: DW_AT_name SHIFTR 002097: DW_AT_type indirect DW_FORM_ref2 0x971 00209a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 00209d: 30 = 0xd (DW_TAG_member) 00209e: DW_AT_name TSTR 0020a3: DW_AT_type indirect DW_FORM_ref2 0x971 0020a6: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 0020a9: 30 = 0xd (DW_TAG_member) 0020aa: DW_AT_name TSDR 0020af: DW_AT_type indirect DW_FORM_ref2 0x971 0020b2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 0020b5: 30 = 0xd (DW_TAG_member) 0020b6: DW_AT_name TSSSR 0020bc: DW_AT_type indirect DW_FORM_ref2 0x971 0020bf: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 0020c2: 30 = 0xd (DW_TAG_member) 0020c3: DW_AT_name CALR 0020c8: DW_AT_type indirect DW_FORM_ref2 0x971 0020cb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 60 } 0020ce: 30 = 0xd (DW_TAG_member) 0020cf: DW_AT_name TAMPCR 0020d6: DW_AT_type indirect DW_FORM_ref2 0x971 0020d9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 64 } 0020dc: 30 = 0xd (DW_TAG_member) 0020dd: DW_AT_name ALRMASSR 0020e6: DW_AT_type indirect DW_FORM_ref2 0x971 0020e9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 68 } 0020ec: 30 = 0xd (DW_TAG_member) 0020ed: DW_AT_name ALRMBSSR 0020f6: DW_AT_type indirect DW_FORM_ref2 0x971 0020f9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 72 } 0020fc: 30 = 0xd (DW_TAG_member) 0020fd: DW_AT_name OR 002100: DW_AT_type indirect DW_FORM_ref2 0x971 002103: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 76 } 002106: 30 = 0xd (DW_TAG_member) 002107: DW_AT_name BKP0R 00210d: DW_AT_type indirect DW_FORM_ref2 0x971 002110: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 80 } 002113: 30 = 0xd (DW_TAG_member) 002114: DW_AT_name BKP1R 00211a: DW_AT_type indirect DW_FORM_ref2 0x971 00211d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 84 } 002120: 30 = 0xd (DW_TAG_member) 002121: DW_AT_name BKP2R 002127: DW_AT_type indirect DW_FORM_ref2 0x971 00212a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 88 } 00212d: 30 = 0xd (DW_TAG_member) 00212e: DW_AT_name BKP3R 002134: DW_AT_type indirect DW_FORM_ref2 0x971 002137: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 92 } 00213a: 30 = 0xd (DW_TAG_member) 00213b: DW_AT_name BKP4R 002141: DW_AT_type indirect DW_FORM_ref2 0x971 002144: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 96 } 002147: 30 = 0xd (DW_TAG_member) 002148: DW_AT_name BKP5R 00214e: DW_AT_type indirect DW_FORM_ref2 0x971 002151: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 100 } 002154: 30 = 0xd (DW_TAG_member) 002155: DW_AT_name BKP6R 00215b: DW_AT_type indirect DW_FORM_ref2 0x971 00215e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 104 } 002161: 30 = 0xd (DW_TAG_member) 002162: DW_AT_name BKP7R 002168: DW_AT_type indirect DW_FORM_ref2 0x971 00216b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 108 } 00216e: 30 = 0xd (DW_TAG_member) 00216f: DW_AT_name BKP8R 002175: DW_AT_type indirect DW_FORM_ref2 0x971 002178: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 112 } 00217b: 30 = 0xd (DW_TAG_member) 00217c: DW_AT_name BKP9R 002182: DW_AT_type indirect DW_FORM_ref2 0x971 002185: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 116 } 002188: 30 = 0xd (DW_TAG_member) 002189: DW_AT_name BKP10R 002190: DW_AT_type indirect DW_FORM_ref2 0x971 002193: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 120 } 002196: 30 = 0xd (DW_TAG_member) 002197: DW_AT_name BKP11R 00219e: DW_AT_type indirect DW_FORM_ref2 0x971 0021a1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 124 } 0021a4: 30 = 0xd (DW_TAG_member) 0021a5: DW_AT_name BKP12R 0021ac: DW_AT_type indirect DW_FORM_ref2 0x971 0021af: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 128 } 0021b3: 30 = 0xd (DW_TAG_member) 0021b4: DW_AT_name BKP13R 0021bb: DW_AT_type indirect DW_FORM_ref2 0x971 0021be: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 132 } 0021c2: 30 = 0xd (DW_TAG_member) 0021c3: DW_AT_name BKP14R 0021ca: DW_AT_type indirect DW_FORM_ref2 0x971 0021cd: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 136 } 0021d1: 30 = 0xd (DW_TAG_member) 0021d2: DW_AT_name BKP15R 0021d9: DW_AT_type indirect DW_FORM_ref2 0x971 0021dc: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 140 } 0021e0: 30 = 0xd (DW_TAG_member) 0021e1: DW_AT_name BKP16R 0021e8: DW_AT_type indirect DW_FORM_ref2 0x971 0021eb: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 144 } 0021ef: 30 = 0xd (DW_TAG_member) 0021f0: DW_AT_name BKP17R 0021f7: DW_AT_type indirect DW_FORM_ref2 0x971 0021fa: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 148 } 0021fe: 30 = 0xd (DW_TAG_member) 0021ff: DW_AT_name BKP18R 002206: DW_AT_type indirect DW_FORM_ref2 0x971 002209: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 152 } 00220d: 30 = 0xd (DW_TAG_member) 00220e: DW_AT_name BKP19R 002215: DW_AT_type indirect DW_FORM_ref2 0x971 002218: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 156 } 00221c: 30 = 0xd (DW_TAG_member) 00221d: DW_AT_name BKP20R 002224: DW_AT_type indirect DW_FORM_ref2 0x971 002227: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 160 } 00222b: 30 = 0xd (DW_TAG_member) 00222c: DW_AT_name BKP21R 002233: DW_AT_type indirect DW_FORM_ref2 0x971 002236: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 164 } 00223a: 30 = 0xd (DW_TAG_member) 00223b: DW_AT_name BKP22R 002242: DW_AT_type indirect DW_FORM_ref2 0x971 002245: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 168 } 002249: 30 = 0xd (DW_TAG_member) 00224a: DW_AT_name BKP23R 002251: DW_AT_type indirect DW_FORM_ref2 0x971 002254: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 172 } 002258: 30 = 0xd (DW_TAG_member) 002259: DW_AT_name BKP24R 002260: DW_AT_type indirect DW_FORM_ref2 0x971 002263: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 176 } 002267: 30 = 0xd (DW_TAG_member) 002268: DW_AT_name BKP25R 00226f: DW_AT_type indirect DW_FORM_ref2 0x971 002272: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 180 } 002276: 30 = 0xd (DW_TAG_member) 002277: DW_AT_name BKP26R 00227e: DW_AT_type indirect DW_FORM_ref2 0x971 002281: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 184 } 002285: 30 = 0xd (DW_TAG_member) 002286: DW_AT_name BKP27R 00228d: DW_AT_type indirect DW_FORM_ref2 0x971 002290: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 188 } 002294: 30 = 0xd (DW_TAG_member) 002295: DW_AT_name BKP28R 00229c: DW_AT_type indirect DW_FORM_ref2 0x971 00229f: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 192 } 0022a3: 30 = 0xd (DW_TAG_member) 0022a4: DW_AT_name BKP29R 0022ab: DW_AT_type indirect DW_FORM_ref2 0x971 0022ae: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 196 } 0022b2: 30 = 0xd (DW_TAG_member) 0022b3: DW_AT_name BKP30R 0022ba: DW_AT_type indirect DW_FORM_ref2 0x971 0022bd: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 200 } 0022c1: 30 = 0xd (DW_TAG_member) 0022c2: DW_AT_name BKP31R 0022c9: DW_AT_type indirect DW_FORM_ref2 0x971 0022cc: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 204 } 0022d0: 0 null 0022d1: 80 = 0x16 (DW_TAG_typedef) 0022d2: DW_AT_name RTC_TypeDef 0022de: DW_AT_type indirect DW_FORM_ref2 0x2005 0022e1: DW_AT_decl_file 0x1 0022e2: DW_AT_decl_line 0x35e 0022e4: DW_AT_decl_column 0x3 0022e5: 42 = 0x13 (DW_TAG_structure_type) 0022e6: DW_AT_sibling 0x22f5 0022e8: DW_AT_byte_size 0x4 0022e9: 30 = 0xd (DW_TAG_member) 0022ea: DW_AT_name GCR 0022ee: DW_AT_type indirect DW_FORM_ref2 0x971 0022f1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0022f4: 0 null 0022f5: 80 = 0x16 (DW_TAG_typedef) 0022f6: DW_AT_name SAI_TypeDef 002302: DW_AT_type indirect DW_FORM_ref2 0x22e5 002305: DW_AT_decl_file 0x1 002306: DW_AT_decl_line 0x368 002308: DW_AT_decl_column 0x3 002309: 42 = 0x13 (DW_TAG_structure_type) 00230a: DW_AT_sibling 0x2369 00230c: DW_AT_byte_size 0x20 00230d: 30 = 0xd (DW_TAG_member) 00230e: DW_AT_name CR1 002312: DW_AT_type indirect DW_FORM_ref2 0x971 002315: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 002318: 30 = 0xd (DW_TAG_member) 002319: DW_AT_name CR2 00231d: DW_AT_type indirect DW_FORM_ref2 0x971 002320: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 002323: 30 = 0xd (DW_TAG_member) 002324: DW_AT_name FRCR 002329: DW_AT_type indirect DW_FORM_ref2 0x971 00232c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 00232f: 30 = 0xd (DW_TAG_member) 002330: DW_AT_name SLOTR 002336: DW_AT_type indirect DW_FORM_ref2 0x971 002339: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00233c: 30 = 0xd (DW_TAG_member) 00233d: DW_AT_name IMR 002341: DW_AT_type indirect DW_FORM_ref2 0x971 002344: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 002347: 30 = 0xd (DW_TAG_member) 002348: DW_AT_name SR 00234b: DW_AT_type indirect DW_FORM_ref2 0x971 00234e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 002351: 30 = 0xd (DW_TAG_member) 002352: DW_AT_name CLRFR 002358: DW_AT_type indirect DW_FORM_ref2 0x971 00235b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 00235e: 30 = 0xd (DW_TAG_member) 00235f: DW_AT_name DR 002362: DW_AT_type indirect DW_FORM_ref2 0x971 002365: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 002368: 0 null 002369: 80 = 0x16 (DW_TAG_typedef) 00236a: DW_AT_name SAI_Block_TypeDef 00237c: DW_AT_type indirect DW_FORM_ref2 0x2309 00237f: DW_AT_decl_file 0x1 002380: DW_AT_decl_line 0x374 002382: DW_AT_decl_column 0x3 002383: 42 = 0x13 (DW_TAG_structure_type) 002384: DW_AT_sibling 0x23d3 002386: DW_AT_byte_size 0x1c 002387: 30 = 0xd (DW_TAG_member) 002388: DW_AT_name CR 00238b: DW_AT_type indirect DW_FORM_ref2 0x971 00238e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 002391: 30 = 0xd (DW_TAG_member) 002392: DW_AT_name IMR 002396: DW_AT_type indirect DW_FORM_ref2 0x971 002399: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00239c: 30 = 0xd (DW_TAG_member) 00239d: DW_AT_name SR 0023a0: DW_AT_type indirect DW_FORM_ref2 0x971 0023a3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0023a6: 30 = 0xd (DW_TAG_member) 0023a7: DW_AT_name IFCR 0023ac: DW_AT_type indirect DW_FORM_ref2 0x971 0023af: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0023b2: 30 = 0xd (DW_TAG_member) 0023b3: DW_AT_name DR 0023b6: DW_AT_type indirect DW_FORM_ref2 0x971 0023b9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 0023bc: 30 = 0xd (DW_TAG_member) 0023bd: DW_AT_name CSR 0023c1: DW_AT_type indirect DW_FORM_ref2 0x971 0023c4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 0023c7: 30 = 0xd (DW_TAG_member) 0023c8: DW_AT_name DIR 0023cc: DW_AT_type indirect DW_FORM_ref2 0x971 0023cf: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 0023d2: 0 null 0023d3: 80 = 0x16 (DW_TAG_typedef) 0023d4: DW_AT_name SPDIFRX_TypeDef 0023e4: DW_AT_type indirect DW_FORM_ref2 0x2383 0023e7: DW_AT_decl_file 0x1 0023e8: DW_AT_decl_line 0x383 0023ea: DW_AT_decl_column 0x3 0023eb: 42 = 0x13 (DW_TAG_structure_type) 0023ec: DW_AT_sibling 0x250f 0023ee: DW_AT_byte_size 0x84 0023f0: 30 = 0xd (DW_TAG_member) 0023f1: DW_AT_name POWER 0023f7: DW_AT_type indirect DW_FORM_ref2 0x971 0023fa: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0023fd: 30 = 0xd (DW_TAG_member) 0023fe: DW_AT_name CLKCR 002404: DW_AT_type indirect DW_FORM_ref2 0x971 002407: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00240a: 30 = 0xd (DW_TAG_member) 00240b: DW_AT_name ARG 00240f: DW_AT_type indirect DW_FORM_ref2 0x971 002412: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 002415: 30 = 0xd (DW_TAG_member) 002416: DW_AT_name CMD 00241a: DW_AT_type indirect DW_FORM_ref2 0x971 00241d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 002420: 30 = 0xd (DW_TAG_member) 002421: DW_AT_name RESPCMD 002429: DW_AT_type indirect DW_FORM_ref2 0x2515 00242c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 00242f: 30 = 0xd (DW_TAG_member) 002430: DW_AT_name RESP1 002436: DW_AT_type indirect DW_FORM_ref2 0x2515 002439: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 00243c: 30 = 0xd (DW_TAG_member) 00243d: DW_AT_name RESP2 002443: DW_AT_type indirect DW_FORM_ref2 0x2515 002446: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 002449: 30 = 0xd (DW_TAG_member) 00244a: DW_AT_name RESP3 002450: DW_AT_type indirect DW_FORM_ref2 0x2515 002453: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 002456: 30 = 0xd (DW_TAG_member) 002457: DW_AT_name RESP4 00245d: DW_AT_type indirect DW_FORM_ref2 0x2515 002460: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 002463: 30 = 0xd (DW_TAG_member) 002464: DW_AT_name DTIMER 00246b: DW_AT_type indirect DW_FORM_ref2 0x971 00246e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 002471: 30 = 0xd (DW_TAG_member) 002472: DW_AT_name DLEN 002477: DW_AT_type indirect DW_FORM_ref2 0x971 00247a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 00247d: 30 = 0xd (DW_TAG_member) 00247e: DW_AT_name DCTRL 002484: DW_AT_type indirect DW_FORM_ref2 0x971 002487: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 00248a: 30 = 0xd (DW_TAG_member) 00248b: DW_AT_name DCOUNT 002492: DW_AT_type indirect DW_FORM_ref2 0x2515 002495: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 002498: 30 = 0xd (DW_TAG_member) 002499: DW_AT_name STA 00249d: DW_AT_type indirect DW_FORM_ref2 0x2515 0024a0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 0024a3: 30 = 0xd (DW_TAG_member) 0024a4: DW_AT_name ICR 0024a8: DW_AT_type indirect DW_FORM_ref2 0x971 0024ab: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 0024ae: 30 = 0xd (DW_TAG_member) 0024af: DW_AT_name MASK 0024b4: DW_AT_type indirect DW_FORM_ref2 0x971 0024b7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 60 } 0024ba: 3 = 0x1 (DW_TAG_array_type) 0024bb: DW_AT_sibling 0x24c5 0024bd: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0024c2: 1 = 0x21 (DW_TAG_subrange_type) 0024c3: DW_AT_upper_bound 0x1 0024c4: 0 null 0024c5: 30 = 0xd (DW_TAG_member) 0024c6: DW_AT_name RESERVED0 0024d0: DW_AT_type indirect DW_FORM_ref2 0x24ba 0024d3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 64 } 0024d6: 30 = 0xd (DW_TAG_member) 0024d7: DW_AT_name FIFOCNT 0024df: DW_AT_type indirect DW_FORM_ref2 0x2515 0024e2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 72 } 0024e5: 3 = 0x1 (DW_TAG_array_type) 0024e6: DW_AT_sibling 0x24f0 0024e8: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0024ed: 1 = 0x21 (DW_TAG_subrange_type) 0024ee: DW_AT_upper_bound 0xc 0024ef: 0 null 0024f0: 30 = 0xd (DW_TAG_member) 0024f1: DW_AT_name RESERVED1 0024fb: DW_AT_type indirect DW_FORM_ref2 0x24e5 0024fe: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 76 } 002501: 30 = 0xd (DW_TAG_member) 002502: DW_AT_name FIFO 002507: DW_AT_type indirect DW_FORM_ref2 0x971 00250a: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 128 } 00250e: 0 null 00250f: 17 = 0x26 (DW_TAG_const_type) 002510: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 002515: 116 = 0x35 (DW_TAG_volatile_type) 002516: DW_AT_type indirect DW_FORM_ref2 0x250f 002519: 80 = 0x16 (DW_TAG_typedef) 00251a: DW_AT_name SDMMC_TypeDef 002528: DW_AT_type indirect DW_FORM_ref2 0x23eb 00252b: DW_AT_decl_file 0x1 00252c: DW_AT_decl_line 0x39f 00252e: DW_AT_decl_column 0x3 00252f: 42 = 0x13 (DW_TAG_structure_type) 002530: DW_AT_sibling 0x25a3 002532: DW_AT_byte_size 0x24 002533: 30 = 0xd (DW_TAG_member) 002534: DW_AT_name CR1 002538: DW_AT_type indirect DW_FORM_ref2 0x971 00253b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00253e: 30 = 0xd (DW_TAG_member) 00253f: DW_AT_name CR2 002543: DW_AT_type indirect DW_FORM_ref2 0x971 002546: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 002549: 30 = 0xd (DW_TAG_member) 00254a: DW_AT_name SR 00254d: DW_AT_type indirect DW_FORM_ref2 0x971 002550: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 002553: 30 = 0xd (DW_TAG_member) 002554: DW_AT_name DR 002557: DW_AT_type indirect DW_FORM_ref2 0x971 00255a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00255d: 30 = 0xd (DW_TAG_member) 00255e: DW_AT_name CRCPR 002564: DW_AT_type indirect DW_FORM_ref2 0x971 002567: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 00256a: 30 = 0xd (DW_TAG_member) 00256b: DW_AT_name RXCRCR 002572: DW_AT_type indirect DW_FORM_ref2 0x971 002575: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 002578: 30 = 0xd (DW_TAG_member) 002579: DW_AT_name TXCRCR 002580: DW_AT_type indirect DW_FORM_ref2 0x971 002583: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 002586: 30 = 0xd (DW_TAG_member) 002587: DW_AT_name I2SCFGR 00258f: DW_AT_type indirect DW_FORM_ref2 0x971 002592: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 002595: 30 = 0xd (DW_TAG_member) 002596: DW_AT_name I2SPR 00259c: DW_AT_type indirect DW_FORM_ref2 0x971 00259f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 0025a2: 0 null 0025a3: 80 = 0x16 (DW_TAG_typedef) 0025a4: DW_AT_name SPI_TypeDef 0025b0: DW_AT_type indirect DW_FORM_ref2 0x252f 0025b3: DW_AT_decl_file 0x1 0025b4: DW_AT_decl_line 0x3b0 0025b6: DW_AT_decl_column 0x3 0025b7: 42 = 0x13 (DW_TAG_structure_type) 0025b8: DW_AT_sibling 0x264c 0025ba: DW_AT_byte_size 0x34 0025bb: 30 = 0xd (DW_TAG_member) 0025bc: DW_AT_name CR 0025bf: DW_AT_type indirect DW_FORM_ref2 0x971 0025c2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0025c5: 30 = 0xd (DW_TAG_member) 0025c6: DW_AT_name DCR 0025ca: DW_AT_type indirect DW_FORM_ref2 0x971 0025cd: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0025d0: 30 = 0xd (DW_TAG_member) 0025d1: DW_AT_name SR 0025d4: DW_AT_type indirect DW_FORM_ref2 0x971 0025d7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0025da: 30 = 0xd (DW_TAG_member) 0025db: DW_AT_name FCR 0025df: DW_AT_type indirect DW_FORM_ref2 0x971 0025e2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0025e5: 30 = 0xd (DW_TAG_member) 0025e6: DW_AT_name DLR 0025ea: DW_AT_type indirect DW_FORM_ref2 0x971 0025ed: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 0025f0: 30 = 0xd (DW_TAG_member) 0025f1: DW_AT_name CCR 0025f5: DW_AT_type indirect DW_FORM_ref2 0x971 0025f8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 0025fb: 30 = 0xd (DW_TAG_member) 0025fc: DW_AT_name AR 0025ff: DW_AT_type indirect DW_FORM_ref2 0x971 002602: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 002605: 30 = 0xd (DW_TAG_member) 002606: DW_AT_name ABR 00260a: DW_AT_type indirect DW_FORM_ref2 0x971 00260d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 002610: 30 = 0xd (DW_TAG_member) 002611: DW_AT_name DR 002614: DW_AT_type indirect DW_FORM_ref2 0x971 002617: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 00261a: 30 = 0xd (DW_TAG_member) 00261b: DW_AT_name PSMKR 002621: DW_AT_type indirect DW_FORM_ref2 0x971 002624: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 002627: 30 = 0xd (DW_TAG_member) 002628: DW_AT_name PSMAR 00262e: DW_AT_type indirect DW_FORM_ref2 0x971 002631: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 002634: 30 = 0xd (DW_TAG_member) 002635: DW_AT_name PIR 002639: DW_AT_type indirect DW_FORM_ref2 0x971 00263c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 00263f: 30 = 0xd (DW_TAG_member) 002640: DW_AT_name LPTR 002645: DW_AT_type indirect DW_FORM_ref2 0x971 002648: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 00264b: 0 null 00264c: 80 = 0x16 (DW_TAG_typedef) 00264d: DW_AT_name QUADSPI_TypeDef 00265d: DW_AT_type indirect DW_FORM_ref2 0x25b7 002660: DW_AT_decl_file 0x1 002661: DW_AT_decl_line 0x3c5 002663: DW_AT_decl_column 0x3 002664: 42 = 0x13 (DW_TAG_structure_type) 002665: DW_AT_sibling 0x2796 002667: DW_AT_byte_size 0x68 002668: 30 = 0xd (DW_TAG_member) 002669: DW_AT_name CR1 00266d: DW_AT_type indirect DW_FORM_ref2 0x971 002670: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 002673: 30 = 0xd (DW_TAG_member) 002674: DW_AT_name CR2 002678: DW_AT_type indirect DW_FORM_ref2 0x971 00267b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00267e: 30 = 0xd (DW_TAG_member) 00267f: DW_AT_name SMCR 002684: DW_AT_type indirect DW_FORM_ref2 0x971 002687: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 00268a: 30 = 0xd (DW_TAG_member) 00268b: DW_AT_name DIER 002690: DW_AT_type indirect DW_FORM_ref2 0x971 002693: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 002696: 30 = 0xd (DW_TAG_member) 002697: DW_AT_name SR 00269a: DW_AT_type indirect DW_FORM_ref2 0x971 00269d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 0026a0: 30 = 0xd (DW_TAG_member) 0026a1: DW_AT_name EGR 0026a5: DW_AT_type indirect DW_FORM_ref2 0x971 0026a8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 0026ab: 30 = 0xd (DW_TAG_member) 0026ac: DW_AT_name CCMR1 0026b2: DW_AT_type indirect DW_FORM_ref2 0x971 0026b5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 0026b8: 30 = 0xd (DW_TAG_member) 0026b9: DW_AT_name CCMR2 0026bf: DW_AT_type indirect DW_FORM_ref2 0x971 0026c2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 0026c5: 30 = 0xd (DW_TAG_member) 0026c6: DW_AT_name CCER 0026cb: DW_AT_type indirect DW_FORM_ref2 0x971 0026ce: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 0026d1: 30 = 0xd (DW_TAG_member) 0026d2: DW_AT_name CNT 0026d6: DW_AT_type indirect DW_FORM_ref2 0x971 0026d9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 0026dc: 30 = 0xd (DW_TAG_member) 0026dd: DW_AT_name PSC 0026e1: DW_AT_type indirect DW_FORM_ref2 0x971 0026e4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 0026e7: 30 = 0xd (DW_TAG_member) 0026e8: DW_AT_name ARR 0026ec: DW_AT_type indirect DW_FORM_ref2 0x971 0026ef: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 0026f2: 30 = 0xd (DW_TAG_member) 0026f3: DW_AT_name RCR 0026f7: DW_AT_type indirect DW_FORM_ref2 0x971 0026fa: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 0026fd: 30 = 0xd (DW_TAG_member) 0026fe: DW_AT_name CCR1 002703: DW_AT_type indirect DW_FORM_ref2 0x971 002706: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 002709: 30 = 0xd (DW_TAG_member) 00270a: DW_AT_name CCR2 00270f: DW_AT_type indirect DW_FORM_ref2 0x971 002712: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 002715: 30 = 0xd (DW_TAG_member) 002716: DW_AT_name CCR3 00271b: DW_AT_type indirect DW_FORM_ref2 0x971 00271e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 60 } 002721: 30 = 0xd (DW_TAG_member) 002722: DW_AT_name CCR4 002727: DW_AT_type indirect DW_FORM_ref2 0x971 00272a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 64 } 00272d: 30 = 0xd (DW_TAG_member) 00272e: DW_AT_name BDTR 002733: DW_AT_type indirect DW_FORM_ref2 0x971 002736: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 68 } 002739: 30 = 0xd (DW_TAG_member) 00273a: DW_AT_name DCR 00273e: DW_AT_type indirect DW_FORM_ref2 0x971 002741: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 72 } 002744: 30 = 0xd (DW_TAG_member) 002745: DW_AT_name DMAR 00274a: DW_AT_type indirect DW_FORM_ref2 0x971 00274d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 76 } 002750: 30 = 0xd (DW_TAG_member) 002751: DW_AT_name OR 002754: DW_AT_type indirect DW_FORM_ref2 0x971 002757: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 80 } 00275a: 30 = 0xd (DW_TAG_member) 00275b: DW_AT_name CCMR3 002761: DW_AT_type indirect DW_FORM_ref2 0x971 002764: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 84 } 002767: 30 = 0xd (DW_TAG_member) 002768: DW_AT_name CCR5 00276d: DW_AT_type indirect DW_FORM_ref2 0x971 002770: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 88 } 002773: 30 = 0xd (DW_TAG_member) 002774: DW_AT_name CCR6 002779: DW_AT_type indirect DW_FORM_ref2 0x971 00277c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 92 } 00277f: 30 = 0xd (DW_TAG_member) 002780: DW_AT_name AF1 002784: DW_AT_type indirect DW_FORM_ref2 0x971 002787: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 96 } 00278a: 30 = 0xd (DW_TAG_member) 00278b: DW_AT_name AF2 00278f: DW_AT_type indirect DW_FORM_ref2 0x971 002792: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 100 } 002795: 0 null 002796: 80 = 0x16 (DW_TAG_typedef) 002797: DW_AT_name TIM_TypeDef 0027a3: DW_AT_type indirect DW_FORM_ref2 0x2664 0027a6: DW_AT_decl_file 0x1 0027a7: DW_AT_decl_line 0x3e8 0027a9: DW_AT_decl_column 0x3 0027aa: 42 = 0x13 (DW_TAG_structure_type) 0027ab: DW_AT_sibling 0x2807 0027ad: DW_AT_byte_size 0x20 0027ae: 30 = 0xd (DW_TAG_member) 0027af: DW_AT_name ISR 0027b3: DW_AT_type indirect DW_FORM_ref2 0x971 0027b6: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0027b9: 30 = 0xd (DW_TAG_member) 0027ba: DW_AT_name ICR 0027be: DW_AT_type indirect DW_FORM_ref2 0x971 0027c1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0027c4: 30 = 0xd (DW_TAG_member) 0027c5: DW_AT_name IER 0027c9: DW_AT_type indirect DW_FORM_ref2 0x971 0027cc: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0027cf: 30 = 0xd (DW_TAG_member) 0027d0: DW_AT_name CFGR 0027d5: DW_AT_type indirect DW_FORM_ref2 0x971 0027d8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0027db: 30 = 0xd (DW_TAG_member) 0027dc: DW_AT_name CR 0027df: DW_AT_type indirect DW_FORM_ref2 0x971 0027e2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 0027e5: 30 = 0xd (DW_TAG_member) 0027e6: DW_AT_name CMP 0027ea: DW_AT_type indirect DW_FORM_ref2 0x971 0027ed: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 0027f0: 30 = 0xd (DW_TAG_member) 0027f1: DW_AT_name ARR 0027f5: DW_AT_type indirect DW_FORM_ref2 0x971 0027f8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 0027fb: 30 = 0xd (DW_TAG_member) 0027fc: DW_AT_name CNT 002800: DW_AT_type indirect DW_FORM_ref2 0x971 002803: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 002806: 0 null 002807: 80 = 0x16 (DW_TAG_typedef) 002808: DW_AT_name LPTIM_TypeDef 002816: DW_AT_type indirect DW_FORM_ref2 0x27aa 002819: DW_AT_decl_file 0x1 00281a: DW_AT_decl_line 0x3f7 00281c: DW_AT_decl_column 0x3 00281d: 42 = 0x13 (DW_TAG_structure_type) 00281e: DW_AT_sibling 0x289d 002820: DW_AT_byte_size 0x2c 002821: 30 = 0xd (DW_TAG_member) 002822: DW_AT_name CR1 002826: DW_AT_type indirect DW_FORM_ref2 0x971 002829: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00282c: 30 = 0xd (DW_TAG_member) 00282d: DW_AT_name CR2 002831: DW_AT_type indirect DW_FORM_ref2 0x971 002834: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 002837: 30 = 0xd (DW_TAG_member) 002838: DW_AT_name CR3 00283c: DW_AT_type indirect DW_FORM_ref2 0x971 00283f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 002842: 30 = 0xd (DW_TAG_member) 002843: DW_AT_name BRR 002847: DW_AT_type indirect DW_FORM_ref2 0x971 00284a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00284d: 30 = 0xd (DW_TAG_member) 00284e: DW_AT_name GTPR 002853: DW_AT_type indirect DW_FORM_ref2 0x971 002856: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 002859: 30 = 0xd (DW_TAG_member) 00285a: DW_AT_name RTOR 00285f: DW_AT_type indirect DW_FORM_ref2 0x971 002862: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 002865: 30 = 0xd (DW_TAG_member) 002866: DW_AT_name RQR 00286a: DW_AT_type indirect DW_FORM_ref2 0x971 00286d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 002870: 30 = 0xd (DW_TAG_member) 002871: DW_AT_name ISR 002875: DW_AT_type indirect DW_FORM_ref2 0x971 002878: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 00287b: 30 = 0xd (DW_TAG_member) 00287c: DW_AT_name ICR 002880: DW_AT_type indirect DW_FORM_ref2 0x971 002883: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 002886: 30 = 0xd (DW_TAG_member) 002887: DW_AT_name RDR 00288b: DW_AT_type indirect DW_FORM_ref2 0x971 00288e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 002891: 30 = 0xd (DW_TAG_member) 002892: DW_AT_name TDR 002896: DW_AT_type indirect DW_FORM_ref2 0x971 002899: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 00289c: 0 null 00289d: 80 = 0x16 (DW_TAG_typedef) 00289e: DW_AT_name USART_TypeDef 0028ac: DW_AT_type indirect DW_FORM_ref2 0x281d 0028af: DW_AT_decl_file 0x1 0028b0: DW_AT_decl_line 0x40b 0028b2: DW_AT_decl_column 0x3 0028b3: 42 = 0x13 (DW_TAG_structure_type) 0028b4: DW_AT_sibling 0x28d7 0028b6: DW_AT_byte_size 0xc 0028b7: 30 = 0xd (DW_TAG_member) 0028b8: DW_AT_name CR 0028bb: DW_AT_type indirect DW_FORM_ref2 0x971 0028be: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0028c1: 30 = 0xd (DW_TAG_member) 0028c2: DW_AT_name CFR 0028c6: DW_AT_type indirect DW_FORM_ref2 0x971 0028c9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0028cc: 30 = 0xd (DW_TAG_member) 0028cd: DW_AT_name SR 0028d0: DW_AT_type indirect DW_FORM_ref2 0x971 0028d3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0028d6: 0 null 0028d7: 80 = 0x16 (DW_TAG_typedef) 0028d8: DW_AT_name WWDG_TypeDef 0028e5: DW_AT_type indirect DW_FORM_ref2 0x28b3 0028e8: DW_AT_decl_file 0x1 0028e9: DW_AT_decl_line 0x417 0028eb: DW_AT_decl_column 0x3 0028ec: 42 = 0x13 (DW_TAG_structure_type) 0028ed: DW_AT_sibling 0x290f 0028ef: DW_AT_byte_size 0xc 0028f0: 30 = 0xd (DW_TAG_member) 0028f1: DW_AT_name CR 0028f4: DW_AT_type indirect DW_FORM_ref2 0x971 0028f7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0028fa: 30 = 0xd (DW_TAG_member) 0028fb: DW_AT_name SR 0028fe: DW_AT_type indirect DW_FORM_ref2 0x971 002901: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 002904: 30 = 0xd (DW_TAG_member) 002905: DW_AT_name DR 002908: DW_AT_type indirect DW_FORM_ref2 0x971 00290b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 00290e: 0 null 00290f: 80 = 0x16 (DW_TAG_typedef) 002910: DW_AT_name RNG_TypeDef 00291c: DW_AT_type indirect DW_FORM_ref2 0x28ec 00291f: DW_AT_decl_file 0x1 002920: DW_AT_decl_line 0x423 002922: DW_AT_decl_column 0x3 002923: 42 = 0x13 (DW_TAG_structure_type) 002924: DW_AT_sibling 0x2ae0 002926: DW_AT_byte_size 0x140 002928: 30 = 0xd (DW_TAG_member) 002929: DW_AT_name GOTGCTL 002931: DW_AT_type indirect DW_FORM_ref2 0x971 002934: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 002937: 30 = 0xd (DW_TAG_member) 002938: DW_AT_name GOTGINT 002940: DW_AT_type indirect DW_FORM_ref2 0x971 002943: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 002946: 30 = 0xd (DW_TAG_member) 002947: DW_AT_name GAHBCFG 00294f: DW_AT_type indirect DW_FORM_ref2 0x971 002952: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 002955: 30 = 0xd (DW_TAG_member) 002956: DW_AT_name GUSBCFG 00295e: DW_AT_type indirect DW_FORM_ref2 0x971 002961: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 002964: 30 = 0xd (DW_TAG_member) 002965: DW_AT_name GRSTCTL 00296d: DW_AT_type indirect DW_FORM_ref2 0x971 002970: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 002973: 30 = 0xd (DW_TAG_member) 002974: DW_AT_name GINTSTS 00297c: DW_AT_type indirect DW_FORM_ref2 0x971 00297f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 002982: 30 = 0xd (DW_TAG_member) 002983: DW_AT_name GINTMSK 00298b: DW_AT_type indirect DW_FORM_ref2 0x971 00298e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 002991: 30 = 0xd (DW_TAG_member) 002992: DW_AT_name GRXSTSR 00299a: DW_AT_type indirect DW_FORM_ref2 0x971 00299d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 0029a0: 30 = 0xd (DW_TAG_member) 0029a1: DW_AT_name GRXSTSP 0029a9: DW_AT_type indirect DW_FORM_ref2 0x971 0029ac: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 0029af: 30 = 0xd (DW_TAG_member) 0029b0: DW_AT_name GRXFSIZ 0029b8: DW_AT_type indirect DW_FORM_ref2 0x971 0029bb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 0029be: 30 = 0xd (DW_TAG_member) 0029bf: DW_AT_name DIEPTXF0_HNPTXFSIZ 0029d2: DW_AT_type indirect DW_FORM_ref2 0x971 0029d5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 0029d8: 30 = 0xd (DW_TAG_member) 0029d9: DW_AT_name HNPTXSTS 0029e2: DW_AT_type indirect DW_FORM_ref2 0x971 0029e5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 0029e8: 3 = 0x1 (DW_TAG_array_type) 0029e9: DW_AT_sibling 0x29f3 0029eb: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0029f0: 1 = 0x21 (DW_TAG_subrange_type) 0029f1: DW_AT_upper_bound 0x1 0029f2: 0 null 0029f3: 30 = 0xd (DW_TAG_member) 0029f4: DW_AT_name Reserved30 0029ff: DW_AT_type indirect DW_FORM_ref2 0x29e8 002a02: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 002a05: 30 = 0xd (DW_TAG_member) 002a06: DW_AT_name GCCFG 002a0c: DW_AT_type indirect DW_FORM_ref2 0x971 002a0f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 002a12: 30 = 0xd (DW_TAG_member) 002a13: DW_AT_name CID 002a17: DW_AT_type indirect DW_FORM_ref2 0x971 002a1a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 60 } 002a1d: 3 = 0x1 (DW_TAG_array_type) 002a1e: DW_AT_sibling 0x2a28 002a20: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 002a25: 1 = 0x21 (DW_TAG_subrange_type) 002a26: DW_AT_upper_bound 0x2 002a27: 0 null 002a28: 30 = 0xd (DW_TAG_member) 002a29: DW_AT_name Reserved5 002a33: DW_AT_type indirect DW_FORM_ref2 0x2a1d 002a36: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 64 } 002a39: 30 = 0xd (DW_TAG_member) 002a3a: DW_AT_name GHWCFG3 002a42: DW_AT_type indirect DW_FORM_ref2 0x971 002a45: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 76 } 002a48: 30 = 0xd (DW_TAG_member) 002a49: DW_AT_name Reserved6 002a53: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 002a58: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 80 } 002a5b: 30 = 0xd (DW_TAG_member) 002a5c: DW_AT_name GLPMCFG 002a64: DW_AT_type indirect DW_FORM_ref2 0x971 002a67: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 84 } 002a6a: 30 = 0xd (DW_TAG_member) 002a6b: DW_AT_name GPWRDN 002a72: DW_AT_type indirect DW_FORM_ref2 0x971 002a75: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 88 } 002a78: 30 = 0xd (DW_TAG_member) 002a79: DW_AT_name GDFIFOCFG 002a83: DW_AT_type indirect DW_FORM_ref2 0x971 002a86: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 92 } 002a89: 30 = 0xd (DW_TAG_member) 002a8a: DW_AT_name GADPCTL 002a92: DW_AT_type indirect DW_FORM_ref2 0x971 002a95: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 96 } 002a98: 3 = 0x1 (DW_TAG_array_type) 002a99: DW_AT_sibling 0x2aa3 002a9b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 002aa0: 1 = 0x21 (DW_TAG_subrange_type) 002aa1: DW_AT_upper_bound 0x26 002aa2: 0 null 002aa3: 30 = 0xd (DW_TAG_member) 002aa4: DW_AT_name Reserved43 002aaf: DW_AT_type indirect DW_FORM_ref2 0x2a98 002ab2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 100 } 002ab5: 30 = 0xd (DW_TAG_member) 002ab6: DW_AT_name HPTXFSIZ 002abf: DW_AT_type indirect DW_FORM_ref2 0x971 002ac2: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 256 } 002ac6: 3 = 0x1 (DW_TAG_array_type) 002ac7: DW_AT_sibling 0x2acf 002ac9: DW_AT_type indirect DW_FORM_ref2 0x971 002acc: 1 = 0x21 (DW_TAG_subrange_type) 002acd: DW_AT_upper_bound 0xe 002ace: 0 null 002acf: 30 = 0xd (DW_TAG_member) 002ad0: DW_AT_name DIEPTXF 002ad8: DW_AT_type indirect DW_FORM_ref2 0x2ac6 002adb: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 260 } 002adf: 0 null 002ae0: 80 = 0x16 (DW_TAG_typedef) 002ae1: DW_AT_name USB_OTG_GlobalTypeDef 002af7: DW_AT_type indirect DW_FORM_ref2 0x2923 002afa: DW_AT_decl_file 0x1 002afb: DW_AT_decl_line 0x447 002afd: DW_AT_decl_column 0x3 002afe: 42 = 0x13 (DW_TAG_structure_type) 002aff: DW_AT_sibling 0x2c56 002b01: DW_AT_byte_size 0x88 002b03: 30 = 0xd (DW_TAG_member) 002b04: DW_AT_name DCFG 002b09: DW_AT_type indirect DW_FORM_ref2 0x971 002b0c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 002b0f: 30 = 0xd (DW_TAG_member) 002b10: DW_AT_name DCTL 002b15: DW_AT_type indirect DW_FORM_ref2 0x971 002b18: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 002b1b: 30 = 0xd (DW_TAG_member) 002b1c: DW_AT_name DSTS 002b21: DW_AT_type indirect DW_FORM_ref2 0x971 002b24: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 002b27: 30 = 0xd (DW_TAG_member) 002b28: DW_AT_name Reserved0C 002b33: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 002b38: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 002b3b: 30 = 0xd (DW_TAG_member) 002b3c: DW_AT_name DIEPMSK 002b44: DW_AT_type indirect DW_FORM_ref2 0x971 002b47: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 002b4a: 30 = 0xd (DW_TAG_member) 002b4b: DW_AT_name DOEPMSK 002b53: DW_AT_type indirect DW_FORM_ref2 0x971 002b56: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 002b59: 30 = 0xd (DW_TAG_member) 002b5a: DW_AT_name DAINT 002b60: DW_AT_type indirect DW_FORM_ref2 0x971 002b63: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 002b66: 30 = 0xd (DW_TAG_member) 002b67: DW_AT_name DAINTMSK 002b70: DW_AT_type indirect DW_FORM_ref2 0x971 002b73: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 002b76: 30 = 0xd (DW_TAG_member) 002b77: DW_AT_name Reserved20 002b82: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 002b87: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 002b8a: 30 = 0xd (DW_TAG_member) 002b8b: DW_AT_name Reserved9 002b95: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 002b9a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 002b9d: 30 = 0xd (DW_TAG_member) 002b9e: DW_AT_name DVBUSDIS 002ba7: DW_AT_type indirect DW_FORM_ref2 0x971 002baa: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 002bad: 30 = 0xd (DW_TAG_member) 002bae: DW_AT_name DVBUSPULSE 002bb9: DW_AT_type indirect DW_FORM_ref2 0x971 002bbc: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 002bbf: 30 = 0xd (DW_TAG_member) 002bc0: DW_AT_name DTHRCTL 002bc8: DW_AT_type indirect DW_FORM_ref2 0x971 002bcb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 002bce: 30 = 0xd (DW_TAG_member) 002bcf: DW_AT_name DIEPEMPMSK 002bda: DW_AT_type indirect DW_FORM_ref2 0x971 002bdd: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 002be0: 30 = 0xd (DW_TAG_member) 002be1: DW_AT_name DEACHINT 002bea: DW_AT_type indirect DW_FORM_ref2 0x971 002bed: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 002bf0: 30 = 0xd (DW_TAG_member) 002bf1: DW_AT_name DEACHMSK 002bfa: DW_AT_type indirect DW_FORM_ref2 0x971 002bfd: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 60 } 002c00: 30 = 0xd (DW_TAG_member) 002c01: DW_AT_name Reserved40 002c0c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 002c11: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 64 } 002c14: 30 = 0xd (DW_TAG_member) 002c15: DW_AT_name DINEP1MSK 002c1f: DW_AT_type indirect DW_FORM_ref2 0x971 002c22: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 68 } 002c25: 3 = 0x1 (DW_TAG_array_type) 002c26: DW_AT_sibling 0x2c30 002c28: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 002c2d: 1 = 0x21 (DW_TAG_subrange_type) 002c2e: DW_AT_upper_bound 0xe 002c2f: 0 null 002c30: 30 = 0xd (DW_TAG_member) 002c31: DW_AT_name Reserved44 002c3c: DW_AT_type indirect DW_FORM_ref2 0x2c25 002c3f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 72 } 002c42: 30 = 0xd (DW_TAG_member) 002c43: DW_AT_name DOUTEP1MSK 002c4e: DW_AT_type indirect DW_FORM_ref2 0x971 002c51: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 132 } 002c55: 0 null 002c56: 80 = 0x16 (DW_TAG_typedef) 002c57: DW_AT_name USB_OTG_DeviceTypeDef 002c6d: DW_AT_type indirect DW_FORM_ref2 0x2afe 002c70: DW_AT_decl_file 0x1 002c71: DW_AT_decl_line 0x463 002c73: DW_AT_decl_column 0x3 002c74: 42 = 0x13 (DW_TAG_structure_type) 002c75: DW_AT_sibling 0x2d01 002c77: DW_AT_byte_size 0x20 002c78: 30 = 0xd (DW_TAG_member) 002c79: DW_AT_name DIEPCTL 002c81: DW_AT_type indirect DW_FORM_ref2 0x971 002c84: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 002c87: 30 = 0xd (DW_TAG_member) 002c88: DW_AT_name Reserved04 002c93: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 002c98: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 002c9b: 30 = 0xd (DW_TAG_member) 002c9c: DW_AT_name DIEPINT 002ca4: DW_AT_type indirect DW_FORM_ref2 0x971 002ca7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 002caa: 30 = 0xd (DW_TAG_member) 002cab: DW_AT_name Reserved0C 002cb6: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 002cbb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 002cbe: 30 = 0xd (DW_TAG_member) 002cbf: DW_AT_name DIEPTSIZ 002cc8: DW_AT_type indirect DW_FORM_ref2 0x971 002ccb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 002cce: 30 = 0xd (DW_TAG_member) 002ccf: DW_AT_name DIEPDMA 002cd7: DW_AT_type indirect DW_FORM_ref2 0x971 002cda: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 002cdd: 30 = 0xd (DW_TAG_member) 002cde: DW_AT_name DTXFSTS 002ce6: DW_AT_type indirect DW_FORM_ref2 0x971 002ce9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 002cec: 30 = 0xd (DW_TAG_member) 002ced: DW_AT_name Reserved18 002cf8: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 002cfd: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 002d00: 0 null 002d01: 80 = 0x16 (DW_TAG_typedef) 002d02: DW_AT_name USB_OTG_INEndpointTypeDef 002d1c: DW_AT_type indirect DW_FORM_ref2 0x2c74 002d1f: DW_AT_decl_file 0x1 002d20: DW_AT_decl_line 0x473 002d22: DW_AT_decl_column 0x3 002d23: 42 = 0x13 (DW_TAG_structure_type) 002d24: DW_AT_sibling 0x2daa 002d26: DW_AT_byte_size 0x20 002d27: 30 = 0xd (DW_TAG_member) 002d28: DW_AT_name DOEPCTL 002d30: DW_AT_type indirect DW_FORM_ref2 0x971 002d33: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 002d36: 30 = 0xd (DW_TAG_member) 002d37: DW_AT_name Reserved04 002d42: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 002d47: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 002d4a: 30 = 0xd (DW_TAG_member) 002d4b: DW_AT_name DOEPINT 002d53: DW_AT_type indirect DW_FORM_ref2 0x971 002d56: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 002d59: 30 = 0xd (DW_TAG_member) 002d5a: DW_AT_name Reserved0C 002d65: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 002d6a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 002d6d: 30 = 0xd (DW_TAG_member) 002d6e: DW_AT_name DOEPTSIZ 002d77: DW_AT_type indirect DW_FORM_ref2 0x971 002d7a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 002d7d: 30 = 0xd (DW_TAG_member) 002d7e: DW_AT_name DOEPDMA 002d86: DW_AT_type indirect DW_FORM_ref2 0x971 002d89: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 002d8c: 3 = 0x1 (DW_TAG_array_type) 002d8d: DW_AT_sibling 0x2d97 002d8f: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 002d94: 1 = 0x21 (DW_TAG_subrange_type) 002d95: DW_AT_upper_bound 0x1 002d96: 0 null 002d97: 30 = 0xd (DW_TAG_member) 002d98: DW_AT_name Reserved18 002da3: DW_AT_type indirect DW_FORM_ref2 0x2d8c 002da6: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 002da9: 0 null 002daa: 80 = 0x16 (DW_TAG_typedef) 002dab: DW_AT_name USB_OTG_OUTEndpointTypeDef 002dc6: DW_AT_type indirect DW_FORM_ref2 0x2d23 002dc9: DW_AT_decl_file 0x1 002dca: DW_AT_decl_line 0x482 002dcc: DW_AT_decl_column 0x3 002dcd: 42 = 0x13 (DW_TAG_structure_type) 002dce: DW_AT_sibling 0x2e38 002dd0: DW_AT_byte_size 0x1c 002dd1: 30 = 0xd (DW_TAG_member) 002dd2: DW_AT_name HCFG 002dd7: DW_AT_type indirect DW_FORM_ref2 0x971 002dda: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 002ddd: 30 = 0xd (DW_TAG_member) 002dde: DW_AT_name HFIR 002de3: DW_AT_type indirect DW_FORM_ref2 0x971 002de6: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 002de9: 30 = 0xd (DW_TAG_member) 002dea: DW_AT_name HFNUM 002df0: DW_AT_type indirect DW_FORM_ref2 0x971 002df3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 002df6: 30 = 0xd (DW_TAG_member) 002df7: DW_AT_name Reserved40C 002e03: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 002e08: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 002e0b: 30 = 0xd (DW_TAG_member) 002e0c: DW_AT_name HPTXSTS 002e14: DW_AT_type indirect DW_FORM_ref2 0x971 002e17: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 002e1a: 30 = 0xd (DW_TAG_member) 002e1b: DW_AT_name HAINT 002e21: DW_AT_type indirect DW_FORM_ref2 0x971 002e24: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 002e27: 30 = 0xd (DW_TAG_member) 002e28: DW_AT_name HAINTMSK 002e31: DW_AT_type indirect DW_FORM_ref2 0x971 002e34: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 002e37: 0 null 002e38: 80 = 0x16 (DW_TAG_typedef) 002e39: DW_AT_name USB_OTG_HostTypeDef 002e4d: DW_AT_type indirect DW_FORM_ref2 0x2dcd 002e50: DW_AT_decl_file 0x1 002e51: DW_AT_decl_line 0x491 002e53: DW_AT_decl_column 0x3 002e54: 42 = 0x13 (DW_TAG_structure_type) 002e55: DW_AT_sibling 0x2ec8 002e57: DW_AT_byte_size 0x20 002e58: 30 = 0xd (DW_TAG_member) 002e59: DW_AT_name HCCHAR 002e60: DW_AT_type indirect DW_FORM_ref2 0x971 002e63: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 002e66: 30 = 0xd (DW_TAG_member) 002e67: DW_AT_name HCSPLT 002e6e: DW_AT_type indirect DW_FORM_ref2 0x971 002e71: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 002e74: 30 = 0xd (DW_TAG_member) 002e75: DW_AT_name HCINT 002e7b: DW_AT_type indirect DW_FORM_ref2 0x971 002e7e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 002e81: 30 = 0xd (DW_TAG_member) 002e82: DW_AT_name HCINTMSK 002e8b: DW_AT_type indirect DW_FORM_ref2 0x971 002e8e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 002e91: 30 = 0xd (DW_TAG_member) 002e92: DW_AT_name HCTSIZ 002e99: DW_AT_type indirect DW_FORM_ref2 0x971 002e9c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 002e9f: 30 = 0xd (DW_TAG_member) 002ea0: DW_AT_name HCDMA 002ea6: DW_AT_type indirect DW_FORM_ref2 0x971 002ea9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 002eac: 3 = 0x1 (DW_TAG_array_type) 002ead: DW_AT_sibling 0x2eb7 002eaf: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 002eb4: 1 = 0x21 (DW_TAG_subrange_type) 002eb5: DW_AT_upper_bound 0x1 002eb6: 0 null 002eb7: 30 = 0xd (DW_TAG_member) 002eb8: DW_AT_name Reserved 002ec1: DW_AT_type indirect DW_FORM_ref2 0x2eac 002ec4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 002ec7: 0 null 002ec8: 80 = 0x16 (DW_TAG_typedef) 002ec9: DW_AT_name USB_OTG_HostChannelTypeDef 002ee4: DW_AT_type indirect DW_FORM_ref2 0x2e54 002ee7: DW_AT_decl_file 0x1 002ee8: DW_AT_decl_line 0x49f 002eea: DW_AT_decl_column 0x3 002eeb: 42 = 0x13 (DW_TAG_structure_type) 002eec: DW_AT_sibling 0x312e 002eee: DW_AT_byte_size 0x800 002ef0: 30 = 0xd (DW_TAG_member) 002ef1: DW_AT_name CONFR0 002ef8: DW_AT_type indirect DW_FORM_ref2 0x971 002efb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 002efe: 30 = 0xd (DW_TAG_member) 002eff: DW_AT_name CONFR1 002f06: DW_AT_type indirect DW_FORM_ref2 0x971 002f09: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 002f0c: 30 = 0xd (DW_TAG_member) 002f0d: DW_AT_name CONFR2 002f14: DW_AT_type indirect DW_FORM_ref2 0x971 002f17: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 002f1a: 30 = 0xd (DW_TAG_member) 002f1b: DW_AT_name CONFR3 002f22: DW_AT_type indirect DW_FORM_ref2 0x971 002f25: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 002f28: 30 = 0xd (DW_TAG_member) 002f29: DW_AT_name CONFR4 002f30: DW_AT_type indirect DW_FORM_ref2 0x971 002f33: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 002f36: 30 = 0xd (DW_TAG_member) 002f37: DW_AT_name CONFR5 002f3e: DW_AT_type indirect DW_FORM_ref2 0x971 002f41: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 002f44: 30 = 0xd (DW_TAG_member) 002f45: DW_AT_name CONFR6 002f4c: DW_AT_type indirect DW_FORM_ref2 0x971 002f4f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 002f52: 30 = 0xd (DW_TAG_member) 002f53: DW_AT_name CONFR7 002f5a: DW_AT_type indirect DW_FORM_ref2 0x971 002f5d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 002f60: 3 = 0x1 (DW_TAG_array_type) 002f61: DW_AT_sibling 0x2f6b 002f63: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 002f68: 1 = 0x21 (DW_TAG_subrange_type) 002f69: DW_AT_upper_bound 0x3 002f6a: 0 null 002f6b: 30 = 0xd (DW_TAG_member) 002f6c: DW_AT_name Reserved20 002f77: DW_AT_type indirect DW_FORM_ref2 0x2f60 002f7a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 002f7d: 30 = 0xd (DW_TAG_member) 002f7e: DW_AT_name CR 002f81: DW_AT_type indirect DW_FORM_ref2 0x971 002f84: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 002f87: 30 = 0xd (DW_TAG_member) 002f88: DW_AT_name SR 002f8b: DW_AT_type indirect DW_FORM_ref2 0x971 002f8e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 002f91: 30 = 0xd (DW_TAG_member) 002f92: DW_AT_name CFR 002f96: DW_AT_type indirect DW_FORM_ref2 0x971 002f99: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 002f9c: 30 = 0xd (DW_TAG_member) 002f9d: DW_AT_name Reserved3c 002fa8: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 002fad: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 60 } 002fb0: 30 = 0xd (DW_TAG_member) 002fb1: DW_AT_name DIR 002fb5: DW_AT_type indirect DW_FORM_ref2 0x971 002fb8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 64 } 002fbb: 30 = 0xd (DW_TAG_member) 002fbc: DW_AT_name DOR 002fc0: DW_AT_type indirect DW_FORM_ref2 0x971 002fc3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 68 } 002fc6: 3 = 0x1 (DW_TAG_array_type) 002fc7: DW_AT_sibling 0x2fd1 002fc9: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 002fce: 1 = 0x21 (DW_TAG_subrange_type) 002fcf: DW_AT_upper_bound 0x1 002fd0: 0 null 002fd1: 30 = 0xd (DW_TAG_member) 002fd2: DW_AT_name Reserved48 002fdd: DW_AT_type indirect DW_FORM_ref2 0x2fc6 002fe0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 72 } 002fe3: 3 = 0x1 (DW_TAG_array_type) 002fe4: DW_AT_sibling 0x2fec 002fe6: DW_AT_type indirect DW_FORM_ref2 0x971 002fe9: 1 = 0x21 (DW_TAG_subrange_type) 002fea: DW_AT_upper_bound 0xf 002feb: 0 null 002fec: 30 = 0xd (DW_TAG_member) 002fed: DW_AT_name QMEM0 002ff3: DW_AT_type indirect DW_FORM_ref2 0x2fe3 002ff6: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 80 } 002ff9: 3 = 0x1 (DW_TAG_array_type) 002ffa: DW_AT_sibling 0x3002 002ffc: DW_AT_type indirect DW_FORM_ref2 0x971 002fff: 1 = 0x21 (DW_TAG_subrange_type) 003000: DW_AT_upper_bound 0xf 003001: 0 null 003002: 30 = 0xd (DW_TAG_member) 003003: DW_AT_name QMEM1 003009: DW_AT_type indirect DW_FORM_ref2 0x2ff9 00300c: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 144 } 003010: 3 = 0x1 (DW_TAG_array_type) 003011: DW_AT_sibling 0x3019 003013: DW_AT_type indirect DW_FORM_ref2 0x971 003016: 1 = 0x21 (DW_TAG_subrange_type) 003017: DW_AT_upper_bound 0xf 003018: 0 null 003019: 30 = 0xd (DW_TAG_member) 00301a: DW_AT_name QMEM2 003020: DW_AT_type indirect DW_FORM_ref2 0x3010 003023: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 208 } 003027: 3 = 0x1 (DW_TAG_array_type) 003028: DW_AT_sibling 0x3030 00302a: DW_AT_type indirect DW_FORM_ref2 0x971 00302d: 1 = 0x21 (DW_TAG_subrange_type) 00302e: DW_AT_upper_bound 0xf 00302f: 0 null 003030: 30 = 0xd (DW_TAG_member) 003031: DW_AT_name QMEM3 003037: DW_AT_type indirect DW_FORM_ref2 0x3027 00303a: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 272 } 00303e: 3 = 0x1 (DW_TAG_array_type) 00303f: DW_AT_sibling 0x3047 003041: DW_AT_type indirect DW_FORM_ref2 0x971 003044: 1 = 0x21 (DW_TAG_subrange_type) 003045: DW_AT_upper_bound 0xf 003046: 0 null 003047: 30 = 0xd (DW_TAG_member) 003048: DW_AT_name HUFFMIN 003050: DW_AT_type indirect DW_FORM_ref2 0x303e 003053: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 336 } 003057: 3 = 0x1 (DW_TAG_array_type) 003058: DW_AT_sibling 0x3060 00305a: DW_AT_type indirect DW_FORM_ref2 0x971 00305d: 1 = 0x21 (DW_TAG_subrange_type) 00305e: DW_AT_upper_bound 0x1f 00305f: 0 null 003060: 30 = 0xd (DW_TAG_member) 003061: DW_AT_name HUFFBASE 00306a: DW_AT_type indirect DW_FORM_ref2 0x3057 00306d: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 400 } 003071: 3 = 0x1 (DW_TAG_array_type) 003072: DW_AT_sibling 0x307a 003074: DW_AT_type indirect DW_FORM_ref2 0x971 003077: 1 = 0x21 (DW_TAG_subrange_type) 003078: DW_AT_upper_bound 0x53 003079: 0 null 00307a: 30 = 0xd (DW_TAG_member) 00307b: DW_AT_name HUFFSYMB 003084: DW_AT_type indirect DW_FORM_ref2 0x3071 003087: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 528 } 00308b: 3 = 0x1 (DW_TAG_array_type) 00308c: DW_AT_sibling 0x3094 00308e: DW_AT_type indirect DW_FORM_ref2 0x971 003091: 1 = 0x21 (DW_TAG_subrange_type) 003092: DW_AT_upper_bound 0x66 003093: 0 null 003094: 30 = 0xd (DW_TAG_member) 003095: DW_AT_name DHTMEM 00309c: DW_AT_type indirect DW_FORM_ref2 0x308b 00309f: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 864 } 0030a3: 30 = 0xd (DW_TAG_member) 0030a4: DW_AT_name Reserved4FC 0030b0: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0030b5: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 1276 } 0030b9: 3 = 0x1 (DW_TAG_array_type) 0030ba: DW_AT_sibling 0x30c2 0030bc: DW_AT_type indirect DW_FORM_ref2 0x971 0030bf: 1 = 0x21 (DW_TAG_subrange_type) 0030c0: DW_AT_upper_bound 0x57 0030c1: 0 null 0030c2: 30 = 0xd (DW_TAG_member) 0030c3: DW_AT_name HUFFENC_AC0 0030cf: DW_AT_type indirect DW_FORM_ref2 0x30b9 0030d2: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 1280 } 0030d6: 3 = 0x1 (DW_TAG_array_type) 0030d7: DW_AT_sibling 0x30df 0030d9: DW_AT_type indirect DW_FORM_ref2 0x971 0030dc: 1 = 0x21 (DW_TAG_subrange_type) 0030dd: DW_AT_upper_bound 0x57 0030de: 0 null 0030df: 30 = 0xd (DW_TAG_member) 0030e0: DW_AT_name HUFFENC_AC1 0030ec: DW_AT_type indirect DW_FORM_ref2 0x30d6 0030ef: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 1632 } 0030f3: 3 = 0x1 (DW_TAG_array_type) 0030f4: DW_AT_sibling 0x30fc 0030f6: DW_AT_type indirect DW_FORM_ref2 0x971 0030f9: 1 = 0x21 (DW_TAG_subrange_type) 0030fa: DW_AT_upper_bound 0x7 0030fb: 0 null 0030fc: 30 = 0xd (DW_TAG_member) 0030fd: DW_AT_name HUFFENC_DC0 003109: DW_AT_type indirect DW_FORM_ref2 0x30f3 00310c: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 1984 } 003110: 3 = 0x1 (DW_TAG_array_type) 003111: DW_AT_sibling 0x3119 003113: DW_AT_type indirect DW_FORM_ref2 0x971 003116: 1 = 0x21 (DW_TAG_subrange_type) 003117: DW_AT_upper_bound 0x7 003118: 0 null 003119: 30 = 0xd (DW_TAG_member) 00311a: DW_AT_name HUFFENC_DC1 003126: DW_AT_type indirect DW_FORM_ref2 0x3110 003129: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 2016 } 00312d: 0 null 00312e: 80 = 0x16 (DW_TAG_typedef) 00312f: DW_AT_name JPEG_TypeDef 00313c: DW_AT_type indirect DW_FORM_ref2 0x2eeb 00313f: DW_AT_decl_file 0x1 003140: DW_AT_decl_line 0x4c7 003142: DW_AT_decl_column 0x3 003143: 42 = 0x13 (DW_TAG_structure_type) 003144: DW_AT_sibling 0x3584 003146: DW_AT_byte_size 0x200 003148: 30 = 0xd (DW_TAG_member) 003149: DW_AT_name CR 00314c: DW_AT_type indirect DW_FORM_ref2 0x971 00314f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 003152: 30 = 0xd (DW_TAG_member) 003153: DW_AT_name WRFR 003158: DW_AT_type indirect DW_FORM_ref2 0x971 00315b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00315e: 30 = 0xd (DW_TAG_member) 00315f: DW_AT_name CWRFR 003165: DW_AT_type indirect DW_FORM_ref2 0x971 003168: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 00316b: 30 = 0xd (DW_TAG_member) 00316c: DW_AT_name RDFR 003171: DW_AT_type indirect DW_FORM_ref2 0x971 003174: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 003177: 30 = 0xd (DW_TAG_member) 003178: DW_AT_name CRDFR 00317e: DW_AT_type indirect DW_FORM_ref2 0x971 003181: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 003184: 30 = 0xd (DW_TAG_member) 003185: DW_AT_name SR 003188: DW_AT_type indirect DW_FORM_ref2 0x971 00318b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 00318e: 30 = 0xd (DW_TAG_member) 00318f: DW_AT_name CLRFR 003195: DW_AT_type indirect DW_FORM_ref2 0x971 003198: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 00319b: 3 = 0x1 (DW_TAG_array_type) 00319c: DW_AT_sibling 0x31a6 00319e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0031a3: 1 = 0x21 (DW_TAG_subrange_type) 0031a4: DW_AT_upper_bound 0x38 0031a5: 0 null 0031a6: 30 = 0xd (DW_TAG_member) 0031a7: DW_AT_name RESERVED0 0031b1: DW_AT_type indirect DW_FORM_ref2 0x319b 0031b4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 0031b7: 30 = 0xd (DW_TAG_member) 0031b8: DW_AT_name DINR0 0031be: DW_AT_type indirect DW_FORM_ref2 0x971 0031c1: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 256 } 0031c5: 30 = 0xd (DW_TAG_member) 0031c6: DW_AT_name DINR1 0031cc: DW_AT_type indirect DW_FORM_ref2 0x971 0031cf: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 260 } 0031d3: 30 = 0xd (DW_TAG_member) 0031d4: DW_AT_name DINR2 0031da: DW_AT_type indirect DW_FORM_ref2 0x971 0031dd: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 264 } 0031e1: 30 = 0xd (DW_TAG_member) 0031e2: DW_AT_name DINR3 0031e8: DW_AT_type indirect DW_FORM_ref2 0x971 0031eb: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 268 } 0031ef: 30 = 0xd (DW_TAG_member) 0031f0: DW_AT_name DINR4 0031f6: DW_AT_type indirect DW_FORM_ref2 0x971 0031f9: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 272 } 0031fd: 30 = 0xd (DW_TAG_member) 0031fe: DW_AT_name DINR5 003204: DW_AT_type indirect DW_FORM_ref2 0x971 003207: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 276 } 00320b: 30 = 0xd (DW_TAG_member) 00320c: DW_AT_name DINR6 003212: DW_AT_type indirect DW_FORM_ref2 0x971 003215: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 280 } 003219: 30 = 0xd (DW_TAG_member) 00321a: DW_AT_name DINR7 003220: DW_AT_type indirect DW_FORM_ref2 0x971 003223: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 284 } 003227: 30 = 0xd (DW_TAG_member) 003228: DW_AT_name DINR8 00322e: DW_AT_type indirect DW_FORM_ref2 0x971 003231: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 288 } 003235: 30 = 0xd (DW_TAG_member) 003236: DW_AT_name DINR9 00323c: DW_AT_type indirect DW_FORM_ref2 0x971 00323f: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 292 } 003243: 30 = 0xd (DW_TAG_member) 003244: DW_AT_name DINR10 00324b: DW_AT_type indirect DW_FORM_ref2 0x971 00324e: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 296 } 003252: 30 = 0xd (DW_TAG_member) 003253: DW_AT_name DINR11 00325a: DW_AT_type indirect DW_FORM_ref2 0x971 00325d: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 300 } 003261: 30 = 0xd (DW_TAG_member) 003262: DW_AT_name DINR12 003269: DW_AT_type indirect DW_FORM_ref2 0x971 00326c: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 304 } 003270: 30 = 0xd (DW_TAG_member) 003271: DW_AT_name DINR13 003278: DW_AT_type indirect DW_FORM_ref2 0x971 00327b: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 308 } 00327f: 30 = 0xd (DW_TAG_member) 003280: DW_AT_name DINR14 003287: DW_AT_type indirect DW_FORM_ref2 0x971 00328a: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 312 } 00328e: 30 = 0xd (DW_TAG_member) 00328f: DW_AT_name DINR15 003296: DW_AT_type indirect DW_FORM_ref2 0x971 003299: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 316 } 00329d: 30 = 0xd (DW_TAG_member) 00329e: DW_AT_name DINR16 0032a5: DW_AT_type indirect DW_FORM_ref2 0x971 0032a8: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 320 } 0032ac: 30 = 0xd (DW_TAG_member) 0032ad: DW_AT_name DINR17 0032b4: DW_AT_type indirect DW_FORM_ref2 0x971 0032b7: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 324 } 0032bb: 30 = 0xd (DW_TAG_member) 0032bc: DW_AT_name DINR18 0032c3: DW_AT_type indirect DW_FORM_ref2 0x971 0032c6: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 328 } 0032ca: 30 = 0xd (DW_TAG_member) 0032cb: DW_AT_name DINR19 0032d2: DW_AT_type indirect DW_FORM_ref2 0x971 0032d5: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 332 } 0032d9: 30 = 0xd (DW_TAG_member) 0032da: DW_AT_name DINR20 0032e1: DW_AT_type indirect DW_FORM_ref2 0x971 0032e4: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 336 } 0032e8: 30 = 0xd (DW_TAG_member) 0032e9: DW_AT_name DINR21 0032f0: DW_AT_type indirect DW_FORM_ref2 0x971 0032f3: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 340 } 0032f7: 30 = 0xd (DW_TAG_member) 0032f8: DW_AT_name DINR22 0032ff: DW_AT_type indirect DW_FORM_ref2 0x971 003302: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 344 } 003306: 30 = 0xd (DW_TAG_member) 003307: DW_AT_name DINR23 00330e: DW_AT_type indirect DW_FORM_ref2 0x971 003311: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 348 } 003315: 30 = 0xd (DW_TAG_member) 003316: DW_AT_name DINR24 00331d: DW_AT_type indirect DW_FORM_ref2 0x971 003320: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 352 } 003324: 30 = 0xd (DW_TAG_member) 003325: DW_AT_name DINR25 00332c: DW_AT_type indirect DW_FORM_ref2 0x971 00332f: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 356 } 003333: 30 = 0xd (DW_TAG_member) 003334: DW_AT_name DINR26 00333b: DW_AT_type indirect DW_FORM_ref2 0x971 00333e: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 360 } 003342: 30 = 0xd (DW_TAG_member) 003343: DW_AT_name DINR27 00334a: DW_AT_type indirect DW_FORM_ref2 0x971 00334d: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 364 } 003351: 30 = 0xd (DW_TAG_member) 003352: DW_AT_name DINR28 003359: DW_AT_type indirect DW_FORM_ref2 0x971 00335c: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 368 } 003360: 30 = 0xd (DW_TAG_member) 003361: DW_AT_name DINR29 003368: DW_AT_type indirect DW_FORM_ref2 0x971 00336b: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 372 } 00336f: 30 = 0xd (DW_TAG_member) 003370: DW_AT_name DINR30 003377: DW_AT_type indirect DW_FORM_ref2 0x971 00337a: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 376 } 00337e: 30 = 0xd (DW_TAG_member) 00337f: DW_AT_name DINR31 003386: DW_AT_type indirect DW_FORM_ref2 0x971 003389: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 380 } 00338d: 30 = 0xd (DW_TAG_member) 00338e: DW_AT_name DOUTR0 003395: DW_AT_type indirect DW_FORM_ref2 0x971 003398: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 384 } 00339c: 30 = 0xd (DW_TAG_member) 00339d: DW_AT_name DOUTR1 0033a4: DW_AT_type indirect DW_FORM_ref2 0x971 0033a7: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 388 } 0033ab: 30 = 0xd (DW_TAG_member) 0033ac: DW_AT_name DOUTR2 0033b3: DW_AT_type indirect DW_FORM_ref2 0x971 0033b6: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 392 } 0033ba: 30 = 0xd (DW_TAG_member) 0033bb: DW_AT_name DOUTR3 0033c2: DW_AT_type indirect DW_FORM_ref2 0x971 0033c5: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 396 } 0033c9: 30 = 0xd (DW_TAG_member) 0033ca: DW_AT_name DOUTR4 0033d1: DW_AT_type indirect DW_FORM_ref2 0x971 0033d4: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 400 } 0033d8: 30 = 0xd (DW_TAG_member) 0033d9: DW_AT_name DOUTR5 0033e0: DW_AT_type indirect DW_FORM_ref2 0x971 0033e3: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 404 } 0033e7: 30 = 0xd (DW_TAG_member) 0033e8: DW_AT_name DOUTR6 0033ef: DW_AT_type indirect DW_FORM_ref2 0x971 0033f2: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 408 } 0033f6: 30 = 0xd (DW_TAG_member) 0033f7: DW_AT_name DOUTR7 0033fe: DW_AT_type indirect DW_FORM_ref2 0x971 003401: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 412 } 003405: 30 = 0xd (DW_TAG_member) 003406: DW_AT_name DOUTR8 00340d: DW_AT_type indirect DW_FORM_ref2 0x971 003410: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 416 } 003414: 30 = 0xd (DW_TAG_member) 003415: DW_AT_name DOUTR9 00341c: DW_AT_type indirect DW_FORM_ref2 0x971 00341f: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 420 } 003423: 30 = 0xd (DW_TAG_member) 003424: DW_AT_name DOUTR10 00342c: DW_AT_type indirect DW_FORM_ref2 0x971 00342f: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 424 } 003433: 30 = 0xd (DW_TAG_member) 003434: DW_AT_name DOUTR11 00343c: DW_AT_type indirect DW_FORM_ref2 0x971 00343f: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 428 } 003443: 30 = 0xd (DW_TAG_member) 003444: DW_AT_name DOUTR12 00344c: DW_AT_type indirect DW_FORM_ref2 0x971 00344f: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 432 } 003453: 30 = 0xd (DW_TAG_member) 003454: DW_AT_name DOUTR13 00345c: DW_AT_type indirect DW_FORM_ref2 0x971 00345f: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 436 } 003463: 30 = 0xd (DW_TAG_member) 003464: DW_AT_name DOUTR14 00346c: DW_AT_type indirect DW_FORM_ref2 0x971 00346f: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 440 } 003473: 30 = 0xd (DW_TAG_member) 003474: DW_AT_name DOUTR15 00347c: DW_AT_type indirect DW_FORM_ref2 0x971 00347f: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 444 } 003483: 30 = 0xd (DW_TAG_member) 003484: DW_AT_name DOUTR16 00348c: DW_AT_type indirect DW_FORM_ref2 0x971 00348f: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 448 } 003493: 30 = 0xd (DW_TAG_member) 003494: DW_AT_name DOUTR17 00349c: DW_AT_type indirect DW_FORM_ref2 0x971 00349f: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 452 } 0034a3: 30 = 0xd (DW_TAG_member) 0034a4: DW_AT_name DOUTR18 0034ac: DW_AT_type indirect DW_FORM_ref2 0x971 0034af: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 456 } 0034b3: 30 = 0xd (DW_TAG_member) 0034b4: DW_AT_name DOUTR19 0034bc: DW_AT_type indirect DW_FORM_ref2 0x971 0034bf: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 460 } 0034c3: 30 = 0xd (DW_TAG_member) 0034c4: DW_AT_name DOUTR20 0034cc: DW_AT_type indirect DW_FORM_ref2 0x971 0034cf: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 464 } 0034d3: 30 = 0xd (DW_TAG_member) 0034d4: DW_AT_name DOUTR21 0034dc: DW_AT_type indirect DW_FORM_ref2 0x971 0034df: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 468 } 0034e3: 30 = 0xd (DW_TAG_member) 0034e4: DW_AT_name DOUTR22 0034ec: DW_AT_type indirect DW_FORM_ref2 0x971 0034ef: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 472 } 0034f3: 30 = 0xd (DW_TAG_member) 0034f4: DW_AT_name DOUTR23 0034fc: DW_AT_type indirect DW_FORM_ref2 0x971 0034ff: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 476 } 003503: 30 = 0xd (DW_TAG_member) 003504: DW_AT_name DOUTR24 00350c: DW_AT_type indirect DW_FORM_ref2 0x971 00350f: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 480 } 003513: 30 = 0xd (DW_TAG_member) 003514: DW_AT_name DOUTR25 00351c: DW_AT_type indirect DW_FORM_ref2 0x971 00351f: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 484 } 003523: 30 = 0xd (DW_TAG_member) 003524: DW_AT_name DOUTR26 00352c: DW_AT_type indirect DW_FORM_ref2 0x971 00352f: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 488 } 003533: 30 = 0xd (DW_TAG_member) 003534: DW_AT_name DOUTR27 00353c: DW_AT_type indirect DW_FORM_ref2 0x971 00353f: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 492 } 003543: 30 = 0xd (DW_TAG_member) 003544: DW_AT_name DOUTR28 00354c: DW_AT_type indirect DW_FORM_ref2 0x971 00354f: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 496 } 003553: 30 = 0xd (DW_TAG_member) 003554: DW_AT_name DOUTR29 00355c: DW_AT_type indirect DW_FORM_ref2 0x971 00355f: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 500 } 003563: 30 = 0xd (DW_TAG_member) 003564: DW_AT_name DOUTR30 00356c: DW_AT_type indirect DW_FORM_ref2 0x971 00356f: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 504 } 003573: 30 = 0xd (DW_TAG_member) 003574: DW_AT_name DOUTR31 00357c: DW_AT_type indirect DW_FORM_ref2 0x971 00357f: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 508 } 003583: 0 null 003584: 80 = 0x16 (DW_TAG_typedef) 003585: DW_AT_name MDIOS_TypeDef 003593: DW_AT_type indirect DW_FORM_ref2 0x3143 003596: DW_AT_decl_file 0x1 003597: DW_AT_decl_line 0x517 003599: DW_AT_decl_column 0x3 00359a: 0 null 00359b: 0 padding ** Section #368 '.rel.debug_info' (SHT_REL) Size : 528 bytes (alignment 4) Symbol table #343 '.symtab' 66 relocations applied to section #57 '.debug_info' ** Section #58 '__ARM_grp.stm32f7xx.h.2_UW0000_aRwJTR5xRm2_300000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #59 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 796 bytes 000000: include at line 0 - file 1 000003: line 57 define __STM32F7xx_H 000014: line 71 define STM32F7 00001f: line 116 define __STM32F7_CMSIS_VERSION_MAIN (0x01) 000045: line 117 define __STM32F7_CMSIS_VERSION_SUB1 (0x01) 00006b: line 118 define __STM32F7_CMSIS_VERSION_SUB2 (0x02) 000091: line 119 define __STM32F7_CMSIS_VERSION_RC (0x00) 0000b5: line 120 define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24) |(__STM32F7_CMSIS_VERSION_SUB1 << 16) |(__STM32F7_CMSIS_VERSION_SUB2 << 8 ) |(__STM32F7_CMSIS_VERSION)) 00015d: include at line 148 - file 2 000161: end include 000162: line 177 define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) 0001ae: line 192 define SET_BIT(REG,BIT) ((REG) |= (BIT)) 0001d3: line 194 define CLEAR_BIT(REG,BIT) ((REG) &= ~(BIT)) 0001fb: line 196 define READ_BIT(REG,BIT) ((REG) & (BIT)) 000220: line 198 define CLEAR_REG(REG) ((REG) = (0x0)) 000242: line 200 define WRITE_REG(REG,VAL) ((REG) = (VAL)) 000268: line 202 define READ_REG(REG) ((REG)) 000281: line 204 define MODIFY_REG(REG,CLEARMASK,SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) 0002e9: line 206 define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) 000313: include at line 213 - file 3 000317: end include 000318: end include 000319: end of translation unit ** Section #60 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 152 bytes 000000: Header: length 148 (not including this field) version 3 prologue length 138 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\CMSIS\Device\ST\STM32F7xx\Include\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 43 4d 53 49 53 5c 44 65 76 69 63 65 5c 53 54 5c 53 54 4d 33 32 46 37 78 78 5c 49 6e 63 6c 75 64 65 5c 00 00004e: directory "..\..\User\" : 2e 2e 5c 2e 2e 5c 55 73 65 72 5c 00 00005a: directory "" : 00 00005b: file "stm32f7xx.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 2e 68 00 01 00 00 00006a: file "stm32f767xx.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 36 37 78 78 2e 68 00 01 00 00 00007b: file "stm32f7xx_hal_conf.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 63 6f 6e 66 2e 68 00 02 00 00 000093: file "" : 00 000094: DW_LNS_negate_stmt : 06 000095: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\CMSIS\Device\ST\STM32F7xx\Include\stm32f7xx.h:1.0 [ ** Section #61 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 428 bytes 000000: Header: size 0x1a8 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\CMSIS\Device\ST\STM32F7xx\Include\stm32f7xx.h 00004a: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000091: DW_AT_language DW_LANG_C89 000093: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010a: DW_AT_macro_info 0x0 00010e: DW_AT_stmt_list 0x0 000112: 19 = 0x4 (DW_TAG_enumeration_type) 000113: DW_AT_sibling 0x127 000115: DW_AT_byte_size 0x1 000116: 20 = 0x28 (DW_TAG_enumerator) 000117: DW_AT_name RESET 00011d: DW_AT_const_value indirect DW_FORM_data1 0x0 00011f: 20 = 0x28 (DW_TAG_enumerator) 000120: DW_AT_name SET 000124: DW_AT_const_value indirect DW_FORM_data1 0x1 000126: 0 null 000127: 80 = 0x16 (DW_TAG_typedef) 000128: DW_AT_name FlagStatus 000133: DW_AT_type indirect DW_FORM_ref2 0x112 000136: DW_AT_decl_file 0x1 000137: DW_AT_decl_line 0xaa 000139: DW_AT_decl_column 0x3 00013a: 80 = 0x16 (DW_TAG_typedef) 00013b: DW_AT_name ITStatus 000144: DW_AT_type indirect DW_FORM_ref2 0x112 000147: DW_AT_decl_file 0x1 000148: DW_AT_decl_line 0xaa 00014a: DW_AT_decl_column 0xf 00014b: 19 = 0x4 (DW_TAG_enumeration_type) 00014c: DW_AT_sibling 0x165 00014e: DW_AT_byte_size 0x1 00014f: 20 = 0x28 (DW_TAG_enumerator) 000150: DW_AT_name DISABLE 000158: DW_AT_const_value indirect DW_FORM_data1 0x0 00015a: 20 = 0x28 (DW_TAG_enumerator) 00015b: DW_AT_name ENABLE 000162: DW_AT_const_value indirect DW_FORM_data1 0x1 000164: 0 null 000165: 80 = 0x16 (DW_TAG_typedef) 000166: DW_AT_name FunctionalState 000176: DW_AT_type indirect DW_FORM_ref2 0x14b 000179: DW_AT_decl_file 0x1 00017a: DW_AT_decl_line 0xb0 00017c: DW_AT_decl_column 0x3 00017d: 19 = 0x4 (DW_TAG_enumeration_type) 00017e: DW_AT_sibling 0x196 000180: DW_AT_byte_size 0x1 000181: 20 = 0x28 (DW_TAG_enumerator) 000182: DW_AT_name ERROR 000188: DW_AT_const_value indirect DW_FORM_data1 0x0 00018a: 20 = 0x28 (DW_TAG_enumerator) 00018b: DW_AT_name SUCCESS 000193: DW_AT_const_value indirect DW_FORM_data1 0x1 000195: 0 null 000196: 80 = 0x16 (DW_TAG_typedef) 000197: DW_AT_name ErrorStatus 0001a3: DW_AT_type indirect DW_FORM_ref2 0x17d 0001a6: DW_AT_decl_file 0x1 0001a7: DW_AT_decl_line 0xb7 0001a9: DW_AT_decl_column 0x3 0001aa: 0 null 0001ab: 0 padding ** Section #369 '.rel.debug_info' (SHT_REL) Size : 24 bytes (alignment 4) Symbol table #343 '.symtab' 3 relocations applied to section #61 '.debug_info' ** Section #62 '__ARM_grp.stm32_hal_legacy.h.2_E5Q000_A8eEaLqDmx3_300000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #63 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 105708 bytes 000000: include at line 0 - file 1 000003: line 41 define __STM32_HAL_LEGACY 000019: line 54 define AES_FLAG_RDERR CRYP_FLAG_RDERR 00003a: line 55 define AES_FLAG_WRERR CRYP_FLAG_WRERR 00005b: line 56 define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF 000082: line 57 define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR 0000ad: line 58 define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR 0000d8: line 67 define ADC_RESOLUTION12b ADC_RESOLUTION_12B 0000ff: line 68 define ADC_RESOLUTION10b ADC_RESOLUTION_10B 000126: line 69 define ADC_RESOLUTION8b ADC_RESOLUTION_8B 00014b: line 70 define ADC_RESOLUTION6b ADC_RESOLUTION_6B 000170: line 71 define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN 0001a0: line 72 define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED 0001cc: line 73 define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV 0001f2: line 74 define EOC_SEQ_CONV ADC_EOC_SEQ_CONV 000212: line 75 define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV 000240: line 76 define REGULAR_GROUP ADC_REGULAR_GROUP 000262: line 77 define INJECTED_GROUP ADC_INJECTED_GROUP 000286: line 78 define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP 0002ba: line 79 define AWD_EVENT ADC_AWD_EVENT 0002d4: line 80 define AWD1_EVENT ADC_AWD1_EVENT 0002f0: line 81 define AWD2_EVENT ADC_AWD2_EVENT 00030c: line 82 define AWD3_EVENT ADC_AWD3_EVENT 000328: line 83 define OVR_EVENT ADC_OVR_EVENT 000342: line 84 define JQOVF_EVENT ADC_JQOVF_EVENT 000360: line 85 define ALL_CHANNELS ADC_ALL_CHANNELS 000380: line 86 define REGULAR_CHANNELS ADC_REGULAR_CHANNELS 0003a8: line 87 define INJECTED_CHANNELS ADC_INJECTED_CHANNELS 0003d2: line 88 define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR 0003fb: line 89 define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT 000423: line 90 define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 00045b: line 91 define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 000493: line 92 define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 0004cb: line 93 define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 000503: line 94 define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 00053b: line 95 define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO 000574: line 96 define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 0005ad: line 97 define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO 0005e6: line 98 define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 00061d: line 99 define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO 000658: line 100 define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 000693: line 101 define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 0006ba: line 102 define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE 0006f5: line 103 define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING 000734: line 104 define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING 000775: line 105 define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING 0007c2: line 106 define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 0007f5: line 108 define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY 000825: line 109 define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY 000855: line 110 define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC 000883: line 111 define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC 0008b1: line 112 define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL 0008e4: line 113 define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL 000915: line 114 define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 00093c: line 123 define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG 000962: line 132 define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE 000996: line 133 define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE 0009c8: line 134 define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 0009fb: line 135 define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 000a2e: line 136 define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 000a61: line 137 define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 000a94: line 138 define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 000ac7: line 139 define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 000afa: line 140 define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 000b2d: line 141 define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED 000b6e: line 142 define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR 000bae: line 221 define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig 000bec: line 230 define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE 000c32: line 231 define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE 000c76: line 241 define DAC1_CHANNEL_1 DAC_CHANNEL_1 000c96: line 242 define DAC1_CHANNEL_2 DAC_CHANNEL_2 000cb6: line 243 define DAC2_CHANNEL_1 DAC_CHANNEL_1 000cd6: line 244 define DAC_WAVE_NONE ((uint32_t)0x00000000U) 000cff: line 245 define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0) 000d2c: line 246 define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) 000d5c: line 247 define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE 000d85: line 248 define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE 000db0: line 249 define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE 000de1: line 258 define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 000e13: line 259 define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 000e51: line 260 define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 000e8f: line 261 define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 000ec5: line 262 define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 000efb: line 263 define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 000f35: line 264 define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 000f6b: line 265 define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 000fa1: line 266 define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 000fd7: line 267 define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 001011: line 268 define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 00104b: line 269 define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 001081: line 270 define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 0010b5: line 271 define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 0010e9: line 272 define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 00111d: line 274 define IS_HAL_REMAPDMA IS_DMA_REMAP 00113d: line 275 define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE 00117d: line 276 define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE 0011bf: line 288 define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE 0011ea: line 289 define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD 00121d: line 290 define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD 001248: line 291 define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD 00127f: line 292 define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS 0012ac: line 293 define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES 0012d5: line 294 define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES 001302: line 295 define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE 001333: line 296 define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE 00135b: line 297 define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE 001381: line 298 define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE 0013b0: line 299 define OBEX_PCROP OPTIONBYTE_PCROP 0013cf: line 300 define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG 0013f8: line 301 define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE 001425: line 302 define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE 001450: line 303 define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE 00147f: line 304 define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD 0014b6: line 305 define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD 0014e5: line 306 define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE 001518: line 307 define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD 001553: line 308 define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD 001586: line 309 define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE 0015c1: line 310 define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD 001604: line 311 define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD 00163f: line 312 define PAGESIZE FLASH_PAGE_SIZE 00165b: line 313 define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE 00168a: line 314 define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD 0016c1: line 315 define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD 0016f0: line 316 define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 001719: line 317 define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 001742: line 318 define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 00176b: line 319 define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 001794: line 320 define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST 0017bf: line 321 define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST 0017fc: line 322 define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA 00182a: line 323 define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB 001858: line 324 define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA 001886: line 325 define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB 0018b4: line 326 define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE 0018de: line 327 define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN 001905: line 328 define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE 00192d: line 329 define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN 001952: line 330 define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE 00197b: line 331 define FLASH_ERROR_RD HAL_FLASH_ERROR_RD 0019a0: line 332 define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG 0019c7: line 333 define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS 0019ee: line 334 define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP 001a15: line 335 define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV 001a3e: line 336 define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR 001a6d: line 337 define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG 001a96: line 338 define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION 001ac2: line 339 define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA 001ae9: line 340 define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE 001b12: line 341 define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE 001b3a: line 342 define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS 001b61: line 343 define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS 001b88: line 344 define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST 001bb1: line 345 define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR 001bde: line 346 define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO 001c0d: line 347 define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION 001c40: line 348 define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS 001c67: line 349 define OB_WDG_SW OB_IWDG_SW 001c7f: line 350 define OB_WDG_HW OB_IWDG_HW 001c97: line 351 define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET 001cce: line 352 define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET 001d09: line 353 define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET 001d37: line 354 define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET 001d69: line 355 define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR 001d9e: line 356 define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 001dbe: line 357 define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 001dde: line 358 define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 001dfe: line 368 define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 001e36: line 369 define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 001e70: line 370 define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 001ea8: line 371 define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 001ee0: line 372 define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 001f18: line 373 define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 001f50: line 374 define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 001f86: line 375 define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 001fbc: line 376 define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 001ff2: line 386 define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE 002035: line 387 define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE 002076: line 388 define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 0020af: line 389 define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 0020ea: line 404 define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef 002117: line 405 define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef 002156: line 413 define GET_GPIO_SOURCE GPIO_GET_INDEX 002178: line 414 define GET_GPIO_INDEX GPIO_GET_INDEX 002199: line 422 define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 0021bc: line 423 define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 0021e0: line 431 define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 002202: line 432 define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 002224: line 433 define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 002246: line 436 define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW 00226c: line 437 define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM 002298: line 438 define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH 0022c0: line 439 define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH 0022ed: line 455 define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 00230f: line 463 define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED 002363: line 464 define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 0023c8: line 465 define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 00242d: line 466 define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 002492: line 467 define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 0024f1: line 468 define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 002558: line 469 define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 0025bf: line 470 define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 002624: line 471 define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 002683: line 473 define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER 0026b4: line 474 define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER 0026e5: line 475 define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD 002714: line 476 define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD 002743: line 477 define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER 002782: line 478 define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER 0027c1: line 479 define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE 0027f2: line 480 define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE 002823: line 488 define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE 002857: line 489 define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE 002889: line 490 define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE 0028bd: line 491 define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE 0028ef: line 492 define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE 00291f: line 493 define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE 00294d: line 494 define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE 002981: line 495 define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE 0029b7: line 497 define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX 0029ea: line 498 define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX 002a1d: line 499 define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX 002a53: line 500 define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX 002a89: line 501 define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX 002abe: line 502 define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX 002af3: line 511 define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE 002b2f: line 512 define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE 002b69: line 521 define KR_KEY_RELOAD IWDG_KEY_RELOAD 002b8a: line 522 define KR_KEY_ENABLE IWDG_KEY_ENABLE 002bab: line 523 define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE 002bd6: line 524 define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE 002c02: line 533 define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 002c54: line 534 define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS 002c9e: line 535 define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS 002ce8: line 536 define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS 002d32: line 538 define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING 002d6f: line 539 define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING 002dae: line 540 define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING 002df2: line 542 define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 002e42: line 543 define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS 002e8a: line 544 define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS 002ed2: line 545 define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS 002f1a: line 549 define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS 002f60: line 550 define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS 002fa6: line 551 define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS 002fec: line 560 define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b 003018: line 561 define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b 003046: line 562 define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b 00307c: line 563 define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b 0030b4: line 565 define NAND_AddressTypedef NAND_AddressTypeDef 0030df: line 567 define __ARRAY_ADDRESS ARRAY_ADDRESS 003100: line 568 define __ADDR_1st_CYCLE ADDR_1ST_CYCLE 003123: line 569 define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE 003146: line 570 define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE 003169: line 571 define __ADDR_4th_CYCLE ADDR_4TH_CYCLE 00318c: line 579 define NOR_StatusTypedef HAL_NOR_StatusTypeDef 0031b7: line 580 define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS 0031dd: line 581 define NOR_ONGOING HAL_NOR_STATUS_ONGOING 003203: line 582 define NOR_ERROR HAL_NOR_STATUS_ERROR 003225: line 583 define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT 00324b: line 585 define __NOR_WRITE NOR_WRITE 003264: line 586 define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT 003287: line 595 define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 0032c2: line 596 define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 0032fd: line 597 define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 003338: line 598 define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 003373: line 600 define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 0033b6: line 601 define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 0033f9: line 602 define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 00343c: line 603 define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 00347f: line 605 define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 0034b4: line 606 define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 0034e9: line 608 define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 00351f: line 609 define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 003555: line 611 define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 003592: line 612 define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 0035cf: line 614 define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 003609: line 616 define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO 003644: line 617 define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 003681: line 618 define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 0036be: line 627 define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS 0036ec: line 629 define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL 00370e: line 640 define CF_DATA ATA_DATA 003722: line 641 define CF_SECTOR_COUNT ATA_SECTOR_COUNT 003746: line 642 define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER 00376c: line 643 define CF_CYLINDER_LOW ATA_CYLINDER_LOW 003790: line 644 define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH 0037b6: line 645 define CF_CARD_HEAD ATA_CARD_HEAD 0037d4: line 646 define CF_STATUS_CMD ATA_STATUS_CMD 0037f4: line 647 define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE 003828: line 648 define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA 003854: line 651 define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD 00387e: line 652 define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD 0038aa: line 653 define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD 0038d6: line 654 define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD 0038fa: line 656 define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef 00392b: line 657 define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS 003957: line 658 define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING 003983: line 659 define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR 0039ab: line 660 define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT 0039d7: line 669 define FORMAT_BIN RTC_FORMAT_BIN 0039f4: line 670 define FORMAT_BCD RTC_FORMAT_BCD 003a11: line 672 define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE 003a4c: line 673 define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE 003a8c: line 674 define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE 003ace: line 675 define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE 003b0a: line 676 define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE 003b44: line 678 define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE 003b7f: line 679 define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE 003bb8: line 680 define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE 003bf8: line 681 define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE 003c3a: line 682 define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE 003c75: line 683 define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE 003cae: line 684 define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT 003ce2: line 685 define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT 003d18: line 687 define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT 003d4a: line 688 define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 003d78: line 689 define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 003da6: line 690 define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 003dd4: line 692 define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE 003e03: line 693 define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 003e32: line 694 define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 003e60: line 696 define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT 003e8c: line 697 define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 003eb4: line 698 define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 003edc: line 708 define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE 003f0c: line 709 define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE 003f3e: line 711 define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE 003f85: line 712 define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE 003fca: line 713 define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE 004010: line 714 define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE 004054: line 716 define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE 00408c: line 717 define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE 0040c2: line 719 define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE 0040fa: line 720 define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE 004130: line 729 define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE 004168: line 730 define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE 00419e: line 731 define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE 0041d6: line 732 define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE 00420c: line 733 define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE 004240: line 734 define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE 004272: line 735 define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE 0042aa: line 736 define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE 0042e4: line 737 define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE 00430c: line 738 define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE 004332: line 739 define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN 004369: line 747 define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE 004393: line 748 define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE 0043bb: line 750 define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE 0043f5: line 751 define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE 00442d: line 753 define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE 00445d: line 754 define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE 00448b: line 763 define CCER_CCxE_MASK TIM_CCER_CCxE_MASK 0044b0: line 764 define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK 0044d7: line 766 define TIM_DMABase_CR1 TIM_DMABASE_CR1 0044fa: line 767 define TIM_DMABase_CR2 TIM_DMABASE_CR2 00451d: line 768 define TIM_DMABase_SMCR TIM_DMABASE_SMCR 004542: line 769 define TIM_DMABase_DIER TIM_DMABASE_DIER 004567: line 770 define TIM_DMABase_SR TIM_DMABASE_SR 004588: line 771 define TIM_DMABase_EGR TIM_DMABASE_EGR 0045ab: line 772 define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 0045d2: line 773 define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 0045f9: line 774 define TIM_DMABase_CCER TIM_DMABASE_CCER 00461e: line 775 define TIM_DMABase_CNT TIM_DMABASE_CNT 004641: line 776 define TIM_DMABase_PSC TIM_DMABASE_PSC 004664: line 777 define TIM_DMABase_ARR TIM_DMABASE_ARR 004687: line 778 define TIM_DMABase_RCR TIM_DMABASE_RCR 0046aa: line 779 define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 0046cf: line 780 define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 0046f4: line 781 define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 004719: line 782 define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 00473e: line 783 define TIM_DMABase_BDTR TIM_DMABASE_BDTR 004763: line 784 define TIM_DMABase_DCR TIM_DMABASE_DCR 004786: line 785 define TIM_DMABase_DMAR TIM_DMABASE_DMAR 0047ab: line 786 define TIM_DMABase_OR1 TIM_DMABASE_OR1 0047ce: line 787 define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 0047f5: line 788 define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 00481a: line 789 define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 00483f: line 790 define TIM_DMABase_OR2 TIM_DMABASE_OR2 004862: line 791 define TIM_DMABase_OR3 TIM_DMABASE_OR3 004885: line 792 define TIM_DMABase_OR TIM_DMABASE_OR 0048a6: line 794 define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE 0048d7: line 795 define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 004902: line 796 define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 00492d: line 797 define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 004958: line 798 define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 004983: line 799 define TIM_EventSource_COM TIM_EVENTSOURCE_COM 0049ae: line 800 define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER 0049e1: line 801 define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK 004a10: line 802 define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 004a41: line 804 define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER 004a7e: line 805 define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS 004abd: line 806 define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS 004afc: line 807 define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS 004b3b: line 808 define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS 004b7a: line 809 define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS 004bb9: line 810 define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS 004bf8: line 811 define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS 004c37: line 812 define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS 004c76: line 813 define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS 004cb7: line 814 define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS 004cf8: line 815 define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS 004d39: line 816 define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS 004d7a: line 817 define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS 004dbb: line 818 define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS 004dfc: line 819 define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS 004e3d: line 820 define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS 004e7e: line 821 define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS 004ebf: line 830 define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING 004eee: line 831 define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING 004f21: line 839 define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE 004f5e: line 840 define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE 004f99: line 841 define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE 004fd5: line 842 define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE 00500f: line 844 define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE 00504c: line 845 define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE 00508b: line 847 define __DIV_SAMPLING16 UART_DIV_SAMPLING16 0050b3: line 848 define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 0050e3: line 849 define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 005113: line 850 define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 005140: line 852 define __DIV_SAMPLING8 UART_DIV_SAMPLING8 005166: line 853 define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 005194: line 854 define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 0051c2: line 855 define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 0051ed: line 857 define __DIV_LPUART UART_DIV_LPUART 00520d: line 859 define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE 005247: line 860 define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK 005287: line 871 define USART_CLOCK_DISABLED USART_CLOCK_DISABLE 0052b3: line 872 define USART_CLOCK_ENABLED USART_CLOCK_ENABLE 0052dd: line 874 define USARTNACK_ENABLED USART_NACK_ENABLE 005304: line 875 define USARTNACK_DISABLED USART_NACK_DISABLE 00532d: line 883 define CFR_BASE WWDG_CFR_BASE 005347: line 892 define CAN_FilterFIFO0 CAN_FILTER_FIFO0 00536b: line 893 define CAN_FilterFIFO1 CAN_FILTER_FIFO1 00538f: line 894 define CAN_IT_RQCP0 CAN_IT_TME 0053aa: line 895 define CAN_IT_RQCP1 CAN_IT_TME 0053c5: line 896 define CAN_IT_RQCP2 CAN_IT_TME 0053e0: line 897 define INAK_TIMEOUT CAN_TIMEOUT_VALUE 005402: line 898 define SLAK_TIMEOUT CAN_TIMEOUT_VALUE 005424: line 899 define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) 00544c: line 900 define CAN_TXSTATUS_OK ((uint8_t)0x01U) 005470: line 901 define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) 005499: line 911 define VLAN_TAG ETH_VLAN_TAG 0054b2: line 912 define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD 0054d9: line 913 define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD 005500: line 914 define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD 00552f: line 915 define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK 005558: line 916 define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK 005581: line 917 define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK 0055ac: line 918 define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK 0055d7: line 920 define ETH_MMCCR ((uint32_t)0x00000100U) 0055fc: line 921 define ETH_MMCRIR ((uint32_t)0x00000104U) 005622: line 922 define ETH_MMCTIR ((uint32_t)0x00000108U) 005648: line 923 define ETH_MMCRIMR ((uint32_t)0x0000010CU) 00566f: line 924 define ETH_MMCTIMR ((uint32_t)0x00000110U) 005696: line 925 define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU) 0056c0: line 926 define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U) 0056eb: line 927 define ETH_MMCTGFCR ((uint32_t)0x00000168U) 005713: line 928 define ETH_MMCRFCECR ((uint32_t)0x00000194U) 00573c: line 929 define ETH_MMCRFAECR ((uint32_t)0x00000198U) 005765: line 930 define ETH_MMCRGUFCR ((uint32_t)0x000001C4U) 00578e: line 932 define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) 0057bc: line 933 define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) 0057ee: line 934 define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) 005824: line 935 define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) 005852: line 936 define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) 005880: line 937 define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) 0058b1: line 938 define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) 0058e2: line 939 define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) 005917: line 940 define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) 005956: line 941 define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) 005998: line 942 define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) 0059e0: line 943 define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) 005a27: line 944 define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) 005a5d: line 945 define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) 005a8c: line 946 define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) 005ac5: line 947 define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) 005afe: line 948 define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) 005b2c: line 951 define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) 005b62: line 952 define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) 005ba0: line 953 define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) 005be0: line 955 define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) 005c1a: line 956 define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) 005c50: line 957 define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) 005c87: line 958 define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) 005cc0: line 959 define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) 005cfa: line 960 define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) 005d31: line 961 define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) 005d6f: line 970 define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR 005d98: line 971 define DCMI_IT_OVF DCMI_IT_OVR 005db3: line 972 define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI 005dd6: line 973 define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI 005df9: line 975 define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop 005e24: line 976 define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop 005e4f: line 977 define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop 005e7c: line 988 define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 005ea4: line 989 define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 005ec8: line 990 define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 005eec: line 991 define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 005f14: line 992 define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 005f3c: line 994 define CM_ARGB8888 DMA2D_INPUT_ARGB8888 005f60: line 995 define CM_RGB888 DMA2D_INPUT_RGB888 005f80: line 996 define CM_RGB565 DMA2D_INPUT_RGB565 005fa0: line 997 define CM_ARGB1555 DMA2D_INPUT_ARGB1555 005fc4: line 998 define CM_ARGB4444 DMA2D_INPUT_ARGB4444 005fe8: line 999 define CM_L8 DMA2D_INPUT_L8 006000: line 1000 define CM_AL44 DMA2D_INPUT_AL44 00601c: line 1001 define CM_AL88 DMA2D_INPUT_AL88 006038: line 1002 define CM_L4 DMA2D_INPUT_L4 006050: line 1003 define CM_A8 DMA2D_INPUT_A8 006068: line 1004 define CM_A4 DMA2D_INPUT_A4 006080: line 1023 define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback 0060c7: line 1031 define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef 0060f6: line 1032 define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef 006124: line 1033 define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish 00614f: line 1034 define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish 00617c: line 1035 define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish 0061ad: line 1036 define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish 0061de: line 1040 define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 006211: line 1041 define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 006248: line 1042 define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 00627f: line 1043 define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 0062b0: line 1045 define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH 0062d9: line 1046 define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC 006302: line 1048 define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY 00633a: line 1049 define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY 006370: line 1057 define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode 0063a8: line 1058 define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode 0063e2: line 1059 define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode 006418: line 1060 define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode 006450: line 1061 define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode 00648c: line 1062 define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode 0064ca: line 1063 define HAL_DBG_LowPowerConfig(Periph,cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) 00655e: line 1064 define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect 00659a: line 1065 define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) 006608: line 1068 define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) 00666c: line 1070 define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) 0066d8: line 1071 define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) 00675e: line 1079 define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram 006793: line 1080 define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown 0067ce: line 1081 define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown 00680b: line 1082 define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock 006845: line 1083 define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock 00687b: line 1084 define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase 0068b3: line 1085 define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program 0068ef: line 1094 define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter 00692d: line 1095 define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter 00696d: line 1096 define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter 0069b1: line 1097 define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter 0069f7: line 1099 define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus,cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) 006aaf: line 1107 define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD 006ad6: line 1108 define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg 006b09: line 1109 define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown 006b4a: line 1110 define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor 006b89: line 1111 define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg 006bba: line 1112 define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown 006bf9: line 1113 define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor 006c36: line 1114 define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler 006c71: line 1115 define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD 006c9d: line 1116 define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler 006ce4: line 1117 define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback 006d25: line 1118 define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive 006d5e: line 1119 define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive 006d9a: line 1120 define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC 006dd1: line 1121 define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC 006e06: line 1122 define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM 006e31: line 1124 define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL 006e58: line 1125 define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING 006e85: line 1126 define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING 006eb4: line 1127 define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING 006ef1: line 1128 define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING 006f24: line 1129 define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING 006f59: line 1130 define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING 006f9c: line 1132 define CR_OFFSET_BB PWR_CR_OFFSET_BB 006fbd: line 1133 define CSR_OFFSET_BB PWR_CSR_OFFSET_BB 006fe0: line 1135 define DBP_BitNumber DBP_BIT_NUMBER 007000: line 1136 define PVDE_BitNumber PVDE_BIT_NUMBER 007022: line 1137 define PMODE_BitNumber PMODE_BIT_NUMBER 007046: line 1138 define EWUP_BitNumber EWUP_BIT_NUMBER 007068: line 1139 define FPDS_BitNumber FPDS_BIT_NUMBER 00708a: line 1140 define ODEN_BitNumber ODEN_BIT_NUMBER 0070ac: line 1141 define ODSWEN_BitNumber ODSWEN_BIT_NUMBER 0070d2: line 1142 define MRLVDS_BitNumber MRLVDS_BIT_NUMBER 0070f8: line 1143 define LPLVDS_BitNumber LPLVDS_BIT_NUMBER 00711e: line 1144 define BRE_BitNumber BRE_BIT_NUMBER 00713e: line 1146 define PWR_MODE_EVT PWR_PVD_MODE_NORMAL 007162: line 1155 define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT 007199: line 1156 define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback 0071cf: line 1157 define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback 007211: line 1165 define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo 00723e: line 1173 define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt 007271: line 1174 define HAL_TIM_DMAError TIM_DMAError 007292: line 1175 define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt 0072bf: line 1176 define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt 0072f8: line 1184 define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback 00732d: line 1192 define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback 007365: line 1211 define AES_IT_CC CRYP_IT_CC 00737d: line 1212 define AES_IT_ERR CRYP_IT_ERR 007397: line 1213 define AES_FLAG_CCF CRYP_FLAG_CCF 0073b5: line 1221 define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE 0073e7: line 1222 define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH 007421: line 1223 define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH 007467: line 1224 define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM 00749f: line 1225 define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC 0074d5: line 1226 define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM 007517: line 1227 define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC 00754f: line 1228 define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI 00758d: line 1229 define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK 0075b5: line 1230 define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG 0075dd: line 1231 define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG 007609: line 1232 define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE 007645: line 1233 define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE 007683: line 1235 define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY 0076b7: line 1236 define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 0076da: line 1237 define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS 00770f: line 1238 define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER 007739: line 1239 define CMP_PD_BitNumber CMP_PD_BIT_NUMBER 00775f: line 1249 define __ADC_ENABLE __HAL_ADC_ENABLE 007780: line 1250 define __ADC_DISABLE __HAL_ADC_DISABLE 0077a3: line 1251 define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS 0077dc: line 1252 define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS 007817: line 1253 define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE 00783d: line 1254 define __ADC_IS_ENABLED ADC_IS_ENABLE 00785f: line 1255 define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR 0078a4: line 1256 define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED 0078eb: line 1257 define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED 00794a: line 1258 define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR 007997: line 1259 define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED 0079e6: line 1260 define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING 007a23: line 1261 define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE 007a54: line 1263 define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION 007a83: line 1264 define __HAL_ADC_JSQR_RK ADC_JSQR_RK 007aa4: line 1265 define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT 007ad3: line 1266 define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR 007afe: line 1267 define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION 007b47: line 1268 define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE 007b8c: line 1269 define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS 007bd3: line 1270 define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS 007c14: line 1271 define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM 007c53: line 1272 define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT 007c80: line 1273 define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS 007cb1: line 1274 define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN 007cdc: line 1275 define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ 007d0d: line 1276 define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET 007d3a: line 1277 define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET 007d69: line 1278 define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL 007d92: line 1279 define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL 007dc1: line 1280 define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET 007df4: line 1281 define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET 007e27: line 1282 define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD 007e5c: line 1284 define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION 007e9d: line 1285 define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION 007eec: line 1286 define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION 007f3d: line 1287 define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER 007f6e: line 1288 define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI 007fa1: line 1289 define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE 007fdb: line 1290 define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE 008011: line 1291 define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER 008062: line 1292 define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER 008095: line 1293 define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE 0080be: line 1295 define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT 0080e3: line 1296 define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT 00810a: line 1297 define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL 008131: line 1298 define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM 00816e: line 1299 define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET 008195: line 1300 define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE 0081d0: line 1301 define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE 00820d: line 1302 define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER 008246: line 1304 define __HAL_ADC_SQR1 ADC_SQR1 008261: line 1305 define __HAL_ADC_SMPR1 ADC_SMPR1 00827e: line 1306 define __HAL_ADC_SMPR2 ADC_SMPR2 00829b: line 1307 define __HAL_ADC_SQR3_RK ADC_SQR3_RK 0082bc: line 1308 define __HAL_ADC_SQR2_RK ADC_SQR2_RK 0082dd: line 1309 define __HAL_ADC_SQR1_RK ADC_SQR1_RK 0082fe: line 1310 define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS 00832d: line 1311 define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS 008362: line 1312 define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV 00838d: line 1313 define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection 0083c0: line 1314 define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq 0083ef: line 1315 define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION 00841e: line 1316 define __HAL_ADC_JSQR ADC_JSQR 008439: line 1318 define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL 008468: line 1319 define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS 0084ab: line 1320 define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF 0084d8: line 1321 define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT 008507: line 1322 define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS 00853a: line 1323 define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN 008567: line 1324 define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR 008594: line 1325 define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ 0085c7: line 1334 define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT 0085f9: line 1335 define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT 00862b: line 1336 define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT 00865d: line 1337 define IS_DAC_GENERATE_WAVE IS_DAC_WAVE 008681: line 1346 define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 0086b6: line 1347 define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 0086ef: line 1348 define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 008724: line 1349 define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 00875d: line 1350 define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 008792: line 1351 define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 0087cb: line 1352 define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 008800: line 1353 define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 008839: line 1354 define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 00886e: line 1355 define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 0088a7: line 1356 define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 0088dc: line 1357 define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 008915: line 1358 define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 00894a: line 1359 define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 008983: line 1360 define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 0089b8: line 1361 define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 0089f1: line 1363 define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 008a26: line 1364 define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 008a5f: line 1365 define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 008a96: line 1366 define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 008ad1: line 1367 define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 008b08: line 1368 define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 008b43: line 1369 define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 008b7a: line 1370 define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 008bb5: line 1371 define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 008bec: line 1372 define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 008c27: line 1373 define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 008c5e: line 1374 define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 008c99: line 1375 define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 008cce: line 1376 define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 008d07: line 1379 define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 008d3e: line 1380 define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 008d79: line 1381 define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 008db0: line 1382 define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 008deb: line 1383 define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 008e22: line 1384 define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 008e5d: line 1385 define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC 008e90: line 1386 define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC 008ec7: line 1387 define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG 008efc: line 1388 define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG 008f35: line 1389 define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG 008f6a: line 1390 define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG 008fa3: line 1391 define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT 008fe8: line 1392 define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT 009031: line 1393 define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT 009076: line 1394 define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT 0090bf: line 1395 define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT 009104: line 1396 define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT 00914d: line 1397 define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 009182: line 1398 define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 0091bb: line 1399 define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 0091f4: line 1400 define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 009231: line 1401 define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 00926a: line 1402 define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 0092a7: line 1553 define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) 00935e: line 1555 define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) 009418: line 1557 define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) 0094d2: line 1559 define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) 00958f: line 1561 define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : __HAL_COMP_COMP2_EXTI_ENABLE_IT()) 00962d: line 1563 define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : __HAL_COMP_COMP2_EXTI_DISABLE_IT()) 0096ce: line 1565 define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : __HAL_COMP_COMP2_EXTI_GET_FLAG()) 009761: line 1567 define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) 0097fa: line 1571 define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE 009829: line 1599 define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || ((WAVE) == DAC_WAVE_NOISE)|| ((WAVE) == DAC_WAVE_TRIANGLE)) 009898: line 1611 define IS_WRPAREA IS_OB_WRPAREA 0098b4: line 1612 define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM 0098db: line 1613 define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM 009907: line 1614 define IS_TYPEERASE IS_FLASH_TYPEERASE 00992a: line 1615 define IS_NBSECTORS IS_FLASH_NBSECTORS 00994d: line 1616 define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE 009973: line 1626 define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 009998: line 1627 define __HAL_I2C_GENERATE_START I2C_GENERATE_START 0099c7: line 1628 define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE 0099ee: line 1629 define __HAL_I2C_RISE_TIME I2C_RISE_TIME 009a13: line 1630 define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD 009a42: line 1631 define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST 009a69: line 1632 define __HAL_I2C_SPEED I2C_SPEED 009a86: line 1633 define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE 009ab5: line 1634 define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ 009ae2: line 1635 define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS 009b0f: line 1636 define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE 009b46: line 1637 define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ 009b7b: line 1638 define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB 009ba4: line 1639 define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB 009bcd: line 1640 define __HAL_I2C_FREQRANGE I2C_FREQRANGE 009bf2: line 1649 define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE 009c19: line 1650 define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT 009c48: line 1660 define __IRDA_DISABLE __HAL_IRDA_DISABLE 009c6d: line 1661 define __IRDA_ENABLE __HAL_IRDA_ENABLE 009c90: line 1663 define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE 009cc1: line 1664 define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION 009cf6: line 1665 define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE 009d23: line 1666 define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION 009d54: line 1668 define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE 009d84: line 1679 define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS 009dbf: line 1680 define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS 009dfc: line 1690 define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT 009e32: line 1691 define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT 009e6a: line 1692 define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE 009ea0: line 1702 define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD 009ec7: line 1703 define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX 009eee: line 1704 define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX 009f15: line 1705 define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX 009f3c: line 1706 define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX 009f63: line 1707 define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L 009f90: line 1708 define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H 009fbd: line 1709 define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM 009fe6: line 1710 define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES 00a019: line 1711 define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX 00a044: line 1712 define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT 00a073: line 1713 define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION 00a0b6: line 1714 define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET 00a0e7: line 1724 define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT 00a123: line 1725 define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT 00a15d: line 1726 define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE 00a1ae: line 1727 define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 00a1fd: line 1728 define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE 00a24c: line 1729 define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 00a299: line 1730 define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE 00a2d0: line 1731 define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE 00a305: line 1732 define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE 00a358: line 1733 define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE 00a3a9: line 1734 define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE 00a3fa: line 1735 define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE 00a449: line 1736 define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine 00a491: line 1737 define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine 00a4d7: line 1738 define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig 00a526: line 1739 define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig 00a573: line 1740 define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) 00a602: line 1741 define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT 00a647: line 1742 define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT 00a68a: line 1743 define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE 00a6df: line 1744 define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 00a732: line 1745 define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE 00a785: line 1746 define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 00a7d6: line 1747 define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 00a82c: line 1748 define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 00a880: line 1749 define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) 00a90c: line 1750 define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) 00a993: line 1751 define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention 00a9e5: line 1752 define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention 00aa35: line 1753 define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 00aa69: line 1754 define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 00aa9b: line 1755 define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE 00aaf2: line 1756 define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE 00ab4e: line 1757 define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB 00ab82: line 1758 define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB 00abb4: line 1767 define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG 00abef: line 1768 define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT 00ac2a: line 1769 define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT 00ac63: line 1770 define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT 00aca4: line 1771 define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG 00acdb: line 1782 define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI 00ad0f: line 1783 define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI 00ad43: line 1785 define HAL_RCC_CCSCallback HAL_RCC_CSSCallback 00ad6e: line 1786 define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) 00ade7: line 1788 define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE 00ae16: line 1789 define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE 00ae43: line 1790 define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE 00ae7e: line 1791 define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE 00aeb7: line 1792 define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET 00aee6: line 1793 define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET 00af19: line 1794 define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE 00af4a: line 1795 define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE 00af79: line 1796 define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET 00afaa: line 1797 define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET 00afdf: line 1798 define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE 00b01a: line 1799 define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE 00b057: line 1800 define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE 00b088: line 1801 define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE 00b0b7: line 1802 define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET 00b0e8: line 1803 define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET 00b11d: line 1804 define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE 00b14e: line 1805 define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE 00b17d: line 1806 define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET 00b1ae: line 1807 define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET 00b1e3: line 1808 define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE 00b212: line 1809 define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE 00b23f: line 1810 define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE 00b27a: line 1811 define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE 00b2b3: line 1812 define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET 00b2e2: line 1813 define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET 00b315: line 1814 define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE 00b350: line 1815 define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE 00b38d: line 1816 define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE 00b3bc: line 1817 define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE 00b3ed: line 1818 define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET 00b41e: line 1819 define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET 00b453: line 1820 define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE 00b484: line 1821 define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE 00b4b3: line 1822 define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET 00b4e4: line 1823 define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET 00b519: line 1824 define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET 00b548: line 1825 define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET 00b57b: line 1826 define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET 00b5ac: line 1827 define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET 00b5e1: line 1828 define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET 00b612: line 1829 define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET 00b647: line 1830 define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET 00b678: line 1831 define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET 00b6ad: line 1832 define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET 00b6de: line 1833 define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET 00b713: line 1834 define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET 00b744: line 1835 define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET 00b779: line 1836 define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE 00b7a8: line 1837 define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE 00b7d5: line 1838 define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET 00b804: line 1839 define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET 00b837: line 1840 define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE 00b868: line 1841 define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE 00b897: line 1842 define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE 00b8d4: line 1843 define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE 00b90f: line 1844 define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET 00b940: line 1845 define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET 00b975: line 1846 define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE 00b9a5: line 1847 define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE 00b9d3: line 1848 define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET 00ba03: line 1849 define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET 00ba37: line 1850 define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE 00ba68: line 1851 define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE 00ba97: line 1852 define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET 00bac8: line 1853 define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET 00bafd: line 1854 define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE 00bb2c: line 1855 define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE 00bb59: line 1856 define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE 00bb8a: line 1857 define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE 00bbb9: line 1858 define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET 00bbea: line 1859 define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET 00bc1f: line 1860 define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE 00bc5a: line 1861 define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE 00bc97: line 1862 define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET 00bcc6: line 1863 define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET 00bcf9: line 1864 define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE 00bd28: line 1865 define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE 00bd55: line 1866 define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE 00bd90: line 1867 define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE 00bdc9: line 1868 define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET 00bdf8: line 1869 define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET 00be2b: line 1870 define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE 00be5a: line 1871 define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE 00be87: line 1872 define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET 00beb6: line 1873 define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET 00bee9: line 1874 define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE 00bf1a: line 1875 define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE 00bf49: line 1876 define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE 00bf86: line 1877 define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE 00bfc1: line 1878 define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET 00bff2: line 1879 define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET 00c027: line 1880 define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE 00c05a: line 1881 define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE 00c08f: line 1882 define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET 00c0c4: line 1883 define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET 00c0fd: line 1884 define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE 00c130: line 1885 define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE 00c161: line 1886 define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE 00c1a0: line 1887 define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE 00c1dd: line 1888 define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET 00c210: line 1889 define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET 00c247: line 1890 define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE 00c278: line 1891 define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE 00c2a7: line 1892 define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE 00c2e4: line 1893 define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE 00c31f: line 1894 define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET 00c350: line 1895 define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET 00c385: line 1896 define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE 00c3b6: line 1897 define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE 00c3e5: line 1898 define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE 00c422: line 1899 define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE 00c45d: line 1900 define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET 00c48e: line 1901 define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET 00c4c3: line 1902 define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE 00c4f8: line 1903 define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE 00c52b: line 1904 define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET 00c560: line 1905 define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET 00c599: line 1906 define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE 00c5d2: line 1907 define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE 00c609: line 1908 define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE 00c642: line 1909 define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE 00c679: line 1910 define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE 00c6b2: line 1911 define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE 00c6e9: line 1912 define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE 00c71c: line 1913 define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE 00c74d: line 1914 define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE 00c78c: line 1915 define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE 00c7c9: line 1916 define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET 00c7fc: line 1917 define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET 00c833: line 1918 define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE 00c866: line 1919 define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE 00c897: line 1920 define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET 00c8ca: line 1921 define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET 00c901: line 1922 define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE 00c93e: line 1923 define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE 00c97d: line 1924 define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE 00c9ac: line 1925 define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE 00c9d9: line 1926 define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE 00ca14: line 1927 define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE 00ca4d: line 1928 define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET 00ca7c: line 1929 define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET 00caaf: line 1930 define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE 00cae0: line 1931 define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE 00cb0f: line 1932 define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE 00cb42: line 1933 define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE 00cb73: line 1934 define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE 00cbb2: line 1935 define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE 00cbef: line 1936 define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET 00cc22: line 1937 define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET 00cc59: line 1938 define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE 00cc8c: line 1939 define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE 00ccbd: line 1940 define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE 00ccfc: line 1941 define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE 00cd39: line 1942 define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET 00cd6c: line 1943 define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET 00cda3: line 1944 define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE 00cdd6: line 1945 define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE 00ce07: line 1946 define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE 00ce46: line 1947 define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE 00ce83: line 1948 define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET 00ceb6: line 1949 define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET 00ceed: line 1950 define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE 00cf20: line 1951 define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE 00cf51: line 1952 define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE 00cf90: line 1953 define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE 00cfcd: line 1954 define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET 00d000: line 1955 define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET 00d037: line 1956 define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE 00d06a: line 1957 define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE 00d09b: line 1958 define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE 00d0da: line 1959 define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE 00d117: line 1960 define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET 00d14a: line 1961 define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET 00d181: line 1962 define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE 00d1b4: line 1963 define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE 00d1e5: line 1964 define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE 00d224: line 1965 define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE 00d261: line 1966 define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET 00d294: line 1967 define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET 00d2cb: line 1968 define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE 00d2fe: line 1969 define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE 00d32f: line 1970 define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE 00d36e: line 1971 define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE 00d3ab: line 1972 define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET 00d3de: line 1973 define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET 00d415: line 1974 define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE 00d448: line 1975 define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE 00d479: line 1976 define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE 00d4b8: line 1977 define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE 00d4f5: line 1978 define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET 00d528: line 1979 define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET 00d55f: line 1980 define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE 00d590: line 1981 define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE 00d5bf: line 1982 define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE 00d5fc: line 1983 define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE 00d637: line 1984 define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET 00d668: line 1985 define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET 00d69d: line 1986 define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE 00d6ce: line 1987 define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE 00d6fd: line 1988 define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE 00d73a: line 1989 define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE 00d775: line 1990 define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET 00d7a6: line 1991 define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET 00d7db: line 1992 define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE 00d80c: line 1993 define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE 00d83b: line 1994 define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE 00d878: line 1995 define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE 00d8b3: line 1996 define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET 00d8e4: line 1997 define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET 00d919: line 1998 define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE 00d948: line 1999 define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE 00d975: line 2000 define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE 00d9b0: line 2001 define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE 00d9e9: line 2002 define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET 00da18: line 2003 define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET 00da4b: line 2004 define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE 00da80: line 2005 define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE 00dab3: line 2006 define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE 00daf4: line 2007 define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE 00db33: line 2008 define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET 00db68: line 2009 define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET 00dba1: line 2010 define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE 00dbd6: line 2011 define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE 00dc09: line 2012 define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE 00dc4a: line 2013 define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE 00dc89: line 2014 define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET 00dcbe: line 2015 define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET 00dcf7: line 2016 define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE 00dd2e: line 2017 define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE 00dd63: line 2018 define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE 00dda6: line 2019 define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE 00dde7: line 2020 define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET 00de1e: line 2021 define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET 00de59: line 2022 define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE 00de8c: line 2023 define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE 00debd: line 2024 define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE 00defc: line 2025 define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE 00df39: line 2026 define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET 00df6c: line 2027 define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET 00dfa3: line 2028 define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE 00dfd6: line 2029 define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE 00e007: line 2030 define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE 00e046: line 2031 define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE 00e083: line 2032 define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET 00e0b6: line 2033 define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET 00e0ed: line 2034 define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE 00e11c: line 2035 define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE 00e149: line 2036 define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE 00e184: line 2037 define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE 00e1bd: line 2038 define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET 00e1ec: line 2039 define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET 00e21f: line 2040 define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE 00e250: line 2041 define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE 00e27f: line 2042 define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE 00e2bc: line 2043 define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE 00e2f7: line 2044 define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET 00e328: line 2045 define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET 00e35d: line 2046 define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE 00e38c: line 2047 define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE 00e3b9: line 2048 define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE 00e3f4: line 2049 define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE 00e42d: line 2050 define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET 00e45c: line 2051 define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET 00e48f: line 2052 define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE 00e4c0: line 2053 define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE 00e4ef: line 2054 define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE 00e52c: line 2055 define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE 00e567: line 2056 define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET 00e598: line 2057 define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET 00e5cd: line 2058 define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE 00e5fe: line 2059 define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE 00e62d: line 2060 define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE 00e66a: line 2061 define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE 00e6a5: line 2062 define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET 00e6d6: line 2063 define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET 00e70b: line 2064 define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE 00e73c: line 2065 define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE 00e76b: line 2066 define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE 00e79e: line 2067 define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE 00e7cf: line 2068 define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE 00e80e: line 2069 define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE 00e84b: line 2070 define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET 00e87e: line 2071 define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET 00e8b5: line 2072 define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE 00e8e6: line 2073 define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE 00e915: line 2074 define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE 00e952: line 2075 define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE 00e98d: line 2076 define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET 00e9be: line 2077 define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET 00e9f3: line 2078 define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE 00ea24: line 2079 define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE 00ea53: line 2080 define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE 00ea90: line 2081 define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE 00eacb: line 2082 define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET 00eafc: line 2083 define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET 00eb31: line 2084 define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE 00eb62: line 2085 define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE 00eb91: line 2086 define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE 00ebce: line 2087 define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE 00ec09: line 2088 define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET 00ec3a: line 2089 define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET 00ec6f: line 2090 define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE 00eca0: line 2091 define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE 00eccf: line 2092 define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE 00ed0e: line 2093 define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE 00ed4b: line 2094 define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE 00ed8a: line 2095 define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE 00edc7: line 2096 define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE 00edfc: line 2097 define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE 00ee2f: line 2098 define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE 00ee70: line 2099 define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE 00eeaf: line 2100 define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET 00eee4: line 2101 define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET 00ef1d: line 2102 define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE 00ef52: line 2103 define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE 00ef85: line 2104 define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE 00efc6: line 2105 define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE 00f005: line 2106 define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET 00f03a: line 2107 define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET 00f073: line 2108 define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE 00f0a4: line 2109 define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE 00f0d3: line 2110 define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE 00f110: line 2111 define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE 00f14b: line 2112 define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET 00f17c: line 2113 define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET 00f1b1: line 2114 define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE 00f1e4: line 2115 define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE 00f215: line 2116 define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET 00f248: line 2117 define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET 00f27f: line 2118 define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE 00f2b2: line 2119 define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE 00f2e3: line 2120 define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET 00f316: line 2121 define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET 00f34d: line 2122 define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE 00f380: line 2123 define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE 00f3b1: line 2124 define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET 00f3e4: line 2125 define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET 00f41b: line 2126 define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE 00f44e: line 2127 define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE 00f47f: line 2128 define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET 00f4b2: line 2129 define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET 00f4e9: line 2130 define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE 00f51c: line 2131 define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE 00f54d: line 2132 define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET 00f580: line 2133 define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET 00f5b7: line 2134 define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE 00f5ea: line 2135 define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE 00f61b: line 2136 define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE 00f65a: line 2137 define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE 00f697: line 2138 define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET 00f6ca: line 2139 define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET 00f701: line 2140 define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE 00f734: line 2141 define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE 00f765: line 2142 define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE 00f7a4: line 2143 define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE 00f7e1: line 2144 define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET 00f814: line 2145 define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET 00f84b: line 2146 define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE 00f87e: line 2147 define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE 00f8af: line 2148 define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE 00f8ee: line 2149 define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE 00f92b: line 2150 define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET 00f95e: line 2151 define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET 00f995: line 2152 define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE 00f9c6: line 2153 define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE 00f9f5: line 2154 define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE 00fa32: line 2155 define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE 00fa6d: line 2156 define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET 00fa9e: line 2157 define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET 00fad3: line 2158 define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE 00fb04: line 2159 define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE 00fb33: line 2160 define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE 00fb70: line 2161 define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE 00fbab: line 2162 define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET 00fbdc: line 2163 define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET 00fc11: line 2164 define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE 00fc42: line 2165 define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE 00fc71: line 2166 define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE 00fcae: line 2167 define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE 00fce9: line 2168 define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET 00fd1a: line 2169 define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET 00fd4f: line 2170 define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE 00fd80: line 2171 define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE 00fdaf: line 2172 define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE 00fdec: line 2173 define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE 00fe27: line 2174 define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET 00fe58: line 2175 define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET 00fe8d: line 2176 define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE 00febe: line 2177 define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE 00feed: line 2178 define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE 00ff2a: line 2179 define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE 00ff65: line 2180 define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET 00ff96: line 2181 define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET 00ffcb: line 2182 define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE 00fffc: line 2183 define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE 01002b: line 2184 define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE 010068: line 2185 define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE 0100a3: line 2186 define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET 0100d4: line 2187 define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET 010109: line 2188 define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE 01013a: line 2189 define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE 010169: line 2190 define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE 0101a6: line 2191 define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE 0101e1: line 2192 define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET 010212: line 2193 define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET 010247: line 2194 define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE 010278: line 2195 define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE 0102a7: line 2196 define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET 0102d8: line 2197 define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET 01030d: line 2198 define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE 01033c: line 2199 define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE 010369: line 2200 define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE 0103a4: line 2201 define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE 0103dd: line 2202 define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET 01040c: line 2203 define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET 01043f: line 2204 define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE 010472: line 2205 define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE 0104a3: line 2206 define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE 0104e2: line 2207 define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE 01051f: line 2208 define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET 010552: line 2209 define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET 010589: line 2210 define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE 0105bc: line 2211 define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE 0105ed: line 2212 define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE 01062c: line 2213 define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE 010669: line 2214 define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET 01069c: line 2215 define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET 0106d3: line 2216 define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE 010708: line 2217 define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE 01073b: line 2218 define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE 01077c: line 2219 define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE 0107bb: line 2220 define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET 0107f0: line 2221 define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET 010829: line 2222 define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE 01085e: line 2223 define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE 010891: line 2224 define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE 0108d2: line 2225 define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE 010911: line 2226 define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET 010946: line 2227 define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET 01097f: line 2228 define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE 0109b4: line 2229 define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE 0109e7: line 2230 define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE 010a28: line 2231 define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE 010a67: line 2232 define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET 010a9c: line 2233 define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET 010ad5: line 2234 define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE 010b0a: line 2235 define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE 010b3d: line 2236 define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE 010b7c: line 2237 define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE 010bbd: line 2238 define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET 010bf2: line 2239 define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET 010c2b: line 2240 define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE 010c60: line 2241 define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE 010c93: line 2242 define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE 010cd2: line 2243 define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE 010d13: line 2244 define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET 010d48: line 2245 define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET 010d81: line 2246 define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE 010db6: line 2247 define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE 010de9: line 2248 define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET 010e1e: line 2249 define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET 010e57: line 2250 define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE 010e8c: line 2251 define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE 010ebf: line 2252 define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET 010ef4: line 2253 define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET 010f2d: line 2254 define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE 010f5c: line 2255 define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE 010f89: line 2256 define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET 010fb8: line 2257 define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE 010ff1: line 2258 define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE 01102c: line 2259 define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE 011069: line 2260 define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE 0110a4: line 2261 define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET 0110d7: line 2262 define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE 011108: line 2263 define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE 011137: line 2264 define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE 011174: line 2265 define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE 0111af: line 2266 define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET 0111e0: line 2267 define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET 011215: line 2268 define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE 011246: line 2269 define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE 011279: line 2270 define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET 0112ac: line 2271 define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET 0112e3: line 2272 define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE 011320: line 2273 define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE 01135f: line 2274 define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE 011390: line 2275 define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE 0113c3: line 2276 define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET 0113f6: line 2277 define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET 01142d: line 2278 define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE 01146a: line 2279 define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE 0114a9: line 2280 define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE 0114d8: line 2281 define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE 011505: line 2282 define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE 011540: line 2283 define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE 011579: line 2284 define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET 0115a8: line 2285 define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET 0115db: line 2286 define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE 011612: line 2287 define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE 01164d: line 2289 define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET 01168a: line 2290 define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET 0116cb: line 2291 define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE 011712: line 2292 define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE 01175b: line 2293 define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE 011798: line 2294 define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE 0117d3: line 2295 define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE 011818: line 2296 define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE 01185f: line 2297 define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE 01189a: line 2298 define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE 0118d7: line 2299 define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE 011914: line 2300 define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE 011953: line 2301 define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE 011990: line 2302 define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE 0119cf: line 2303 define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE 011a14: line 2304 define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE 011a5b: line 2305 define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE 011a94: line 2306 define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE 011acf: line 2307 define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE 011afe: line 2308 define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET 011b2f: line 2309 define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET 011b64: line 2310 define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE 011b9f: line 2311 define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE 011bdc: line 2312 define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE 011c0d: line 2313 define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE 011c3c: line 2314 define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE 011c6d: line 2315 define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET 011c9e: line 2316 define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET 011cd3: line 2317 define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE 011d0e: line 2318 define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE 011d4b: line 2319 define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE 011d7a: line 2320 define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE 011dab: line 2321 define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET 011ddc: line 2322 define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET 011e11: line 2323 define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE 011e4c: line 2324 define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE 011e89: line 2325 define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE 011eb8: line 2326 define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE 011ee9: line 2327 define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET 011f1a: line 2328 define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET 011f4f: line 2329 define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE 011f8a: line 2330 define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE 011fc9: line 2331 define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE 01200a: line 2332 define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE 01204d: line 2333 define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE 012092: line 2334 define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE 0120d5: line 2335 define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE 01211a: line 2336 define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE 012157: line 2337 define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE 012196: line 2338 define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE 0121d3: line 2339 define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE 012212: line 2340 define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE 01224f: line 2341 define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE 01228e: line 2342 define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE 0122c3: line 2343 define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE 0122fa: line 2344 define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE 01233b: line 2345 define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE 01237e: line 2346 define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE 0123bd: line 2347 define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE 0123fe: line 2348 define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE 012431: line 2349 define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE 012466: line 2350 define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET 01249b: line 2351 define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET 0124d4: line 2352 define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE 012513: line 2353 define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE 012554: line 2354 define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE 012583: line 2355 define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE 0125b4: line 2356 define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET 0125e5: line 2357 define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET 01261a: line 2358 define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE 012655: line 2359 define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE 012692: line 2360 define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE 0126c3: line 2361 define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE 0126f6: line 2362 define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET 012729: line 2363 define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET 012760: line 2364 define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE 01279d: line 2365 define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE 0127dc: line 2366 define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE 01280d: line 2367 define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE 012840: line 2368 define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET 012873: line 2369 define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET 0128aa: line 2370 define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE 0128e7: line 2371 define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE 012926: line 2372 define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE 012957: line 2373 define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE 01298a: line 2374 define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET 0129c1: line 2375 define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE 0129fe: line 2376 define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE 012a3d: line 2377 define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE 012a6a: line 2378 define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE 012a99: line 2379 define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE 012ac8: line 2380 define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE 012af9: line 2381 define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET 012b2a: line 2382 define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET 012b5f: line 2383 define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE 012b9a: line 2384 define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE 012bd7: line 2385 define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE 012c08: line 2386 define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE 012c3b: line 2387 define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET 012c72: line 2388 define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET 012ca5: line 2389 define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE 012ce2: line 2390 define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE 012d21: line 2391 define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE 012d52: line 2392 define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE 012d85: line 2393 define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET 012db8: line 2394 define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET 012def: line 2395 define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE 012e2c: line 2396 define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE 012e6b: line 2397 define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE 012ead: line 2398 define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE 012ef1: line 2399 define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET 012f29: line 2400 define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET 012f65: line 2401 define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE 012fb0: line 2402 define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 012ffd: line 2403 define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE 013047: line 2404 define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE 013093: line 2405 define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED 0130e5: line 2406 define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED 013139: line 2407 define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET 013179: line 2408 define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET 0131bd: line 2409 define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE 013210: line 2410 define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 013265: line 2411 define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED 0132c0: line 2412 define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED 01331d: line 2413 define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET 01334e: line 2414 define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE 01338b: line 2415 define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE 0133c6: line 2416 define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE 013403: line 2417 define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE 01343c: line 2418 define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE 013477: line 2419 define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE 0134b2: line 2420 define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE 0134ef: line 2421 define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE 01352a: line 2422 define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE 013567: line 2423 define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET 013598: line 2424 define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET 0135cd: line 2425 define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE 013608: line 2426 define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE 013645: line 2427 define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET 013676: line 2428 define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET 0136ab: line 2429 define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE 0136e8: line 2430 define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE 013723: line 2431 define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE 013754: line 2432 define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE 013787: line 2433 define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET 0137ba: line 2434 define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET 0137f1: line 2435 define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE 01382e: line 2436 define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE 01386d: line 2439 define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET 0138ad: line 2440 define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET 0138f1: line 2442 define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE 013922: line 2443 define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE 013955: line 2444 define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE 013986: line 2445 define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE 0139b9: line 2446 define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE 0139ea: line 2447 define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE 013a1d: line 2448 define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE 013a4c: line 2449 define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE 013a7d: line 2450 define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE 013aae: line 2451 define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE 013ae1: line 2452 define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE 013b12: line 2453 define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE 013b45: line 2454 define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE 013b76: line 2455 define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE 013ba9: line 2456 define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE 013bdc: line 2457 define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE 013c11: line 2458 define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE 013c44: line 2459 define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE 013c77: line 2460 define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE 013caa: line 2461 define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE 013cdf: line 2462 define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE 013d14: line 2463 define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE 013d49: line 2465 define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET 013d7c: line 2466 define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET 013db3: line 2467 define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET 013de6: line 2468 define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET 013e1d: line 2469 define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET 013e50: line 2470 define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET 013e87: line 2471 define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET 013eb8: line 2472 define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET 013eed: line 2473 define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET 013f20: line 2474 define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET 013f57: line 2475 define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET 013f8a: line 2476 define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET 013fc1: line 2477 define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET 013ff4: line 2478 define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET 01402b: line 2479 define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET 014060: line 2480 define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET 014099: line 2481 define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET 0140ce: line 2482 define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET 014103: line 2483 define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET 014138: line 2484 define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET 014171: line 2485 define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET 0141aa: line 2486 define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET 0141e3: line 2488 define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED 01421a: line 2489 define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED 014253: line 2490 define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED 01428c: line 2491 define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED 0142c7: line 2492 define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED 014300: line 2493 define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED 01433b: line 2494 define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED 014370: line 2495 define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED 0143a7: line 2496 define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED 0143dc: line 2497 define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED 014413: line 2498 define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED 01444a: line 2499 define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED 014483: line 2500 define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED 0144ba: line 2501 define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED 0144f3: line 2502 define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED 01452a: line 2503 define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED 014563: line 2504 define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED 01459a: line 2505 define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED 0145d3: line 2506 define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED 01460c: line 2507 define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED 014647: line 2508 define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED 01467c: line 2509 define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED 0146b3: line 2510 define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED 0146ec: line 2511 define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED 014727: line 2512 define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED 014760: line 2513 define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED 01479b: line 2514 define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED 0147d4: line 2515 define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED 01480f: line 2516 define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED 014848: line 2517 define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED 014883: line 2518 define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED 0148bc: line 2519 define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED 0148f7: line 2520 define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED 014930: line 2521 define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED 01496b: line 2522 define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED 0149a4: line 2523 define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED 0149df: line 2524 define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED 014a18: line 2525 define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED 014a53: line 2526 define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED 014a8e: line 2527 define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED 014acb: line 2528 define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED 014b02: line 2529 define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED 014b3b: line 2530 define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED 014b72: line 2531 define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED 014bab: line 2532 define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED 014be2: line 2533 define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED 014c1b: line 2534 define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED 014c50: line 2535 define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED 014c87: line 2536 define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED 014cc2: line 2537 define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED 014cff: line 2538 define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED 014d36: line 2539 define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED 014d6f: line 2540 define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED 014da6: line 2541 define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED 014ddf: line 2542 define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED 014e16: line 2543 define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED 014e4f: line 2544 define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED 014e86: line 2545 define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED 014ebf: line 2546 define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED 014efa: line 2547 define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED 014f37: line 2548 define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED 014f72: line 2549 define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED 014faf: line 2550 define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED 014fea: line 2551 define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED 015027: line 2552 define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED 01505e: line 2553 define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED 015097: line 2554 define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED 0150ce: line 2555 define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED 015107: line 2556 define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED 01513e: line 2557 define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED 015177: line 2558 define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED 0151ae: line 2559 define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED 0151e7: line 2560 define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED 01521e: line 2561 define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED 015257: line 2562 define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED 01528e: line 2563 define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED 0152c7: line 2564 define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED 0152fe: line 2565 define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED 015337: line 2566 define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED 01536e: line 2567 define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED 0153a7: line 2568 define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED 0153de: line 2569 define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED 015417: line 2570 define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED 015450: line 2571 define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED 01548b: line 2572 define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED 0154c4: line 2573 define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED 0154ff: line 2574 define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED 015538: line 2575 define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED 015573: line 2576 define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED 0155ac: line 2577 define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED 0155e7: line 2578 define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED 015620: line 2579 define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED 01565b: line 2580 define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED 015694: line 2581 define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED 0156cf: line 2582 define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED 015708: line 2583 define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED 015743: line 2584 define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED 01577c: line 2585 define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED 0157b7: line 2586 define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED 0157f0: line 2587 define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED 01582b: line 2588 define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED 015860: line 2589 define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED 015897: line 2590 define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED 0158d0: line 2591 define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED 01590b: line 2592 define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED 015944: line 2593 define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED 01597f: line 2594 define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED 0159ba: line 2595 define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED 0159f7: line 2596 define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED 015a32: line 2597 define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED 015a6f: line 2598 define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED 015aaa: line 2599 define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED 015ae7: line 2600 define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED 015b1c: line 2601 define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED 015b53: line 2602 define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED 015b8a: line 2603 define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED 015bc3: line 2623 define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET 015bfe: line 2624 define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET 015c3d: line 2625 define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE 015c82: line 2626 define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE 015cc9: line 2627 define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE 015d02: line 2628 define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE 015d3d: line 2629 define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED 015d7e: line 2630 define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED 015dc1: line 2631 define SdioClockSelection Sdmmc1ClockSelection 015dec: line 2632 define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 015e17: line 2633 define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG 015e48: line 2634 define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE 015e81: line 2638 define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 015eb6: line 2639 define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK 015eed: line 2642 define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG 015f16: line 2643 define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG 015f46: line 2645 define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE 015f6c: line 2647 define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE 015f96: line 2648 define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE 015fc2: line 2649 define IS_RCC_SYSCLK_DIV IS_RCC_HCLK 015fe3: line 2650 define IS_RCC_HCLK_DIV IS_RCC_PCLK 016002: line 2651 define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK 016029: line 2653 define RCC_IT_HSI14 RCC_IT_HSI14RDY 016049: line 2655 define RCC_IT_CSSLSE RCC_IT_LSECSS 016068: line 2656 define RCC_IT_CSSHSE RCC_IT_CSS 016084: line 2658 define RCC_PLLMUL_3 RCC_PLL_MUL3 0160a1: line 2659 define RCC_PLLMUL_4 RCC_PLL_MUL4 0160be: line 2660 define RCC_PLLMUL_6 RCC_PLL_MUL6 0160db: line 2661 define RCC_PLLMUL_8 RCC_PLL_MUL8 0160f8: line 2662 define RCC_PLLMUL_12 RCC_PLL_MUL12 016117: line 2663 define RCC_PLLMUL_16 RCC_PLL_MUL16 016136: line 2664 define RCC_PLLMUL_24 RCC_PLL_MUL24 016155: line 2665 define RCC_PLLMUL_32 RCC_PLL_MUL32 016174: line 2666 define RCC_PLLMUL_48 RCC_PLL_MUL48 016193: line 2668 define RCC_PLLDIV_2 RCC_PLL_DIV2 0161b0: line 2669 define RCC_PLLDIV_3 RCC_PLL_DIV3 0161cd: line 2670 define RCC_PLLDIV_4 RCC_PLL_DIV4 0161ea: line 2672 define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE 016210: line 2673 define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG 01623e: line 2674 define RCC_MCO_NODIV RCC_MCODIV_1 01625c: line 2675 define RCC_MCO_DIV1 RCC_MCODIV_1 016279: line 2676 define RCC_MCO_DIV2 RCC_MCODIV_2 016296: line 2677 define RCC_MCO_DIV4 RCC_MCODIV_4 0162b3: line 2678 define RCC_MCO_DIV8 RCC_MCODIV_8 0162d0: line 2679 define RCC_MCO_DIV16 RCC_MCODIV_16 0162ef: line 2680 define RCC_MCO_DIV32 RCC_MCODIV_32 01630e: line 2681 define RCC_MCO_DIV64 RCC_MCODIV_64 01632d: line 2682 define RCC_MCO_DIV128 RCC_MCODIV_128 01634e: line 2683 define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK 01637b: line 2684 define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI 0163a3: line 2685 define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE 0163cb: line 2686 define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK 0163f9: line 2687 define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI 016421: line 2688 define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 01644d: line 2689 define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 016479: line 2690 define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE 0164a1: line 2691 define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK 0164d4: line 2692 define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK 016508: line 2693 define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 016540: line 2695 define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK 016571: line 2697 define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 0165a0: line 2698 define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL 0165c7: line 2699 define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI 0165ee: line 2700 define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL 01661e: line 2701 define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL 016649: line 2702 define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 01667d: line 2703 define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 0166ad: line 2704 define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 0166dd: line 2706 define HSION_BitNumber RCC_HSION_BIT_NUMBER 016705: line 2707 define HSION_BITNUMBER RCC_HSION_BIT_NUMBER 01672d: line 2708 define HSEON_BitNumber RCC_HSEON_BIT_NUMBER 016755: line 2709 define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER 01677d: line 2710 define MSION_BITNUMBER RCC_MSION_BIT_NUMBER 0167a5: line 2711 define CSSON_BitNumber RCC_CSSON_BIT_NUMBER 0167cd: line 2712 define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER 0167f5: line 2713 define PLLON_BitNumber RCC_PLLON_BIT_NUMBER 01681d: line 2714 define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER 016845: line 2715 define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER 016873: line 2716 define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER 01689d: line 2717 define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER 0168c5: line 2718 define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER 0168ed: line 2719 define BDRST_BitNumber RCC_BDRST_BIT_NUMBER 016915: line 2720 define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER 01693d: line 2721 define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER 016967: line 2722 define LSION_BitNumber RCC_LSION_BIT_NUMBER 01698f: line 2723 define LSION_BITNUMBER RCC_LSION_BIT_NUMBER 0169b7: line 2724 define LSEON_BitNumber RCC_LSEON_BIT_NUMBER 0169df: line 2725 define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER 016a07: line 2726 define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER 016a31: line 2727 define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER 016a5f: line 2728 define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER 016a89: line 2729 define RMVF_BitNumber RCC_RMVF_BIT_NUMBER 016aaf: line 2730 define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER 016ad5: line 2731 define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER 016b0d: line 2732 define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS 016b36: line 2733 define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS 016b61: line 2734 define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS 016b8c: line 2735 define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS 016bb9: line 2736 define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE 016be4: line 2737 define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE 016c0f: line 2739 define CR_HSION_BB RCC_CR_HSION_BB 016c2e: line 2740 define CR_CSSON_BB RCC_CR_CSSON_BB 016c4d: line 2741 define CR_PLLON_BB RCC_CR_PLLON_BB 016c6c: line 2742 define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB 016c91: line 2743 define CR_MSION_BB RCC_CR_MSION_BB 016cb0: line 2744 define CSR_LSION_BB RCC_CSR_LSION_BB 016cd1: line 2745 define CSR_LSEON_BB RCC_CSR_LSEON_BB 016cf2: line 2746 define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB 016d15: line 2747 define CSR_RTCEN_BB RCC_CSR_RTCEN_BB 016d36: line 2748 define CSR_RTCRST_BB RCC_CSR_RTCRST_BB 016d59: line 2749 define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB 016d7e: line 2750 define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB 016da1: line 2751 define BDCR_BDRST_BB RCC_BDCR_BDRST_BB 016dc4: line 2752 define CR_HSEON_BB RCC_CR_HSEON_BB 016de3: line 2753 define CSR_RMVF_BB RCC_CSR_RMVF_BB 016e02: line 2754 define CR_PLLSAION_BB RCC_CR_PLLSAION_BB 016e27: line 2755 define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB 016e52: line 2757 define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE 016ea5: line 2758 define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE 016efa: line 2759 define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE 016f47: line 2760 define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE 016f96: line 2761 define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE 016fe1: line 2763 define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT 01700d: line 2765 define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN 017032: line 2766 define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF 017054: line 2768 define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 01707e: line 2769 define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ 0170b0: line 2770 define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP 0170e8: line 2771 define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ 017120: line 2772 define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE 01714e: line 2773 define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 017180: line 2775 define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE 0171ba: line 2776 define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE 0171f6: line 2777 define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED 017238: line 2778 define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED 01727c: line 2779 define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET 0172b8: line 2780 define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET 0172f8: line 2781 define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE 01733e: line 2782 define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE 017386: line 2783 define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED 0173d4: line 2784 define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED 017424: line 2785 define DfsdmClockSelection Dfsdm1ClockSelection 017450: line 2786 define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 01747c: line 2787 define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK 0174b0: line 2788 define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK 0174e8: line 2789 define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG 01751a: line 2790 define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE 017554: line 2799 define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) 0175b7: line 2809 define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG 0175e9: line 2810 define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT 01761b: line 2811 define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT 01764b: line 2824 define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) 01775e: line 2827 define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) 01786d: line 2830 define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) 017980: line 2833 define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) 017a8b: line 2836 define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) 017baa: line 2841 define IS_ALARM IS_RTC_ALARM 017bc3: line 2842 define IS_ALARM_MASK IS_RTC_ALARM_MASK 017be6: line 2843 define IS_TAMPER IS_RTC_TAMPER 017c01: line 2844 define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE 017c32: line 2845 define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER 017c5b: line 2846 define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT 017c8a: line 2847 define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE 017cc3: line 2848 define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION 017d04: line 2849 define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE 017d39: line 2850 define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ 017d70: line 2851 define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION 017dc3: line 2852 define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER 017dee: line 2853 define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK 017e15: line 2854 define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER 017e40: line 2856 define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE 017e81: line 2857 define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE 017ec4: line 2867 define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE 017efa: line 2868 define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS 017f26: line 2897 define SD_SDIO_DISABLED SD_SDMMC_DISABLED 017f4c: line 2898 define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY 017f7c: line 2899 define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED 017fb0: line 2900 define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION 017fe6: line 2901 define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND 01801a: line 2902 define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT 01804a: line 2903 define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED 01807e: line 2904 define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE 0180ac: line 2905 define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE 0180dc: line 2906 define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE 018112: line 2907 define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE 018149: line 2908 define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT 01817d: line 2909 define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT 0181b3: line 2910 define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG 0181e5: line 2911 define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG 01821b: line 2912 define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT 018249: line 2913 define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT 01827b: line 2914 define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS 0182a3: line 2915 define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT 0182c9: line 2916 define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND 0182f7: line 2918 define SDIO_IRQn SDMMC1_IRQn 018310: line 2919 define SDIO_IRQHandler SDMMC1_IRQHandler 018335: line 2929 define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT 018368: line 2930 define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT 01839d: line 2931 define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE 0183ca: line 2932 define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE 0183f9: line 2933 define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE 01843e: line 2934 define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE 018485: line 2936 define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE 0184c0: line 2937 define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE 0184f7: line 2939 define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE 018533: line 2948 define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 01855c: line 2949 define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 018585: line 2950 define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START 0185b8: line 2951 define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH 0185eb: line 2952 define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR 018610: line 2953 define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE 018641: line 2954 define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE 018670: line 2955 define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED 0186a9: line 2964 define __HAL_SPI_1LINE_TX SPI_1LINE_TX 0186cc: line 2965 define __HAL_SPI_1LINE_RX SPI_1LINE_RX 0186ef: line 2966 define __HAL_SPI_RESET_CRC SPI_RESET_CRC 018714: line 2976 define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE 018745: line 2977 define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION 01877a: line 2978 define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE 0187a7: line 2979 define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION 0187d8: line 2981 define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD 018806: line 2983 define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE 018836: line 2984 define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE 018868: line 2995 define __USART_ENABLE_IT __HAL_USART_ENABLE_IT 018893: line 2996 define __USART_DISABLE_IT __HAL_USART_DISABLE_IT 0188c0: line 2997 define __USART_ENABLE __HAL_USART_ENABLE 0188e5: line 2998 define __USART_DISABLE __HAL_USART_DISABLE 01890c: line 3000 define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE 01893f: line 3001 define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE 01896e: line 3010 define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE 01899b: line 3012 define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0189e1: line 3013 define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 018a29: line 3014 define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 018a75: line 3015 define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE 018aac: line 3017 define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 018af2: line 3018 define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 018b3a: line 3019 define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 018b86: line 3020 define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE 018bbd: line 3022 define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT 018bf9: line 3023 define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT 018c37: line 3024 define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG 018c71: line 3025 define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG 018caf: line 3026 define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE 018d02: line 3027 define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE 018d57: line 3028 define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 018db4: line 3030 define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT 018dfa: line 3031 define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT 018e42: line 3032 define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG 018e86: line 3033 define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG 018ece: line 3034 define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE 018f2b: line 3035 define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE 018f8a: line 3036 define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 018ff1: line 3037 define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT 01903f: line 3039 define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT 019085: line 3040 define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT 0190cd: line 3041 define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG 019111: line 3042 define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG 019159: line 3043 define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE 0191b6: line 3044 define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE 019215: line 3045 define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 01927c: line 3046 define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT 0192ca: line 3048 define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup 019305: line 3049 define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup 019344: line 3051 define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo 01936d: line 3052 define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo 019396: line 3060 define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE 0193d0: line 3061 define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE 01940e: line 3063 define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE 01943a: line 3064 define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT 019461: line 3066 define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE 019493: line 3068 define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN 0194d0: line 3069 define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER 0194ff: line 3070 define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER 01952d: line 3071 define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER 01955b: line 3072 define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD 01958f: line 3073 define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD 0195c3: line 3074 define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION 0195fd: line 3075 define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION 019637: line 3076 define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER 01966d: line 3077 define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER 0196a3: line 3078 define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE 0196d1: line 3079 define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE 0196ff: line 3081 define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 019739: line 3090 define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT 019775: line 3091 define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT 0197b3: line 3092 define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG 0197ed: line 3093 define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG 01982b: line 3094 define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER 019886: line 3095 define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER 0198e3: line 3096 define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER 019942: line 3098 define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE 01997c: line 3099 define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE 0199b8: line 3100 define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE 0199eb: line 3108 define __HAL_LTDC_LAYER LTDC_LAYER 019a0a: line 3116 define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE 019a3e: line 3117 define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE 019a70: line 3118 define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE 019aa6: line 3119 define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE 019ade: line 3120 define SAI_STREOMODE SAI_STEREOMODE 019afe: line 3121 define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY 019b2b: line 3122 define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL 019b6e: line 3123 define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL 019ba9: line 3124 define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL 019bdc: line 3125 define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL 019c18: line 3126 define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL 019c43: line 3127 define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE 019c81: line 3128 define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 019cb1: line 3129 define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE 019ce7: end include 019ce8: end of translation unit ** Section #64 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 104 bytes 000000: Header: length 100 (not including this field) version 3 prologue length 90 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "Legacy/stm32_hal_legacy.h": dir 1 time 0x0 length 0: 4c 65 67 61 63 79 2f 73 74 6d 33 32 5f 68 61 6c 5f 6c 65 67 61 63 79 2e 68 00 01 00 00 000063: file "" : 00 000064: DW_LNS_negate_stmt : 06 000065: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\Legacy/stm32_hal_legacy.h:1.0 [ ** Section #65 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 284 bytes 000000: Header: size 0x118 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\Legacy/stm32_hal_legacy.h 00004f: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000096: DW_AT_language DW_LANG_C89 000098: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010f: DW_AT_macro_info 0x0 000113: DW_AT_stmt_list 0x0 000117: 0 null 000118: 0 padding 000119: 0 padding 00011a: 0 padding 00011b: 0 padding ** Section #370 '.rel.debug_info' (SHT_REL) Size : 24 bytes (alignment 4) Symbol table #343 '.symtab' 3 relocations applied to section #65 '.debug_info' ** Section #66 '__ARM_grp.stdio.h.2_It1000_FCx4$7ABOZc_700000' (SHT_GROUP) Size : 20 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #67 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 584 bytes 000000: include at line 0 - file 1 000003: line 19 define __stdio_h 000010: line 20 define __ARMCLIB_VERSION 5060016 00002c: line 34 define _ARMABI __declspec(__nothrow) 00004c: line 37 define __STDIO_DECLS 00005d: line 39 undef __CLIBNS 000068: line 45 define __CLIBNS 000074: line 60 undef NULL 00007b: line 61 define NULL 0 000084: line 103 define _SYS_OPEN 16 000093: line 165 define stdin (&__CLIBNS __stdin) 0000b0: line 167 define stdout (&__CLIBNS __stdout) 0000cf: line 169 define stderr (&__CLIBNS __stderr) 0000ee: line 172 define _IOFBF 0x100 0000fe: line 173 define _IOLBF 0x200 00010e: line 174 define _IONBF 0x400 00011e: line 177 define BUFSIZ (512) 00012e: line 179 define FOPEN_MAX _SYS_OPEN 000145: line 185 define FILENAME_MAX 256 000159: line 190 define L_tmpnam FILENAME_MAX 000172: line 196 define TMP_MAX 256 000181: line 204 define EOF (-1) 00018d: line 210 define SEEK_SET 0 00019b: line 211 define SEEK_CUR 1 0001a9: line 212 define SEEK_END 2 0001b7: line 218 define _IOBIN 0x04 0001c6: line 220 define __STDIN_BUFSIZ (64) 0001dd: line 221 define __STDOUT_BUFSIZ (64) 0001f5: line 222 define __STDERR_BUFSIZ (16) 00020d: line 703 define getchar() getc(stdin) 000226: line 736 define putchar(c) putc(c, stdout) 000244: end include 000245: end of translation unit ** Section #68 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 100 bytes 000000: Header: length 96 (not including this field) version 3 prologue length 87 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "D:\Program Files (x86)\Keil_v5\ARM\ARMCC\Bin\..\include\": 44 3a 5c 50 72 6f 67 72 61 6d 20 46 69 6c 65 73 20 28 78 38 36 29 5c 4b 65 69 6c 5f 76 35 5c 41 52 4d 5c 41 52 4d 43 43 5c 42 69 6e 5c 2e 2e 5c 69 6e 63 6c 75 64 65 5c 00 000054: directory "" : 00 000055: file "stdio.h": dir 1 time 0x0 length 0: 73 74 64 69 6f 2e 68 00 01 00 00 000060: file "" : 00 000061: DW_LNE_end sequence : 00 01 01 00000000: D:\Program Files (x86)\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h:1.0 ** Section #69 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 472 bytes 000000: Header: size 0x1d4 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 16 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name D:\Program Files (x86)\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h 00004c: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000093: DW_AT_language DW_LANG_C89 000095: DW_AT_macro_info 0x0 000099: DW_AT_stmt_list 0x0 00009d: 4 = 0x24 (DW_TAG_base_type) 00009e: DW_AT_byte_size 0x4 00009f: DW_AT_encoding DW_ATE_unsigned 0000a0: DW_AT_name unsigned int 0000ad: 4 = 0x24 (DW_TAG_base_type) 0000ae: DW_AT_byte_size 0x8 0000af: DW_AT_encoding DW_ATE_unsigned 0000b0: DW_AT_name unsigned long long 0000c3: 80 = 0x16 (DW_TAG_typedef) 0000c4: DW_AT_name size_t 0000cb: DW_AT_type indirect DW_FORM_ref2 0x9d 0000ce: DW_AT_decl_file 0x1 0000cf: DW_AT_decl_line 0x35 0000d0: DW_AT_decl_column 0x1a 0000d1: 45 = 0x13 (DW_TAG_structure_type) 0000d2: DW_AT_name __va_list 0000dc: 80 = 0x16 (DW_TAG_typedef) 0000dd: DW_AT_name __va_list 0000e7: DW_AT_type indirect DW_FORM_ref2 0xd1 0000ea: DW_AT_decl_file 0x1 0000eb: DW_AT_decl_line 0x46 0000ec: DW_AT_decl_column 0x1e 0000ed: 42 = 0x13 (DW_TAG_structure_type) 0000ee: DW_AT_sibling 0x112 0000f0: DW_AT_byte_size 0x8 0000f1: 30 = 0xd (DW_TAG_member) 0000f2: DW_AT_name __state1 0000fb: DW_AT_type indirect DW_FORM_ref2 0x9d 0000fe: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000101: 30 = 0xd (DW_TAG_member) 000102: DW_AT_name __state2 00010b: DW_AT_type indirect DW_FORM_ref2 0x9d 00010e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000111: 0 null 000112: 41 = 0x13 (DW_TAG_structure_type) 000113: DW_AT_sibling 0x145 000115: DW_AT_name __fpos_t_struct 000125: DW_AT_byte_size 0x10 000126: 30 = 0xd (DW_TAG_member) 000127: DW_AT_name __pos 00012d: DW_AT_type indirect DW_FORM_ref2 0xad 000130: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000133: 30 = 0xd (DW_TAG_member) 000134: DW_AT_name __mbstate 00013e: DW_AT_type indirect DW_FORM_ref2 0xed 000141: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000144: 0 null 000145: 80 = 0x16 (DW_TAG_typedef) 000146: DW_AT_name fpos_t 00014d: DW_AT_type indirect DW_FORM_ref2 0x112 000150: DW_AT_decl_file 0x1 000151: DW_AT_decl_line 0x61 000152: DW_AT_decl_column 0x3 000153: 45 = 0x13 (DW_TAG_structure_type) 000154: DW_AT_name __FILE 00015b: 80 = 0x16 (DW_TAG_typedef) 00015c: DW_AT_name FILE 000161: DW_AT_type indirect DW_FORM_ref2 0x153 000164: DW_AT_decl_file 0x1 000165: DW_AT_decl_line 0x6c 000166: DW_AT_decl_column 0x17 000167: 113 = 0x34 (DW_TAG_variable) 000168: DW_AT_name __stdin 000170: DW_AT_type indirect DW_FORM_ref2 0x15b 000173: DW_AT_external 0x1 000174: DW_AT_declaration 0x1 000175: 113 = 0x34 (DW_TAG_variable) 000176: DW_AT_name __stdout 00017f: DW_AT_type indirect DW_FORM_ref2 0x15b 000182: DW_AT_external 0x1 000183: DW_AT_declaration 0x1 000184: 113 = 0x34 (DW_TAG_variable) 000185: DW_AT_name __stderr 00018e: DW_AT_type indirect DW_FORM_ref2 0x15b 000191: DW_AT_external 0x1 000192: DW_AT_declaration 0x1 000193: 34 = 0xf (DW_TAG_pointer_type) 000194: DW_AT_type indirect DW_FORM_ref2 0x15b 000197: 113 = 0x34 (DW_TAG_variable) 000198: DW_AT_name __aeabi_stdin 0001a6: DW_AT_type indirect DW_FORM_ref2 0x193 0001a9: DW_AT_external 0x1 0001aa: DW_AT_declaration 0x1 0001ab: 113 = 0x34 (DW_TAG_variable) 0001ac: DW_AT_name __aeabi_stdout 0001bb: DW_AT_type indirect DW_FORM_ref2 0x193 0001be: DW_AT_external 0x1 0001bf: DW_AT_declaration 0x1 0001c0: 113 = 0x34 (DW_TAG_variable) 0001c1: DW_AT_name __aeabi_stderr 0001d0: DW_AT_type indirect DW_FORM_ref2 0x193 0001d3: DW_AT_external 0x1 0001d4: DW_AT_declaration 0x1 0001d5: 0 null 0001d6: 0 padding 0001d7: 0 padding ** Section #371 '.rel.debug_info' (SHT_REL) Size : 24 bytes (alignment 4) Symbol table #343 '.symtab' 3 relocations applied to section #69 '.debug_info' ** Section #70 '.debug_pubnames' (SHT_PROGBITS) [SHF_GROUP] Size : 112 bytes 0x00000000: Compilation unit (112 bytes) vsn 2: 0x00000006: reference to offset __ARM_grp..debug_info$stdio.h$.2_It1000_FCx4$7ABOZc_700000 0x0000000a: 472 bytes generated for unit 0x0000000e: Offset 0x167 (0x167) 0x00000012: 5f 5f 73 74 64 69 6e 00 __stdin 0x0000001a: Offset 0x175 (0x175) 0x0000001e: 5f 5f 73 74 64 6f 75 74 00 __stdout 0x00000027: Offset 0x184 (0x184) 0x0000002b: 5f 5f 73 74 64 65 72 72 00 __stderr 0x00000034: Offset 0x197 (0x197) 0x00000038: 5f 5f 61 65 61 62 69 5f 73 74 64 69 __aeabi_stdi 0x00000044: 6e 00 n 0x00000046: Offset 0x1ab (0x1ab) 0x0000004a: 5f 5f 61 65 61 62 69 5f 73 74 64 6f __aeabi_stdo 0x00000056: 75 74 00 ut 0x00000059: Offset 0x1c0 (0x1c0) 0x0000005d: 5f 5f 61 65 61 62 69 5f 73 74 64 65 __aeabi_stde 0x00000069: 72 72 00 rr 0x0000006c: End of list for compilation unit (zero offset) ** Section #372 '.rel.debug_pubnames' (SHT_REL) Size : 8 bytes (alignment 4) Symbol table #343 '.symtab' 1 relocations applied to section #70 '.debug_pubnames' ** Section #71 '__ARM_grp.stm32f7xx_hal_def.h.2_kZ0000_qdUHTrAfbN8_300000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #72 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 772 bytes 000000: include at line 0 - file 1 000003: line 41 define __STM32F7xx_HAL_DEF 00001a: include at line 48 - file 2 00001d: end include 00001e: include at line 49 - file 3 000021: end include 000022: include at line 50 - file 4 000025: end include 000026: line 74 define HAL_MAX_DELAY 0xFFFFFFFFU 000042: line 76 define HAL_IS_BIT_SET(REG,BIT) (((REG) & (BIT)) != RESET) 000077: line 77 define HAL_IS_BIT_CLR(REG,BIT) (((REG) & (BIT)) == RESET) 0000ac: line 79 define __HAL_LINKDMA(__HANDLE__,__PPP_DMA_FIELD__,__DMA_HANDLE__) do{ (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); (__DMA_HANDLE__).Parent = (__HANDLE__); } while(0) 000155: line 85 define UNUSED(x) ((void)(x)) 00016d: line 102 define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) 0001af: line 108 define __HAL_LOCK(__HANDLE__) do{ if((__HANDLE__)->Lock == HAL_LOCKED) { return HAL_BUSY; } else { (__HANDLE__)->Lock = HAL_LOCKED; } }while (0) 00023b: line 120 define __HAL_UNLOCK(__HANDLE__) do{ (__HANDLE__)->Lock = HAL_UNLOCKED; }while (0) 000288: line 146 define __ALIGN_END 000298: line 150 define __ALIGN_BEGIN __align(4) 0002b4: line 171 define __RAM_FUNC HAL_StatusTypeDef 0002d4: line 197 define __NOINLINE __attribute__ ( (noinline) ) 0002ff: end include 000300: end of translation unit ** Section #73 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 260 bytes 000000: Header: length 256 (not including this field) version 3 prologue length 247 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "..\..\Libraries\CMSIS\Device\ST\STM32F7xx\Include\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 43 4d 53 49 53 5c 44 65 76 69 63 65 5c 53 54 5c 53 54 4d 33 32 46 37 78 78 5c 49 6e 63 6c 75 64 65 5c 00 000078: directory "D:\Program Files (x86)\Keil_v5\ARM\ARMCC\Bin\..\include\": 44 3a 5c 50 72 6f 67 72 61 6d 20 46 69 6c 65 73 20 28 78 38 36 29 5c 4b 65 69 6c 5f 76 35 5c 41 52 4d 5c 41 52 4d 43 43 5c 42 69 6e 5c 2e 2e 5c 69 6e 63 6c 75 64 65 5c 00 0000b1: directory "" : 00 0000b2: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 0000c9: file "stm32f7xx.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 2e 68 00 02 00 00 0000d8: file "Legacy/stm32_hal_legacy.h": dir 1 time 0x0 length 0: 4c 65 67 61 63 79 2f 73 74 6d 33 32 5f 68 61 6c 5f 6c 65 67 61 63 79 2e 68 00 01 00 00 0000f5: file "stdio.h": dir 3 time 0x0 length 0: 73 74 64 69 6f 2e 68 00 03 00 00 000100: file "" : 00 000101: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_def.h:1.0 ** Section #74 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 416 bytes 000000: Header: size 0x19c bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_def.h 000049: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000090: DW_AT_language DW_LANG_C89 000092: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 000109: DW_AT_macro_info 0x0 00010d: DW_AT_stmt_list 0x0 000111: 19 = 0x4 (DW_TAG_enumeration_type) 000112: DW_AT_sibling 0x148 000114: DW_AT_byte_size 0x1 000115: 20 = 0x28 (DW_TAG_enumerator) 000116: DW_AT_name HAL_OK 00011d: DW_AT_const_value indirect DW_FORM_data1 0x0 00011f: 20 = 0x28 (DW_TAG_enumerator) 000120: DW_AT_name HAL_ERROR 00012a: DW_AT_const_value indirect DW_FORM_data1 0x1 00012c: 20 = 0x28 (DW_TAG_enumerator) 00012d: DW_AT_name HAL_BUSY 000136: DW_AT_const_value indirect DW_FORM_data1 0x2 000138: 20 = 0x28 (DW_TAG_enumerator) 000139: DW_AT_name HAL_TIMEOUT 000145: DW_AT_const_value indirect DW_FORM_data1 0x3 000147: 0 null 000148: 80 = 0x16 (DW_TAG_typedef) 000149: DW_AT_name HAL_StatusTypeDef 00015b: DW_AT_type indirect DW_FORM_ref2 0x111 00015e: DW_AT_decl_file 0x1 00015f: DW_AT_decl_line 0x3e 000160: DW_AT_decl_column 0x3 000161: 19 = 0x4 (DW_TAG_enumeration_type) 000162: DW_AT_sibling 0x184 000164: DW_AT_byte_size 0x1 000165: 20 = 0x28 (DW_TAG_enumerator) 000166: DW_AT_name HAL_UNLOCKED 000173: DW_AT_const_value indirect DW_FORM_data1 0x0 000175: 20 = 0x28 (DW_TAG_enumerator) 000176: DW_AT_name HAL_LOCKED 000181: DW_AT_const_value indirect DW_FORM_data1 0x1 000183: 0 null 000184: 80 = 0x16 (DW_TAG_typedef) 000185: DW_AT_name HAL_LockTypeDef 000195: DW_AT_type indirect DW_FORM_ref2 0x161 000198: DW_AT_decl_file 0x1 000199: DW_AT_decl_line 0x47 00019a: DW_AT_decl_column 0x3 00019b: 0 null 00019c: 0 padding 00019d: 0 padding 00019e: 0 padding 00019f: 0 padding ** Section #373 '.rel.debug_info' (SHT_REL) Size : 24 bytes (alignment 4) Symbol table #343 '.symtab' 3 relocations applied to section #74 '.debug_info' ** Section #75 '__ARM_grp.stm32f7xx_hal_rcc_ex.h.2_YWK000_XnipifzSIRa_N00000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #76 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 92956 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_RCC_EX_H 00001f: include at line 47 - file 2 000022: end include 000023: line 252 define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U) 000050: line 254 define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008U) 00007e: line 256 define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U) 0000ab: line 257 define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U) 0000d8: line 258 define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040U) 000108: line 259 define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080U) 000138: line 260 define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100U) 000168: line 261 define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200U) 000197: line 262 define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400U) 0001c6: line 263 define RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800U) 0001f6: line 264 define RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000U) 000225: line 265 define RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000U) 000254: line 266 define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000U) 000282: line 267 define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000U) 0002b0: line 268 define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000U) 0002de: line 269 define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000U) 00030c: line 270 define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000U) 00033c: line 271 define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000U) 00036a: line 272 define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000U) 000398: line 273 define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000U) 0003c7: line 274 define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000U) 0003f4: line 275 define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000U) 000424: line 276 define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000U) 000455: line 277 define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000U) 000485: line 279 define RCC_PERIPHCLK_SDMMC2 ((uint32_t)0x04000000U) 0004b5: line 280 define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x08000000U) 0004e5: line 281 define RCC_PERIPHCLK_DFSDM1_AUDIO ((uint32_t)0x10000000U) 00051b: line 293 define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000000U) 000547: line 294 define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000001U) 000573: line 295 define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000002U) 00059f: line 296 define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000003U) 0005cb: line 305 define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000U) 0005f7: line 306 define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001U) 000623: line 307 define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002U) 00064f: line 308 define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003U) 00067b: line 316 define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000U) 0006a7: line 317 define RCC_PLLSAIDIVR_4 RCC_DCKCFGR1_PLLSAIDIVR_0 0006d5: line 318 define RCC_PLLSAIDIVR_8 RCC_DCKCFGR1_PLLSAIDIVR_1 000703: line 319 define RCC_PLLSAIDIVR_16 RCC_DCKCFGR1_PLLSAIDIVR 000730: line 327 define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000U) 000763: line 328 define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC 00078b: line 338 define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000U) 0007bf: line 339 define RCC_SAI1CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI1SEL_0 0007f2: line 340 define RCC_SAI1CLKSOURCE_PIN RCC_DCKCFGR1_SAI1SEL_1 000822: line 342 define RCC_SAI1CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI1SEL 000853: line 351 define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000U) 000887: line 352 define RCC_SAI2CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI2SEL_0 0008ba: line 353 define RCC_SAI2CLKSOURCE_PIN RCC_DCKCFGR1_SAI2SEL_1 0008ea: line 355 define RCC_SAI2CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI2SEL 00091b: line 364 define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000U) 00094b: line 365 define RCC_CECCLKSOURCE_HSI RCC_DCKCFGR2_CECSEL 000977: line 373 define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) 0009ac: line 374 define RCC_USART1CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART1SEL_0 0009e3: line 375 define RCC_USART1CLKSOURCE_HSI RCC_DCKCFGR2_USART1SEL_1 000a17: line 376 define RCC_USART1CLKSOURCE_LSE RCC_DCKCFGR2_USART1SEL 000a49: line 384 define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 000a7e: line 385 define RCC_USART2CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART2SEL_0 000ab5: line 386 define RCC_USART2CLKSOURCE_HSI RCC_DCKCFGR2_USART2SEL_1 000ae9: line 387 define RCC_USART2CLKSOURCE_LSE RCC_DCKCFGR2_USART2SEL 000b1b: line 395 define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 000b50: line 396 define RCC_USART3CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART3SEL_0 000b87: line 397 define RCC_USART3CLKSOURCE_HSI RCC_DCKCFGR2_USART3SEL_1 000bbb: line 398 define RCC_USART3CLKSOURCE_LSE RCC_DCKCFGR2_USART3SEL 000bed: line 406 define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 000c21: line 407 define RCC_UART4CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART4SEL_0 000c56: line 408 define RCC_UART4CLKSOURCE_HSI RCC_DCKCFGR2_UART4SEL_1 000c88: line 409 define RCC_UART4CLKSOURCE_LSE RCC_DCKCFGR2_UART4SEL 000cb8: line 417 define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 000cec: line 418 define RCC_UART5CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART5SEL_0 000d21: line 419 define RCC_UART5CLKSOURCE_HSI RCC_DCKCFGR2_UART5SEL_1 000d53: line 420 define RCC_UART5CLKSOURCE_LSE RCC_DCKCFGR2_UART5SEL 000d83: line 428 define RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) 000db8: line 429 define RCC_USART6CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART6SEL_0 000def: line 430 define RCC_USART6CLKSOURCE_HSI RCC_DCKCFGR2_USART6SEL_1 000e23: line 431 define RCC_USART6CLKSOURCE_LSE RCC_DCKCFGR2_USART6SEL 000e55: line 439 define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 000e89: line 440 define RCC_UART7CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART7SEL_0 000ebe: line 441 define RCC_UART7CLKSOURCE_HSI RCC_DCKCFGR2_UART7SEL_1 000ef0: line 442 define RCC_UART7CLKSOURCE_LSE RCC_DCKCFGR2_UART7SEL 000f20: line 450 define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 000f54: line 451 define RCC_UART8CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART8SEL_0 000f89: line 452 define RCC_UART8CLKSOURCE_HSI RCC_DCKCFGR2_UART8SEL_1 000fbb: line 453 define RCC_UART8CLKSOURCE_LSE RCC_DCKCFGR2_UART8SEL 000feb: line 461 define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 00101e: line 462 define RCC_I2C1CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C1SEL_0 001051: line 463 define RCC_I2C1CLKSOURCE_HSI RCC_DCKCFGR2_I2C1SEL_1 001081: line 471 define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 0010b4: line 472 define RCC_I2C2CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C2SEL_0 0010e7: line 473 define RCC_I2C2CLKSOURCE_HSI RCC_DCKCFGR2_I2C2SEL_1 001117: line 482 define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 00114a: line 483 define RCC_I2C3CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C3SEL_0 00117d: line 484 define RCC_I2C3CLKSOURCE_HSI RCC_DCKCFGR2_I2C3SEL_1 0011ad: line 492 define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 0011e0: line 493 define RCC_I2C4CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C4SEL_0 001213: line 494 define RCC_I2C4CLKSOURCE_HSI RCC_DCKCFGR2_I2C4SEL_1 001243: line 502 define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000U) 001277: line 503 define RCC_LPTIM1CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0 0012ab: line 504 define RCC_LPTIM1CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1 0012df: line 505 define RCC_LPTIM1CLKSOURCE_LSE RCC_DCKCFGR2_LPTIM1SEL 001311: line 514 define RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000U) 001340: line 515 define RCC_CLK48SOURCE_PLLSAIP RCC_DCKCFGR2_CK48MSEL 001371: line 523 define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000U) 0013a5: line 524 define RCC_TIMPRES_ACTIVATED RCC_DCKCFGR1_TIMPRE 0013d2: line 532 define RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000U) 001407: line 533 define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL 00143c: line 542 define RCC_SDMMC2CLKSOURCE_CLK48 ((uint32_t)0x00000000U) 001471: line 543 define RCC_SDMMC2CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC2SEL 0014a6: line 551 define RCC_DFSDM1CLKSOURCE_PCLK ((uint32_t)0x00000000U) 0014da: line 552 define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_DCKCFGR1_DFSDM1SEL 00150f: line 560 define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 ((uint32_t)0x00000000U) 001548: line 561 define RCC_DFSDM1AUDIOCLKSOURCE_SAI2 RCC_DCKCFGR1_ADFSDM1SEL 001581: line 599 define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN); UNUSED(tmpreg); } while(0) 00163f: line 607 define __HAL_RCC_DTCMRAMEN_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN); UNUSED(tmpreg); } while(0) 0016ff: line 615 define __HAL_RCC_DMA2_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); UNUSED(tmpreg); } while(0) 0017b4: line 623 define __HAL_RCC_DMA2D_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); UNUSED(tmpreg); } while(0) 00186c: line 631 define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN); UNUSED(tmpreg); } while(0) 001929: line 639 define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN); UNUSED(tmpreg); } while(0) 0019f3: line 647 define __HAL_RCC_GPIOA_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN); UNUSED(tmpreg); } while(0) 001aab: line 655 define __HAL_RCC_GPIOB_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN); UNUSED(tmpreg); } while(0) 001b63: line 663 define __HAL_RCC_GPIOC_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); UNUSED(tmpreg); } while(0) 001c1b: line 671 define __HAL_RCC_GPIOD_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); UNUSED(tmpreg); } while(0) 001cd3: line 679 define __HAL_RCC_GPIOE_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN); UNUSED(tmpreg); } while(0) 001d8b: line 687 define __HAL_RCC_GPIOF_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN); UNUSED(tmpreg); } while(0) 001e43: line 695 define __HAL_RCC_GPIOG_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN); UNUSED(tmpreg); } while(0) 001efb: line 703 define __HAL_RCC_GPIOH_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN); UNUSED(tmpreg); } while(0) 001fb3: line 711 define __HAL_RCC_GPIOI_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN); UNUSED(tmpreg); } while(0) 00206b: line 719 define __HAL_RCC_GPIOJ_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN); UNUSED(tmpreg); } while(0) 002123: line 727 define __HAL_RCC_GPIOK_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN); UNUSED(tmpreg); } while(0) 0021db: line 735 define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) 002229: line 736 define __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN)) 002279: line 737 define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN)) 0022c1: line 738 define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN)) 00230b: line 739 define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) 00235a: line 740 define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) 0023b2: line 741 define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN)) 0023fc: line 742 define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN)) 002446: line 743 define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN)) 002490: line 744 define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) 0024da: line 745 define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) 002524: line 746 define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) 00256e: line 747 define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) 0025b8: line 748 define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN)) 002602: line 749 define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) 00264c: line 750 define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN)) 002696: line 751 define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN)) 0026e0: line 755 define __HAL_RCC_ETHMAC_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN); UNUSED(tmpreg); } while(0) 00279b: line 763 define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN); UNUSED(tmpreg); } while(0) 00285c: line 771 define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN); UNUSED(tmpreg); } while(0) 00291d: line 779 define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN); UNUSED(tmpreg); } while(0) 0029e1: line 787 define __HAL_RCC_ETH_CLK_ENABLE() do { __HAL_RCC_ETHMAC_CLK_ENABLE(); __HAL_RCC_ETHMACTX_CLK_ENABLE(); __HAL_RCC_ETHMACRX_CLK_ENABLE(); } while(0) 002a70: line 795 define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) 002abc: line 796 define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) 002b0c: line 797 define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) 002b5c: line 798 define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) 002bae: line 799 define __HAL_RCC_ETH_CLK_DISABLE() do { __HAL_RCC_ETHMACTX_CLK_DISABLE(); __HAL_RCC_ETHMACRX_CLK_DISABLE(); __HAL_RCC_ETHMAC_CLK_DISABLE(); } while(0) 002c41: line 810 define __HAL_RCC_DCMI_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); UNUSED(tmpreg); } while(0) 002cf6: line 819 define __HAL_RCC_JPEG_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN); tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN); UNUSED(tmpreg); } while(0) 002dab: line 826 define __HAL_RCC_JPEG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_JPEGEN)) 002df3: line 829 define __HAL_RCC_RNG_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); UNUSED(tmpreg); } while(0) 002ea5: line 837 define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); UNUSED(tmpreg); __HAL_RCC_SYSCFG_CLK_ENABLE(); } while(0) 002f81: line 846 define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) 002fc9: line 847 define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) 00300f: line 849 define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) 00305e: line 876 define __HAL_RCC_FMC_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); UNUSED(tmpreg); } while(0) 003110: line 884 define __HAL_RCC_QSPI_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); UNUSED(tmpreg); } while(0) 0031c5: line 892 define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) 00320b: line 893 define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) 003253: line 900 define __HAL_RCC_TIM2_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN); UNUSED(tmpreg); } while(0) 003308: line 908 define __HAL_RCC_TIM3_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN); UNUSED(tmpreg); } while(0) 0033bd: line 916 define __HAL_RCC_TIM4_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN); UNUSED(tmpreg); } while(0) 003472: line 924 define __HAL_RCC_TIM5_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN); UNUSED(tmpreg); } while(0) 003527: line 932 define __HAL_RCC_TIM6_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN); UNUSED(tmpreg); } while(0) 0035dc: line 940 define __HAL_RCC_TIM7_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN); UNUSED(tmpreg); } while(0) 003691: line 948 define __HAL_RCC_TIM12_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN); UNUSED(tmpreg); } while(0) 003749: line 956 define __HAL_RCC_TIM13_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN); UNUSED(tmpreg); } while(0) 003801: line 964 define __HAL_RCC_TIM14_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN); UNUSED(tmpreg); } while(0) 0038b9: line 972 define __HAL_RCC_LPTIM1_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN); UNUSED(tmpreg); } while(0) 003974: line 981 define __HAL_RCC_RTC_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN); UNUSED(tmpreg); } while(0) 003a26: line 989 define __HAL_RCC_CAN3_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN); UNUSED(tmpreg); } while(0) 003adb: line 998 define __HAL_RCC_SPI2_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN); UNUSED(tmpreg); } while(0) 003b90: line 1006 define __HAL_RCC_SPI3_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN); UNUSED(tmpreg); } while(0) 003c45: line 1014 define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN); UNUSED(tmpreg); } while(0) 003d03: line 1022 define __HAL_RCC_USART2_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN); UNUSED(tmpreg); } while(0) 003dbe: line 1030 define __HAL_RCC_USART3_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN); UNUSED(tmpreg); } while(0) 003e79: line 1038 define __HAL_RCC_UART4_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN); UNUSED(tmpreg); } while(0) 003f31: line 1046 define __HAL_RCC_UART5_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN); UNUSED(tmpreg); } while(0) 003fe9: line 1054 define __HAL_RCC_I2C1_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN); UNUSED(tmpreg); } while(0) 00409e: line 1062 define __HAL_RCC_I2C2_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN); UNUSED(tmpreg); } while(0) 004153: line 1070 define __HAL_RCC_I2C3_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN); UNUSED(tmpreg); } while(0) 004208: line 1078 define __HAL_RCC_I2C4_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN); UNUSED(tmpreg); } while(0) 0042bd: line 1086 define __HAL_RCC_CAN1_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN); UNUSED(tmpreg); } while(0) 004372: line 1094 define __HAL_RCC_CAN2_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN); UNUSED(tmpreg); } while(0) 004427: line 1102 define __HAL_RCC_CEC_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN); UNUSED(tmpreg); } while(0) 0044d9: line 1110 define __HAL_RCC_DAC_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN); UNUSED(tmpreg); } while(0) 00458b: line 1118 define __HAL_RCC_UART7_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN); UNUSED(tmpreg); } while(0) 004643: line 1126 define __HAL_RCC_UART8_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN); UNUSED(tmpreg); } while(0) 0046fb: line 1134 define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 004743: line 1135 define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 00478b: line 1136 define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 0047d3: line 1137 define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) 00481b: line 1138 define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 004863: line 1139 define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 0048ab: line 1140 define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) 0048f5: line 1141 define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) 00493f: line 1142 define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 004989: line 1143 define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) 0049d5: line 1145 define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCEN)) 004a1b: line 1146 define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN)) 004a63: line 1148 define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) 004aab: line 1149 define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 004af3: line 1150 define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN)) 004b41: line 1151 define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) 004b8d: line 1152 define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) 004bd9: line 1153 define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) 004c23: line 1154 define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) 004c6d: line 1155 define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) 004cb5: line 1156 define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) 004cfd: line 1157 define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 004d45: line 1158 define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN)) 004d8d: line 1159 define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) 004dd5: line 1160 define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) 004e1d: line 1161 define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) 004e63: line 1162 define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 004ea9: line 1163 define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) 004ef3: line 1164 define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) 004f3d: line 1171 define __HAL_RCC_TIM1_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); UNUSED(tmpreg); } while(0) 004ff2: line 1179 define __HAL_RCC_TIM8_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); UNUSED(tmpreg); } while(0) 0050a7: line 1187 define __HAL_RCC_USART1_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); UNUSED(tmpreg); } while(0) 005162: line 1195 define __HAL_RCC_USART6_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN); UNUSED(tmpreg); } while(0) 00521d: line 1204 define __HAL_RCC_SDMMC2_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN); UNUSED(tmpreg); } while(0) 0052d8: line 1213 define __HAL_RCC_ADC1_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN); UNUSED(tmpreg); } while(0) 00538d: line 1221 define __HAL_RCC_ADC2_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN); UNUSED(tmpreg); } while(0) 005442: line 1229 define __HAL_RCC_ADC3_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN); UNUSED(tmpreg); } while(0) 0054f7: line 1237 define __HAL_RCC_SDMMC1_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); UNUSED(tmpreg); } while(0) 0055b2: line 1245 define __HAL_RCC_SPI1_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); UNUSED(tmpreg); } while(0) 005667: line 1253 define __HAL_RCC_SPI4_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); UNUSED(tmpreg); } while(0) 00571c: line 1261 define __HAL_RCC_TIM9_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN); UNUSED(tmpreg); } while(0) 0057d1: line 1269 define __HAL_RCC_TIM10_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN); UNUSED(tmpreg); } while(0) 005889: line 1277 define __HAL_RCC_TIM11_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN); UNUSED(tmpreg); } while(0) 005941: line 1285 define __HAL_RCC_SPI5_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN); UNUSED(tmpreg); } while(0) 0059f6: line 1293 define __HAL_RCC_SPI6_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN); UNUSED(tmpreg); } while(0) 005aab: line 1301 define __HAL_RCC_SAI1_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); UNUSED(tmpreg); } while(0) 005b60: line 1309 define __HAL_RCC_SAI2_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); UNUSED(tmpreg); } while(0) 005c15: line 1318 define __HAL_RCC_LTDC_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); UNUSED(tmpreg); } while(0) 005cca: line 1338 define __HAL_RCC_DFSDM1_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); UNUSED(tmpreg); } while(0) 005d85: line 1346 define __HAL_RCC_MDIO_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN); UNUSED(tmpreg); } while(0) 005e3a: line 1355 define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) 005e82: line 1356 define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) 005eca: line 1357 define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) 005f16: line 1358 define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) 005f62: line 1360 define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC2EN)) 005fae: line 1362 define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) 005ff6: line 1363 define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) 00603e: line 1364 define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) 006086: line 1365 define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN)) 0060d2: line 1366 define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) 00611a: line 1367 define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) 006162: line 1368 define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) 0061aa: line 1369 define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 0061f4: line 1370 define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) 00623e: line 1371 define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) 006286: line 1372 define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) 0062ce: line 1373 define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) 006316: line 1374 define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN)) 00635e: line 1376 define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) 0063a6: line 1382 define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN)) 0063f2: line 1383 define __HAL_RCC_MDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_MDIOEN)) 00643a: line 1404 define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) 006494: line 1405 define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET) 0064f0: line 1406 define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET) 006544: line 1407 define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET) 00659a: line 1408 define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) 0065f5: line 1409 define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) 006659: line 1410 define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET) 0066af: line 1411 define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET) 006705: line 1412 define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET) 00675b: line 1413 define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 0067b1: line 1414 define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 006807: line 1415 define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) 00685d: line 1416 define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) 0068b3: line 1417 define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET) 006909: line 1418 define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) 00695f: line 1419 define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET) 0069b5: line 1420 define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET) 006a0b: line 1422 define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) 006a66: line 1423 define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET) 006ac3: line 1424 define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET) 006b18: line 1425 define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET) 006b6f: line 1426 define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) 006bcb: line 1427 define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) 006c30: line 1428 define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET) 006c87: line 1429 define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET) 006cde: line 1430 define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET) 006d35: line 1431 define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 006d8c: line 1432 define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 006de3: line 1433 define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) 006e3a: line 1434 define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) 006e91: line 1435 define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET) 006ee8: line 1436 define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) 006f3f: line 1437 define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET) 006f96: line 1438 define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET) 006fed: line 1442 define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) 007045: line 1443 define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET) 0070a1: line 1444 define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET) 0070fd: line 1445 define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET) 00715b: line 1446 define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) 0071ef: line 1453 define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) 007248: line 1454 define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET) 0072a5: line 1455 define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET) 007302: line 1456 define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET) 007361: line 1457 define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) 0073f9: line 1466 define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) 00744d: line 1467 define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) 00749f: line 1468 define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) 0074fa: line 1470 define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) 00754f: line 1471 define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) 0075a2: line 1472 define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 0075fe: line 1482 define __HAL_RCC_JPEG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) != RESET) 007652: line 1483 define __HAL_RCC_JPEG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) == RESET) 0076a7: line 1491 define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET) 0076f9: line 1492 define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) 00774d: line 1494 define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET) 0077a0: line 1495 define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) 0077f5: line 1502 define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 007849: line 1503 define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 00789d: line 1504 define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 0078f1: line 1505 define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) 007945: line 1506 define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 007999: line 1507 define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 0079ed: line 1508 define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 007a43: line 1509 define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 007a99: line 1510 define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 007aef: line 1511 define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) 007b47: line 1513 define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) != RESET) 007b99: line 1514 define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET) 007bed: line 1516 define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) 007c41: line 1517 define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 007c95: line 1518 define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET) 007cef: line 1519 define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) 007d47: line 1520 define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 007d9f: line 1521 define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 007df5: line 1522 define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 007e4b: line 1523 define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) 007e9f: line 1524 define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) 007ef3: line 1525 define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 007f47: line 1526 define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET) 007f9b: line 1527 define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) 007fef: line 1528 define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) 008043: line 1529 define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) 008095: line 1530 define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 0080e7: line 1531 define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET) 00813d: line 1532 define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) 008193: line 1534 define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 0081e8: line 1535 define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 00823d: line 1536 define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 008292: line 1537 define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) 0082e7: line 1538 define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 00833c: line 1539 define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 008391: line 1540 define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 0083e8: line 1541 define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 00843f: line 1542 define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 008496: line 1543 define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) 0084ef: line 1545 define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) == RESET) 008542: line 1546 define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET) 008597: line 1548 define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) 0085ec: line 1549 define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 008641: line 1550 define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET) 00869c: line 1551 define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) 0086f5: line 1552 define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 00874e: line 1553 define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 0087a5: line 1554 define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 0087fc: line 1555 define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) 008851: line 1556 define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) 0088a6: line 1557 define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 0088fb: line 1558 define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET) 008950: line 1559 define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) 0089a5: line 1560 define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) 0089fa: line 1561 define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) 008a4d: line 1562 define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 008aa0: line 1563 define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) 008af7: line 1564 define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) 008b4e: line 1571 define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) 008ba2: line 1572 define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) 008bf6: line 1573 define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) 008c4e: line 1574 define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET) 008ca6: line 1575 define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) 008cfa: line 1576 define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) 008d4e: line 1577 define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) 008da2: line 1578 define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET) 008dfa: line 1579 define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) 008e4e: line 1580 define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 008ea2: line 1581 define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET) 008ef6: line 1582 define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 008f4c: line 1583 define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) 008fa2: line 1584 define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) 008ff6: line 1585 define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET) 00904a: line 1586 define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) 00909e: line 1587 define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET) 0090f2: line 1589 define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET) 009146: line 1595 define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) != RESET) 00919e: line 1596 define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET) 0091f6: line 1597 define __HAL_RCC_MDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) != RESET) 00924a: line 1599 define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) 00929f: line 1600 define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) 0092f4: line 1601 define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) 00934d: line 1602 define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET) 0093a6: line 1603 define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) 0093fb: line 1604 define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) 009450: line 1605 define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) 0094a5: line 1606 define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET) 0094fe: line 1607 define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) 009553: line 1608 define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 0095a8: line 1609 define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET) 0095fd: line 1610 define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 009654: line 1611 define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) 0096ab: line 1612 define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) 009700: line 1613 define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET) 009755: line 1614 define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) 0097aa: line 1615 define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET) 0097ff: line 1617 define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET) 009854: line 1623 define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) == RESET) 0098ad: line 1624 define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET) 009906: line 1625 define __HAL_RCC_MDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) == RESET) 00995b: line 1638 define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST)) 0099a5: line 1639 define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST)) 0099f1: line 1640 define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) 009a3f: line 1641 define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) 009a8f: line 1642 define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST)) 009adb: line 1643 define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST)) 009b27: line 1644 define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST)) 009b73: line 1645 define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) 009bbf: line 1646 define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) 009c0b: line 1647 define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) 009c57: line 1648 define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) 009ca3: line 1649 define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST)) 009cef: line 1650 define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) 009d3b: line 1651 define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST)) 009d87: line 1652 define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST)) 009dd3: line 1654 define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST)) 009e20: line 1655 define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST)) 009e6f: line 1656 define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) 009ec0: line 1657 define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) 009f13: line 1658 define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST)) 009f62: line 1659 define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST)) 009fb1: line 1660 define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST)) 00a000: line 1661 define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) 00a04f: line 1662 define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) 00a09e: line 1663 define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) 00a0ed: line 1664 define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) 00a13c: line 1665 define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST)) 00a18b: line 1666 define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) 00a1da: line 1667 define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST)) 00a229: line 1668 define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST)) 00a278: line 1672 define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) 00a2b6: line 1673 define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) 00a300: line 1674 define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) 00a348: line 1675 define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) 00a399: line 1677 define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 00a3d3: line 1678 define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) 00a420: line 1679 define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) 00a46b: line 1680 define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) 00a4bf: line 1683 define __HAL_RCC_JPEG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_JPEGRST)) 00a509: line 1684 define __HAL_RCC_JPEG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_JPEGRST)) 00a556: line 1696 define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) 00a594: line 1697 define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) 00a5dc: line 1698 define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) 00a626: line 1700 define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 00a660: line 1701 define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) 00a6ab: line 1702 define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) 00a6f8: line 1706 define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 00a742: line 1707 define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 00a78c: line 1708 define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 00a7d6: line 1709 define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) 00a820: line 1710 define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 00a86a: line 1711 define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 00a8b4: line 1712 define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) 00a900: line 1713 define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) 00a94c: line 1714 define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 00a998: line 1715 define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) 00a9e6: line 1717 define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST)) 00aa30: line 1719 define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) 00aa7a: line 1720 define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 00aac4: line 1721 define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST)) 00ab14: line 1722 define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) 00ab62: line 1723 define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) 00abb0: line 1724 define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) 00abfc: line 1725 define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) 00ac48: line 1726 define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) 00ac92: line 1727 define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) 00acdc: line 1728 define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 00ad26: line 1729 define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST)) 00ad70: line 1730 define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) 00adba: line 1731 define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) 00ae04: line 1732 define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) 00ae4c: line 1733 define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 00ae94: line 1734 define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) 00aee0: line 1735 define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) 00af2c: line 1737 define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 00af79: line 1738 define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 00afc6: line 1739 define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 00b013: line 1740 define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) 00b060: line 1741 define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 00b0ad: line 1742 define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 00b0fa: line 1743 define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) 00b149: line 1744 define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) 00b198: line 1745 define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 00b1e7: line 1746 define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) 00b238: line 1748 define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST)) 00b285: line 1750 define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) 00b2d2: line 1751 define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 00b31f: line 1752 define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST)) 00b372: line 1753 define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) 00b3c3: line 1754 define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) 00b414: line 1755 define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) 00b463: line 1756 define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) 00b4b2: line 1757 define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) 00b4ff: line 1758 define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) 00b54c: line 1759 define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 00b599: line 1760 define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST)) 00b5e6: line 1761 define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) 00b633: line 1762 define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) 00b680: line 1763 define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) 00b6cb: line 1764 define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 00b716: line 1765 define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) 00b765: line 1766 define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) 00b7b4: line 1770 define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) 00b7fe: line 1771 define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) 00b848: line 1772 define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) 00b896: line 1773 define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) 00b8e4: line 1774 define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST)) 00b92c: line 1775 define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC1RST)) 00b97a: line 1776 define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) 00b9c4: line 1777 define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) 00ba0e: line 1778 define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) 00ba58: line 1779 define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 00baa4: line 1780 define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) 00baf0: line 1781 define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) 00bb3a: line 1782 define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) 00bb84: line 1783 define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) 00bbce: line 1784 define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST)) 00bc18: line 1786 define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST)) 00bc62: line 1789 define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) 00bcaf: line 1790 define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) 00bcfc: line 1791 define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) 00bd4d: line 1792 define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST)) 00bd9e: line 1793 define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST)) 00bde9: line 1794 define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST)) 00be3a: line 1795 define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) 00be87: line 1796 define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) 00bed4: line 1797 define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) 00bf21: line 1798 define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 00bf70: line 1799 define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) 00bfbf: line 1800 define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) 00c00c: line 1801 define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST)) 00c059: line 1802 define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) 00c0a6: line 1803 define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) 00c0f3: line 1805 define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST)) 00c140: line 1814 define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC2RST)) 00c18e: line 1815 define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST)) 00c1dc: line 1816 define __HAL_RCC_MDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_MDIORST)) 00c226: line 1818 define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC2RST)) 00c277: line 1819 define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST)) 00c2c8: line 1820 define __HAL_RCC_MDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_MDIORST)) 00c315: line 1837 define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 00c369: line 1838 define __HAL_RCC_AXI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_AXILPEN)) 00c3b9: line 1839 define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 00c40d: line 1840 define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) 00c461: line 1841 define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) 00c4b9: line 1842 define __HAL_RCC_DTCM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DTCMLPEN)) 00c50b: line 1843 define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) 00c55d: line 1844 define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN)) 00c5b1: line 1845 define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) 00c607: line 1846 define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) 00c661: line 1847 define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) 00c6bb: line 1848 define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) 00c717: line 1849 define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) 00c770: line 1850 define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) 00c7d2: line 1851 define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN)) 00c826: line 1852 define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN)) 00c87a: line 1853 define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN)) 00c8ce: line 1854 define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) 00c922: line 1855 define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) 00c976: line 1856 define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) 00c9ca: line 1857 define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) 00ca1e: line 1858 define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN)) 00ca72: line 1859 define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) 00cac6: line 1860 define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN)) 00cb1a: line 1861 define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN)) 00cb6e: line 1863 define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 00cbc4: line 1864 define __HAL_RCC_AXI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN)) 00cc16: line 1865 define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 00cc6c: line 1866 define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) 00ccc2: line 1867 define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) 00cd1c: line 1868 define __HAL_RCC_DTCM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN)) 00cd70: line 1869 define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN)) 00cdc4: line 1870 define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN)) 00ce1a: line 1871 define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) 00ce72: line 1872 define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) 00cece: line 1873 define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) 00cf2a: line 1874 define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) 00cf88: line 1875 define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) 00cfe3: line 1876 define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) 00d047: line 1877 define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN)) 00d09d: line 1878 define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN)) 00d0f3: line 1879 define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN)) 00d149: line 1880 define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) 00d19f: line 1881 define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) 00d1f5: line 1882 define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) 00d24b: line 1883 define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) 00d2a1: line 1884 define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN)) 00d2f7: line 1885 define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) 00d34d: line 1886 define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN)) 00d3a3: line 1887 define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN)) 00d3f9: line 1895 define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) 00d44b: line 1896 define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) 00d49f: line 1899 define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_JPEGLPEN)) 00d4f1: line 1900 define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_JPEGLPEN)) 00d545: line 1903 define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) 00d595: line 1904 define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) 00d5e7: line 1906 define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) 00d640: line 1907 define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) 00d69b: line 1923 define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) 00d6eb: line 1924 define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) 00d73d: line 1926 define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) 00d78f: line 1927 define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) 00d7e3: line 1935 define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 00d835: line 1936 define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 00d887: line 1937 define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 00d8d9: line 1938 define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN)) 00d92b: line 1939 define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) 00d97d: line 1940 define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) 00d9cf: line 1941 define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) 00da23: line 1942 define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) 00da77: line 1943 define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) 00dacb: line 1944 define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) 00db21: line 1946 define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCLPEN)) 00db71: line 1947 define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN)) 00dbc3: line 1949 define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN)) 00dc15: line 1950 define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 00dc67: line 1951 define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN)) 00dcbf: line 1952 define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN)) 00dd15: line 1953 define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) 00dd6b: line 1954 define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) 00ddbf: line 1955 define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) 00de13: line 1956 define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN)) 00de65: line 1957 define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN)) 00deb7: line 1958 define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) 00df09: line 1959 define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN)) 00df5b: line 1960 define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) 00dfad: line 1961 define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) 00dfff: line 1962 define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN)) 00e04f: line 1963 define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) 00e09f: line 1964 define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) 00e0f3: line 1965 define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) 00e147: line 1967 define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 00e19b: line 1968 define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 00e1ef: line 1969 define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 00e243: line 1970 define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN)) 00e297: line 1971 define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) 00e2eb: line 1972 define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) 00e33f: line 1973 define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) 00e395: line 1974 define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) 00e3eb: line 1975 define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) 00e441: line 1976 define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) 00e499: line 1978 define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCLPEN)) 00e4eb: line 1979 define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN)) 00e53f: line 1981 define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN)) 00e593: line 1982 define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 00e5e7: line 1983 define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN)) 00e641: line 1984 define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN)) 00e699: line 1985 define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) 00e6f1: line 1986 define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) 00e747: line 1987 define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) 00e79d: line 1988 define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN)) 00e7f1: line 1989 define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN)) 00e845: line 1990 define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) 00e899: line 1991 define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN)) 00e8ed: line 1992 define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) 00e941: line 1993 define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) 00e995: line 1994 define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN)) 00e9e7: line 1995 define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) 00ea39: line 1996 define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) 00ea8f: line 1997 define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) 00eae5: line 2005 define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN)) 00eb37: line 2006 define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) 00eb89: line 2007 define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN)) 00ebdf: line 2008 define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN)) 00ec35: line 2009 define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN)) 00ec87: line 2010 define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) 00ecd9: line 2011 define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) 00ed2b: line 2012 define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC1LPEN)) 00ed81: line 2013 define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN)) 00edd3: line 2014 define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) 00ee25: line 2015 define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN)) 00ee77: line 2016 define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 00eecb: line 2017 define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN)) 00ef1f: line 2018 define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) 00ef71: line 2019 define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) 00efc3: line 2020 define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) 00f015: line 2021 define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN)) 00f067: line 2023 define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN)) 00f0b9: line 2026 define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN)) 00f10d: line 2027 define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) 00f161: line 2028 define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN)) 00f1b9: line 2029 define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN)) 00f211: line 2030 define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN)) 00f265: line 2031 define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) 00f2b9: line 2032 define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) 00f30d: line 2033 define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN)) 00f365: line 2034 define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN)) 00f3b9: line 2035 define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) 00f40d: line 2036 define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN)) 00f461: line 2037 define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 00f4b7: line 2038 define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN)) 00f50d: line 2039 define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) 00f561: line 2040 define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) 00f5b5: line 2041 define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) 00f609: line 2042 define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN)) 00f65d: line 2044 define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN)) 00f6b1: line 2051 define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC2LPEN)) 00f707: line 2052 define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN)) 00f75d: line 2053 define __HAL_RCC_MDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_MDIOLPEN)) 00f7af: line 2055 define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC2LPEN)) 00f807: line 2056 define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN)) 00f85f: line 2057 define __HAL_RCC_MDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_MDIOLPEN)) 00f8b3: line 2078 define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET) 00f915: line 2079 define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET) 00f973: line 2080 define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET) 00f9d5: line 2081 define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET) 00fa37: line 2082 define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET) 00fa9d: line 2083 define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET) 00fafd: line 2084 define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET) 00fb5d: line 2085 define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET) 00fbbf: line 2086 define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET) 00fc23: line 2087 define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET) 00fc8b: line 2088 define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET) 00fcf3: line 2089 define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET) 00fd5d: line 2090 define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET) 00fdc4: line 2091 define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET) 00fe34: line 2092 define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET) 00fe96: line 2093 define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET) 00fef8: line 2094 define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET) 00ff5a: line 2095 define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET) 00ffbc: line 2096 define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET) 01001e: line 2097 define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET) 010080: line 2098 define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET) 0100e2: line 2099 define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET) 010144: line 2100 define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET) 0101a6: line 2101 define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET) 010208: line 2102 define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET) 01026a: line 2104 define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET) 0102cd: line 2105 define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET) 01032c: line 2106 define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET) 01038f: line 2107 define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET) 0103f2: line 2108 define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET) 010459: line 2109 define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET) 0104ba: line 2110 define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET) 01051b: line 2111 define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET) 01057e: line 2112 define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET) 0105e3: line 2113 define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET) 01064c: line 2114 define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET) 0106b5: line 2115 define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET) 010720: line 2116 define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET) 010788: line 2117 define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET) 0107f9: line 2118 define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET) 01085c: line 2119 define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET) 0108bf: line 2120 define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET) 010922: line 2121 define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET) 010985: line 2122 define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET) 0109e8: line 2123 define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET) 010a4b: line 2124 define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET) 010aae: line 2125 define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET) 010b11: line 2126 define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET) 010b74: line 2127 define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET) 010bd7: line 2128 define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET) 010c3a: line 2136 define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET) 010c9a: line 2137 define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET) 010cfb: line 2140 define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) != RESET) 010d5b: line 2141 define __HAL_RCC_JPEG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) == RESET) 010dbc: line 2144 define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET) 010e1a: line 2145 define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET) 010e79: line 2147 define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET) 010ee0: line 2148 define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET) 010f48: line 2164 define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET) 010fa6: line 2165 define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET) 011005: line 2167 define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET) 011065: line 2168 define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET) 0110c6: line 2176 define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET) 011126: line 2177 define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET) 011186: line 2178 define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET) 0111e6: line 2179 define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET) 011246: line 2180 define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET) 0112a6: line 2181 define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET) 011306: line 2182 define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET) 011368: line 2183 define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET) 0113ca: line 2184 define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET) 01142c: line 2185 define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET) 011490: line 2187 define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) != RESET) 0114ee: line 2188 define __HAL_RCC_CAN3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) != RESET) 01154e: line 2190 define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET) 0115ae: line 2191 define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET) 01160e: line 2192 define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET) 011674: line 2193 define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET) 0116d8: line 2194 define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET) 01173c: line 2195 define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET) 01179e: line 2196 define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET) 011800: line 2197 define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET) 011860: line 2198 define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET) 0118c0: line 2199 define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET) 011920: line 2200 define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET) 011980: line 2201 define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET) 0119e0: line 2202 define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET) 011a40: line 2203 define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET) 011a9e: line 2204 define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET) 011afc: line 2205 define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET) 011b5e: line 2206 define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET) 011bc0: line 2208 define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET) 011c21: line 2209 define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET) 011c82: line 2210 define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET) 011ce3: line 2211 define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET) 011d44: line 2212 define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET) 011da5: line 2213 define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET) 011e06: line 2214 define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET) 011e69: line 2215 define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET) 011ecc: line 2216 define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET) 011f2f: line 2217 define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET) 011f94: line 2219 define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) == RESET) 011ff3: line 2220 define __HAL_RCC_CAN3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) == RESET) 012054: line 2222 define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET) 0120b5: line 2223 define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET) 012116: line 2224 define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET) 01217d: line 2225 define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET) 0121e2: line 2226 define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET) 012247: line 2227 define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET) 0122aa: line 2228 define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET) 01230d: line 2229 define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET) 01236e: line 2230 define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET) 0123cf: line 2231 define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET) 012430: line 2232 define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET) 012491: line 2233 define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET) 0124f2: line 2234 define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET) 012553: line 2235 define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET) 0125b2: line 2236 define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET) 012611: line 2237 define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET) 012674: line 2238 define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET) 0126d7: line 2246 define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET) 012737: line 2247 define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET) 012797: line 2248 define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET) 0127fb: line 2249 define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET) 01285f: line 2250 define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET) 0128bf: line 2251 define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET) 01291f: line 2252 define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET) 01297f: line 2253 define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET) 0129e3: line 2254 define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET) 012a43: line 2255 define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET) 012aa3: line 2256 define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET) 012b03: line 2257 define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET) 012b65: line 2258 define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET) 012bc7: line 2259 define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET) 012c27: line 2260 define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET) 012c87: line 2261 define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET) 012ce7: line 2262 define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET) 012d47: line 2264 define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET) 012da7: line 2270 define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) != RESET) 012e0b: line 2271 define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != RESET) 012e6f: line 2272 define __HAL_RCC_MDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) != RESET) 012ecf: line 2275 define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET) 012f30: line 2276 define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET) 012f91: line 2277 define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET) 012ff6: line 2278 define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET) 01305b: line 2279 define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET) 0130bc: line 2280 define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET) 01311d: line 2281 define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET) 01317e: line 2282 define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET) 0131e3: line 2283 define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET) 013244: line 2284 define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET) 0132a5: line 2285 define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET) 013306: line 2286 define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET) 013369: line 2287 define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET) 0133cc: line 2288 define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET) 01342d: line 2289 define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET) 01348e: line 2290 define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET) 0134ef: line 2291 define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET) 013550: line 2293 define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET) 0135b1: line 2299 define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) == RESET) 013616: line 2300 define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == RESET) 01367b: line 2301 define __HAL_RCC_MDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) == RESET) 0136dc: line 2338 define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__,__PLLM__,__PLLN__,__PLLP__,__PLLQ__,__PLLR__) (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)) | ((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR)))) 013838: line 2392 define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE); RCC->DCKCFGR1 |= (__PRESC__); }while(0) 0138b5: line 2399 define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION)) 0138f1: line 2400 define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION)) 01392f: line 2417 define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__,__PLLSAIP__,__PLLSAIQ__,__PLLSAIR__) (RCC->PLLSAICFGR = ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) | ((__PLLSAIP__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) | ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) | ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))) 013a75: line 2440 define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__,__PLLI2SP__,__PLLI2SQ__,__PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) | ((__PLLI2SP__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) | ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) | ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))) 013bbb: line 2452 define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1)) 013c3d: line 2460 define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8)) 013cc4: line 2469 define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__)) 013d4c: line 2487 define __HAL_RCC_SAI1_CONFIG(__SOURCE__) MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__)) 013db9: line 2502 define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL))) 013e14: line 2520 define __HAL_RCC_SAI2_CONFIG(__SOURCE__) MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__)) 013e81: line 2536 define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL))) 013edc: line 2541 define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE)) 013f20: line 2545 define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE)) 013f66: line 2549 define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF)) 013fa8: line 2554 define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE)) 014003: line 2559 define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY)) 014059: line 2566 define __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)) 0140a0: line 2576 define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) 01411d: line 2585 define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL))) 014178: line 2595 define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) 0141f5: line 2604 define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL))) 014250: line 2614 define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__)) 0142cd: line 2623 define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL))) 014328: line 2633 define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__)) 0143a5: line 2642 define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL))) 014400: line 2653 define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) 014485: line 2663 define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL))) 0144e4: line 2674 define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) 014569: line 2684 define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL))) 0145c8: line 2695 define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) 01464d: line 2705 define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL))) 0146ac: line 2716 define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__)) 01472d: line 2726 define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL))) 01478a: line 2737 define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__)) 01480b: line 2747 define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL))) 014868: line 2758 define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__)) 0148ed: line 2768 define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL))) 01494c: line 2779 define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__)) 0149cd: line 2789 define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL))) 014a2a: line 2800 define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__)) 014aab: line 2810 define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL))) 014b08: line 2821 define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) 014b8d: line 2831 define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))) 014bec: line 2840 define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__)) 014c65: line 2848 define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))) 014cbe: line 2857 define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__)) 014d39: line 2865 define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))) 014d96: line 2874 define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__)) 014e1b: line 2882 define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL))) 014e7a: line 2891 define __HAL_RCC_SDMMC2_CONFIG(__SDMMC2_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL, (uint32_t)(__SDMMC2_CLKSOURCE__)) 014eff: line 2899 define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL))) 014f5e: line 2907 define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__)) 014fe3: line 2915 define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL))) 015042: line 2923 define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, (uint32_t)(__DFSDM1AUDIO_CLKSOURCE__)) 0150d7: line 2931 define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL))) 01513c: line 3022 define IS_RCC_PERIPHCLOCK(SELECTION) ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 0157e0: line 3077 define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) 015825: line 3078 define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) || ((VALUE) == RCC_PLLI2SP_DIV4) || ((VALUE) == RCC_PLLI2SP_DIV6) || ((VALUE) == RCC_PLLI2SP_DIV8)) 0158c7: line 3082 define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) 01590a: line 3083 define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) 01594c: line 3085 define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) 015991: line 3086 define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) || ((VALUE) == RCC_PLLSAIP_DIV4) || ((VALUE) == RCC_PLLSAIP_DIV6) || ((VALUE) == RCC_PLLSAIP_DIV8)) 015a33: line 3090 define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) 015a76: line 3091 define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) 015ab8: line 3093 define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) 015aff: line 3095 define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) 015b46: line 3097 define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) || ((VALUE) == RCC_PLLSAIDIVR_4) || ((VALUE) == RCC_PLLSAIDIVR_8) || ((VALUE) == RCC_PLLSAIDIVR_16)) 015bed: line 3101 define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) || ((SOURCE) == RCC_I2SCLKSOURCE_EXT)) 015c5a: line 3104 define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || ((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48)) 015cd2: line 3107 define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || ((SOURCE) == RCC_CECCLKSOURCE_LSE)) 015d3c: line 3109 define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) 015e06: line 3115 define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || ((SOURCE) == RCC_USART2CLKSOURCE_HSI)) 015ed0: line 3120 define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || ((SOURCE) == RCC_USART3CLKSOURCE_HSI)) 015f9a: line 3126 define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || ((SOURCE) == RCC_UART4CLKSOURCE_HSI)) 01605f: line 3132 define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || ((SOURCE) == RCC_UART5CLKSOURCE_HSI)) 016124: line 3138 define IS_RCC_USART6CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART6CLKSOURCE_PCLK2) || ((SOURCE) == RCC_USART6CLKSOURCE_SYSCLK) || ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || ((SOURCE) == RCC_USART6CLKSOURCE_HSI)) 0161ee: line 3144 define IS_RCC_UART7CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART7CLKSOURCE_PCLK1) || ((SOURCE) == RCC_UART7CLKSOURCE_SYSCLK) || ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || ((SOURCE) == RCC_UART7CLKSOURCE_HSI)) 0162b3: line 3150 define IS_RCC_UART8CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART8CLKSOURCE_PCLK1) || ((SOURCE) == RCC_UART8CLKSOURCE_SYSCLK) || ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || ((SOURCE) == RCC_UART8CLKSOURCE_HSI)) 016378: line 3155 define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) || ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)|| ((SOURCE) == RCC_I2C1CLKSOURCE_HSI)) 016410: line 3159 define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_PCLK1) || ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)|| ((SOURCE) == RCC_I2C2CLKSOURCE_HSI)) 0164a8: line 3164 define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_PCLK1) || ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)|| ((SOURCE) == RCC_I2C3CLKSOURCE_HSI)) 016540: line 3168 define IS_RCC_I2C4CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C4CLKSOURCE_PCLK1) || ((SOURCE) == RCC_I2C4CLKSOURCE_SYSCLK)|| ((SOURCE) == RCC_I2C4CLKSOURCE_HSI)) 0165d8: line 3172 define IS_RCC_LPTIM1CLK(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) 016698: line 3177 define IS_RCC_CLK48SOURCE(SOURCE) (((SOURCE) == RCC_CLK48SOURCE_PLLSAIP) || ((SOURCE) == RCC_CLK48SOURCE_PLL)) 016703: line 3180 define IS_RCC_TIMPRES(VALUE) (((VALUE) == RCC_TIMPRES_DESACTIVATED) || ((VALUE) == RCC_TIMPRES_ACTIVATED)) 01676a: line 3194 define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) 0167a9: line 3196 define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || ((SOURCE) == RCC_SAI1CLKSOURCE_PIN) || ((SOURCE) == RCC_SAI1CLKSOURCE_PLLSRC)) 01686d: line 3201 define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || ((SOURCE) == RCC_SAI2CLKSOURCE_PIN) || ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC)) 016931: line 3206 define IS_RCC_SDMMC2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC2CLKSOURCE_SYSCLK) || ((SOURCE) == RCC_SDMMC2CLKSOURCE_CLK48)) 0169a9: line 3209 define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_PCLK) || ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYSCLK)) 016a20: line 3212 define IS_RCC_DFSDM1AUDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI2)) 016aa4: line 3217 define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) || ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY)) 016b1a: end include 016b1b: end of translation unit ** Section #77 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 124 bytes 000000: Header: length 120 (not including this field) version 3 prologue length 110 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_rcc_ex.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 72 63 63 5f 65 78 2e 68 00 01 00 00 000060: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000077: file "" : 00 000078: DW_LNS_negate_stmt : 06 000079: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc_ex.h:1.0 [ ** Section #78 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 1480 bytes 000000: Header: size 0x5c4 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc_ex.h 00004c: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000093: DW_AT_language DW_LANG_C89 000095: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010c: DW_AT_macro_info 0x0 000110: DW_AT_stmt_list 0x0 000114: 42 = 0x13 (DW_TAG_structure_type) 000115: DW_AT_sibling 0x184 000117: DW_AT_byte_size 0x1c 000118: 30 = 0xd (DW_TAG_member) 000119: DW_AT_name PLLState 000122: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000127: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00012a: 30 = 0xd (DW_TAG_member) 00012b: DW_AT_name PLLSource 000135: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00013a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00013d: 30 = 0xd (DW_TAG_member) 00013e: DW_AT_name PLLM 000143: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000148: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 00014b: 30 = 0xd (DW_TAG_member) 00014c: DW_AT_name PLLN 000151: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000156: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000159: 30 = 0xd (DW_TAG_member) 00015a: DW_AT_name PLLP 00015f: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000164: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000167: 30 = 0xd (DW_TAG_member) 000168: DW_AT_name PLLQ 00016d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000172: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 000175: 30 = 0xd (DW_TAG_member) 000176: DW_AT_name PLLR 00017b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000180: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 000183: 0 null 000184: 80 = 0x16 (DW_TAG_typedef) 000185: DW_AT_name RCC_PLLInitTypeDef 000198: DW_AT_type indirect DW_FORM_ref2 0x114 00019b: DW_AT_decl_file 0x1 00019c: DW_AT_decl_line 0x59 00019d: DW_AT_decl_column 0x2 00019e: 42 = 0x13 (DW_TAG_structure_type) 00019f: DW_AT_sibling 0x1e7 0001a1: DW_AT_byte_size 0x10 0001a2: 30 = 0xd (DW_TAG_member) 0001a3: DW_AT_name PLLI2SN 0001ab: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001b0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0001b3: 30 = 0xd (DW_TAG_member) 0001b4: DW_AT_name PLLI2SR 0001bc: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001c1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0001c4: 30 = 0xd (DW_TAG_member) 0001c5: DW_AT_name PLLI2SQ 0001cd: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001d2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0001d5: 30 = 0xd (DW_TAG_member) 0001d6: DW_AT_name PLLI2SP 0001de: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001e3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0001e6: 0 null 0001e7: 80 = 0x16 (DW_TAG_typedef) 0001e8: DW_AT_name RCC_PLLI2SInitTypeDef 0001fe: DW_AT_type indirect DW_FORM_ref2 0x19e 000201: DW_AT_decl_file 0x1 000202: DW_AT_decl_line 0x72 000203: DW_AT_decl_column 0x2 000204: 42 = 0x13 (DW_TAG_structure_type) 000205: DW_AT_sibling 0x24d 000207: DW_AT_byte_size 0x10 000208: 30 = 0xd (DW_TAG_member) 000209: DW_AT_name PLLSAIN 000211: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000216: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000219: 30 = 0xd (DW_TAG_member) 00021a: DW_AT_name PLLSAIQ 000222: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000227: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00022a: 30 = 0xd (DW_TAG_member) 00022b: DW_AT_name PLLSAIR 000233: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000238: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 00023b: 30 = 0xd (DW_TAG_member) 00023c: DW_AT_name PLLSAIP 000244: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000249: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00024c: 0 null 00024d: 80 = 0x16 (DW_TAG_typedef) 00024e: DW_AT_name RCC_PLLSAIInitTypeDef 000264: DW_AT_type indirect DW_FORM_ref2 0x204 000267: DW_AT_decl_file 0x1 000268: DW_AT_decl_line 0x8b 00026a: DW_AT_decl_column 0x2 00026b: 42 = 0x13 (DW_TAG_structure_type) 00026c: DW_AT_sibling 0x5a2 00026e: DW_AT_byte_size 0x90 000270: 30 = 0xd (DW_TAG_member) 000271: DW_AT_name PeriphClockSelection 000286: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00028b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00028e: 30 = 0xd (DW_TAG_member) 00028f: DW_AT_name PLLI2S 000296: DW_AT_type indirect DW_FORM_ref2 0x1e7 000299: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00029c: 30 = 0xd (DW_TAG_member) 00029d: DW_AT_name PLLSAI 0002a4: DW_AT_type indirect DW_FORM_ref2 0x24d 0002a7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 0002aa: 30 = 0xd (DW_TAG_member) 0002ab: DW_AT_name PLLI2SDivQ 0002b6: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002bb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 0002be: 30 = 0xd (DW_TAG_member) 0002bf: DW_AT_name PLLSAIDivQ 0002ca: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002cf: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 0002d2: 30 = 0xd (DW_TAG_member) 0002d3: DW_AT_name PLLSAIDivR 0002de: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002e3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 0002e6: 30 = 0xd (DW_TAG_member) 0002e7: DW_AT_name RTCClockSelection 0002f9: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002fe: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 000301: 30 = 0xd (DW_TAG_member) 000302: DW_AT_name I2sClockSelection 000314: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000319: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 00031c: 30 = 0xd (DW_TAG_member) 00031d: DW_AT_name TIMPresSelection 00032e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000333: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 000336: 30 = 0xd (DW_TAG_member) 000337: DW_AT_name Sai1ClockSelection 00034a: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00034f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 60 } 000352: 30 = 0xd (DW_TAG_member) 000353: DW_AT_name Sai2ClockSelection 000366: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00036b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 64 } 00036e: 30 = 0xd (DW_TAG_member) 00036f: DW_AT_name Usart1ClockSelection 000384: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000389: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 68 } 00038c: 30 = 0xd (DW_TAG_member) 00038d: DW_AT_name Usart2ClockSelection 0003a2: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003a7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 72 } 0003aa: 30 = 0xd (DW_TAG_member) 0003ab: DW_AT_name Usart3ClockSelection 0003c0: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003c5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 76 } 0003c8: 30 = 0xd (DW_TAG_member) 0003c9: DW_AT_name Uart4ClockSelection 0003dd: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003e2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 80 } 0003e5: 30 = 0xd (DW_TAG_member) 0003e6: DW_AT_name Uart5ClockSelection 0003fa: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003ff: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 84 } 000402: 30 = 0xd (DW_TAG_member) 000403: DW_AT_name Usart6ClockSelection 000418: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00041d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 88 } 000420: 30 = 0xd (DW_TAG_member) 000421: DW_AT_name Uart7ClockSelection 000435: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00043a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 92 } 00043d: 30 = 0xd (DW_TAG_member) 00043e: DW_AT_name Uart8ClockSelection 000452: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000457: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 96 } 00045a: 30 = 0xd (DW_TAG_member) 00045b: DW_AT_name I2c1ClockSelection 00046e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000473: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 100 } 000476: 30 = 0xd (DW_TAG_member) 000477: DW_AT_name I2c2ClockSelection 00048a: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00048f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 104 } 000492: 30 = 0xd (DW_TAG_member) 000493: DW_AT_name I2c3ClockSelection 0004a6: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004ab: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 108 } 0004ae: 30 = 0xd (DW_TAG_member) 0004af: DW_AT_name I2c4ClockSelection 0004c2: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004c7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 112 } 0004ca: 30 = 0xd (DW_TAG_member) 0004cb: DW_AT_name Lptim1ClockSelection 0004e0: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004e5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 116 } 0004e8: 30 = 0xd (DW_TAG_member) 0004e9: DW_AT_name CecClockSelection 0004fb: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000500: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 120 } 000503: 30 = 0xd (DW_TAG_member) 000504: DW_AT_name Clk48ClockSelection 000518: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00051d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 124 } 000520: 30 = 0xd (DW_TAG_member) 000521: DW_AT_name Sdmmc1ClockSelection 000536: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00053b: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 128 } 00053f: 30 = 0xd (DW_TAG_member) 000540: DW_AT_name Sdmmc2ClockSelection 000555: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00055a: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 132 } 00055e: 30 = 0xd (DW_TAG_member) 00055f: DW_AT_name Dfsdm1ClockSelection 000574: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000579: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 136 } 00057d: 30 = 0xd (DW_TAG_member) 00057e: DW_AT_name Dfsdm1AudioClockSelection 000598: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00059d: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 140 } 0005a1: 0 null 0005a2: 80 = 0x16 (DW_TAG_typedef) 0005a3: DW_AT_name RCC_PeriphCLKInitTypeDef 0005bc: DW_AT_type indirect DW_FORM_ref2 0x26b 0005bf: DW_AT_decl_file 0x1 0005c0: DW_AT_decl_line 0xef 0005c2: DW_AT_decl_column 0x2 0005c3: 0 null 0005c4: 0 padding 0005c5: 0 padding 0005c6: 0 padding 0005c7: 0 padding ** Section #374 '.rel.debug_info' (SHT_REL) Size : 368 bytes (alignment 4) Symbol table #343 '.symtab' 46 relocations applied to section #78 '.debug_info' ** Section #79 '__ARM_grp.stm32f7xx_hal_rcc.h.2_osx000_rPY_SLA2$z5_010000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #80 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 18496 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_RCC_H 00001c: include at line 47 - file 2 00001f: end include 000020: include at line 51 - file 3 000023: end include 000024: line 128 define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U) 000057: line 129 define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U) 000089: line 130 define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U) 0000bb: line 131 define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U) 0000ed: line 132 define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U) 00011f: line 140 define RCC_HSE_OFF ((uint32_t)0x00000000U) 000146: line 141 define RCC_HSE_ON RCC_CR_HSEON 000161: line 142 define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) 00019e: line 150 define RCC_LSE_OFF ((uint32_t)0x00000000U) 0001c5: line 151 define RCC_LSE_ON RCC_BDCR_LSEON 0001e2: line 152 define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) 000223: line 160 define RCC_HSI_OFF ((uint32_t)0x00000000U) 00024a: line 161 define RCC_HSI_ON RCC_CR_HSION 000265: line 163 define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) 000295: line 171 define RCC_LSI_OFF ((uint32_t)0x00000000U) 0002bc: line 172 define RCC_LSI_ON RCC_CSR_LSION 0002d8: line 180 define RCC_PLL_NONE ((uint32_t)0x00000000U) 000300: line 181 define RCC_PLL_OFF ((uint32_t)0x00000001U) 000327: line 182 define RCC_PLL_ON ((uint32_t)0x00000002U) 00034d: line 190 define RCC_PLLP_DIV2 ((uint32_t)0x00000002U) 000376: line 191 define RCC_PLLP_DIV4 ((uint32_t)0x00000004U) 00039f: line 192 define RCC_PLLP_DIV6 ((uint32_t)0x00000006U) 0003c8: line 193 define RCC_PLLP_DIV8 ((uint32_t)0x00000008U) 0003f1: line 201 define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI 00041d: line 202 define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE 000449: line 210 define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U) 000479: line 211 define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U) 0004a7: line 212 define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U) 0004d6: line 213 define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U) 000505: line 221 define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI 00052d: line 222 define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE 000555: line 223 define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL 000580: line 232 define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI 0005b0: line 233 define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE 0005e0: line 234 define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL 000613: line 242 define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 000639: line 243 define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 00065f: line 244 define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 000685: line 245 define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 0006ab: line 246 define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 0006d3: line 247 define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 0006fb: line 248 define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 000725: line 249 define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 00074f: line 250 define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 000779: line 258 define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 00079e: line 259 define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 0007c3: line 260 define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 0007e8: line 261 define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 00080d: line 262 define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 000834: line 270 define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U) 000864: line 271 define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U) 000894: line 272 define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U) 0008c9: line 273 define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U) 0008fe: line 274 define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U) 000933: line 275 define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300U) 000968: line 276 define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300U) 00099d: line 277 define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300U) 0009d2: line 278 define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300U) 000a07: line 279 define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300U) 000a3c: line 280 define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300U) 000a72: line 281 define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300U) 000aa8: line 282 define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300U) 000ade: line 283 define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300U) 000b14: line 284 define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300U) 000b4a: line 285 define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300U) 000b80: line 286 define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300U) 000bb6: line 287 define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300U) 000bec: line 288 define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300U) 000c22: line 289 define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300U) 000c58: line 290 define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300U) 000c8e: line 291 define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300U) 000cc4: line 292 define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300U) 000cfa: line 293 define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300U) 000d30: line 294 define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300U) 000d66: line 295 define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300U) 000d9c: line 296 define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300U) 000dd2: line 297 define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300U) 000e08: line 298 define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300U) 000e3e: line 299 define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300U) 000e74: line 300 define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300U) 000eaa: line 301 define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300U) 000ee0: line 311 define RCC_MCO1 ((uint32_t)0x00000000U) 000f04: line 312 define RCC_MCO2 ((uint32_t)0x00000001U) 000f28: line 320 define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000U) 000f56: line 321 define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0 000f7c: line 322 define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1 000fa2: line 323 define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1 000fc9: line 331 define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000U) 000ffa: line 332 define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0 001026: line 333 define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 00104c: line 334 define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 001073: line 342 define RCC_MCODIV_1 ((uint32_t)0x00000000U) 00109b: line 343 define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2 0010be: line 344 define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2) 001102: line 345 define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) 001146: line 346 define RCC_MCODIV_5 RCC_CFGR_MCO1PRE 001167: line 354 define RCC_IT_LSIRDY ((uint8_t)0x01U) 001189: line 355 define RCC_IT_LSERDY ((uint8_t)0x02U) 0011ab: line 356 define RCC_IT_HSIRDY ((uint8_t)0x04U) 0011cd: line 357 define RCC_IT_HSERDY ((uint8_t)0x08U) 0011ef: line 358 define RCC_IT_PLLRDY ((uint8_t)0x10U) 001211: line 359 define RCC_IT_PLLI2SRDY ((uint8_t)0x20U) 001236: line 360 define RCC_IT_PLLSAIRDY ((uint8_t)0x40U) 00125b: line 361 define RCC_IT_CSS ((uint8_t)0x80U) 00127a: line 376 define RCC_FLAG_HSIRDY ((uint8_t)0x21U) 00129e: line 377 define RCC_FLAG_HSERDY ((uint8_t)0x31U) 0012c2: line 378 define RCC_FLAG_PLLRDY ((uint8_t)0x39U) 0012e6: line 379 define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3BU) 00130d: line 380 define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3CU) 001334: line 383 define RCC_FLAG_LSERDY ((uint8_t)0x41U) 001358: line 386 define RCC_FLAG_LSIRDY ((uint8_t)0x61U) 00137c: line 387 define RCC_FLAG_BORRST ((uint8_t)0x79U) 0013a0: line 388 define RCC_FLAG_PINRST ((uint8_t)0x7AU) 0013c4: line 389 define RCC_FLAG_PORRST ((uint8_t)0x7BU) 0013e8: line 390 define RCC_FLAG_SFTRST ((uint8_t)0x7CU) 00140c: line 391 define RCC_FLAG_IWDGRST ((uint8_t)0x7DU) 001431: line 392 define RCC_FLAG_WWDGRST ((uint8_t)0x7EU) 001456: line 393 define RCC_FLAG_LPWRRST ((uint8_t)0x7FU) 00147b: line 401 define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) 0014a7: line 402 define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 0014d3: line 403 define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 001500: line 404 define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV 001525: line 425 define __HAL_RCC_CRC_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); UNUSED(tmpreg); } while(0) 0015d7: line 433 define __HAL_RCC_DMA1_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); UNUSED(tmpreg); } while(0) 00168c: line 441 define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 0016d2: line 442 define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN)) 00171a: line 455 define __HAL_RCC_WWDG_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN); UNUSED(tmpreg); } while(0) 0017cf: line 463 define __HAL_RCC_PWR_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN); UNUSED(tmpreg); } while(0) 001881: line 471 define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) 0018c9: line 472 define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) 00190f: line 484 define __HAL_RCC_SYSCFG_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); UNUSED(tmpreg); } while(0) 0019ca: line 492 define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) 001a16: line 505 define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 001a68: line 506 define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != RESET) 001abc: line 508 define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 001b0f: line 509 define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == RESET) 001b64: line 521 define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) 001bb8: line 522 define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) 001c0a: line 524 define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) 001c5f: line 525 define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) 001cb2: line 537 define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET) 001d0a: line 538 define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET) 001d63: line 547 define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU) 001da1: line 548 define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 001de9: line 549 define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST)) 001e33: line 551 define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) 001e6d: line 552 define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 001eb8: line 553 define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST)) 001f05: line 562 define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) 001f43: line 563 define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) 001f8d: line 564 define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) 001fd5: line 566 define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) 00200f: line 567 define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) 00205c: line 568 define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) 0020a7: line 577 define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) 0020e5: line 578 define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) 002133: line 580 define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) 00216d: line 581 define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) 0021be: line 594 define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 00220e: line 595 define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) 002260: line 597 define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 0022b2: line 598 define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN)) 002306: line 606 define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN)) 002358: line 607 define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN)) 0023a8: line 609 define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN)) 0023fc: line 610 define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN)) 00244e: line 618 define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN)) 0024a4: line 619 define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN)) 0024fc: line 633 define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != RESET) 00255a: line 634 define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != RESET) 0025ba: line 636 define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == RESET) 002619: line 637 define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == RESET) 00267a: line 650 define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET) 0026da: line 651 define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET) 002738: line 653 define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET) 002799: line 654 define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET) 0027f8: line 667 define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET) 00285c: line 668 define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET) 0028c1: line 691 define __HAL_RCC_HSI_ENABLE() (RCC->CR |= (RCC_CR_HSION)) 0028f7: line 692 define __HAL_RCC_HSI_DISABLE() (RCC->CR &= ~(RCC_CR_HSION)) 00292f: line 700 define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_CR_HSITRIM))) 0029dc: line 718 define __HAL_RCC_LSI_ENABLE() (RCC->CSR |= (RCC_CSR_LSION)) 002a14: line 719 define __HAL_RCC_LSI_DISABLE() (RCC->CSR &= ~(RCC_CSR_LSION)) 002a4e: line 749 define __HAL_RCC_HSE_CONFIG(__STATE__) do { if ((__STATE__) == RCC_HSE_ON) { SET_BIT(RCC->CR, RCC_CR_HSEON); } else if ((__STATE__) == RCC_HSE_OFF) { CLEAR_BIT(RCC->CR, RCC_CR_HSEON); CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); } else if ((__STATE__) == RCC_HSE_BYPASS) { SET_BIT(RCC->CR, RCC_CR_HSEBYP); SET_BIT(RCC->CR, RCC_CR_HSEON); } else { CLEAR_BIT(RCC->CR, RCC_CR_HSEON); CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); } } while(0) 002bed: line 797 define __HAL_RCC_LSE_CONFIG(__STATE__) do { if((__STATE__) == RCC_LSE_ON) { SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); } else if((__STATE__) == RCC_LSE_OFF) { CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); } else if((__STATE__) == RCC_LSE_BYPASS) { SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); } else { CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); } } while(0) 002da5: line 830 define __HAL_RCC_RTC_ENABLE() (RCC->BDCR |= (RCC_BDCR_RTCEN)) 002ddf: line 831 define __HAL_RCC_RTC_DISABLE() (RCC->BDCR &= ~(RCC_BDCR_RTCEN)) 002e1b: line 854 define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) 002efa: line 857 define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); } while (0) 002f93: line 866 define __HAL_RCC_BACKUPRESET_FORCE() (RCC->BDCR |= (RCC_BDCR_BDRST)) 002fd4: line 867 define __HAL_RCC_BACKUPRESET_RELEASE() (RCC->BDCR &= ~(RCC_BDCR_BDRST)) 003018: line 883 define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) 003051: line 884 define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) 00308d: line 894 define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) 0030fc: line 905 define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) 00315a: line 922 define __HAL_RCC_I2S_CONFIG(__SOURCE__) do {RCC->CFGR &= ~(RCC_CFGR_I2SSRC); RCC->CFGR |= (__SOURCE__); }while(0) 0031c8: line 929 define __HAL_RCC_PLLI2S_ENABLE() (RCC->CR |= (RCC_CR_PLLI2SON)) 003204: line 930 define __HAL_RCC_PLLI2S_DISABLE() (RCC->CR &= ~(RCC_CR_PLLI2SON)) 003242: line 946 define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__)) 0032ae: line 955 define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS)) 0032f6: line 971 define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) )) 00336d: line 980 define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC)) 0033be: line 1005 define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__,__MCODIV__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 003453: line 1024 define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__,__MCODIV__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3))); 0034f0: line 1046 define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) 003553: line 1059 define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) 0035c3: line 1073 define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) 003624: line 1087 define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) 003679: line 1092 define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) 0036b5: line 1112 define RCC_FLAG_MASK ((uint8_t)0x1F) 0036d6: line 1113 define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0) 0037b3: include at line 1124 - file 3 0037b7: end include 0037b8: line 1175 define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT 0037e1: line 1176 define HSI_TIMEOUT_VALUE ((uint32_t)2) 003804: line 1177 define LSI_TIMEOUT_VALUE ((uint32_t)2) 003827: line 1178 define PLL_TIMEOUT_VALUE ((uint32_t)2) 00384a: line 1179 define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) 003878: line 1186 define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01)) 0038b6: line 1189 define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02)) 0038f4: line 1191 define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) 00391d: line 1192 define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 00394a: line 1208 define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15) 003984: line 1210 define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || ((HSE) == RCC_HSE_BYPASS)) 0039e6: line 1213 define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || ((LSE) == RCC_LSE_BYPASS)) 003a48: line 1216 define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)) 003a8d: line 1218 define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) 003ad2: line 1220 define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON)) 003b31: line 1222 define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || ((SOURCE) == RCC_PLLSOURCE_HSE)) 003b92: line 1225 define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) 003c25: line 1228 define IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63)) 003c65: line 1230 define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) 003ca7: line 1232 define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == RCC_PLLP_DIV2) || ((VALUE) == RCC_PLLP_DIV4) || ((VALUE) == RCC_PLLP_DIV6) || ((VALUE) == RCC_PLLP_DIV8)) 003d3a: line 1234 define IS_RCC_PLLQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) 003d7a: line 1236 define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || ((HCLK) == RCC_SYSCLK_DIV512)) 003ead: line 1242 define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15)) 003ee6: line 1244 define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || ((PCLK) == RCC_HCLK_DIV16)) 003f8c: line 1248 define IS_RCC_MCO(MCOX) (((MCOX) == RCC_MCO1) || ((MCOX) == RCC_MCO2)) 003fcf: line 1251 define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK)) 00407e: line 1254 define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) 004135: line 1257 define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || ((DIV) == RCC_MCODIV_5)) 0041d1: line 1260 define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) 004206: line 1262 define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31)) 004790: line 1280 define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW) || ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW) || ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || ((DRIVE) == RCC_LSEDRIVE_HIGH)) 00483c: end include 00483d: end of translation unit ** Section #81 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 148 bytes 000000: Header: length 144 (not including this field) version 3 prologue length 133 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_rcc.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 72 63 63 2e 68 00 01 00 00 00005d: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000074: file "stm32f7xx_hal_rcc_ex.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 72 63 63 5f 65 78 2e 68 00 01 00 00 00008e: file "" : 00 00008f: DW_LNS_negate_stmt : 06 000090: DW_LNS_negate_stmt : 06 000091: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc.h:1.0 ** Section #82 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 588 bytes 000000: Header: size 0x248 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc.h 000049: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000090: DW_AT_language DW_LANG_C89 000092: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 000109: DW_AT_macro_info 0x0 00010d: DW_AT_stmt_list 0x0 000111: 42 = 0x13 (DW_TAG_structure_type) 000112: DW_AT_sibling 0x1a0 000114: DW_AT_byte_size 0x34 000115: 30 = 0xd (DW_TAG_member) 000116: DW_AT_name OscillatorType 000125: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00012a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00012d: 30 = 0xd (DW_TAG_member) 00012e: DW_AT_name HSEState 000137: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00013c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00013f: 30 = 0xd (DW_TAG_member) 000140: DW_AT_name LSEState 000149: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00014e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000151: 30 = 0xd (DW_TAG_member) 000152: DW_AT_name HSIState 00015b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000160: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000163: 30 = 0xd (DW_TAG_member) 000164: DW_AT_name HSICalibrationValue 000178: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00017d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000180: 30 = 0xd (DW_TAG_member) 000181: DW_AT_name LSIState 00018a: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00018f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 000192: 30 = 0xd (DW_TAG_member) 000193: DW_AT_name PLL 000197: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_rcc_ex.h$.2_YWK000_XnipifzSIRa_N00000 00019c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 00019f: 0 null 0001a0: 80 = 0x16 (DW_TAG_typedef) 0001a1: DW_AT_name RCC_OscInitTypeDef 0001b4: DW_AT_type indirect DW_FORM_ref2 0x111 0001b7: DW_AT_decl_file 0x1 0001b8: DW_AT_decl_line 0x5c 0001b9: DW_AT_decl_column 0x2 0001ba: 42 = 0x13 (DW_TAG_structure_type) 0001bb: DW_AT_sibling 0x22f 0001bd: DW_AT_byte_size 0x14 0001be: 30 = 0xd (DW_TAG_member) 0001bf: DW_AT_name ClockType 0001c9: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001ce: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0001d1: 30 = 0xd (DW_TAG_member) 0001d2: DW_AT_name SYSCLKSource 0001df: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001e4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0001e7: 30 = 0xd (DW_TAG_member) 0001e8: DW_AT_name AHBCLKDivider 0001f6: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001fb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0001fe: 30 = 0xd (DW_TAG_member) 0001ff: DW_AT_name APB1CLKDivider 00020e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000213: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000216: 30 = 0xd (DW_TAG_member) 000217: DW_AT_name APB2CLKDivider 000226: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00022b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 00022e: 0 null 00022f: 80 = 0x16 (DW_TAG_typedef) 000230: DW_AT_name RCC_ClkInitTypeDef 000243: DW_AT_type indirect DW_FORM_ref2 0x1ba 000246: DW_AT_decl_file 0x1 000247: DW_AT_decl_line 0x72 000248: DW_AT_decl_column 0x2 000249: 0 null 00024a: 0 padding 00024b: 0 padding ** Section #375 '.rel.debug_info' (SHT_REL) Size : 120 bytes (alignment 4) Symbol table #343 '.symtab' 15 relocations applied to section #82 '.debug_info' ** Section #83 '__ARM_grp.stm32f7xx_hal_gpio_ex.h.2_sV3000_duy21SF0gr5_300000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #84 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 6996 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_GPIO_EX_H 000020: include at line 47 - file 2 000023: end include 000024: line 73 define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) 000049: line 74 define GPIO_AF0_MCO ((uint8_t)0x00U) 000069: line 75 define GPIO_AF0_SWJ ((uint8_t)0x00U) 000089: line 76 define GPIO_AF0_TRACE ((uint8_t)0x00U) 0000ab: line 81 define GPIO_AF1_TIM1 ((uint8_t)0x01U) 0000cc: line 82 define GPIO_AF1_TIM2 ((uint8_t)0x01U) 0000ed: line 84 define GPIO_AF1_UART5 ((uint8_t)0x01U) 00010f: line 85 define GPIO_AF1_I2C4 ((uint8_t)0x01U) 000130: line 91 define GPIO_AF2_TIM3 ((uint8_t)0x02U) 000151: line 92 define GPIO_AF2_TIM4 ((uint8_t)0x02U) 000172: line 93 define GPIO_AF2_TIM5 ((uint8_t)0x02U) 000193: line 98 define GPIO_AF3_TIM8 ((uint8_t)0x03U) 0001b4: line 99 define GPIO_AF3_TIM9 ((uint8_t)0x03U) 0001d5: line 100 define GPIO_AF3_TIM10 ((uint8_t)0x03U) 0001f7: line 101 define GPIO_AF3_TIM11 ((uint8_t)0x03U) 000219: line 102 define GPIO_AF3_LPTIM1 ((uint8_t)0x03U) 00023c: line 103 define GPIO_AF3_CEC ((uint8_t)0x03U) 00025c: line 105 define GPIO_AF3_DFSDM1 ((uint8_t)0x03U) 00027f: line 110 define GPIO_AF4_I2C1 ((uint8_t)0x04U) 0002a0: line 111 define GPIO_AF4_I2C2 ((uint8_t)0x04U) 0002c1: line 112 define GPIO_AF4_I2C3 ((uint8_t)0x04U) 0002e2: line 113 define GPIO_AF4_I2C4 ((uint8_t)0x04U) 000303: line 114 define GPIO_AF4_CEC ((uint8_t)0x04U) 000323: line 116 define GPIO_AF4_USART1 ((uint8_t)0x04) 000345: line 122 define GPIO_AF5_SPI1 ((uint8_t)0x05U) 000366: line 123 define GPIO_AF5_SPI2 ((uint8_t)0x05U) 000387: line 124 define GPIO_AF5_SPI3 ((uint8_t)0x05U) 0003a8: line 125 define GPIO_AF5_SPI4 ((uint8_t)0x05U) 0003c9: line 126 define GPIO_AF5_SPI5 ((uint8_t)0x05U) 0003ea: line 127 define GPIO_AF5_SPI6 ((uint8_t)0x05U) 00040b: line 132 define GPIO_AF6_SPI3 ((uint8_t)0x06U) 00042d: line 133 define GPIO_AF6_SAI1 ((uint8_t)0x06U) 00044f: line 135 define GPIO_AF6_UART4 ((uint8_t)0x06U) 000472: line 136 define GPIO_AF6_DFSDM1 ((uint8_t)0x06U) 000496: line 142 define GPIO_AF7_USART1 ((uint8_t)0x07U) 0004ba: line 143 define GPIO_AF7_USART2 ((uint8_t)0x07U) 0004de: line 144 define GPIO_AF7_USART3 ((uint8_t)0x07U) 000502: line 145 define GPIO_AF7_UART5 ((uint8_t)0x07U) 000525: line 146 define GPIO_AF7_SPDIFRX ((uint8_t)0x07U) 00054a: line 147 define GPIO_AF7_SPI2 ((uint8_t)0x07U) 00056c: line 148 define GPIO_AF7_SPI3 ((uint8_t)0x07U) 00058e: line 150 define GPIO_AF7_SPI6 ((uint8_t)0x07U) 0005b0: line 151 define GPIO_AF7_DFSDM1 ((uint8_t)0x07U) 0005d4: line 157 define GPIO_AF8_UART4 ((uint8_t)0x08U) 0005f7: line 158 define GPIO_AF8_UART5 ((uint8_t)0x08U) 00061a: line 159 define GPIO_AF8_USART6 ((uint8_t)0x08U) 00063e: line 160 define GPIO_AF8_UART7 ((uint8_t)0x08U) 000661: line 161 define GPIO_AF8_UART8 ((uint8_t)0x08U) 000684: line 162 define GPIO_AF8_SPDIFRX ((uint8_t)0x08U) 0006a9: line 163 define GPIO_AF8_SAI2 ((uint8_t)0x08U) 0006cb: line 165 define GPIO_AF8_SPI6 ((uint8_t)0x08U) 0006ed: line 172 define GPIO_AF9_CAN1 ((uint8_t)0x09U) 00070f: line 173 define GPIO_AF9_CAN2 ((uint8_t)0x09U) 000731: line 174 define GPIO_AF9_TIM12 ((uint8_t)0x09U) 000754: line 175 define GPIO_AF9_TIM13 ((uint8_t)0x09U) 000777: line 176 define GPIO_AF9_TIM14 ((uint8_t)0x09U) 00079a: line 177 define GPIO_AF9_QUADSPI ((uint8_t)0x09U) 0007bf: line 179 define GPIO_AF9_LTDC ((uint8_t)0x09U) 0007e1: line 182 define GPIO_AF9_FMC ((uint8_t)0x09U) 000802: line 187 define GPIO_AF10_OTG_FS ((uint8_t)0xAU) 000826: line 188 define GPIO_AF10_OTG_HS ((uint8_t)0xAU) 00084a: line 189 define GPIO_AF10_QUADSPI ((uint8_t)0xAU) 00086f: line 190 define GPIO_AF10_SAI2 ((uint8_t)0xAU) 000891: line 192 define GPIO_AF10_DFSDM1 ((uint8_t)0x0AU) 0008b6: line 193 define GPIO_AF10_SDMMC2 ((uint8_t)0x0AU) 0008db: line 194 define GPIO_AF10_LTDC ((uint8_t)0x0AU) 0008fe: line 200 define GPIO_AF11_ETH ((uint8_t)0x0BU) 000920: line 202 define GPIO_AF11_CAN3 ((uint8_t)0x0BU) 000943: line 203 define GPIO_AF11_SDMMC2 ((uint8_t)0x0BU) 000968: line 204 define GPIO_AF11_I2C4 ((uint8_t)0x0BU) 00098b: line 210 define GPIO_AF12_FMC ((uint8_t)0xCU) 0009ac: line 211 define GPIO_AF12_OTG_HS_FS ((uint8_t)0xCU) 0009d3: line 212 define GPIO_AF12_SDMMC1 ((uint8_t)0xCU) 0009f7: line 214 define GPIO_AF12_MDIOS ((uint8_t)0xCU) 000a1a: line 215 define GPIO_AF12_UART7 ((uint8_t)0xCU) 000a3d: line 221 define GPIO_AF13_DCMI ((uint8_t)0x0DU) 000a60: line 226 define GPIO_AF13_LTDC ((uint8_t)0x0DU) 000a83: line 231 define GPIO_AF14_LTDC ((uint8_t)0x0EU) 000aa6: line 236 define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) 000acd: line 274 define GPIOA_PIN_AVAILABLE GPIO_PIN_All 000af1: line 275 define GPIOB_PIN_AVAILABLE GPIO_PIN_All 000b15: line 276 define GPIOC_PIN_AVAILABLE GPIO_PIN_All 000b39: line 277 define GPIOD_PIN_AVAILABLE GPIO_PIN_All 000b5d: line 278 define GPIOE_PIN_AVAILABLE GPIO_PIN_All 000b81: line 279 define GPIOF_PIN_AVAILABLE GPIO_PIN_All 000ba5: line 280 define GPIOG_PIN_AVAILABLE GPIO_PIN_All 000bc9: line 281 define GPIOI_PIN_AVAILABLE GPIO_PIN_All 000bed: line 282 define GPIOJ_PIN_AVAILABLE GPIO_PIN_All 000c11: line 283 define GPIOH_PIN_AVAILABLE GPIO_PIN_All 000c35: line 284 define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7) 000ca7: line 300 define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U : ((__GPIOx__) == (GPIOB))? 1U : ((__GPIOx__) == (GPIOC))? 2U : ((__GPIOx__) == (GPIOD))? 3U : ((__GPIOx__) == (GPIOE))? 4U : ((__GPIOx__) == (GPIOF))? 5U : ((__GPIOx__) == (GPIOG))? 6U : ((__GPIOx__) == (GPIOH))? 7U : ((__GPIOx__) == (GPIOI))? 8U : ((__GPIOx__) == (GPIOJ))? 9U : 10U) 000e09: line 316 define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__) ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))) || (((__INSTANCE__) == GPIOE) && (((__PIN__) & (GPIOE_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOE_PIN_AVAILABLE)) == (GPIOE_PIN_AVAILABLE))) || (((__INSTANCE__) == GPIOF) && (((__PIN__) & (GPIOF_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOF_PIN_AVAILABLE)) == (GPIOF_PIN_AVAILABLE))) || (((__INSTANCE__) == GPIOG) && (((__PIN__) & (GPIOG_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOG_PIN_AVAILABLE)) == (GPIOG_PIN_AVAILABLE))) || (((__INSTANCE__) == GPIOI) && (((__PIN__) & (GPIOI_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOI_PIN_AVAILABLE)) == (GPIOI_PIN_AVAILABLE))) || (((__INSTANCE__) == GPIOJ) && (((__PIN__) & (GPIOJ_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOJ_PIN_AVAILABLE)) == (GPIOJ_PIN_AVAILABLE))) || (((__INSTANCE__) == GPIOK) && (((__PIN__) & (GPIOK_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOK_PIN_AVAILABLE)) == (GPIOK_PIN_AVAILABLE))) || (((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE)))) 00145c: line 393 define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF9_LTDC) || ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || ((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF14_LTDC)) 001b52: end include 001b53: end of translation unit ** Section #85 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 124 bytes 000000: Header: length 120 (not including this field) version 3 prologue length 111 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_gpio_ex.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 67 70 69 6f 5f 65 78 2e 68 00 01 00 00 000061: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000078: file "" : 00 000079: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio_ex.h:1.0 ** Section #86 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 280 bytes 000000: Header: size 0x114 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio_ex.h 00004d: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000094: DW_AT_language DW_LANG_C89 000096: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010d: DW_AT_macro_info 0x0 000111: DW_AT_stmt_list 0x0 000115: 0 null 000116: 0 padding 000117: 0 padding ** Section #376 '.rel.debug_info' (SHT_REL) Size : 24 bytes (alignment 4) Symbol table #343 '.symtab' 3 relocations applied to section #86 '.debug_info' ** Section #87 '__ARM_grp.stm32f7xx_hal_gpio.h.2_kF2000__UQBfUsVDnd_b00000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #88 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 2776 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_GPIO_H 00001d: include at line 47 - file 2 000020: end include 000021: line 104 define GPIO_PIN_0 ((uint16_t)0x0001U) 000042: line 105 define GPIO_PIN_1 ((uint16_t)0x0002U) 000063: line 106 define GPIO_PIN_2 ((uint16_t)0x0004U) 000084: line 107 define GPIO_PIN_3 ((uint16_t)0x0008U) 0000a5: line 108 define GPIO_PIN_4 ((uint16_t)0x0010U) 0000c6: line 109 define GPIO_PIN_5 ((uint16_t)0x0020U) 0000e7: line 110 define GPIO_PIN_6 ((uint16_t)0x0040U) 000108: line 111 define GPIO_PIN_7 ((uint16_t)0x0080U) 000129: line 112 define GPIO_PIN_8 ((uint16_t)0x0100U) 00014a: line 113 define GPIO_PIN_9 ((uint16_t)0x0200U) 00016b: line 114 define GPIO_PIN_10 ((uint16_t)0x0400U) 00018d: line 115 define GPIO_PIN_11 ((uint16_t)0x0800U) 0001af: line 116 define GPIO_PIN_12 ((uint16_t)0x1000U) 0001d1: line 117 define GPIO_PIN_13 ((uint16_t)0x2000U) 0001f3: line 118 define GPIO_PIN_14 ((uint16_t)0x4000U) 000215: line 119 define GPIO_PIN_15 ((uint16_t)0x8000U) 000237: line 120 define GPIO_PIN_All ((uint16_t)0xFFFFU) 00025a: line 122 define GPIO_PIN_MASK ((uint32_t)0x0000FFFFU) 000282: line 137 define GPIO_MODE_INPUT ((uint32_t)0x00000000U) 0002ad: line 138 define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001U) 0002dc: line 139 define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011U) 00030b: line 140 define GPIO_MODE_AF_PP ((uint32_t)0x00000002U) 000336: line 141 define GPIO_MODE_AF_OD ((uint32_t)0x00000012U) 000361: line 143 define GPIO_MODE_ANALOG ((uint32_t)0x00000003U) 00038d: line 145 define GPIO_MODE_IT_RISING ((uint32_t)0x10110000U) 0003bc: line 146 define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000U) 0003ec: line 147 define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000U) 000423: line 149 define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000U) 000453: line 150 define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000U) 000484: line 151 define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000U) 0004bc: line 160 define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U) 0004eb: line 161 define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001U) 00051d: line 162 define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002U) 00054d: line 163 define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003U) 000582: line 172 define GPIO_NOPULL ((uint32_t)0x00000000U) 0005a9: line 173 define GPIO_PULLUP ((uint32_t)0x00000001U) 0005d0: line 174 define GPIO_PULLDOWN ((uint32_t)0x00000002U) 0005f9: line 194 define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) 000641: line 202 define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) 00068b: line 210 define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) 0006d1: line 218 define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) 000719: line 226 define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) 00076a: include at line 232 - file 3 00076e: end include 00076f: line 282 define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) 0007ca: line 283 define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00)) 000814: line 284 define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) || ((MODE) == GPIO_MODE_OUTPUT_PP) || ((MODE) == GPIO_MODE_OUTPUT_OD) || ((MODE) == GPIO_MODE_AF_PP) || ((MODE) == GPIO_MODE_AF_OD) || ((MODE) == GPIO_MODE_IT_RISING) || ((MODE) == GPIO_MODE_IT_FALLING) || ((MODE) == GPIO_MODE_IT_RISING_FALLING) || ((MODE) == GPIO_MODE_EVT_RISING) || ((MODE) == GPIO_MODE_EVT_FALLING) || ((MODE) == GPIO_MODE_EVT_RISING_FALLING) || ((MODE) == GPIO_MODE_ANALOG)) 0009d3: line 296 define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_LOW) || ((SPEED) == GPIO_SPEED_MEDIUM) || ((SPEED) == GPIO_SPEED_FAST) || ((SPEED) == GPIO_SPEED_HIGH)) 000a6b: line 298 define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || ((PULL) == GPIO_PULLDOWN)) 000ad3: end include 000ad4: end of translation unit ** Section #89 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 148 bytes 000000: Header: length 144 (not including this field) version 3 prologue length 135 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_gpio.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 67 70 69 6f 2e 68 00 01 00 00 00005e: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000075: file "stm32f7xx_hal_gpio_ex.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 67 70 69 6f 5f 65 78 2e 68 00 01 00 00 000090: file "" : 00 000091: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio.h:1.0 ** Section #90 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 440 bytes 000000: Header: size 0x1b4 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio.h 00004a: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000091: DW_AT_language DW_LANG_C89 000093: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010a: DW_AT_macro_info 0x0 00010e: DW_AT_stmt_list 0x0 000112: 42 = 0x13 (DW_TAG_structure_type) 000113: DW_AT_sibling 0x162 000115: DW_AT_byte_size 0x14 000116: 30 = 0xd (DW_TAG_member) 000117: DW_AT_name Pin 00011b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000120: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000123: 30 = 0xd (DW_TAG_member) 000124: DW_AT_name Mode 000129: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00012e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000131: 30 = 0xd (DW_TAG_member) 000132: DW_AT_name Pull 000137: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00013c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 00013f: 30 = 0xd (DW_TAG_member) 000140: DW_AT_name Speed 000146: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00014b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00014e: 30 = 0xd (DW_TAG_member) 00014f: DW_AT_name Alternate 000159: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00015e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000161: 0 null 000162: 80 = 0x16 (DW_TAG_typedef) 000163: DW_AT_name GPIO_InitTypeDef 000174: DW_AT_type indirect DW_FORM_ref2 0x112 000177: DW_AT_decl_file 0x1 000178: DW_AT_decl_line 0x51 000179: DW_AT_decl_column 0x2 00017a: 19 = 0x4 (DW_TAG_enumeration_type) 00017b: DW_AT_sibling 0x1a1 00017d: DW_AT_byte_size 0x1 00017e: 20 = 0x28 (DW_TAG_enumerator) 00017f: DW_AT_name GPIO_PIN_RESET 00018e: DW_AT_const_value indirect DW_FORM_data1 0x0 000190: 20 = 0x28 (DW_TAG_enumerator) 000191: DW_AT_name GPIO_PIN_SET 00019e: DW_AT_const_value indirect DW_FORM_data1 0x1 0001a0: 0 null 0001a1: 80 = 0x16 (DW_TAG_typedef) 0001a2: DW_AT_name GPIO_PinState 0001b0: DW_AT_type indirect DW_FORM_ref2 0x17a 0001b3: DW_AT_decl_file 0x1 0001b4: DW_AT_decl_line 0x5a 0001b5: DW_AT_decl_column 0x2 0001b6: 0 null 0001b7: 0 padding ** Section #377 '.rel.debug_info' (SHT_REL) Size : 64 bytes (alignment 4) Symbol table #343 '.symtab' 8 relocations applied to section #90 '.debug_info' ** Section #91 '__ARM_grp.stm32f7xx_hal_dma_ex.h.2_461000_MwmL$mbEE31_300000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #92 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 1228 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_DMA_EX_H 00001f: include at line 47 - file 2 000022: end include 000023: line 88 define DMA_CHANNEL_0 ((uint32_t)0x00000000U) 00004b: line 89 define DMA_CHANNEL_1 ((uint32_t)0x02000000U) 000073: line 90 define DMA_CHANNEL_2 ((uint32_t)0x04000000U) 00009b: line 91 define DMA_CHANNEL_3 ((uint32_t)0x06000000U) 0000c3: line 92 define DMA_CHANNEL_4 ((uint32_t)0x08000000U) 0000eb: line 93 define DMA_CHANNEL_5 ((uint32_t)0x0A000000U) 000113: line 94 define DMA_CHANNEL_6 ((uint32_t)0x0C000000U) 00013b: line 95 define DMA_CHANNEL_7 ((uint32_t)0x0E000000U) 000163: line 97 define DMA_CHANNEL_8 ((uint32_t)0x10000000U) 00018b: line 98 define DMA_CHANNEL_9 ((uint32_t)0x12000000U) 0001b3: line 99 define DMA_CHANNEL_10 ((uint32_t)0x14000000U) 0001dc: line 100 define DMA_CHANNEL_11 ((uint32_t)0x16000000U) 000205: line 101 define DMA_CHANNEL_12 ((uint32_t)0x18000000U) 00022e: line 102 define DMA_CHANNEL_13 ((uint32_t)0x1A000000U) 000257: line 103 define DMA_CHANNEL_14 ((uint32_t)0x1C000000U) 000280: line 104 define DMA_CHANNEL_15 ((uint32_t)0x1E000000U) 0002a9: line 144 define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || ((CHANNEL) == DMA_CHANNEL_1) || ((CHANNEL) == DMA_CHANNEL_2) || ((CHANNEL) == DMA_CHANNEL_3) || ((CHANNEL) == DMA_CHANNEL_4) || ((CHANNEL) == DMA_CHANNEL_5) || ((CHANNEL) == DMA_CHANNEL_6) || ((CHANNEL) == DMA_CHANNEL_7) || ((CHANNEL) == DMA_CHANNEL_8) || ((CHANNEL) == DMA_CHANNEL_9) || ((CHANNEL) == DMA_CHANNEL_10) || ((CHANNEL) == DMA_CHANNEL_11) || ((CHANNEL) == DMA_CHANNEL_12) || ((CHANNEL) == DMA_CHANNEL_13) || ((CHANNEL) == DMA_CHANNEL_14) || ((CHANNEL) == DMA_CHANNEL_15)) 0004c9: end include 0004ca: end of translation unit ** Section #93 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 124 bytes 000000: Header: length 120 (not including this field) version 3 prologue length 110 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_dma_ex.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 6d 61 5f 65 78 2e 68 00 01 00 00 000060: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000077: file "" : 00 000078: DW_LNS_negate_stmt : 06 000079: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma_ex.h:1.0 [ ** Section #94 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 336 bytes 000000: Header: size 0x14c bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma_ex.h 00004c: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000093: DW_AT_language DW_LANG_C89 000095: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010c: DW_AT_macro_info 0x0 000110: DW_AT_stmt_list 0x0 000114: 19 = 0x4 (DW_TAG_enumeration_type) 000115: DW_AT_sibling 0x12f 000117: DW_AT_byte_size 0x1 000118: 20 = 0x28 (DW_TAG_enumerator) 000119: DW_AT_name MEMORY0 000121: DW_AT_const_value indirect DW_FORM_data1 0x0 000123: 20 = 0x28 (DW_TAG_enumerator) 000124: DW_AT_name MEMORY1 00012c: DW_AT_const_value indirect DW_FORM_data1 0x1 00012e: 0 null 00012f: 80 = 0x16 (DW_TAG_typedef) 000130: DW_AT_name HAL_DMA_MemoryTypeDef 000146: DW_AT_type indirect DW_FORM_ref2 0x114 000149: DW_AT_decl_file 0x1 00014a: DW_AT_decl_line 0x47 00014b: DW_AT_decl_column 0x2 00014c: 0 null 00014d: 0 padding 00014e: 0 padding 00014f: 0 padding ** Section #378 '.rel.debug_info' (SHT_REL) Size : 24 bytes (alignment 4) Symbol table #343 '.symtab' 3 relocations applied to section #94 '.debug_info' ** Section #95 '__ARM_grp.stm32f7xx_hal_dma.h.2_wD1100_gh0hnOcebnc_s10000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #96 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 11988 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_DMA_H 00001c: include at line 47 - file 2 00001f: end include 000020: line 204 define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) 00004e: line 205 define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) 00007a: line 206 define HAL_DMA_ERROR_FE ((uint32_t)0x00000002U) 0000a6: line 207 define HAL_DMA_ERROR_DME ((uint32_t)0x00000004U) 0000d3: line 208 define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) 000104: line 209 define HAL_DMA_ERROR_PARAM ((uint32_t)0x00000040U) 000133: line 210 define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000080U) 000164: line 211 define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100U) 00019b: line 220 define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) 0001cb: line 221 define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) 0001fe: line 222 define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) 000231: line 231 define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) 00025e: line 232 define DMA_PINC_DISABLE ((uint32_t)0x00000000U) 00028a: line 241 define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) 0002b7: line 242 define DMA_MINC_DISABLE ((uint32_t)0x00000000U) 0002e3: line 251 define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) 000312: line 252 define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) 00034a: line 253 define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) 00037e: line 262 define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) 0003ad: line 263 define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) 0003e5: line 264 define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) 000419: line 273 define DMA_NORMAL ((uint32_t)0x00000000U) 00043f: line 274 define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) 000469: line 275 define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) 000493: line 284 define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) 0004bf: line 285 define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) 0004f0: line 286 define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) 00051f: line 287 define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) 000551: line 296 define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U) 000581: line 297 define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) 0005b4: line 306 define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U) 0005ef: line 307 define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) 00062a: line 308 define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) 00066a: line 309 define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) 00069f: line 318 define DMA_MBURST_SINGLE ((uint32_t)0x00000000U) 0006cc: line 319 define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) 0006fd: line 320 define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) 00072e: line 321 define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) 00075e: line 330 define DMA_PBURST_SINGLE ((uint32_t)0x00000000U) 00078b: line 331 define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) 0007bc: line 332 define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) 0007ed: line 333 define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) 00081d: line 342 define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE) 000844: line 343 define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE) 00086b: line 344 define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE) 000892: line 345 define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE) 0008bb: line 346 define DMA_IT_FE ((uint32_t)0x00000080U) 0008e0: line 355 define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001U) 00090c: line 356 define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004U) 000939: line 357 define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U) 000965: line 358 define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U) 000991: line 359 define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U) 0009bd: line 360 define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U) 0009e9: line 361 define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U) 000a16: line 362 define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U) 000a42: line 363 define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U) 000a6e: line 364 define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U) 000a9a: line 365 define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U) 000ac6: line 366 define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U) 000af3: line 367 define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U) 000b1f: line 368 define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U) 000b4b: line 369 define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U) 000b77: line 370 define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U) 000ba3: line 371 define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U) 000bd0: line 372 define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U) 000bfc: line 373 define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U) 000c28: line 374 define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U) 000c54: line 389 define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 000cac: line 403 define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS))) 000cfd: line 410 define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN) 000d49: line 417 define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN) 000d97: line 426 define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 : DMA_FLAG_TCIF3_7) 0011d1: line 446 define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 : DMA_FLAG_HTIF3_7) 00160b: line 466 define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 : DMA_FLAG_TEIF3_7) 001a45: line 486 define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 : DMA_FLAG_FEIF3_7) 001e7f: line 506 define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 : DMA_FLAG_DMEIF3_7) 0022c7: line 534 define __HAL_DMA_GET_FLAG(__HANDLE__,__FLAG__) (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) : ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) : ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) 00241f: line 552 define __HAL_DMA_CLEAR_FLAG(__HANDLE__,__FLAG__) (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) : ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) : ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) 00257d: line 569 define __HAL_DMA_ENABLE_IT(__HANDLE__,__INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__))) 002633: line 584 define __HAL_DMA_DISABLE_IT(__HANDLE__,__INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__))) 0026ec: line 599 define __HAL_DMA_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR & (__INTERRUPT__))) 0027a4: line 620 define __HAL_DMA_SET_COUNTER(__HANDLE__,__COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__)) 00280e: line 628 define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR) 002852: include at line 632 - file 3 002856: end include 002857: line 695 define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 0028f1: line 699 define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U)) 002938: line 701 define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || ((STATE) == DMA_PINC_DISABLE)) 00299e: line 704 define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || ((STATE) == DMA_MINC_DISABLE)) 002a00: line 707 define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || ((SIZE) == DMA_PDATAALIGN_HALFWORD) || ((SIZE) == DMA_PDATAALIGN_WORD)) 002a91: line 711 define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || ((SIZE) == DMA_MDATAALIGN_HALFWORD) || ((SIZE) == DMA_MDATAALIGN_WORD )) 002b1f: line 715 define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || ((MODE) == DMA_CIRCULAR) || ((MODE) == DMA_PFCTRL)) 002b84: line 719 define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || ((PRIORITY) == DMA_PRIORITY_MEDIUM) || ((PRIORITY) == DMA_PRIORITY_HIGH) || ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 002c3b: line 724 define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || ((STATE) == DMA_FIFOMODE_ENABLE)) 002ca5: line 727 define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) 002d8e: line 732 define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || ((BURST) == DMA_MBURST_INC4) || ((BURST) == DMA_MBURST_INC8) || ((BURST) == DMA_MBURST_INC16)) 002e2e: line 737 define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || ((BURST) == DMA_PBURST_INC4) || ((BURST) == DMA_PBURST_INC8) || ((BURST) == DMA_PBURST_INC16)) 002ed2: end include 002ed3: end of translation unit ** Section #97 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 148 bytes 000000: Header: length 144 (not including this field) version 3 prologue length 133 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_dma.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 6d 61 2e 68 00 01 00 00 00005d: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000074: file "stm32f7xx_hal_dma_ex.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 6d 61 5f 65 78 2e 68 00 01 00 00 00008e: file "" : 00 00008f: DW_LNS_negate_stmt : 06 000090: DW_LNS_negate_stmt : 06 000091: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma.h:1.0 ** Section #98 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 1492 bytes 000000: Header: size 0x5d0 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma.h 000049: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000090: DW_AT_language DW_LANG_C89 000092: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 000109: DW_AT_macro_info 0x0 00010d: DW_AT_stmt_list 0x0 000111: 117 = 0x3b (DW_TAG_unspecified_type) 000112: DW_AT_name void 000117: 34 = 0xf (DW_TAG_pointer_type) 000118: DW_AT_type indirect DW_FORM_ref2 0x111 00011b: 34 = 0xf (DW_TAG_pointer_type) 00011c: DW_AT_type indirect DW_FORM_ref2 0x443 00011f: 116 = 0x35 (DW_TAG_volatile_type) 000120: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000125: 80 = 0x16 (DW_TAG_typedef) 000126: DW_AT_name DMA_InitTypeDef 000136: DW_AT_type indirect DW_FORM_ref2 0x1ba 000139: DW_AT_decl_file 0x1 00013a: DW_AT_decl_line 0x73 00013b: DW_AT_decl_column 0x2 00013c: 80 = 0x16 (DW_TAG_typedef) 00013d: DW_AT_name HAL_DMA_StateTypeDef 000152: DW_AT_type indirect DW_FORM_ref2 0x2ad 000155: DW_AT_decl_file 0x1 000156: DW_AT_decl_line 0x80 000158: DW_AT_decl_column 0x2 000159: 80 = 0x16 (DW_TAG_typedef) 00015a: DW_AT_name HAL_DMA_LevelCompleteTypeDef 000177: DW_AT_type indirect DW_FORM_ref2 0x33d 00017a: DW_AT_decl_file 0x1 00017b: DW_AT_decl_line 0x89 00017d: DW_AT_decl_column 0x2 00017e: 80 = 0x16 (DW_TAG_typedef) 00017f: DW_AT_name HAL_DMA_CallbackIDTypeDef 000199: DW_AT_type indirect DW_FORM_ref2 0x374 00019c: DW_AT_decl_file 0x1 00019d: DW_AT_decl_line 0x97 00019f: DW_AT_decl_column 0x2 0001a0: 80 = 0x16 (DW_TAG_typedef) 0001a1: DW_AT_name DMA_HandleTypeDef 0001b3: DW_AT_type indirect DW_FORM_ref2 0x443 0001b6: DW_AT_decl_file 0x1 0001b7: DW_AT_decl_line 0xba 0001b9: DW_AT_decl_column 0x2 0001ba: 42 = 0x13 (DW_TAG_structure_type) 0001bb: DW_AT_sibling 0x2ad 0001bd: DW_AT_byte_size 0x30 0001be: 30 = 0xd (DW_TAG_member) 0001bf: DW_AT_name Channel 0001c7: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001cc: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0001cf: 30 = 0xd (DW_TAG_member) 0001d0: DW_AT_name Direction 0001da: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001df: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0001e2: 30 = 0xd (DW_TAG_member) 0001e3: DW_AT_name PeriphInc 0001ed: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001f2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0001f5: 30 = 0xd (DW_TAG_member) 0001f6: DW_AT_name MemInc 0001fd: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000202: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000205: 30 = 0xd (DW_TAG_member) 000206: DW_AT_name PeriphDataAlignment 00021a: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00021f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000222: 30 = 0xd (DW_TAG_member) 000223: DW_AT_name MemDataAlignment 000234: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000239: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 00023c: 30 = 0xd (DW_TAG_member) 00023d: DW_AT_name Mode 000242: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000247: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 00024a: 30 = 0xd (DW_TAG_member) 00024b: DW_AT_name Priority 000254: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000259: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 00025c: 30 = 0xd (DW_TAG_member) 00025d: DW_AT_name FIFOMode 000266: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00026b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 00026e: 30 = 0xd (DW_TAG_member) 00026f: DW_AT_name FIFOThreshold 00027d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000282: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 000285: 30 = 0xd (DW_TAG_member) 000286: DW_AT_name MemBurst 00028f: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000294: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 000297: 30 = 0xd (DW_TAG_member) 000298: DW_AT_name PeriphBurst 0002a4: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002a9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 0002ac: 0 null 0002ad: 19 = 0x4 (DW_TAG_enumeration_type) 0002ae: DW_AT_sibling 0x33d 0002b0: DW_AT_byte_size 0x1 0002b1: 20 = 0x28 (DW_TAG_enumerator) 0002b2: DW_AT_name HAL_DMA_STATE_RESET 0002c6: DW_AT_const_value indirect DW_FORM_data1 0x0 0002c8: 20 = 0x28 (DW_TAG_enumerator) 0002c9: DW_AT_name HAL_DMA_STATE_READY 0002dd: DW_AT_const_value indirect DW_FORM_data1 0x1 0002df: 20 = 0x28 (DW_TAG_enumerator) 0002e0: DW_AT_name HAL_DMA_STATE_BUSY 0002f3: DW_AT_const_value indirect DW_FORM_data1 0x2 0002f5: 20 = 0x28 (DW_TAG_enumerator) 0002f6: DW_AT_name HAL_DMA_STATE_TIMEOUT 00030c: DW_AT_const_value indirect DW_FORM_data1 0x3 00030e: 20 = 0x28 (DW_TAG_enumerator) 00030f: DW_AT_name HAL_DMA_STATE_ERROR 000323: DW_AT_const_value indirect DW_FORM_data1 0x4 000325: 20 = 0x28 (DW_TAG_enumerator) 000326: DW_AT_name HAL_DMA_STATE_ABORT 00033a: DW_AT_const_value indirect DW_FORM_data1 0x5 00033c: 0 null 00033d: 19 = 0x4 (DW_TAG_enumeration_type) 00033e: DW_AT_sibling 0x374 000340: DW_AT_byte_size 0x1 000341: 20 = 0x28 (DW_TAG_enumerator) 000342: DW_AT_name HAL_DMA_FULL_TRANSFER 000358: DW_AT_const_value indirect DW_FORM_data1 0x0 00035a: 20 = 0x28 (DW_TAG_enumerator) 00035b: DW_AT_name HAL_DMA_HALF_TRANSFER 000371: DW_AT_const_value indirect DW_FORM_data1 0x1 000373: 0 null 000374: 19 = 0x4 (DW_TAG_enumeration_type) 000375: DW_AT_sibling 0x443 000377: DW_AT_byte_size 0x1 000378: 20 = 0x28 (DW_TAG_enumerator) 000379: DW_AT_name HAL_DMA_XFER_CPLT_CB_ID 000391: DW_AT_const_value indirect DW_FORM_data1 0x0 000393: 20 = 0x28 (DW_TAG_enumerator) 000394: DW_AT_name HAL_DMA_XFER_HALFCPLT_CB_ID 0003b0: DW_AT_const_value indirect DW_FORM_data1 0x1 0003b2: 20 = 0x28 (DW_TAG_enumerator) 0003b3: DW_AT_name HAL_DMA_XFER_M1CPLT_CB_ID 0003cd: DW_AT_const_value indirect DW_FORM_data1 0x2 0003cf: 20 = 0x28 (DW_TAG_enumerator) 0003d0: DW_AT_name HAL_DMA_XFER_M1HALFCPLT_CB_ID 0003ee: DW_AT_const_value indirect DW_FORM_data1 0x3 0003f0: 20 = 0x28 (DW_TAG_enumerator) 0003f1: DW_AT_name HAL_DMA_XFER_ERROR_CB_ID 00040a: DW_AT_const_value indirect DW_FORM_data1 0x4 00040c: 20 = 0x28 (DW_TAG_enumerator) 00040d: DW_AT_name HAL_DMA_XFER_ABORT_CB_ID 000426: DW_AT_const_value indirect DW_FORM_data1 0x5 000428: 20 = 0x28 (DW_TAG_enumerator) 000429: DW_AT_name HAL_DMA_XFER_ALL_CB_ID 000440: DW_AT_const_value indirect DW_FORM_data1 0x6 000442: 0 null 000443: 41 = 0x13 (DW_TAG_structure_type) 000444: DW_AT_sibling 0x5c8 000446: DW_AT_name __DMA_HandleTypeDef 00045a: DW_AT_byte_size 0x60 00045b: 30 = 0xd (DW_TAG_member) 00045c: DW_AT_name Instance 000465: DW_AT_type indirect DW_FORM_ref2 0x5c8 000468: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00046b: 30 = 0xd (DW_TAG_member) 00046c: DW_AT_name Init 000471: DW_AT_type indirect DW_FORM_ref2 0x125 000474: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000477: 30 = 0xd (DW_TAG_member) 000478: DW_AT_name Lock 00047d: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 000482: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 000485: 30 = 0xd (DW_TAG_member) 000486: DW_AT_name State 00048c: DW_AT_type indirect DW_FORM_ref2 0x5ce 00048f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 53 } 000492: 30 = 0xd (DW_TAG_member) 000493: DW_AT_name Parent 00049a: DW_AT_type indirect DW_FORM_ref2 0x117 00049d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 0004a0: 79 = 0x15 (DW_TAG_subroutine_type) 0004a1: DW_AT_sibling 0x4a8 0004a3: 37 = 0x5 (DW_TAG_formal_parameter) 0004a4: DW_AT_type indirect DW_FORM_ref2 0x11b 0004a7: 0 null 0004a8: 34 = 0xf (DW_TAG_pointer_type) 0004a9: DW_AT_type indirect DW_FORM_ref2 0x4a0 0004ac: 30 = 0xd (DW_TAG_member) 0004ad: DW_AT_name XferCpltCallback 0004be: DW_AT_type indirect DW_FORM_ref2 0x4a8 0004c1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 60 } 0004c4: 79 = 0x15 (DW_TAG_subroutine_type) 0004c5: DW_AT_sibling 0x4cc 0004c7: 37 = 0x5 (DW_TAG_formal_parameter) 0004c8: DW_AT_type indirect DW_FORM_ref2 0x11b 0004cb: 0 null 0004cc: 34 = 0xf (DW_TAG_pointer_type) 0004cd: DW_AT_type indirect DW_FORM_ref2 0x4c4 0004d0: 30 = 0xd (DW_TAG_member) 0004d1: DW_AT_name XferHalfCpltCallback 0004e6: DW_AT_type indirect DW_FORM_ref2 0x4cc 0004e9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 64 } 0004ec: 79 = 0x15 (DW_TAG_subroutine_type) 0004ed: DW_AT_sibling 0x4f4 0004ef: 37 = 0x5 (DW_TAG_formal_parameter) 0004f0: DW_AT_type indirect DW_FORM_ref2 0x11b 0004f3: 0 null 0004f4: 34 = 0xf (DW_TAG_pointer_type) 0004f5: DW_AT_type indirect DW_FORM_ref2 0x4ec 0004f8: 30 = 0xd (DW_TAG_member) 0004f9: DW_AT_name XferM1CpltCallback 00050c: DW_AT_type indirect DW_FORM_ref2 0x4f4 00050f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 68 } 000512: 79 = 0x15 (DW_TAG_subroutine_type) 000513: DW_AT_sibling 0x51a 000515: 37 = 0x5 (DW_TAG_formal_parameter) 000516: DW_AT_type indirect DW_FORM_ref2 0x11b 000519: 0 null 00051a: 34 = 0xf (DW_TAG_pointer_type) 00051b: DW_AT_type indirect DW_FORM_ref2 0x512 00051e: 30 = 0xd (DW_TAG_member) 00051f: DW_AT_name XferM1HalfCpltCallback 000536: DW_AT_type indirect DW_FORM_ref2 0x51a 000539: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 72 } 00053c: 79 = 0x15 (DW_TAG_subroutine_type) 00053d: DW_AT_sibling 0x544 00053f: 37 = 0x5 (DW_TAG_formal_parameter) 000540: DW_AT_type indirect DW_FORM_ref2 0x11b 000543: 0 null 000544: 34 = 0xf (DW_TAG_pointer_type) 000545: DW_AT_type indirect DW_FORM_ref2 0x53c 000548: 30 = 0xd (DW_TAG_member) 000549: DW_AT_name XferErrorCallback 00055b: DW_AT_type indirect DW_FORM_ref2 0x544 00055e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 76 } 000561: 79 = 0x15 (DW_TAG_subroutine_type) 000562: DW_AT_sibling 0x569 000564: 37 = 0x5 (DW_TAG_formal_parameter) 000565: DW_AT_type indirect DW_FORM_ref2 0x11b 000568: 0 null 000569: 34 = 0xf (DW_TAG_pointer_type) 00056a: DW_AT_type indirect DW_FORM_ref2 0x561 00056d: 30 = 0xd (DW_TAG_member) 00056e: DW_AT_name XferAbortCallback 000580: DW_AT_type indirect DW_FORM_ref2 0x569 000583: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 80 } 000586: 30 = 0xd (DW_TAG_member) 000587: DW_AT_name ErrorCode 000591: DW_AT_type indirect DW_FORM_ref2 0x11f 000594: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 84 } 000597: 30 = 0xd (DW_TAG_member) 000598: DW_AT_name StreamBaseAddress 0005aa: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0005af: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 88 } 0005b2: 30 = 0xd (DW_TAG_member) 0005b3: DW_AT_name StreamIndex 0005bf: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0005c4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 92 } 0005c7: 0 null 0005c8: 34 = 0xf (DW_TAG_pointer_type) 0005c9: DW_AT_type indirect DW_FORM_ref_addr 0x10c6+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 0005ce: 116 = 0x35 (DW_TAG_volatile_type) 0005cf: DW_AT_type indirect DW_FORM_ref2 0x13c 0005d2: 0 null 0005d3: 0 padding ** Section #379 '.rel.debug_info' (SHT_REL) Size : 160 bytes (alignment 4) Symbol table #343 '.symtab' 20 relocations applied to section #98 '.debug_info' ** Section #99 '__ARM_grp.stm32f7xx_hal_cortex.h.2_o44000_BXylCw07LJ6_h00000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #100 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 5664 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_CORTEX_H 00001f: include at line 47 - file 2 000022: end include 000023: line 108 define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007U) 000052: line 110 define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006U) 000081: line 112 define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005U) 0000b0: line 114 define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004U) 0000df: line 116 define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003U) 00010e: line 125 define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U) 000144: line 126 define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) 000175: line 136 define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U) 0001a7: line 137 define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U) 0001d4: line 138 define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U) 000206: line 139 define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U) 000233: line 147 define MPU_REGION_ENABLE ((uint8_t)0x01U) 000259: line 148 define MPU_REGION_DISABLE ((uint8_t)0x00U) 000280: line 156 define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U) 0002b2: line 157 define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U) 0002e5: line 165 define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U) 00030e: line 166 define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U) 00033b: line 174 define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U) 000364: line 175 define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U) 000391: line 183 define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U) 0003bb: line 184 define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U) 0003e9: line 192 define MPU_TEX_LEVEL0 ((uint8_t)0x00U) 00040c: line 193 define MPU_TEX_LEVEL1 ((uint8_t)0x01U) 00042f: line 194 define MPU_TEX_LEVEL2 ((uint8_t)0x02U) 000452: line 202 define MPU_REGION_SIZE_32B ((uint8_t)0x04U) 00047a: line 203 define MPU_REGION_SIZE_64B ((uint8_t)0x05U) 0004a2: line 204 define MPU_REGION_SIZE_128B ((uint8_t)0x06U) 0004cb: line 205 define MPU_REGION_SIZE_256B ((uint8_t)0x07U) 0004f4: line 206 define MPU_REGION_SIZE_512B ((uint8_t)0x08U) 00051d: line 207 define MPU_REGION_SIZE_1KB ((uint8_t)0x09U) 000545: line 208 define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) 00056d: line 209 define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) 000595: line 210 define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) 0005bd: line 211 define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) 0005e6: line 212 define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) 00060f: line 213 define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) 000638: line 214 define MPU_REGION_SIZE_128KB ((uint8_t)0x10U) 000662: line 215 define MPU_REGION_SIZE_256KB ((uint8_t)0x11U) 00068c: line 216 define MPU_REGION_SIZE_512KB ((uint8_t)0x12U) 0006b6: line 217 define MPU_REGION_SIZE_1MB ((uint8_t)0x13U) 0006de: line 218 define MPU_REGION_SIZE_2MB ((uint8_t)0x14U) 000706: line 219 define MPU_REGION_SIZE_4MB ((uint8_t)0x15U) 00072e: line 220 define MPU_REGION_SIZE_8MB ((uint8_t)0x16U) 000756: line 221 define MPU_REGION_SIZE_16MB ((uint8_t)0x17U) 00077f: line 222 define MPU_REGION_SIZE_32MB ((uint8_t)0x18U) 0007a8: line 223 define MPU_REGION_SIZE_64MB ((uint8_t)0x19U) 0007d1: line 224 define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) 0007fb: line 225 define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) 000825: line 226 define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) 00084f: line 227 define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) 000877: line 228 define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) 00089f: line 229 define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) 0008c7: line 237 define MPU_REGION_NO_ACCESS ((uint8_t)0x00U) 0008f0: line 238 define MPU_REGION_PRIV_RW ((uint8_t)0x01U) 000917: line 239 define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U) 000942: line 240 define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U) 00096d: line 241 define MPU_REGION_PRIV_RO ((uint8_t)0x05U) 000994: line 242 define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U) 0009bf: line 250 define MPU_REGION_NUMBER0 ((uint8_t)0x00U) 0009e6: line 251 define MPU_REGION_NUMBER1 ((uint8_t)0x01U) 000a0d: line 252 define MPU_REGION_NUMBER2 ((uint8_t)0x02U) 000a34: line 253 define MPU_REGION_NUMBER3 ((uint8_t)0x03U) 000a5b: line 254 define MPU_REGION_NUMBER4 ((uint8_t)0x04U) 000a82: line 255 define MPU_REGION_NUMBER5 ((uint8_t)0x05U) 000aa9: line 256 define MPU_REGION_NUMBER6 ((uint8_t)0x06U) 000ad0: line 257 define MPU_REGION_NUMBER7 ((uint8_t)0x07U) 000af7: line 322 define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || ((GROUP) == NVIC_PRIORITYGROUP_1) || ((GROUP) == NVIC_PRIORITYGROUP_2) || ((GROUP) == NVIC_PRIORITYGROUP_3) || ((GROUP) == NVIC_PRIORITYGROUP_4)) 000bd0: line 328 define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) 000c0e: line 330 define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) 000c45: line 332 define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) 000c70: line 334 define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) 000ce5: line 338 define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || ((STATE) == MPU_REGION_DISABLE)) 000d48: line 341 define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) 000dc8: line 344 define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) 000e37: line 347 define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) 000ea6: line 350 define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) 000f18: line 353 define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || ((TYPE) == MPU_TEX_LEVEL1) || ((TYPE) == MPU_TEX_LEVEL2)) 000f8b: line 357 define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || ((TYPE) == MPU_REGION_PRIV_RW) || ((TYPE) == MPU_REGION_PRIV_RW_URO) || ((TYPE) == MPU_REGION_FULL_ACCESS) || ((TYPE) == MPU_REGION_PRIV_RO) || ((TYPE) == MPU_REGION_PRIV_RO_URO)) 001090: line 364 define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || ((NUMBER) == MPU_REGION_NUMBER1) || ((NUMBER) == MPU_REGION_NUMBER2) || ((NUMBER) == MPU_REGION_NUMBER3) || ((NUMBER) == MPU_REGION_NUMBER4) || ((NUMBER) == MPU_REGION_NUMBER5) || ((NUMBER) == MPU_REGION_NUMBER6) || ((NUMBER) == MPU_REGION_NUMBER7)) 0011cf: line 373 define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || ((SIZE) == MPU_REGION_SIZE_64B) || ((SIZE) == MPU_REGION_SIZE_128B) || ((SIZE) == MPU_REGION_SIZE_256B) || ((SIZE) == MPU_REGION_SIZE_512B) || ((SIZE) == MPU_REGION_SIZE_1KB) || ((SIZE) == MPU_REGION_SIZE_2KB) || ((SIZE) == MPU_REGION_SIZE_4KB) || ((SIZE) == MPU_REGION_SIZE_8KB) || ((SIZE) == MPU_REGION_SIZE_16KB) || ((SIZE) == MPU_REGION_SIZE_32KB) || ((SIZE) == MPU_REGION_SIZE_64KB) || ((SIZE) == MPU_REGION_SIZE_128KB) || ((SIZE) == MPU_REGION_SIZE_256KB) || ((SIZE) == MPU_REGION_SIZE_512KB) || ((SIZE) == MPU_REGION_SIZE_1MB) || ((SIZE) == MPU_REGION_SIZE_2MB) || ((SIZE) == MPU_REGION_SIZE_4MB) || ((SIZE) == MPU_REGION_SIZE_8MB) || ((SIZE) == MPU_REGION_SIZE_16MB) || ((SIZE) == MPU_REGION_SIZE_32MB) || ((SIZE) == MPU_REGION_SIZE_64MB) || ((SIZE) == MPU_REGION_SIZE_128MB) || ((SIZE) == MPU_REGION_SIZE_256MB) || ((SIZE) == MPU_REGION_SIZE_512MB) || ((SIZE) == MPU_REGION_SIZE_1GB) || ((SIZE) == MPU_REGION_SIZE_2GB) || ((SIZE) == MPU_REGION_SIZE_4GB)) 0015d3: line 402 define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU) 00161d: end include 00161e: end of translation unit ** Section #101 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 124 bytes 000000: Header: length 120 (not including this field) version 3 prologue length 110 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_cortex.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 63 6f 72 74 65 78 2e 68 00 01 00 00 000060: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000077: file "" : 00 000078: DW_LNS_negate_stmt : 06 000079: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_cortex.h:1.0 [ ** Section #102 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 540 bytes 000000: Header: size 0x218 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_cortex.h 00004c: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000093: DW_AT_language DW_LANG_C89 000095: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010c: DW_AT_macro_info 0x0 000110: DW_AT_stmt_list 0x0 000114: 42 = 0x13 (DW_TAG_structure_type) 000115: DW_AT_sibling 0x1fb 000117: DW_AT_byte_size 0x10 000118: 30 = 0xd (DW_TAG_member) 000119: DW_AT_name Enable 000120: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000125: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000128: 30 = 0xd (DW_TAG_member) 000129: DW_AT_name Number 000130: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000135: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 1 } 000138: 30 = 0xd (DW_TAG_member) 000139: DW_AT_name BaseAddress 000145: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00014a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00014d: 30 = 0xd (DW_TAG_member) 00014e: DW_AT_name Size 000153: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000158: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 00015b: 30 = 0xd (DW_TAG_member) 00015c: DW_AT_name SubRegionDisable 00016d: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000172: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 9 } 000175: 30 = 0xd (DW_TAG_member) 000176: DW_AT_name TypeExtField 000183: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000188: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 10 } 00018b: 30 = 0xd (DW_TAG_member) 00018c: DW_AT_name AccessPermission 00019d: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001a2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 11 } 0001a5: 30 = 0xd (DW_TAG_member) 0001a6: DW_AT_name DisableExec 0001b2: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001b7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0001ba: 30 = 0xd (DW_TAG_member) 0001bb: DW_AT_name IsShareable 0001c7: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001cc: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 13 } 0001cf: 30 = 0xd (DW_TAG_member) 0001d0: DW_AT_name IsCacheable 0001dc: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001e1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 14 } 0001e4: 30 = 0xd (DW_TAG_member) 0001e5: DW_AT_name IsBufferable 0001f2: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001f7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 15 } 0001fa: 0 null 0001fb: 80 = 0x16 (DW_TAG_typedef) 0001fc: DW_AT_name MPU_Region_InitTypeDef 000213: DW_AT_type indirect DW_FORM_ref2 0x114 000216: DW_AT_decl_file 0x1 000217: DW_AT_decl_line 0x59 000218: DW_AT_decl_column 0x2 000219: 0 null 00021a: 0 padding 00021b: 0 padding ** Section #380 '.rel.debug_info' (SHT_REL) Size : 112 bytes (alignment 4) Symbol table #343 '.symtab' 14 relocations applied to section #102 '.debug_info' ** Section #103 '__ARM_grp.stm32f7xx_hal_adc_ex.h.2_414000_CgAD9qhmCn2_i00000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #104 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 5488 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_ADC_EX_H 00001b: include at line 47 - file 2 00001e: end include 00001f: line 158 define ADC_MODE_INDEPENDENT ((uint32_t)0x00000000U) 00004f: line 159 define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)ADC_CCR_MULTI_0) 000091: line 160 define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)ADC_CCR_MULTI_1) 0000d1: line 161 define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0)) 00011d: line 162 define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1)) 000167: line 163 define ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0)) 0001c0: line 164 define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0)) 00020a: line 165 define ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0)) 000262: line 166 define ADC_TRIPLEMODE_REGSIMULT_AlterTrig ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1)) 0002b8: line 167 define ADC_TRIPLEMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0)) 000318: line 168 define ADC_TRIPLEMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1)) 000376: line 169 define ADC_TRIPLEMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0)) 0003e3: line 170 define ADC_TRIPLEMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0)) 000441: line 178 define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000U) 000477: line 179 define ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0) 0004a8: line 180 define ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1) 0004d9: line 181 define ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA) 000508: line 189 define ADC_EXTERNALTRIGINJECCONVEDGE_NONE ((uint32_t)0x00000000U) 000546: line 190 define ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0) 00058b: line 191 define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1) 0005d1: line 192 define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN) 00061b: line 200 define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)0x00000000U) 000658: line 201 define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ((uint32_t)ADC_CR2_JEXTSEL_0) 00069a: line 202 define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ((uint32_t)ADC_CR2_JEXTSEL_1) 0006dd: line 203 define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) 000735: line 204 define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ((uint32_t)ADC_CR2_JEXTSEL_2) 000777: line 205 define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) 0007d0: line 207 define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) 00083c: line 208 define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ((uint32_t)ADC_CR2_JEXTSEL_3) 000880: line 209 define ADC_EXTERNALTRIGINJECCONV_T8_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0)) 0008d9: line 210 define ADC_EXTERNALTRIGINJECCONV_T8_TRGO2 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1)) 000933: line 211 define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) 00099f: line 212 define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2)) 0009f8: line 213 define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) 000a64: line 214 define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1)) 000ad1: line 215 define ADC_INJECTED_SOFTWARE_START ((uint32_t)ADC_CR2_JEXTSEL + 1) 000b10: line 223 define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001U) 000b3f: line 224 define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002U) 000b6e: line 225 define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003U) 000b9d: line 226 define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004U) 000bcc: line 234 define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18 | 0x10000000U) 000c0f: line 298 define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18) || ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR)) 000c73: line 301 define IS_ADC_MODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || ((__MODE__) == ADC_DUALMODE_REGSIMULT) || ((__MODE__) == ADC_DUALMODE_INTERL) || ((__MODE__) == ADC_DUALMODE_ALTERTRIG) || ((__MODE__) == ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT) || ((__MODE__) == ADC_TRIPLEMODE_REGSIMULT_AlterTrig) || ((__MODE__) == ADC_TRIPLEMODE_INJECSIMULT) || ((__MODE__) == ADC_TRIPLEMODE_REGSIMULT) || ((__MODE__) == ADC_TRIPLEMODE_INTERL) || ((__MODE__) == ADC_TRIPLEMODE_ALTERTRIG)) 000ee1: line 314 define IS_ADC_DMA_ACCESS_MODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || ((__MODE__) == ADC_DMAACCESSMODE_1) || ((__MODE__) == ADC_DMAACCESSMODE_2) || ((__MODE__) == ADC_DMAACCESSMODE_3)) 000fa7: line 318 define IS_ADC_EXT_INJEC_TRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_NONE) || ((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING) || ((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || ((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING)) 0010b4: line 322 define IS_ADC_EXT_INJEC_TRIG(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START)) 001417: line 337 define IS_ADC_INJECTED_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4))) 001482: line 338 define IS_ADC_INJECTED_RANK(__RANK__) (((__RANK__) >= ((uint32_t)1)) && ((__RANK__) <= ((uint32_t)4))) 0014e5: line 347 define ADC_JSQR(_CHANNELNB_,_RANKNB_,_JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * (uint8_t)(((_RANKNB_) + 3) - (_JSQR_JL_)))) 00156c: end include 00156d: end of translation unit ** Section #105 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 124 bytes 000000: Header: length 120 (not including this field) version 3 prologue length 110 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_adc_ex.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 61 64 63 5f 65 78 2e 68 00 01 00 00 000060: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000077: file "" : 00 000078: DW_LNS_negate_stmt : 06 000079: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_adc_ex.h:1.0 [ ** Section #106 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 680 bytes 000000: Header: size 0x2a4 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_adc_ex.h 00004c: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000093: DW_AT_language DW_LANG_C89 000095: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010c: DW_AT_macro_info 0x0 000110: DW_AT_stmt_list 0x0 000114: 42 = 0x13 (DW_TAG_structure_type) 000115: DW_AT_sibling 0x222 000117: DW_AT_byte_size 0x24 000118: 30 = 0xd (DW_TAG_member) 000119: DW_AT_name InjectedChannel 000129: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00012e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000131: 30 = 0xd (DW_TAG_member) 000132: DW_AT_name InjectedRank 00013f: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000144: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000147: 30 = 0xd (DW_TAG_member) 000148: DW_AT_name InjectedSamplingTime 00015d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000162: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000165: 30 = 0xd (DW_TAG_member) 000166: DW_AT_name InjectedOffset 000175: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00017a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00017d: 30 = 0xd (DW_TAG_member) 00017e: DW_AT_name InjectedNbrOfConversion 000196: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00019b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 00019e: 30 = 0xd (DW_TAG_member) 00019f: DW_AT_name InjectedDiscontinuousConvMode 0001bd: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001c2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 0001c5: 30 = 0xd (DW_TAG_member) 0001c6: DW_AT_name AutoInjectedConv 0001d7: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001dc: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 0001df: 30 = 0xd (DW_TAG_member) 0001e0: DW_AT_name ExternalTrigInjecConv 0001f6: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001fb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 0001fe: 30 = 0xd (DW_TAG_member) 0001ff: DW_AT_name ExternalTrigInjecConvEdge 000219: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00021e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 000221: 0 null 000222: 80 = 0x16 (DW_TAG_typedef) 000223: DW_AT_name ADC_InjectionConfTypeDef 00023c: DW_AT_type indirect DW_FORM_ref2 0x114 00023f: DW_AT_decl_file 0x1 000240: DW_AT_decl_line 0x80 000242: DW_AT_decl_column 0x2 000243: 42 = 0x13 (DW_TAG_structure_type) 000244: DW_AT_sibling 0x287 000246: DW_AT_byte_size 0xc 000247: 30 = 0xd (DW_TAG_member) 000248: DW_AT_name Mode 00024d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000252: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000255: 30 = 0xd (DW_TAG_member) 000256: DW_AT_name DMAAccessMode 000264: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000269: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00026c: 30 = 0xd (DW_TAG_member) 00026d: DW_AT_name TwoSamplingDelay 00027e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000283: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000286: 0 null 000287: 80 = 0x16 (DW_TAG_typedef) 000288: DW_AT_name ADC_MultiModeTypeDef 00029d: DW_AT_type indirect DW_FORM_ref2 0x243 0002a0: DW_AT_decl_file 0x1 0002a1: DW_AT_decl_line 0x90 0002a3: DW_AT_decl_column 0x2 0002a4: 0 null 0002a5: 0 padding 0002a6: 0 padding 0002a7: 0 padding ** Section #381 '.rel.debug_info' (SHT_REL) Size : 120 bytes (alignment 4) Symbol table #343 '.symtab' 15 relocations applied to section #106 '.debug_info' ** Section #107 '__ARM_grp.stm32f7xx_hal_adc.h.2_QU5100_zOr6qrwdxdf_V10000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #108 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 14140 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_ADC_H 000018: include at line 47 - file 2 00001b: end include 00001c: line 175 define HAL_ADC_STATE_RESET ((uint32_t)0x00000000U) 00004b: line 176 define HAL_ADC_STATE_READY ((uint32_t)0x00000001U) 00007a: line 177 define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002U) 0000b1: line 178 define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004U) 0000e2: line 181 define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010U) 00011a: line 182 define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020U) 000150: line 183 define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040U) 000183: line 186 define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100U) 0001b5: line 188 define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200U) 0001e6: line 189 define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400U) 000217: line 192 define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000U) 000249: line 194 define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000U) 00027a: line 197 define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000U) 0002a8: line 198 define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000U) 0002d6: line 199 define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000U) 000304: line 202 define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000U) 00033d: line 236 define HAL_ADC_ERROR_NONE ((uint32_t)0x00U) 000365: line 237 define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01U) 000391: line 239 define HAL_ADC_ERROR_OVR ((uint32_t)0x02U) 0003b8: line 240 define HAL_ADC_ERROR_DMA ((uint32_t)0x04U) 0003df: line 249 define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000U) 000413: line 250 define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0) 00044c: line 251 define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1) 000485: line 252 define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE) 0004bc: line 260 define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000U) 0004f4: line 261 define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0) 000530: line 262 define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1) 00056c: line 263 define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) 0005bc: line 264 define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2) 0005f8: line 265 define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) 000649: line 266 define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) 00069a: line 267 define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) 0006fd: line 268 define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3) 00073a: line 269 define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0)) 00078b: line 270 define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1)) 0007dc: line 271 define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) 00083f: line 272 define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2)) 000890: line 273 define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) 0008f3: line 274 define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) 000956: line 275 define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY) 000991: line 283 define ADC_RESOLUTION_12B ((uint32_t)0x00000000U) 0009bf: line 284 define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0) 0009ef: line 285 define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1) 000a1e: line 286 define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES) 000a4b: line 294 define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000U) 000a84: line 295 define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0) 000ac3: line 296 define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1) 000b03: line 297 define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN) 000b47: line 309 define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000U) 000b7e: line 310 define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0) 000bba: line 311 define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1) 000bf6: line 312 define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) 000c47: line 313 define ADC_EXTERNALTRIGCONV_T5_TRGO ((uint32_t)ADC_CR2_EXTSEL_2) 000c84: line 314 define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) 000cd5: line 315 define ADC_EXTERNALTRIGCONV_T3_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)) 000d26: line 316 define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) 000d8b: line 317 define ADC_EXTERNALTRIGCONV_T8_TRGO2 ((uint32_t)ADC_CR2_EXTSEL_3) 000dc9: line 318 define ADC_EXTERNALTRIGCONV_T1_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0)) 000e1b: line 319 define ADC_EXTERNALTRIGCONV_T1_TRGO2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1)) 000e6e: line 320 define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) 000ed3: line 321 define ADC_EXTERNALTRIGCONV_T4_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2)) 000f25: line 322 define ADC_EXTERNALTRIGCONV_T6_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) 000f8a: line 324 define ADC_EXTERNALTRIGCONV_EXT_IT11 ((uint32_t)ADC_CR2_EXTSEL) 000fc6: line 325 define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1) 000ffb: line 334 define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) 00102a: line 335 define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) 00105a: line 343 define ADC_CHANNEL_0 ((uint32_t)0x00000000U) 001083: line 344 define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0) 0010b0: line 345 define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1) 0010dd: line 346 define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) 00111e: line 347 define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2) 00114b: line 348 define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)) 00118c: line 349 define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1)) 0011cd: line 350 define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) 001220: line 351 define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3) 00124d: line 352 define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)) 00128e: line 353 define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1)) 0012d0: line 354 define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) 001324: line 355 define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2)) 001366: line 356 define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)) 0013ba: line 357 define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1)) 00140e: line 358 define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) 001474: line 359 define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4) 0014a2: line 360 define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)) 0014e4: line 361 define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1)) 001526: line 363 define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17) 001558: line 364 define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18) 001587: line 372 define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000U) 0015b9: line 373 define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0) 0015f2: line 374 define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1) 00162b: line 375 define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0)) 00167a: line 376 define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2) 0016b3: line 377 define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0)) 001703: line 378 define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1)) 001753: line 379 define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10) 00178b: line 387 define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000U) 0017b7: line 388 define ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001U) 0017e6: line 389 define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002U) 001819: line 397 define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) 001843: line 398 define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) 00186d: line 406 define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) 0018bb: line 407 define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) 00190c: line 408 define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) 001970: line 409 define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN) 0019a8: line 410 define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN) 0019e3: line 411 define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) 001a33: line 412 define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000U) 001a66: line 420 define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE) 001a8e: line 421 define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE) 001ab6: line 422 define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE) 001ae0: line 423 define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE) 001b08: line 431 define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD) 001b2f: line 432 define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC) 001b56: line 433 define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC) 001b7f: line 434 define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT) 001baa: line 435 define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT) 001bd3: line 436 define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR) 001bfa: line 444 define ADC_ALL_CHANNELS ((uint32_t)0x00000001U) 001c26: line 445 define ADC_REGULAR_CHANNELS ((uint32_t)0x00000002U) 001c56: line 446 define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003U) 001c87: line 464 define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 001cdf: line 471 define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON) 001d2d: line 478 define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON) 001d7d: line 486 define __HAL_ADC_ENABLE_IT(__HANDLE__,__INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__)) 001de1: line 494 define __HAL_ADC_DISABLE_IT(__HANDLE__,__INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__)) 001e47: line 501 define __HAL_ADC_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) 001ec1: line 509 define __HAL_ADC_CLEAR_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) 001f1b: line 517 define __HAL_ADC_GET_FLAG(__HANDLE__,__FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 001f82: include at line 524 - file 3 001f86: end include 001f87: line 604 define ADC_STAB_DELAY_US ((uint32_t) 3U) 001fac: line 608 define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10U) 001fd8: line 625 define ADC_IS_ENABLE(__HANDLE__) ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) ) ? SET : RESET) 002048: line 635 define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET) 0020ae: line 644 define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET) 002116: line 654 define ADC_STATE_CLR_SET MODIFY_REG 002136: line 661 define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 002188: line 663 define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV6) || ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV8)) 002273: line 667 define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) || ((__DELAY__) == ADC_TWOSAMPLINGDELAY_13CYCLES) || ((__DELAY__) == ADC_TWOSAMPLINGDELAY_14CYCLES) || ((__DELAY__) == ADC_TWOSAMPLINGDELAY_15CYCLES) || ((__DELAY__) == ADC_TWOSAMPLINGDELAY_16CYCLES) || ((__DELAY__) == ADC_TWOSAMPLINGDELAY_17CYCLES) || ((__DELAY__) == ADC_TWOSAMPLINGDELAY_18CYCLES) || ((__DELAY__) == ADC_TWOSAMPLINGDELAY_19CYCLES) || ((__DELAY__) == ADC_TWOSAMPLINGDELAY_20CYCLES)) 0025b1: line 683 define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || ((__RESOLUTION__) == ADC_RESOLUTION_10B) || ((__RESOLUTION__) == ADC_RESOLUTION_8B) || ((__RESOLUTION__) == ADC_RESOLUTION_6B)) 002683: line 687 define IS_ADC_EXT_TRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)) 002776: line 691 define IS_ADC_EXT_TRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC1) || ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC2) || ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC3) || ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_CC2) || ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T5_TRGO) || ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_CC4) || ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T3_CC4) || ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO) || ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO) || ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_TRGO) || ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_TRGO) || ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T6_TRGO) || ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_EXT_IT11) || ((__REGTRIG__) == ADC_SOFTWARE_START)) 002ab8: line 707 define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || ((__ALIGN__) == ADC_DATAALIGN_LEFT)) 002b26: line 710 define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_3CYCLES) || ((__TIME__) == ADC_SAMPLETIME_15CYCLES) || ((__TIME__) == ADC_SAMPLETIME_28CYCLES) || ((__TIME__) == ADC_SAMPLETIME_56CYCLES) || ((__TIME__) == ADC_SAMPLETIME_84CYCLES) || ((__TIME__) == ADC_SAMPLETIME_112CYCLES) || ((__TIME__) == ADC_SAMPLETIME_144CYCLES) || ((__TIME__) == ADC_SAMPLETIME_480CYCLES)) 002c9f: line 718 define IS_ADC_EOCSelection(__EOCSelection__) (((__EOCSelection__) == ADC_EOC_SINGLE_CONV) || ((__EOCSelection__) == ADC_EOC_SEQ_CONV) || ((__EOCSelection__) == ADC_EOC_SINGLE_SEQ_CONV)) 002d55: line 721 define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_AWD_EVENT) || ((__EVENT__) == ADC_OVR_EVENT)) 002db8: line 723 define IS_ADC_ANALOG_WATCHDOG(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REG) || ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_NONE)) 002f51: line 730 define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS)) 002ff7: line 733 define IS_ADC_THRESHOLD(__THRESHOLD__) ((__THRESHOLD__) <= ((uint32_t)0xFFF)) 003041: line 734 define IS_ADC_REGULAR_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16))) 0030ac: line 735 define IS_ADC_REGULAR_RANK(__RANK__) (((__RANK__) >= ((uint32_t)1)) && ((__RANK__) <= ((uint32_t)16))) 00310f: line 736 define IS_ADC_REGULAR_DISC_NUMBER(__NUMBER__) (((__NUMBER__) >= ((uint32_t)1)) && ((__NUMBER__) <= ((uint32_t)8))) 00317e: line 737 define IS_ADC_RANGE(__RESOLUTION__,__ADC_VALUE__) ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= ((uint32_t)0x0FFF))) || (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= ((uint32_t)0x03FF))) || (((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_VALUE__) <= ((uint32_t)0x00FF))) || (((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_VALUE__) <= ((uint32_t)0x003F)))) 00330d: line 748 define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20) 003357: line 756 define ADC_SMPR1(_SAMPLETIME_,_CHANNELNB_) ((_SAMPLETIME_) << (3 * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10))) 0033c5: line 764 define ADC_SMPR2(_SAMPLETIME_,_CHANNELNB_) ((_SAMPLETIME_) << (3 * ((uint32_t)((uint16_t)(_CHANNELNB_))))) 00342c: line 772 define ADC_SQR3_RK(_CHANNELNB_,_RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 1))) 003493: line 780 define ADC_SQR2_RK(_CHANNELNB_,_RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 7))) 0034fa: line 788 define ADC_SQR1_RK(_CHANNELNB_,_RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 13))) 003562: line 795 define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1) 0035a6: line 802 define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM)) 00361b: line 809 define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8) 003659: line 816 define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10) 0036a4: line 823 define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9) 0036e8: line 830 define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES) 003738: end include 003739: end of translation unit ** Section #109 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 148 bytes 000000: Header: length 144 (not including this field) version 3 prologue length 133 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_adc.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 61 64 63 2e 68 00 01 00 00 00005d: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000074: file "stm32f7xx_hal_adc_ex.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 61 64 63 5f 65 78 2e 68 00 01 00 00 00008e: file "" : 00 00008f: DW_LNS_negate_stmt : 06 000090: DW_LNS_negate_stmt : 06 000091: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_adc.h:1.0 ** Section #110 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 1052 bytes 000000: Header: size 0x418 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_adc.h 000049: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000090: DW_AT_language DW_LANG_C89 000092: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 000109: DW_AT_macro_info 0x0 00010d: DW_AT_stmt_list 0x0 000111: 42 = 0x13 (DW_TAG_structure_type) 000112: DW_AT_sibling 0x249 000114: DW_AT_byte_size 0x30 000115: 30 = 0xd (DW_TAG_member) 000116: DW_AT_name ClockPrescaler 000125: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00012a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00012d: 30 = 0xd (DW_TAG_member) 00012e: DW_AT_name Resolution 000139: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00013e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000141: 30 = 0xd (DW_TAG_member) 000142: DW_AT_name DataAlign 00014c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000151: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000154: 30 = 0xd (DW_TAG_member) 000155: DW_AT_name ScanConvMode 000162: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000167: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00016a: 30 = 0xd (DW_TAG_member) 00016b: DW_AT_name EOCSelection 000178: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00017d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000180: 30 = 0xd (DW_TAG_member) 000181: DW_AT_name ContinuousConvMode 000194: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000199: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 00019c: 30 = 0xd (DW_TAG_member) 00019d: DW_AT_name NbrOfConversion 0001ad: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001b2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 0001b5: 30 = 0xd (DW_TAG_member) 0001b6: DW_AT_name DiscontinuousConvMode 0001cc: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001d1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 0001d4: 30 = 0xd (DW_TAG_member) 0001d5: DW_AT_name NbrOfDiscConversion 0001e9: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001ee: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 0001f1: 30 = 0xd (DW_TAG_member) 0001f2: DW_AT_name ExternalTrigConv 000203: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000208: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 00020b: 30 = 0xd (DW_TAG_member) 00020c: DW_AT_name ExternalTrigConvEdge 000221: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000226: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 000229: 30 = 0xd (DW_TAG_member) 00022a: DW_AT_name DMAContinuousRequests 000240: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000245: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 000248: 0 null 000249: 80 = 0x16 (DW_TAG_typedef) 00024a: DW_AT_name ADC_InitTypeDef 00025a: DW_AT_type indirect DW_FORM_ref2 0x111 00025d: DW_AT_decl_file 0x1 00025e: DW_AT_decl_line 0x7c 00025f: DW_AT_decl_column 0x2 000260: 42 = 0x13 (DW_TAG_structure_type) 000261: DW_AT_sibling 0x2aa 000263: DW_AT_byte_size 0x10 000264: 30 = 0xd (DW_TAG_member) 000265: DW_AT_name Channel 00026d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000272: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000275: 30 = 0xd (DW_TAG_member) 000276: DW_AT_name Rank 00027b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000280: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000283: 30 = 0xd (DW_TAG_member) 000284: DW_AT_name SamplingTime 000291: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000296: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000299: 30 = 0xd (DW_TAG_member) 00029a: DW_AT_name Offset 0002a1: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002a6: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0002a9: 0 null 0002aa: 80 = 0x16 (DW_TAG_typedef) 0002ab: DW_AT_name ADC_ChannelConfTypeDef 0002c2: DW_AT_type indirect DW_FORM_ref2 0x260 0002c5: DW_AT_decl_file 0x1 0002c6: DW_AT_decl_line 0x95 0002c8: DW_AT_decl_column 0x2 0002c9: 42 = 0x13 (DW_TAG_structure_type) 0002ca: DW_AT_sibling 0x34a 0002cc: DW_AT_byte_size 0x18 0002cd: 30 = 0xd (DW_TAG_member) 0002ce: DW_AT_name WatchdogMode 0002db: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002e0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0002e3: 30 = 0xd (DW_TAG_member) 0002e4: DW_AT_name HighThreshold 0002f2: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002f7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0002fa: 30 = 0xd (DW_TAG_member) 0002fb: DW_AT_name LowThreshold 000308: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00030d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000310: 30 = 0xd (DW_TAG_member) 000311: DW_AT_name Channel 000319: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00031e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000321: 30 = 0xd (DW_TAG_member) 000322: DW_AT_name ITMode 000329: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00032e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000331: 30 = 0xd (DW_TAG_member) 000332: DW_AT_name WatchdogNumber 000341: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000346: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 000349: 0 null 00034a: 80 = 0x16 (DW_TAG_typedef) 00034b: DW_AT_name ADC_AnalogWDGConfTypeDef 000364: DW_AT_type indirect DW_FORM_ref2 0x2c9 000367: DW_AT_decl_file 0x1 000368: DW_AT_decl_line 0xa9 00036a: DW_AT_decl_column 0x2 00036b: 42 = 0x13 (DW_TAG_structure_type) 00036c: DW_AT_sibling 0x3ec 00036e: DW_AT_byte_size 0x48 00036f: 30 = 0xd (DW_TAG_member) 000370: DW_AT_name Instance 000379: DW_AT_type indirect DW_FORM_ref2 0x3ec 00037c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00037f: 30 = 0xd (DW_TAG_member) 000380: DW_AT_name Init 000385: DW_AT_type indirect DW_FORM_ref2 0x249 000388: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00038b: 30 = 0xd (DW_TAG_member) 00038c: DW_AT_name NbrOfCurrentConversionRank 0003a7: DW_AT_type indirect DW_FORM_ref2 0x3f2 0003aa: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 0003ad: 30 = 0xd (DW_TAG_member) 0003ae: DW_AT_name DMA_Handle 0003b9: DW_AT_type indirect DW_FORM_ref2 0x3f8 0003bc: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 0003bf: 30 = 0xd (DW_TAG_member) 0003c0: DW_AT_name Lock 0003c5: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 0003ca: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 60 } 0003cd: 30 = 0xd (DW_TAG_member) 0003ce: DW_AT_name State 0003d4: DW_AT_type indirect DW_FORM_ref2 0x3f2 0003d7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 64 } 0003da: 30 = 0xd (DW_TAG_member) 0003db: DW_AT_name ErrorCode 0003e5: DW_AT_type indirect DW_FORM_ref2 0x3f2 0003e8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 68 } 0003eb: 0 null 0003ec: 34 = 0xf (DW_TAG_pointer_type) 0003ed: DW_AT_type indirect DW_FORM_ref_addr 0x977+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 0003f2: 116 = 0x35 (DW_TAG_volatile_type) 0003f3: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003f8: 34 = 0xf (DW_TAG_pointer_type) 0003f9: DW_AT_type indirect DW_FORM_ref_addr 0x1a0+__ARM_grp..debug_info$stm32f7xx_hal_dma.h$.2_wD1100_gh0hnOcebnc_s10000 0003fe: 80 = 0x16 (DW_TAG_typedef) 0003ff: DW_AT_name ADC_HandleTypeDef 000411: DW_AT_type indirect DW_FORM_ref2 0x36b 000414: DW_AT_decl_file 0x1 000415: DW_AT_decl_line 0xdf 000417: DW_AT_decl_column 0x2 000418: 0 null 000419: 0 padding 00041a: 0 padding 00041b: 0 padding ** Section #382 '.rel.debug_info' (SHT_REL) Size : 232 bytes (alignment 4) Symbol table #343 '.symtab' 29 relocations applied to section #110 '.debug_info' ** Section #111 '__ARM_grp.stm32f7xx_hal_can.h.2_kR$000_h3fepG4_6zc_N10000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #112 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 8416 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_CAN_H 00001c: include at line 47 - file 2 00001f: end include 000020: line 251 define HAL_CAN_ERROR_NONE 0x00U 00003c: line 252 define HAL_CAN_ERROR_EWG 0x01U 000057: line 253 define HAL_CAN_ERROR_EPV 0x02U 000072: line 254 define HAL_CAN_ERROR_BOF 0x04U 00008d: line 255 define HAL_CAN_ERROR_STF 0x08U 0000a8: line 256 define HAL_CAN_ERROR_FOR 0x10U 0000c3: line 257 define HAL_CAN_ERROR_ACK 0x20U 0000de: line 258 define HAL_CAN_ERROR_BR 0x40U 0000f8: line 259 define HAL_CAN_ERROR_BD 0x80U 000112: line 260 define HAL_CAN_ERROR_CRC 0x100U 00012e: line 268 define CAN_INITSTATUS_FAILED ((uint8_t)0x00U) 000158: line 269 define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01U) 000183: line 277 define CAN_MODE_NORMAL ((uint32_t)0x00000000U) 0001ae: line 278 define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) 0001dc: line 279 define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) 000208: line 280 define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) 00024e: line 288 define CAN_SJW_1TQ ((uint32_t)0x00000000U) 000275: line 289 define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) 00029e: line 290 define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) 0002c7: line 291 define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) 0002ee: line 299 define CAN_BS1_1TQ ((uint32_t)0x00000000U) 000315: line 300 define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) 00033e: line 301 define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) 000367: line 302 define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) 0003a2: line 303 define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) 0003cb: line 304 define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) 000406: line 305 define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) 000441: line 306 define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) 00048c: line 307 define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) 0004b5: line 308 define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) 0004f1: line 309 define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) 00052d: line 310 define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) 000579: line 311 define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) 0005b5: line 312 define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) 000601: line 313 define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) 00064d: line 314 define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) 000675: line 322 define CAN_BS2_1TQ ((uint32_t)0x00000000U) 00069c: line 323 define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) 0006c5: line 324 define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) 0006ee: line 325 define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) 000729: line 326 define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) 000752: line 327 define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) 00078d: line 328 define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) 0007c8: line 329 define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) 0007ef: line 337 define CAN_FILTERMODE_IDMASK ((uint8_t)0x00U) 000819: line 338 define CAN_FILTERMODE_IDLIST ((uint8_t)0x01U) 000843: line 346 define CAN_FILTERSCALE_16BIT ((uint8_t)0x00U) 00086d: line 347 define CAN_FILTERSCALE_32BIT ((uint8_t)0x01U) 000897: line 355 define CAN_FILTER_FIFO0 ((uint8_t)0x00U) 0008bc: line 356 define CAN_FILTER_FIFO1 ((uint8_t)0x01U) 0008e1: line 364 define CAN_ID_STD ((uint32_t)0x00000000U) 000907: line 365 define CAN_ID_EXT ((uint32_t)0x00000004U) 00092d: line 373 define CAN_RTR_DATA ((uint32_t)0x00000000U) 000955: line 374 define CAN_RTR_REMOTE ((uint32_t)0x00000002U) 00097f: line 382 define CAN_FIFO0 ((uint8_t)0x00U) 00099d: line 383 define CAN_FIFO1 ((uint8_t)0x01U) 0009bb: line 397 define CAN_FLAG_RQCP0 ((uint32_t)0x00000500U) 0009e5: line 398 define CAN_FLAG_RQCP1 ((uint32_t)0x00000508U) 000a0f: line 399 define CAN_FLAG_RQCP2 ((uint32_t)0x00000510U) 000a39: line 400 define CAN_FLAG_TXOK0 ((uint32_t)0x00000501U) 000a63: line 401 define CAN_FLAG_TXOK1 ((uint32_t)0x00000509U) 000a8d: line 402 define CAN_FLAG_TXOK2 ((uint32_t)0x00000511U) 000ab7: line 403 define CAN_FLAG_TME0 ((uint32_t)0x0000051AU) 000ae0: line 404 define CAN_FLAG_TME1 ((uint32_t)0x0000051BU) 000b09: line 405 define CAN_FLAG_TME2 ((uint32_t)0x0000051CU) 000b32: line 408 define CAN_FLAG_FF0 ((uint32_t)0x00000203U) 000b5a: line 409 define CAN_FLAG_FOV0 ((uint32_t)0x00000204U) 000b83: line 411 define CAN_FLAG_FF1 ((uint32_t)0x00000403U) 000bab: line 412 define CAN_FLAG_FOV1 ((uint32_t)0x00000404U) 000bd4: line 415 define CAN_FLAG_INAK ((uint32_t)0x00000100U) 000bfd: line 416 define CAN_FLAG_SLAK ((uint32_t)0x00000101U) 000c26: line 417 define CAN_FLAG_ERRI ((uint32_t)0x00000102U) 000c4f: line 418 define CAN_FLAG_WKU ((uint32_t)0x00000103U) 000c77: line 419 define CAN_FLAG_SLAKI ((uint32_t)0x00000104U) 000ca1: line 425 define CAN_FLAG_EWG ((uint32_t)0x00000300U) 000cc9: line 426 define CAN_FLAG_EPV ((uint32_t)0x00000301U) 000cf1: line 427 define CAN_FLAG_BOF ((uint32_t)0x00000302U) 000d19: line 435 define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) 000d41: line 438 define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) 000d6b: line 439 define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) 000d93: line 440 define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) 000dbd: line 441 define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) 000de7: line 442 define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) 000e0f: line 443 define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) 000e39: line 446 define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) 000e61: line 447 define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) 000e89: line 450 define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) 000eb1: line 451 define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) 000ed9: line 452 define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) 000f01: line 453 define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) 000f29: line 454 define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) 000f51: line 462 define CAN_TXMAILBOX_0 ((uint8_t)0x00U) 000f75: line 463 define CAN_TXMAILBOX_1 ((uint8_t)0x01U) 000f99: line 464 define CAN_TXMAILBOX_2 ((uint8_t)0x02U) 000fbd: line 482 define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) 001015: line 490 define __HAL_CAN_ENABLE_IT(__HANDLE__,__INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) 001079: line 498 define __HAL_CAN_DISABLE_IT(__HANDLE__,__INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) 0010df: line 506 define __HAL_CAN_MSG_PENDING(__HANDLE__,__FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? ((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03))) 0011aa: line 536 define __HAL_CAN_GET_FLAG(__HANDLE__,__FLAG__) ((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): ((((__HANDLE__)->Instance->ESR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK)))) 001470: line 567 define __HAL_CAN_CLEAR_FLAG(__HANDLE__,__FLAG__) ((((__FLAG__) >> 8) == 5)? (((__HANDLE__)->Instance->TSR) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): (((__FLAG__) >> 8) == 2)? (((__HANDLE__)->Instance->RF0R) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): (((__FLAG__) >> 8) == 4)? (((__HANDLE__)->Instance->RF1R) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): (((__HANDLE__)->Instance->MSR) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK)))) 001632: line 582 define __HAL_CAN_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 0016bc: line 590 define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__,__TRANSMITMAILBOX__) (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) : ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) : ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2))) 0018e6: line 601 define __HAL_CAN_FIFO_RELEASE(__HANDLE__,__FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? ((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1)) 0019a0: line 610 define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__,__TRANSMITMAILBOX__) (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) : ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) : ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2)) 001ac5: line 624 define __HAL_CAN_DBG_FREEZE(__HANDLE__,__NEWSTATE__) (((__NEWSTATE__) == ENABLE)? ((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) 001b71: line 703 define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04U) 001b9c: line 704 define CAN_FLAG_MASK ((uint32_t)0x000000FFU) 001bc5: line 713 define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || ((MODE) == CAN_MODE_LOOPBACK)|| ((MODE) == CAN_MODE_SILENT) || ((MODE) == CAN_MODE_SILENT_LOOPBACK)) 001c5f: line 717 define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) 001cd8: line 719 define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ) 001d03: line 720 define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ) 001d2d: line 721 define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) 001d7a: line 722 define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) 001dab: line 723 define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || ((MODE) == CAN_FILTERMODE_IDLIST)) 001e10: line 725 define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || ((SCALE) == CAN_FILTERSCALE_32BIT)) 001e79: line 727 define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || ((FIFO) == CAN_FILTER_FIFO1)) 001ed4: line 729 define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28) 001f0a: line 731 define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) 001f5c: line 732 define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) 001f92: line 733 define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) 001fcd: line 734 define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) 001ffb: line 736 define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || ((IDTYPE) == CAN_ID_EXT)) 00204b: line 738 define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) 002095: line 739 define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) 0020db: end include 0020dc: end of translation unit ** Section #113 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 120 bytes 000000: Header: length 116 (not including this field) version 3 prologue length 107 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_can.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 63 61 6e 2e 68 00 01 00 00 00005d: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000074: file "" : 00 000075: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_can.h:1.0 ** Section #114 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 1384 bytes 000000: Header: size 0x564 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_can.h 000049: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000090: DW_AT_language DW_LANG_C89 000092: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 000109: DW_AT_macro_info 0x0 00010d: DW_AT_stmt_list 0x0 000111: 19 = 0x4 (DW_TAG_enumeration_type) 000112: DW_AT_sibling 0x1d8 000114: DW_AT_byte_size 0x1 000115: 20 = 0x28 (DW_TAG_enumerator) 000116: DW_AT_name HAL_CAN_STATE_RESET 00012a: DW_AT_const_value indirect DW_FORM_data1 0x0 00012c: 20 = 0x28 (DW_TAG_enumerator) 00012d: DW_AT_name HAL_CAN_STATE_READY 000141: DW_AT_const_value indirect DW_FORM_data1 0x1 000143: 20 = 0x28 (DW_TAG_enumerator) 000144: DW_AT_name HAL_CAN_STATE_BUSY 000157: DW_AT_const_value indirect DW_FORM_data1 0x2 000159: 20 = 0x28 (DW_TAG_enumerator) 00015a: DW_AT_name HAL_CAN_STATE_BUSY_TX 000170: DW_AT_const_value indirect DW_FORM_data1 0x12 000172: 20 = 0x28 (DW_TAG_enumerator) 000173: DW_AT_name HAL_CAN_STATE_BUSY_RX 000189: DW_AT_const_value indirect DW_FORM_data1 0x22 00018b: 20 = 0x28 (DW_TAG_enumerator) 00018c: DW_AT_name HAL_CAN_STATE_BUSY_TX_RX 0001a5: DW_AT_const_value indirect DW_FORM_data1 0x32 0001a7: 20 = 0x28 (DW_TAG_enumerator) 0001a8: DW_AT_name HAL_CAN_STATE_TIMEOUT 0001be: DW_AT_const_value indirect DW_FORM_data1 0x3 0001c0: 20 = 0x28 (DW_TAG_enumerator) 0001c1: DW_AT_name HAL_CAN_STATE_ERROR 0001d5: DW_AT_const_value indirect DW_FORM_data1 0x4 0001d7: 0 null 0001d8: 80 = 0x16 (DW_TAG_typedef) 0001d9: DW_AT_name HAL_CAN_StateTypeDef 0001ee: DW_AT_type indirect DW_FORM_ref2 0x111 0001f1: DW_AT_decl_file 0x1 0001f2: DW_AT_decl_line 0x4c 0001f3: DW_AT_decl_column 0x2 0001f4: 42 = 0x13 (DW_TAG_structure_type) 0001f5: DW_AT_sibling 0x295 0001f7: DW_AT_byte_size 0x2c 0001f8: 30 = 0xd (DW_TAG_member) 0001f9: DW_AT_name Prescaler 000203: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000208: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00020b: 30 = 0xd (DW_TAG_member) 00020c: DW_AT_name Mode 000211: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000216: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000219: 30 = 0xd (DW_TAG_member) 00021a: DW_AT_name SJW 00021e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000223: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000226: 30 = 0xd (DW_TAG_member) 000227: DW_AT_name BS1 00022b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000230: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000233: 30 = 0xd (DW_TAG_member) 000234: DW_AT_name BS2 000238: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00023d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000240: 30 = 0xd (DW_TAG_member) 000241: DW_AT_name TTCM 000246: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00024b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 00024e: 30 = 0xd (DW_TAG_member) 00024f: DW_AT_name ABOM 000254: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000259: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 00025c: 30 = 0xd (DW_TAG_member) 00025d: DW_AT_name AWUM 000262: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000267: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 00026a: 30 = 0xd (DW_TAG_member) 00026b: DW_AT_name NART 000270: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000275: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 000278: 30 = 0xd (DW_TAG_member) 000279: DW_AT_name RFLM 00027e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000283: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 000286: 30 = 0xd (DW_TAG_member) 000287: DW_AT_name TXFP 00028c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000291: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 000294: 0 null 000295: 80 = 0x16 (DW_TAG_typedef) 000296: DW_AT_name CAN_InitTypeDef 0002a6: DW_AT_type indirect DW_FORM_ref2 0x1f4 0002a9: DW_AT_decl_file 0x1 0002aa: DW_AT_decl_line 0x75 0002ab: DW_AT_decl_column 0x2 0002ac: 42 = 0x13 (DW_TAG_structure_type) 0002ad: DW_AT_sibling 0x39a 0002af: DW_AT_byte_size 0x28 0002b0: 30 = 0xd (DW_TAG_member) 0002b1: DW_AT_name FilterIdHigh 0002be: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002c3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0002c6: 30 = 0xd (DW_TAG_member) 0002c7: DW_AT_name FilterIdLow 0002d3: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002d8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0002db: 30 = 0xd (DW_TAG_member) 0002dc: DW_AT_name FilterMaskIdHigh 0002ed: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002f2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0002f5: 30 = 0xd (DW_TAG_member) 0002f6: DW_AT_name FilterMaskIdLow 000306: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00030b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00030e: 30 = 0xd (DW_TAG_member) 00030f: DW_AT_name FilterFIFOAssignment 000324: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000329: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 00032c: 30 = 0xd (DW_TAG_member) 00032d: DW_AT_name FilterNumber 00033a: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00033f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 000342: 30 = 0xd (DW_TAG_member) 000343: DW_AT_name FilterMode 00034e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000353: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 000356: 30 = 0xd (DW_TAG_member) 000357: DW_AT_name FilterScale 000363: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000368: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 00036b: 30 = 0xd (DW_TAG_member) 00036c: DW_AT_name FilterActivation 00037d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000382: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 000385: 30 = 0xd (DW_TAG_member) 000386: DW_AT_name BankNumber 000391: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000396: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 000399: 0 null 00039a: 80 = 0x16 (DW_TAG_typedef) 00039b: DW_AT_name CAN_FilterConfTypeDef 0003b1: DW_AT_type indirect DW_FORM_ref2 0x2ac 0003b4: DW_AT_decl_file 0x1 0003b5: DW_AT_decl_line 0xa0 0003b7: DW_AT_decl_column 0x2 0003b8: 42 = 0x13 (DW_TAG_structure_type) 0003b9: DW_AT_sibling 0x419 0003bb: DW_AT_byte_size 0x1c 0003bc: 30 = 0xd (DW_TAG_member) 0003bd: DW_AT_name StdId 0003c3: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003c8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0003cb: 30 = 0xd (DW_TAG_member) 0003cc: DW_AT_name ExtId 0003d2: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003d7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0003da: 30 = 0xd (DW_TAG_member) 0003db: DW_AT_name IDE 0003df: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003e4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0003e7: 30 = 0xd (DW_TAG_member) 0003e8: DW_AT_name RTR 0003ec: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003f1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0003f4: 30 = 0xd (DW_TAG_member) 0003f5: DW_AT_name DLC 0003f9: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003fe: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000401: 3 = 0x1 (DW_TAG_array_type) 000402: DW_AT_sibling 0x40c 000404: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000409: 1 = 0x21 (DW_TAG_subrange_type) 00040a: DW_AT_upper_bound 0x7 00040b: 0 null 00040c: 30 = 0xd (DW_TAG_member) 00040d: DW_AT_name Data 000412: DW_AT_type indirect DW_FORM_ref2 0x401 000415: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 000418: 0 null 000419: 80 = 0x16 (DW_TAG_typedef) 00041a: DW_AT_name CanTxMsgTypeDef 00042a: DW_AT_type indirect DW_FORM_ref2 0x3b8 00042d: DW_AT_decl_file 0x1 00042e: DW_AT_decl_line 0xb9 000430: DW_AT_decl_column 0x2 000431: 42 = 0x13 (DW_TAG_structure_type) 000432: DW_AT_sibling 0x4b3 000434: DW_AT_byte_size 0x24 000435: 30 = 0xd (DW_TAG_member) 000436: DW_AT_name StdId 00043c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000441: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000444: 30 = 0xd (DW_TAG_member) 000445: DW_AT_name ExtId 00044b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000450: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000453: 30 = 0xd (DW_TAG_member) 000454: DW_AT_name IDE 000458: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00045d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000460: 30 = 0xd (DW_TAG_member) 000461: DW_AT_name RTR 000465: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00046a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00046d: 30 = 0xd (DW_TAG_member) 00046e: DW_AT_name DLC 000472: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000477: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 00047a: 3 = 0x1 (DW_TAG_array_type) 00047b: DW_AT_sibling 0x485 00047d: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000482: 1 = 0x21 (DW_TAG_subrange_type) 000483: DW_AT_upper_bound 0x7 000484: 0 null 000485: 30 = 0xd (DW_TAG_member) 000486: DW_AT_name Data 00048b: DW_AT_type indirect DW_FORM_ref2 0x47a 00048e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 000491: 30 = 0xd (DW_TAG_member) 000492: DW_AT_name FMI 000496: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00049b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 00049e: 30 = 0xd (DW_TAG_member) 00049f: DW_AT_name FIFONumber 0004aa: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004af: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 0004b2: 0 null 0004b3: 80 = 0x16 (DW_TAG_typedef) 0004b4: DW_AT_name CanRxMsgTypeDef 0004c4: DW_AT_type indirect DW_FORM_ref2 0x431 0004c7: DW_AT_decl_file 0x1 0004c8: DW_AT_decl_line 0xd8 0004ca: DW_AT_decl_column 0x2 0004cb: 42 = 0x13 (DW_TAG_structure_type) 0004cc: DW_AT_sibling 0x534 0004ce: DW_AT_byte_size 0x40 0004cf: 30 = 0xd (DW_TAG_member) 0004d0: DW_AT_name Instance 0004d9: DW_AT_type indirect DW_FORM_ref2 0x534 0004dc: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0004df: 30 = 0xd (DW_TAG_member) 0004e0: DW_AT_name Init 0004e5: DW_AT_type indirect DW_FORM_ref2 0x295 0004e8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0004eb: 30 = 0xd (DW_TAG_member) 0004ec: DW_AT_name pTxMsg 0004f3: DW_AT_type indirect DW_FORM_ref2 0x53a 0004f6: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 0004f9: 30 = 0xd (DW_TAG_member) 0004fa: DW_AT_name pRxMsg 000501: DW_AT_type indirect DW_FORM_ref2 0x53e 000504: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 000507: 30 = 0xd (DW_TAG_member) 000508: DW_AT_name State 00050e: DW_AT_type indirect DW_FORM_ref2 0x542 000511: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 000514: 30 = 0xd (DW_TAG_member) 000515: DW_AT_name Lock 00051a: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 00051f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 57 } 000522: 30 = 0xd (DW_TAG_member) 000523: DW_AT_name ErrorCode 00052d: DW_AT_type indirect DW_FORM_ref2 0x546 000530: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 60 } 000533: 0 null 000534: 34 = 0xf (DW_TAG_pointer_type) 000535: DW_AT_type indirect DW_FORM_ref_addr 0xc3e+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 00053a: 34 = 0xf (DW_TAG_pointer_type) 00053b: DW_AT_type indirect DW_FORM_ref2 0x419 00053e: 34 = 0xf (DW_TAG_pointer_type) 00053f: DW_AT_type indirect DW_FORM_ref2 0x4b3 000542: 116 = 0x35 (DW_TAG_volatile_type) 000543: DW_AT_type indirect DW_FORM_ref2 0x1d8 000546: 116 = 0x35 (DW_TAG_volatile_type) 000547: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00054c: 80 = 0x16 (DW_TAG_typedef) 00054d: DW_AT_name CAN_HandleTypeDef 00055f: DW_AT_type indirect DW_FORM_ref2 0x4cb 000562: DW_AT_decl_file 0x1 000563: DW_AT_decl_line 0xed 000565: DW_AT_decl_column 0x2 000566: 0 null 000567: 0 padding ** Section #383 '.rel.debug_info' (SHT_REL) Size : 328 bytes (alignment 4) Symbol table #343 '.symtab' 41 relocations applied to section #114 '.debug_info' ** Section #115 '__ARM_grp.stm32f7xx_hal_cec.h.2_0C_000_Djuxq28e89b_q10000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #116 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 6104 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_CEC_H 00001c: include at line 49 - file 2 00001f: end include 000020: line 226 define HAL_CEC_ERROR_NONE (uint32_t) 0x0000U 000049: line 227 define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR 00006e: line 228 define HAL_CEC_ERROR_BRE CEC_ISR_BRE 00008f: line 229 define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE 0000b2: line 230 define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE 0000d5: line 231 define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE 0000fc: line 232 define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST 000123: line 233 define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR 000148: line 234 define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR 00016d: line 235 define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE 000194: line 243 define CEC_DEFAULT_SFT ((uint32_t)0x00000000U) 0001bf: line 244 define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U) 0001f0: line 245 define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U) 000221: line 246 define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U) 000252: line 247 define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U) 000283: line 248 define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U) 0002b4: line 249 define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U) 0002e5: line 250 define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U) 000316: line 258 define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U) 000348: line 259 define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL) 00037d: line 267 define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U) 0003ae: line 268 define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP) 0003e0: line 276 define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U) 00041a: line 277 define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN) 000455: line 285 define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U) 000490: line 286 define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN) 0004cd: line 294 define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U) 00050f: line 295 define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN) 00055a: line 303 define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U) 00058c: line 304 define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT) 0005c6: line 312 define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U) 0005fc: line 313 define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN) 000631: line 321 define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U) 00065a: line 329 define CEC_INITIATOR_LSB_POS ((uint32_t) 4U) 000683: line 337 define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) 0006b0: line 338 define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) 0006da: line 339 define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) 000704: line 340 define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) 00072e: line 341 define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) 000758: line 342 define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) 000782: line 343 define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) 0007ac: line 344 define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) 0007d6: line 345 define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) 000800: line 346 define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) 00082a: line 347 define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) 000854: line 348 define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) 00087f: line 349 define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) 0008aa: line 350 define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) 0008d5: line 351 define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) 000900: line 352 define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) 00092b: line 360 define CEC_IT_TXACKE CEC_IER_TXACKEIE 00094d: line 361 define CEC_IT_TXERR CEC_IER_TXERRIE 00096d: line 362 define CEC_IT_TXUDR CEC_IER_TXUDRIE 00098d: line 363 define CEC_IT_TXEND CEC_IER_TXENDIE 0009ad: line 364 define CEC_IT_TXBR CEC_IER_TXBRIE 0009cb: line 365 define CEC_IT_ARBLST CEC_IER_ARBLSTIE 0009ed: line 366 define CEC_IT_RXACKE CEC_IER_RXACKEIE 000a0f: line 367 define CEC_IT_LBPE CEC_IER_LBPEIE 000a2d: line 368 define CEC_IT_SBPE CEC_IER_SBPEIE 000a4b: line 369 define CEC_IT_BRE CEC_IER_BREIE 000a67: line 370 define CEC_IT_RXOVR CEC_IER_RXOVRIE 000a87: line 371 define CEC_IT_RXEND CEC_IER_RXENDIE 000aa7: line 372 define CEC_IT_RXBR CEC_IER_RXBRIE 000ac5: line 380 define CEC_FLAG_TXACKE CEC_ISR_TXACKE 000ae7: line 381 define CEC_FLAG_TXERR CEC_ISR_TXERR 000b07: line 382 define CEC_FLAG_TXUDR CEC_ISR_TXUDR 000b27: line 383 define CEC_FLAG_TXEND CEC_ISR_TXEND 000b47: line 384 define CEC_FLAG_TXBR CEC_ISR_TXBR 000b65: line 385 define CEC_FLAG_ARBLST CEC_ISR_ARBLST 000b87: line 386 define CEC_FLAG_RXACKE CEC_ISR_RXACKE 000ba9: line 387 define CEC_FLAG_LBPE CEC_ISR_LBPE 000bc7: line 388 define CEC_FLAG_SBPE CEC_ISR_SBPE 000be5: line 389 define CEC_FLAG_BRE CEC_ISR_BRE 000c01: line 390 define CEC_FLAG_RXOVR CEC_ISR_RXOVR 000c21: line 391 define CEC_FLAG_RXEND CEC_ISR_RXEND 000c41: line 392 define CEC_FLAG_RXBR CEC_ISR_RXBR 000c5f: line 400 define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE| CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE) 000cfe: line 409 define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE) 000d6d: line 417 define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE) 000dd1: line 435 define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ (__HANDLE__)->gState = HAL_CEC_STATE_RESET; (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; } while(0) 000e65: line 458 define __HAL_CEC_GET_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) 000ebb: line 479 define __HAL_CEC_CLEAR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__)) 000f14: line 500 define __HAL_CEC_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) 000f76: line 521 define __HAL_CEC_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) 000fdc: line 542 define __HAL_CEC_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) 001041: line 548 define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN) 00108e: line 554 define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN) 0010dd: line 560 define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM) 001135: line 567 define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM) 00118c: line 573 define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM) 0011ed: line 579 define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM) 00124c: line 585 define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR) 0012a5: line 593 define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS) 00131e: line 678 define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT) 00135c: line 680 define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || ((__RXTOL__) == CEC_EXTENDED_TOLERANCE)) 0013d0: line 683 define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE)) 00144b: line 686 define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION)) 0014e3: line 689 define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION)) 00157e: line 692 define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION)) 001643: line 695 define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END)) 0016b7: line 698 define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || ((__MODE__) == CEC_FULL_LISTENING_MODE)) 001732: line 708 define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10) 001763: line 715 define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFF) 0017a0: line 722 define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF) 0017d6: end include 0017d7: end of translation unit ** Section #117 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 120 bytes 000000: Header: length 116 (not including this field) version 3 prologue length 107 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_cec.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 63 65 63 2e 68 00 01 00 00 00005d: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000074: file "" : 00 000075: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_cec.h:1.0 ** Section #118 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 932 bytes 000000: Header: size 0x3a0 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_cec.h 000049: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000090: DW_AT_language DW_LANG_C89 000092: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 000109: DW_AT_macro_info 0x0 00010d: DW_AT_stmt_list 0x0 000111: 42 = 0x13 (DW_TAG_structure_type) 000112: DW_AT_sibling 0x1fe 000114: DW_AT_byte_size 0x28 000115: 30 = 0xd (DW_TAG_member) 000116: DW_AT_name SignalFreeTime 000125: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00012a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00012d: 30 = 0xd (DW_TAG_member) 00012e: DW_AT_name Tolerance 000138: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00013d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000140: 30 = 0xd (DW_TAG_member) 000141: DW_AT_name BRERxStop 00014b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000150: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000153: 30 = 0xd (DW_TAG_member) 000154: DW_AT_name BREErrorBitGen 000163: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000168: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00016b: 30 = 0xd (DW_TAG_member) 00016c: DW_AT_name LBPEErrorBitGen 00017c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000181: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000184: 30 = 0xd (DW_TAG_member) 000185: DW_AT_name BroadcastMsgNoErrorBitGen 00019f: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001a4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 0001a7: 30 = 0xd (DW_TAG_member) 0001a8: DW_AT_name SignalFreeTimeOption 0001bd: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001c2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 0001c5: 30 = 0xd (DW_TAG_member) 0001c6: DW_AT_name ListenMode 0001d1: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001d6: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 0001d9: 30 = 0xd (DW_TAG_member) 0001da: DW_AT_name OwnAddress 0001e5: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001ea: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 0001ed: 30 = 0xd (DW_TAG_member) 0001ee: DW_AT_name RxBuffer 0001f7: DW_AT_type indirect DW_FORM_ref2 0x1fe 0001fa: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 0001fd: 0 null 0001fe: 34 = 0xf (DW_TAG_pointer_type) 0001ff: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000204: 80 = 0x16 (DW_TAG_typedef) 000205: DW_AT_name CEC_InitTypeDef 000215: DW_AT_type indirect DW_FORM_ref2 0x111 000218: DW_AT_decl_file 0x1 000219: DW_AT_decl_line 0x81 00021b: DW_AT_decl_column 0x2 00021c: 19 = 0x4 (DW_TAG_enumeration_type) 00021d: DW_AT_sibling 0x2ca 00021f: DW_AT_byte_size 0x1 000220: 20 = 0x28 (DW_TAG_enumerator) 000221: DW_AT_name HAL_CEC_STATE_RESET 000235: DW_AT_const_value indirect DW_FORM_data1 0x0 000237: 20 = 0x28 (DW_TAG_enumerator) 000238: DW_AT_name HAL_CEC_STATE_READY 00024c: DW_AT_const_value indirect DW_FORM_data1 0x20 00024e: 20 = 0x28 (DW_TAG_enumerator) 00024f: DW_AT_name HAL_CEC_STATE_BUSY 000262: DW_AT_const_value indirect DW_FORM_data1 0x24 000264: 20 = 0x28 (DW_TAG_enumerator) 000265: DW_AT_name HAL_CEC_STATE_BUSY_RX 00027b: DW_AT_const_value indirect DW_FORM_data1 0x22 00027d: 20 = 0x28 (DW_TAG_enumerator) 00027e: DW_AT_name HAL_CEC_STATE_BUSY_TX 000294: DW_AT_const_value indirect DW_FORM_data1 0x21 000296: 20 = 0x28 (DW_TAG_enumerator) 000297: DW_AT_name HAL_CEC_STATE_BUSY_RX_TX 0002b0: DW_AT_const_value indirect DW_FORM_data1 0x23 0002b2: 20 = 0x28 (DW_TAG_enumerator) 0002b3: DW_AT_name HAL_CEC_STATE_ERROR 0002c7: DW_AT_const_value indirect DW_FORM_data1 0x60 0002c9: 0 null 0002ca: 80 = 0x16 (DW_TAG_typedef) 0002cb: DW_AT_name HAL_CEC_StateTypeDef 0002e0: DW_AT_type indirect DW_FORM_ref2 0x21c 0002e3: DW_AT_decl_file 0x1 0002e4: DW_AT_decl_line 0xb9 0002e6: DW_AT_decl_column 0x2 0002e7: 42 = 0x13 (DW_TAG_structure_type) 0002e8: DW_AT_sibling 0x381 0002ea: DW_AT_byte_size 0x3c 0002eb: 30 = 0xd (DW_TAG_member) 0002ec: DW_AT_name Instance 0002f5: DW_AT_type indirect DW_FORM_ref2 0x381 0002f8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0002fb: 30 = 0xd (DW_TAG_member) 0002fc: DW_AT_name Init 000301: DW_AT_type indirect DW_FORM_ref2 0x204 000304: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000307: 30 = 0xd (DW_TAG_member) 000308: DW_AT_name pTxBuffPtr 000313: DW_AT_type indirect DW_FORM_ref2 0x1fe 000316: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 000319: 30 = 0xd (DW_TAG_member) 00031a: DW_AT_name TxXferCount 000326: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00032b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 00032e: 30 = 0xd (DW_TAG_member) 00032f: DW_AT_name RxXferSize 00033a: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00033f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 50 } 000342: 30 = 0xd (DW_TAG_member) 000343: DW_AT_name Lock 000348: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 00034d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 000350: 30 = 0xd (DW_TAG_member) 000351: DW_AT_name gState 000358: DW_AT_type indirect DW_FORM_ref2 0x2ca 00035b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 53 } 00035e: 30 = 0xd (DW_TAG_member) 00035f: DW_AT_name RxState 000367: DW_AT_type indirect DW_FORM_ref2 0x2ca 00036a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 54 } 00036d: 30 = 0xd (DW_TAG_member) 00036e: DW_AT_name ErrorCode 000378: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00037d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 000380: 0 null 000381: 34 = 0xf (DW_TAG_pointer_type) 000382: DW_AT_type indirect DW_FORM_ref_addr 0xc9b+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 000387: 80 = 0x16 (DW_TAG_typedef) 000388: DW_AT_name CEC_HandleTypeDef 00039a: DW_AT_type indirect DW_FORM_ref2 0x2e7 00039d: DW_AT_decl_file 0x1 00039e: DW_AT_decl_line 0xd5 0003a0: DW_AT_decl_column 0x2 0003a1: 0 null 0003a2: 0 padding 0003a3: 0 padding ** Section #384 '.rel.debug_info' (SHT_REL) Size : 144 bytes (alignment 4) Symbol table #343 '.symtab' 18 relocations applied to section #118 '.debug_info' ** Section #119 '__ARM_grp.stm32f7xx_hal_crc_ex.h.2_s01000_FAuJqUi3Rza_300000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #120 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 1076 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_CRC_EX_H 00001f: include at line 47 - file 2 000022: end include 000023: line 67 define CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000U) 00005a: line 68 define CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0) 000095: line 69 define CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1) 0000d4: line 70 define CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN) 00010d: line 72 define IS_CRC_INPUTDATA_INVERSION_MODE(__MODE__) (((__MODE__) == CRC_INPUTDATA_INVERSION_NONE) || ((__MODE__) == CRC_INPUTDATA_INVERSION_BYTE) || ((__MODE__) == CRC_INPUTDATA_INVERSION_HALFWORD) || ((__MODE__) == CRC_INPUTDATA_INVERSION_WORD)) 0001fc: line 83 define CRC_OUTPUTDATA_INVERSION_DISABLE ((uint32_t)0x00000000U) 000237: line 84 define CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT) 000274: line 86 define IS_CRC_OUTPUTDATA_INVERSION_MODE(__MODE__) (((__MODE__) == CRC_OUTPUTDATA_INVERSION_DISABLE) || ((__MODE__) == CRC_OUTPUTDATA_INVERSION_ENABLE)) 000307: line 107 define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT) 000364: line 114 define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT)) 0003c5: line 122 define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__,__POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__)) 00042f: end include 000430: end of translation unit ** Section #121 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 124 bytes 000000: Header: length 120 (not including this field) version 3 prologue length 110 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_crc_ex.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 63 72 63 5f 65 78 2e 68 00 01 00 00 000060: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000077: file "" : 00 000078: DW_LNS_negate_stmt : 06 000079: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_crc_ex.h:1.0 [ ** Section #122 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 280 bytes 000000: Header: size 0x114 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_crc_ex.h 00004c: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000093: DW_AT_language DW_LANG_C89 000095: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010c: DW_AT_macro_info 0x0 000110: DW_AT_stmt_list 0x0 000114: 0 null 000115: 0 padding 000116: 0 padding 000117: 0 padding ** Section #385 '.rel.debug_info' (SHT_REL) Size : 24 bytes (alignment 4) Symbol table #343 '.symtab' 3 relocations applied to section #122 '.debug_info' ** Section #123 '__ARM_grp.stm32f7xx_hal_crc.h.2_cBY000_OQbA5PtVzH5_l10000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #124 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 2036 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_CRC_H 00001c: include at line 47 - file 2 00001f: end include 000020: line 162 define DEFAULT_CRC32_POLY 0x04C11DB7U 000042: line 171 define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU 000067: line 180 define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) 000095: line 181 define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) 0000c4: line 191 define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) 0000f2: line 192 define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) 000121: line 201 define CRC_POLYLENGTH_32B ((uint32_t)0x00000000U) 00014f: line 202 define CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0) 000183: line 203 define CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1) 0001b6: line 204 define CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE) 0001e7: line 212 define HAL_CRC_LENGTH_32B 32U 000201: line 213 define HAL_CRC_LENGTH_16B 16U 00021b: line 214 define HAL_CRC_LENGTH_8B 8U 000233: line 215 define HAL_CRC_LENGTH_7B 7U 00024b: line 228 define CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000U) 000285: line 229 define CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001U) 0002bb: line 230 define CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002U) 0002f5: line 231 define CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003U) 00032b: line 249 define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET) 000383: line 256 define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET) 0003d2: line 264 define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__,__INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__)) 000437: line 272 define __HAL_CRC_SET_IDR(__HANDLE__,__VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__))) 0004a5: line 279 define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR) 0004f4: include at line 286 - file 3 0004f8: end include 0004f9: line 306 define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse 000534: line 307 define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse 000571: line 373 define IS_DEFAULT_POLYNOMIAL(__DEFAULT__) (((__DEFAULT__) == DEFAULT_POLYNOMIAL_ENABLE) || ((__DEFAULT__) == DEFAULT_POLYNOMIAL_DISABLE)) 0005f7: line 375 define IS_DEFAULT_INIT_VALUE(__VALUE__) (((__VALUE__) == DEFAULT_INIT_VALUE_ENABLE) || ((__VALUE__) == DEFAULT_INIT_VALUE_DISABLE)) 000677: line 377 define IS_CRC_POL_LENGTH(__LENGTH__) (((__LENGTH__) == CRC_POLYLENGTH_32B) || ((__LENGTH__) == CRC_POLYLENGTH_16B) || ((__LENGTH__) == CRC_POLYLENGTH_8B) || ((__LENGTH__) == CRC_POLYLENGTH_7B)) 000735: line 381 define IS_CRC_INPUTDATA_FORMAT(__FORMAT__) (((__FORMAT__) == CRC_INPUTDATA_FORMAT_BYTES) || ((__FORMAT__) == CRC_INPUTDATA_FORMAT_HALFWORDS) || ((__FORMAT__) == CRC_INPUTDATA_FORMAT_WORDS)) 0007ef: end include 0007f0: end of translation unit ** Section #125 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 148 bytes 000000: Header: length 144 (not including this field) version 3 prologue length 133 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_crc.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 63 72 63 2e 68 00 01 00 00 00005d: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000074: file "stm32f7xx_hal_crc_ex.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 63 72 63 5f 65 78 2e 68 00 01 00 00 00008e: file "" : 00 00008f: DW_LNS_negate_stmt : 06 000090: DW_LNS_negate_stmt : 06 000091: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_crc.h:1.0 ** Section #126 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 768 bytes 000000: Header: size 0x2fc bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_crc.h 000049: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000090: DW_AT_language DW_LANG_C89 000092: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 000109: DW_AT_macro_info 0x0 00010d: DW_AT_stmt_list 0x0 000111: 19 = 0x4 (DW_TAG_enumeration_type) 000112: DW_AT_sibling 0x18a 000114: DW_AT_byte_size 0x1 000115: 20 = 0x28 (DW_TAG_enumerator) 000116: DW_AT_name HAL_CRC_STATE_RESET 00012a: DW_AT_const_value indirect DW_FORM_data1 0x0 00012c: 20 = 0x28 (DW_TAG_enumerator) 00012d: DW_AT_name HAL_CRC_STATE_READY 000141: DW_AT_const_value indirect DW_FORM_data1 0x1 000143: 20 = 0x28 (DW_TAG_enumerator) 000144: DW_AT_name HAL_CRC_STATE_BUSY 000157: DW_AT_const_value indirect DW_FORM_data1 0x2 000159: 20 = 0x28 (DW_TAG_enumerator) 00015a: DW_AT_name HAL_CRC_STATE_TIMEOUT 000170: DW_AT_const_value indirect DW_FORM_data1 0x3 000172: 20 = 0x28 (DW_TAG_enumerator) 000173: DW_AT_name HAL_CRC_STATE_ERROR 000187: DW_AT_const_value indirect DW_FORM_data1 0x4 000189: 0 null 00018a: 80 = 0x16 (DW_TAG_typedef) 00018b: DW_AT_name HAL_CRC_StateTypeDef 0001a0: DW_AT_type indirect DW_FORM_ref2 0x111 0001a3: DW_AT_decl_file 0x1 0001a4: DW_AT_decl_line 0x49 0001a5: DW_AT_decl_column 0x2 0001a6: 42 = 0x13 (DW_TAG_structure_type) 0001a7: DW_AT_sibling 0x26b 0001a9: DW_AT_byte_size 0x18 0001aa: 30 = 0xd (DW_TAG_member) 0001ab: DW_AT_name DefaultPolynomialUse 0001c0: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001c5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0001c8: 30 = 0xd (DW_TAG_member) 0001c9: DW_AT_name DefaultInitValueUse 0001dd: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001e2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 1 } 0001e5: 30 = 0xd (DW_TAG_member) 0001e6: DW_AT_name GeneratingPolynomial 0001fb: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000200: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000203: 30 = 0xd (DW_TAG_member) 000204: DW_AT_name CRCLength 00020e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000213: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000216: 30 = 0xd (DW_TAG_member) 000217: DW_AT_name InitValue 000221: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000226: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000229: 30 = 0xd (DW_TAG_member) 00022a: DW_AT_name InputDataInversionMode 000241: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000246: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000249: 30 = 0xd (DW_TAG_member) 00024a: DW_AT_name OutputDataInversionMode 000262: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000267: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 00026a: 0 null 00026b: 80 = 0x16 (DW_TAG_typedef) 00026c: DW_AT_name CRC_InitTypeDef 00027c: DW_AT_type indirect DW_FORM_ref2 0x1a6 00027f: DW_AT_decl_file 0x1 000280: DW_AT_decl_line 0x78 000281: DW_AT_decl_column 0x2 000282: 42 = 0x13 (DW_TAG_structure_type) 000283: DW_AT_sibling 0x2d7 000285: DW_AT_byte_size 0x24 000286: 30 = 0xd (DW_TAG_member) 000287: DW_AT_name Instance 000290: DW_AT_type indirect DW_FORM_ref2 0x2d7 000293: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000296: 30 = 0xd (DW_TAG_member) 000297: DW_AT_name Init 00029c: DW_AT_type indirect DW_FORM_ref2 0x26b 00029f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0002a2: 30 = 0xd (DW_TAG_member) 0002a3: DW_AT_name Lock 0002a8: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 0002ad: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 0002b0: 30 = 0xd (DW_TAG_member) 0002b1: DW_AT_name State 0002b7: DW_AT_type indirect DW_FORM_ref2 0x2dd 0002ba: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 29 } 0002bd: 30 = 0xd (DW_TAG_member) 0002be: DW_AT_name InputDataFormat 0002ce: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002d3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 0002d6: 0 null 0002d7: 34 = 0xf (DW_TAG_pointer_type) 0002d8: DW_AT_type indirect DW_FORM_ref_addr 0xd29+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 0002dd: 116 = 0x35 (DW_TAG_volatile_type) 0002de: DW_AT_type indirect DW_FORM_ref2 0x18a 0002e1: 80 = 0x16 (DW_TAG_typedef) 0002e2: DW_AT_name CRC_HandleTypeDef 0002f4: DW_AT_type indirect DW_FORM_ref2 0x282 0002f7: DW_AT_decl_file 0x1 0002f8: DW_AT_decl_line 0x91 0002fa: DW_AT_decl_column 0x2 0002fb: 0 null 0002fc: 0 padding 0002fd: 0 padding 0002fe: 0 padding 0002ff: 0 padding ** Section #386 '.rel.debug_info' (SHT_REL) Size : 104 bytes (alignment 4) Symbol table #343 '.symtab' 13 relocations applied to section #126 '.debug_info' ** Section #127 '__ARM_grp.stm32f7xx_hal_cryp.h.2_Uv0000_HHDFQ046MH7_300000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #128 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 36 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_CRYP_H 00001d: include at line 47 - file 2 000020: end include 000021: end include 000022: end of translation unit ** Section #129 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 124 bytes 000000: Header: length 120 (not including this field) version 3 prologue length 108 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_cryp.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 63 72 79 70 2e 68 00 01 00 00 00005e: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000075: file "" : 00 000076: DW_LNS_negate_stmt : 06 000077: DW_LNS_negate_stmt : 06 000078: DW_LNS_negate_stmt : 06 000079: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_cryp.h:1.0 [ ** Section #130 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 276 bytes 000000: Header: size 0x110 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_cryp.h 00004a: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000091: DW_AT_language DW_LANG_C89 000093: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010a: DW_AT_macro_info 0x0 00010e: DW_AT_stmt_list 0x0 000112: 0 null 000113: 0 padding ** Section #387 '.rel.debug_info' (SHT_REL) Size : 24 bytes (alignment 4) Symbol table #343 '.symtab' 3 relocations applied to section #130 '.debug_info' ** Section #131 '__ARM_grp.stm32f7xx_hal_dma2d.h.2_s6_000_xrgxrrQoo$8_v10000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #132 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 4972 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_DMA2D_H 00001e: include at line 49 - file 2 000021: end include 000022: line 64 define MAX_DMA2D_LAYER 2 000036: line 209 define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000U) 000066: line 210 define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001U) 000094: line 211 define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002U) 0000c2: line 212 define HAL_DMA2D_ERROR_CAE ((uint32_t)0x00000004U) 0000f1: line 213 define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020U) 000124: line 221 define DMA2D_M2M ((uint32_t)0x00000000U) 000149: line 222 define DMA2D_M2M_PFC DMA2D_CR_MODE_0 00016a: line 223 define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 00018d: line 224 define DMA2D_R2M DMA2D_CR_MODE 0001a8: line 232 define DMA2D_OUTPUT_ARGB8888 ((uint32_t)0x00000000U) 0001d9: line 233 define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 000202: line 234 define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 00022b: line 235 define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) 00026a: line 236 define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 000295: line 244 define DMA2D_INPUT_ARGB8888 ((uint32_t)0x00000000U) 0002c5: line 245 define DMA2D_INPUT_RGB888 ((uint32_t)0x00000001U) 0002f3: line 246 define DMA2D_INPUT_RGB565 ((uint32_t)0x00000002U) 000321: line 247 define DMA2D_INPUT_ARGB1555 ((uint32_t)0x00000003U) 000351: line 248 define DMA2D_INPUT_ARGB4444 ((uint32_t)0x00000004U) 000381: line 249 define DMA2D_INPUT_L8 ((uint32_t)0x00000005U) 0003ab: line 250 define DMA2D_INPUT_AL44 ((uint32_t)0x00000006U) 0003d7: line 251 define DMA2D_INPUT_AL88 ((uint32_t)0x00000007U) 000403: line 252 define DMA2D_INPUT_L4 ((uint32_t)0x00000008U) 00042d: line 253 define DMA2D_INPUT_A8 ((uint32_t)0x00000009U) 000457: line 254 define DMA2D_INPUT_A4 ((uint32_t)0x0000000AU) 000481: line 262 define DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000U) 0004b1: line 263 define DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001U) 0004e0: line 264 define DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002U) 00050f: line 274 define DMA2D_REGULAR_ALPHA ((uint32_t)0x00000000U) 00053e: line 275 define DMA2D_INVERTED_ALPHA ((uint32_t)0x00000001U) 00056e: line 285 define DMA2D_RB_REGULAR ((uint32_t)0x00000000U) 00059a: line 286 define DMA2D_RB_SWAP ((uint32_t)0x00000001U) 0005c3: line 295 define DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000U) 0005f1: line 296 define DMA2D_CCM_RGB888 ((uint32_t)0x00000001U) 00061d: line 305 define DMA2D_IT_CE DMA2D_CR_CEIE 00063a: line 306 define DMA2D_IT_CTC DMA2D_CR_CTCIE 000659: line 307 define DMA2D_IT_CAE DMA2D_CR_CAEIE 000678: line 308 define DMA2D_IT_TW DMA2D_CR_TWIE 000695: line 309 define DMA2D_IT_TC DMA2D_CR_TCIE 0006b2: line 310 define DMA2D_IT_TE DMA2D_CR_TEIE 0006cf: line 318 define DMA2D_FLAG_CE DMA2D_ISR_CEIF 0006ef: line 319 define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF 000711: line 320 define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF 000733: line 321 define DMA2D_FLAG_TW DMA2D_ISR_TWIF 000753: line 322 define DMA2D_FLAG_TC DMA2D_ISR_TCIF 000773: line 323 define DMA2D_FLAG_TE DMA2D_ISR_TEIF 000793: line 331 define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort 0007c8: line 349 define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET) 000824: line 356 define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START) 000875: line 373 define __HAL_DMA2D_GET_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) 0008cd: line 388 define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__)) 000928: line 403 define __HAL_DMA2D_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) 00098b: line 418 define __HAL_DMA2D_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) 0009f0: line 433 define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) 000a56: line 527 define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW 000a7f: line 535 define DMA2D_COLOR_VALUE ((uint32_t)0x000000FFU) 000aac: line 543 define DMA2D_MAX_LAYER 2 000ac1: line 551 define DMA2D_OFFSET DMA2D_FGOR_LO 000adf: line 559 define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) 000b04: line 560 define DMA2D_LINE DMA2D_NLR_NL 000b1f: line 568 define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8) 000b4a: line 582 define IS_DMA2D_LAYER(LAYER) ((LAYER) <= DMA2D_MAX_LAYER) 000b80: line 583 define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M)) 000c04: line 585 define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444)) 000cee: line 588 define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE) 000d26: line 589 define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE) 000d54: line 590 define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL) 000d86: line 591 define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET) 000dbe: line 592 define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || ((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || ((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || ((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || ((INPUT_CM) == DMA2D_INPUT_A4)) 000f78: line 598 define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || ((AlphaMode) == DMA2D_REPLACE_ALPHA) || ((AlphaMode) == DMA2D_COMBINE_ALPHA)) 001012: line 602 define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA)) 001097: line 605 define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || ((RB_Swap) == DMA2D_RB_SWAP)) 0010f6: line 608 define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888)) 00115a: line 609 define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) 00119c: line 610 define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX) 0011f3: line 611 define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) 00129d: line 614 define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) 001367: end include 001368: end of translation unit ** Section #133 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 124 bytes 000000: Header: length 120 (not including this field) version 3 prologue length 109 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_dma2d.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 6d 61 32 64 2e 68 00 01 00 00 00005f: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000076: file "" : 00 000077: DW_LNS_negate_stmt : 06 000078: DW_LNS_negate_stmt : 06 000079: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma2d.h:1.0 ** Section #134 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 1168 bytes 000000: Header: size 0x48c bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma2d.h 00004b: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000092: DW_AT_language DW_LANG_C89 000094: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010b: DW_AT_macro_info 0x0 00010f: DW_AT_stmt_list 0x0 000113: 42 = 0x13 (DW_TAG_structure_type) 000114: DW_AT_sibling 0x142 000116: DW_AT_byte_size 0xc 000117: 30 = 0xd (DW_TAG_member) 000118: DW_AT_name Blue 00011d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000122: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000125: 30 = 0xd (DW_TAG_member) 000126: DW_AT_name Green 00012c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000131: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000134: 30 = 0xd (DW_TAG_member) 000135: DW_AT_name Red 000139: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00013e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000141: 0 null 000142: 80 = 0x16 (DW_TAG_typedef) 000143: DW_AT_name DMA2D_ColorTypeDef 000156: DW_AT_type indirect DW_FORM_ref2 0x113 000159: DW_AT_decl_file 0x1 00015a: DW_AT_decl_line 0x4f 00015b: DW_AT_decl_column 0x3 00015c: 42 = 0x13 (DW_TAG_structure_type) 00015d: DW_AT_sibling 0x193 00015f: DW_AT_byte_size 0xc 000160: 30 = 0xd (DW_TAG_member) 000161: DW_AT_name pCLUT 000167: DW_AT_type indirect DW_FORM_ref2 0x193 00016a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00016d: 30 = 0xd (DW_TAG_member) 00016e: DW_AT_name CLUTColorMode 00017c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000181: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000184: 30 = 0xd (DW_TAG_member) 000185: DW_AT_name Size 00018a: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00018f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000192: 0 null 000193: 34 = 0xf (DW_TAG_pointer_type) 000194: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000199: 80 = 0x16 (DW_TAG_typedef) 00019a: DW_AT_name DMA2D_CLUTCfgTypeDef 0001af: DW_AT_type indirect DW_FORM_ref2 0x15c 0001b2: DW_AT_decl_file 0x1 0001b3: DW_AT_decl_line 0x5d 0001b4: DW_AT_decl_column 0x3 0001b5: 42 = 0x13 (DW_TAG_structure_type) 0001b6: DW_AT_sibling 0x21d 0001b8: DW_AT_byte_size 0x14 0001b9: 30 = 0xd (DW_TAG_member) 0001ba: DW_AT_name Mode 0001bf: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001c4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0001c7: 30 = 0xd (DW_TAG_member) 0001c8: DW_AT_name ColorMode 0001d2: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001d7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0001da: 30 = 0xd (DW_TAG_member) 0001db: DW_AT_name OutputOffset 0001e8: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001ed: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0001f0: 30 = 0xd (DW_TAG_member) 0001f1: DW_AT_name AlphaInverted 0001ff: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000204: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000207: 30 = 0xd (DW_TAG_member) 000208: DW_AT_name RedBlueSwap 000214: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000219: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 00021c: 0 null 00021d: 80 = 0x16 (DW_TAG_typedef) 00021e: DW_AT_name DMA2D_InitTypeDef 000230: DW_AT_type indirect DW_FORM_ref2 0x1b5 000233: DW_AT_decl_file 0x1 000234: DW_AT_decl_line 0x77 000235: DW_AT_decl_column 0x3 000236: 42 = 0x13 (DW_TAG_structure_type) 000237: DW_AT_sibling 0x2bb 000239: DW_AT_byte_size 0x18 00023a: 30 = 0xd (DW_TAG_member) 00023b: DW_AT_name InputOffset 000247: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00024c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00024f: 30 = 0xd (DW_TAG_member) 000250: DW_AT_name InputColorMode 00025f: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000264: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000267: 30 = 0xd (DW_TAG_member) 000268: DW_AT_name AlphaMode 000272: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000277: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 00027a: 30 = 0xd (DW_TAG_member) 00027b: DW_AT_name InputAlpha 000286: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00028b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00028e: 30 = 0xd (DW_TAG_member) 00028f: DW_AT_name AlphaInverted 00029d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002a2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 0002a5: 30 = 0xd (DW_TAG_member) 0002a6: DW_AT_name RedBlueSwap 0002b2: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002b7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 0002ba: 0 null 0002bb: 80 = 0x16 (DW_TAG_typedef) 0002bc: DW_AT_name DMA2D_LayerCfgTypeDef 0002d2: DW_AT_type indirect DW_FORM_ref2 0x236 0002d5: DW_AT_decl_file 0x1 0002d6: DW_AT_decl_line 0xa1 0002d8: DW_AT_decl_column 0x3 0002d9: 19 = 0x4 (DW_TAG_enumeration_type) 0002da: DW_AT_sibling 0x377 0002dc: DW_AT_byte_size 0x1 0002dd: 20 = 0x28 (DW_TAG_enumerator) 0002de: DW_AT_name HAL_DMA2D_STATE_RESET 0002f4: DW_AT_const_value indirect DW_FORM_data1 0x0 0002f6: 20 = 0x28 (DW_TAG_enumerator) 0002f7: DW_AT_name HAL_DMA2D_STATE_READY 00030d: DW_AT_const_value indirect DW_FORM_data1 0x1 00030f: 20 = 0x28 (DW_TAG_enumerator) 000310: DW_AT_name HAL_DMA2D_STATE_BUSY 000325: DW_AT_const_value indirect DW_FORM_data1 0x2 000327: 20 = 0x28 (DW_TAG_enumerator) 000328: DW_AT_name HAL_DMA2D_STATE_TIMEOUT 000340: DW_AT_const_value indirect DW_FORM_data1 0x3 000342: 20 = 0x28 (DW_TAG_enumerator) 000343: DW_AT_name HAL_DMA2D_STATE_ERROR 000359: DW_AT_const_value indirect DW_FORM_data1 0x4 00035b: 20 = 0x28 (DW_TAG_enumerator) 00035c: DW_AT_name HAL_DMA2D_STATE_SUSPEND 000374: DW_AT_const_value indirect DW_FORM_data1 0x5 000376: 0 null 000377: 80 = 0x16 (DW_TAG_typedef) 000378: DW_AT_name HAL_DMA2D_StateTypeDef 00038f: DW_AT_type indirect DW_FORM_ref2 0x2d9 000392: DW_AT_decl_file 0x1 000393: DW_AT_decl_line 0xae 000395: DW_AT_decl_column 0x2 000396: 41 = 0x13 (DW_TAG_structure_type) 000397: DW_AT_sibling 0x45b 000399: DW_AT_name __DMA2D_HandleTypeDef 0003af: DW_AT_byte_size 0x58 0003b0: 30 = 0xd (DW_TAG_member) 0003b1: DW_AT_name Instance 0003ba: DW_AT_type indirect DW_FORM_ref2 0x45b 0003bd: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0003c0: 30 = 0xd (DW_TAG_member) 0003c1: DW_AT_name Init 0003c6: DW_AT_type indirect DW_FORM_ref2 0x21d 0003c9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0003cc: 79 = 0x15 (DW_TAG_subroutine_type) 0003cd: DW_AT_sibling 0x3d4 0003cf: 37 = 0x5 (DW_TAG_formal_parameter) 0003d0: DW_AT_type indirect DW_FORM_ref2 0x461 0003d3: 0 null 0003d4: 34 = 0xf (DW_TAG_pointer_type) 0003d5: DW_AT_type indirect DW_FORM_ref2 0x3cc 0003d8: 30 = 0xd (DW_TAG_member) 0003d9: DW_AT_name XferCpltCallback 0003ea: DW_AT_type indirect DW_FORM_ref2 0x3d4 0003ed: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 0003f0: 79 = 0x15 (DW_TAG_subroutine_type) 0003f1: DW_AT_sibling 0x3f8 0003f3: 37 = 0x5 (DW_TAG_formal_parameter) 0003f4: DW_AT_type indirect DW_FORM_ref2 0x461 0003f7: 0 null 0003f8: 34 = 0xf (DW_TAG_pointer_type) 0003f9: DW_AT_type indirect DW_FORM_ref2 0x3f0 0003fc: 30 = 0xd (DW_TAG_member) 0003fd: DW_AT_name XferErrorCallback 00040f: DW_AT_type indirect DW_FORM_ref2 0x3f8 000412: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 000415: 3 = 0x1 (DW_TAG_array_type) 000416: DW_AT_sibling 0x41e 000418: DW_AT_type indirect DW_FORM_ref2 0x2bb 00041b: 1 = 0x21 (DW_TAG_subrange_type) 00041c: DW_AT_upper_bound 0x1 00041d: 0 null 00041e: 30 = 0xd (DW_TAG_member) 00041f: DW_AT_name LayerCfg 000428: DW_AT_type indirect DW_FORM_ref2 0x415 00042b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 00042e: 30 = 0xd (DW_TAG_member) 00042f: DW_AT_name Lock 000434: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 000439: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 80 } 00043c: 30 = 0xd (DW_TAG_member) 00043d: DW_AT_name State 000443: DW_AT_type indirect DW_FORM_ref2 0x465 000446: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 81 } 000449: 30 = 0xd (DW_TAG_member) 00044a: DW_AT_name ErrorCode 000454: DW_AT_type indirect DW_FORM_ref2 0x469 000457: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 84 } 00045a: 0 null 00045b: 34 = 0xf (DW_TAG_pointer_type) 00045c: DW_AT_type indirect DW_FORM_ref_addr 0x127e+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 000461: 34 = 0xf (DW_TAG_pointer_type) 000462: DW_AT_type indirect DW_FORM_ref2 0x396 000465: 116 = 0x35 (DW_TAG_volatile_type) 000466: DW_AT_type indirect DW_FORM_ref2 0x377 000469: 116 = 0x35 (DW_TAG_volatile_type) 00046a: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00046f: 80 = 0x16 (DW_TAG_typedef) 000470: DW_AT_name DMA2D_HandleTypeDef 000484: DW_AT_type indirect DW_FORM_ref2 0x396 000487: DW_AT_decl_file 0x1 000488: DW_AT_decl_line 0xc4 00048a: DW_AT_decl_column 0x3 00048b: 0 null 00048c: 0 padding 00048d: 0 padding 00048e: 0 padding 00048f: 0 padding ** Section #388 '.rel.debug_info' (SHT_REL) Size : 184 bytes (alignment 4) Symbol table #343 '.symtab' 23 relocations applied to section #134 '.debug_info' ** Section #135 '__ARM_grp.stm32f7xx_hal_dac_ex.h.2_YM1000_jnWia6OT4ef_300000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #136 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 2628 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_DAC_EX_H 00001f: include at line 47 - file 2 000022: end include 000023: line 66 define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000U) 000051: line 67 define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) 000085: line 68 define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) 0000b9: line 69 define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) 0000fe: line 70 define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) 000132: line 71 define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) 000177: line 72 define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) 0001bc: line 73 define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) 000212: line 74 define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) 000246: line 75 define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) 00028b: line 76 define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) 0002d1: line 77 define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) 000328: line 78 define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000U) 00035a: line 79 define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) 00038f: line 80 define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) 0003c4: line 81 define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) 00040b: line 82 define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) 000441: line 83 define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) 000488: line 84 define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) 0004d0: line 85 define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) 000529: line 86 define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) 000560: line 87 define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) 0005a9: line 88 define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) 0005f2: line 89 define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) 00064c: line 138 define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095)) 000a40: end include 000a41: end of translation unit ** Section #137 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 124 bytes 000000: Header: length 120 (not including this field) version 3 prologue length 110 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_dac_ex.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 61 63 5f 65 78 2e 68 00 01 00 00 000060: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000077: file "" : 00 000078: DW_LNS_negate_stmt : 06 000079: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dac_ex.h:1.0 [ ** Section #138 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 280 bytes 000000: Header: size 0x114 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dac_ex.h 00004c: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000093: DW_AT_language DW_LANG_C89 000095: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010c: DW_AT_macro_info 0x0 000110: DW_AT_stmt_list 0x0 000114: 0 null 000115: 0 padding 000116: 0 padding 000117: 0 padding ** Section #389 '.rel.debug_info' (SHT_REL) Size : 24 bytes (alignment 4) Symbol table #343 '.symtab' 3 relocations applied to section #138 '.debug_info' ** Section #139 '__ARM_grp.stm32f7xx_hal_dac.h.2_8p0100_8v6z3eand98_B10000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #140 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 3084 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_DAC_H 00001c: include at line 47 - file 2 00001f: end include 000020: line 116 define HAL_DAC_ERROR_NONE 0x00U 00003b: line 117 define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U 000060: line 118 define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U 000085: line 119 define HAL_DAC_ERROR_DMA 0x04U 00009f: line 128 define DAC_TRIGGER_NONE ((uint32_t)0x00000000U) 0000cb: line 130 define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) 00010d: line 131 define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) 000160: line 132 define DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) 0001b3: line 133 define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) 0001e2: line 134 define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) 000224: line 135 define DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) 000266: line 137 define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) 0002b9: line 138 define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) 0002fa: line 146 define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000U) 00032d: line 147 define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1) 000362: line 155 define DAC_CHANNEL_1 ((uint32_t)0x00000000U) 00038b: line 156 define DAC_CHANNEL_2 ((uint32_t)0x00000010U) 0003b4: line 164 define DAC_ALIGN_12B_R ((uint32_t)0x00000000U) 0003df: line 165 define DAC_ALIGN_12B_L ((uint32_t)0x00000004U) 00040a: line 166 define DAC_ALIGN_8B_R ((uint32_t)0x00000008U) 000434: line 174 define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1) 000463: line 175 define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2) 000492: line 183 define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1) 0004bf: line 184 define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2) 0004ec: line 202 define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET) 000544: line 209 define __HAL_DAC_ENABLE(__HANDLE__,__DAC_CHANNEL__) ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_CHANNEL__))) 0005b6: line 217 define __HAL_DAC_DISABLE(__HANDLE__,__DAC_CHANNEL__) ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_CHANNEL__))) 00062a: line 226 define __HAL_DAC_ENABLE_IT(__HANDLE__,__INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) 00068d: line 233 define __HAL_DAC_DISABLE_IT(__HANDLE__,__INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) 0006f2: line 243 define __HAL_DAC_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) 00076b: line 253 define __HAL_DAC_GET_FLAG(__HANDLE__,__FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 0007d2: line 263 define __HAL_DAC_CLEAR_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__)) 00082b: include at line 269 - file 3 00082f: end include 000830: line 345 define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U) 000859: line 346 define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || ((ALIGN) == DAC_ALIGN_12B_L) || ((ALIGN) == DAC_ALIGN_8B_R)) 0008ce: line 349 define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || ((CHANNEL) == DAC_CHANNEL_2)) 000928: line 351 define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || ((STATE) == DAC_OUTPUTBUFFER_DISABLE)) 00099d: line 354 define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) 000b0b: line 368 define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008U) + (__ALIGNMENT__)) 000b5f: line 374 define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014U) + (__ALIGNMENT__)) 000bb3: line 380 define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020U) + (__ALIGNMENT__)) 000c07: end include 000c08: end of translation unit ** Section #141 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 148 bytes 000000: Header: length 144 (not including this field) version 3 prologue length 133 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_dac.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 61 63 2e 68 00 01 00 00 00005d: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000074: file "stm32f7xx_hal_dac_ex.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 61 63 5f 65 78 2e 68 00 01 00 00 00008e: file "" : 00 00008f: DW_LNS_negate_stmt : 06 000090: DW_LNS_negate_stmt : 06 000091: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dac.h:1.0 ** Section #142 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 656 bytes 000000: Header: size 0x28c bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dac.h 000049: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000090: DW_AT_language DW_LANG_C89 000092: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 000109: DW_AT_macro_info 0x0 00010d: DW_AT_stmt_list 0x0 000111: 19 = 0x4 (DW_TAG_enumeration_type) 000112: DW_AT_sibling 0x18a 000114: DW_AT_byte_size 0x1 000115: 20 = 0x28 (DW_TAG_enumerator) 000116: DW_AT_name HAL_DAC_STATE_RESET 00012a: DW_AT_const_value indirect DW_FORM_data1 0x0 00012c: 20 = 0x28 (DW_TAG_enumerator) 00012d: DW_AT_name HAL_DAC_STATE_READY 000141: DW_AT_const_value indirect DW_FORM_data1 0x1 000143: 20 = 0x28 (DW_TAG_enumerator) 000144: DW_AT_name HAL_DAC_STATE_BUSY 000157: DW_AT_const_value indirect DW_FORM_data1 0x2 000159: 20 = 0x28 (DW_TAG_enumerator) 00015a: DW_AT_name HAL_DAC_STATE_TIMEOUT 000170: DW_AT_const_value indirect DW_FORM_data1 0x3 000172: 20 = 0x28 (DW_TAG_enumerator) 000173: DW_AT_name HAL_DAC_STATE_ERROR 000187: DW_AT_const_value indirect DW_FORM_data1 0x4 000189: 0 null 00018a: 80 = 0x16 (DW_TAG_typedef) 00018b: DW_AT_name HAL_DAC_StateTypeDef 0001a0: DW_AT_type indirect DW_FORM_ref2 0x111 0001a3: DW_AT_decl_file 0x1 0001a4: DW_AT_decl_line 0x48 0001a5: DW_AT_decl_column 0x2 0001a6: 42 = 0x13 (DW_TAG_structure_type) 0001a7: DW_AT_sibling 0x20d 0001a9: DW_AT_byte_size 0x14 0001aa: 30 = 0xd (DW_TAG_member) 0001ab: DW_AT_name Instance 0001b4: DW_AT_type indirect DW_FORM_ref2 0x20d 0001b7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0001ba: 30 = 0xd (DW_TAG_member) 0001bb: DW_AT_name State 0001c1: DW_AT_type indirect DW_FORM_ref2 0x213 0001c4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0001c7: 30 = 0xd (DW_TAG_member) 0001c8: DW_AT_name Lock 0001cd: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 0001d2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 5 } 0001d5: 30 = 0xd (DW_TAG_member) 0001d6: DW_AT_name DMA_Handle1 0001e2: DW_AT_type indirect DW_FORM_ref2 0x217 0001e5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0001e8: 30 = 0xd (DW_TAG_member) 0001e9: DW_AT_name DMA_Handle2 0001f5: DW_AT_type indirect DW_FORM_ref2 0x217 0001f8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0001fb: 30 = 0xd (DW_TAG_member) 0001fc: DW_AT_name ErrorCode 000206: DW_AT_type indirect DW_FORM_ref2 0x21d 000209: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 00020c: 0 null 00020d: 34 = 0xf (DW_TAG_pointer_type) 00020e: DW_AT_type indirect DW_FORM_ref_addr 0xe01+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 000213: 116 = 0x35 (DW_TAG_volatile_type) 000214: DW_AT_type indirect DW_FORM_ref2 0x18a 000217: 34 = 0xf (DW_TAG_pointer_type) 000218: DW_AT_type indirect DW_FORM_ref_addr 0x1a0+__ARM_grp..debug_info$stm32f7xx_hal_dma.h$.2_wD1100_gh0hnOcebnc_s10000 00021d: 116 = 0x35 (DW_TAG_volatile_type) 00021e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000223: 80 = 0x16 (DW_TAG_typedef) 000224: DW_AT_name DAC_HandleTypeDef 000236: DW_AT_type indirect DW_FORM_ref2 0x1a6 000239: DW_AT_decl_file 0x1 00023a: DW_AT_decl_line 0x5b 00023b: DW_AT_decl_column 0x2 00023c: 42 = 0x13 (DW_TAG_structure_type) 00023d: DW_AT_sibling 0x270 00023f: DW_AT_byte_size 0x8 000240: 30 = 0xd (DW_TAG_member) 000241: DW_AT_name DAC_Trigger 00024d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000252: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000255: 30 = 0xd (DW_TAG_member) 000256: DW_AT_name DAC_OutputBuffer 000267: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00026c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00026f: 0 null 000270: 80 = 0x16 (DW_TAG_typedef) 000271: DW_AT_name DAC_ChannelConfTypeDef 000288: DW_AT_type indirect DW_FORM_ref2 0x23c 00028b: DW_AT_decl_file 0x1 00028c: DW_AT_decl_line 0x67 00028d: DW_AT_decl_column 0x2 00028e: 0 null 00028f: 0 padding ** Section #390 '.rel.debug_info' (SHT_REL) Size : 72 bytes (alignment 4) Symbol table #343 '.symtab' 9 relocations applied to section #142 '.debug_info' ** Section #143 '__ARM_grp.stm32f7xx_hal_dcmi.h.2_4B1100_rinjHYu2Srb_Q10000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #144 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 5316 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_DCMI_H 00001d: include at line 49 - file 2 000020: end include 000021: line 168 define HAL_DCMI_ERROR_NONE ((uint32_t)0x00000000U) 000050: line 169 define HAL_DCMI_ERROR_OVR ((uint32_t)0x00000001U) 00007e: line 170 define HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002U) 0000ad: line 171 define HAL_DCMI_ERROR_TIMEOUT ((uint32_t)0x00000020U) 0000df: line 172 define HAL_DCMI_ERROR_DMA ((uint32_t)0x00000040U) 00010d: line 180 define DCMI_MODE_CONTINUOUS ((uint32_t)0x00000000U) 00013d: line 182 define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) 00016a: line 191 define DCMI_SYNCHRO_HARDWARE ((uint32_t)0x00000000U) 00019b: line 193 define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) 0001cc: line 203 define DCMI_PCKPOLARITY_FALLING ((uint32_t)0x00000000U) 000200: line 204 define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL) 000236: line 213 define DCMI_VSPOLARITY_LOW ((uint32_t)0x00000000U) 000265: line 214 define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL) 000297: line 223 define DCMI_HSPOLARITY_LOW ((uint32_t)0x00000000U) 0002c6: line 224 define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL) 0002f8: line 233 define DCMI_JPEG_DISABLE ((uint32_t)0x00000000U) 000325: line 234 define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG) 000352: line 243 define DCMI_CR_ALL_FRAME ((uint32_t)0x00000000U) 00037f: line 244 define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0) 0003b7: line 245 define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1) 0003ef: line 254 define DCMI_EXTEND_DATA_8B ((uint32_t)0x00000000U) 00041e: line 255 define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0) 000450: line 256 define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) 000482: line 257 define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1)) 0004c6: line 266 define DCMI_WINDOW_COORDINATE ((uint32_t)0x3FFFU) 0004f4: line 275 define DCMI_WINDOW_HEIGHT ((uint32_t)0x1FFFU) 00051e: line 284 define DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE) 00054d: line 285 define DCMI_IT_OVR ((uint32_t)DCMI_IER_OVR_IE) 000578: line 286 define DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE) 0005a3: line 287 define DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE) 0005d2: line 288 define DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE) 0005ff: line 300 define DCMI_FLAG_HSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) 00063a: line 301 define DCMI_FLAG_VSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) 000675: line 302 define DCMI_FLAG_FNE ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE) 0006ac: line 306 define DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RIS_FRAME_RIS) 0006e0: line 307 define DCMI_FLAG_OVRRI ((uint32_t)DCMI_RIS_OVR_RIS) 000710: line 308 define DCMI_FLAG_ERRRI ((uint32_t)DCMI_RIS_ERR_RIS) 000740: line 309 define DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RIS_VSYNC_RIS) 000774: line 310 define DCMI_FLAG_LINERI ((uint32_t)DCMI_RIS_LINE_RIS) 0007a6: line 314 define DCMI_FLAG_FRAMEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS) 0007e9: line 315 define DCMI_FLAG_OVRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS ) 000829: line 316 define DCMI_FLAG_ERRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS ) 000869: line 317 define DCMI_FLAG_VSYNCMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS) 0008ac: line 318 define DCMI_FLAG_LINEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS ) 0008ee: line 326 define DCMI_BSM_ALL ((uint32_t)0x00000000U) 000916: line 327 define DCMI_BSM_OTHER ((uint32_t)DCMI_CR_BSM_0) 000942: line 328 define DCMI_BSM_ALTERNATE_4 ((uint32_t)DCMI_CR_BSM_1) 000974: line 329 define DCMI_BSM_ALTERNATE_2 ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1)) 0009b8: line 338 define DCMI_OEBS_ODD ((uint32_t)0x00000000U) 0009e1: line 339 define DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS) 000a0c: line 348 define DCMI_LSM_ALL ((uint32_t)0x00000000U) 000a34: line 349 define DCMI_LSM_ALTERNATE_2 ((uint32_t)DCMI_CR_LSM) 000a64: line 358 define DCMI_OELS_ODD ((uint32_t)0x00000000U) 000a8d: line 359 define DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS) 000ab8: line 378 define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET) 000b12: line 385 define __HAL_DCMI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE) 000b62: line 392 define __HAL_DCMI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE)) 000bb6: line 415 define __HAL_DCMI_GET_FLAG(__HANDLE__,__FLAG__) ((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0)? ((__HANDLE__)->Instance->RIS & (__FLAG__)) : (((__FLAG__) & DCMI_SR_INDEX) == 0x0)? ((__HANDLE__)->Instance->MIS & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__))) 000cc7: line 431 define __HAL_DCMI_CLEAR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) 000d20: line 445 define __HAL_DCMI_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) 000d83: line 459 define __HAL_DCMI_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__)) 000de8: line 473 define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) 000e4f: line 547 define DCMI_MIS_INDEX ((uint32_t)0x1000) 000e74: line 548 define DCMI_SR_INDEX ((uint32_t)0x2000) 000e98: line 556 define IS_DCMI_CAPTURE_MODE(MODE) (((MODE) == DCMI_MODE_CONTINUOUS) || ((MODE) == DCMI_MODE_SNAPSHOT)) 000efb: line 559 define IS_DCMI_SYNCHRO(MODE) (((MODE) == DCMI_SYNCHRO_HARDWARE) || ((MODE) == DCMI_SYNCHRO_EMBEDDED)) 000f5d: line 562 define IS_DCMI_PCKPOLARITY(POLARITY) (((POLARITY) == DCMI_PCKPOLARITY_FALLING) || ((POLARITY) == DCMI_PCKPOLARITY_RISING)) 000fd4: line 565 define IS_DCMI_VSPOLARITY(POLARITY) (((POLARITY) == DCMI_VSPOLARITY_LOW) || ((POLARITY) == DCMI_VSPOLARITY_HIGH)) 001042: line 568 define IS_DCMI_HSPOLARITY(POLARITY) (((POLARITY) == DCMI_HSPOLARITY_LOW) || ((POLARITY) == DCMI_HSPOLARITY_HIGH)) 0010b0: line 571 define IS_DCMI_MODE_JPEG(JPEG_MODE) (((JPEG_MODE) == DCMI_JPEG_DISABLE) || ((JPEG_MODE) == DCMI_JPEG_ENABLE)) 00111a: line 574 define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME) || ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || ((RATE) == DCMI_CR_ALTERNATE_4_FRAME)) 0011aa: line 578 define IS_DCMI_EXTENDED_DATA(DATA) (((DATA) == DCMI_EXTEND_DATA_8B) || ((DATA) == DCMI_EXTEND_DATA_10B) || ((DATA) == DCMI_EXTEND_DATA_12B) || ((DATA) == DCMI_EXTEND_DATA_14B)) 001257: line 583 define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE) 0012a9: line 585 define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT) 0012eb: line 587 define IS_DCMI_BYTE_SELECT_MODE(MODE) (((MODE) == DCMI_BSM_ALL) || ((MODE) == DCMI_BSM_OTHER) || ((MODE) == DCMI_BSM_ALTERNATE_4) || ((MODE) == DCMI_BSM_ALTERNATE_2)) 00138e: line 592 define IS_DCMI_BYTE_SELECT_START(POLARITY) (((POLARITY) == DCMI_OEBS_ODD) || ((POLARITY) == DCMI_OEBS_EVEN)) 0013f7: line 595 define IS_DCMI_LINE_SELECT_MODE(MODE) (((MODE) == DCMI_LSM_ALL) || ((MODE) == DCMI_LSM_ALTERNATE_2)) 001458: line 598 define IS_DCMI_LINE_SELECT_START(POLARITY) (((POLARITY) == DCMI_OELS_ODD) || ((POLARITY) == DCMI_OELS_EVEN)) 0014c1: end include 0014c2: end of translation unit ** Section #145 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 124 bytes 000000: Header: length 120 (not including this field) version 3 prologue length 108 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_dcmi.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 63 6d 69 2e 68 00 01 00 00 00005e: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000075: file "" : 00 000076: DW_LNS_negate_stmt : 06 000077: DW_LNS_negate_stmt : 06 000078: DW_LNS_negate_stmt : 06 000079: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dcmi.h:1.0 [ ** Section #146 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 1100 bytes 000000: Header: size 0x448 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dcmi.h 00004a: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000091: DW_AT_language DW_LANG_C89 000093: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010a: DW_AT_macro_info 0x0 00010e: DW_AT_stmt_list 0x0 000112: 19 = 0x4 (DW_TAG_enumeration_type) 000113: DW_AT_sibling 0x1ac 000115: DW_AT_byte_size 0x1 000116: 20 = 0x28 (DW_TAG_enumerator) 000117: DW_AT_name HAL_DCMI_STATE_RESET 00012c: DW_AT_const_value indirect DW_FORM_data1 0x0 00012e: 20 = 0x28 (DW_TAG_enumerator) 00012f: DW_AT_name HAL_DCMI_STATE_READY 000144: DW_AT_const_value indirect DW_FORM_data1 0x1 000146: 20 = 0x28 (DW_TAG_enumerator) 000147: DW_AT_name HAL_DCMI_STATE_BUSY 00015b: DW_AT_const_value indirect DW_FORM_data1 0x2 00015d: 20 = 0x28 (DW_TAG_enumerator) 00015e: DW_AT_name HAL_DCMI_STATE_TIMEOUT 000175: DW_AT_const_value indirect DW_FORM_data1 0x3 000177: 20 = 0x28 (DW_TAG_enumerator) 000178: DW_AT_name HAL_DCMI_STATE_ERROR 00018d: DW_AT_const_value indirect DW_FORM_data1 0x4 00018f: 20 = 0x28 (DW_TAG_enumerator) 000190: DW_AT_name HAL_DCMI_STATE_SUSPENDED 0001a9: DW_AT_const_value indirect DW_FORM_data1 0x5 0001ab: 0 null 0001ac: 80 = 0x16 (DW_TAG_typedef) 0001ad: DW_AT_name HAL_DCMI_StateTypeDef 0001c3: DW_AT_type indirect DW_FORM_ref2 0x112 0001c6: DW_AT_decl_file 0x1 0001c7: DW_AT_decl_line 0x4b 0001c8: DW_AT_decl_column 0x2 0001c9: 42 = 0x13 (DW_TAG_structure_type) 0001ca: DW_AT_sibling 0x228 0001cc: DW_AT_byte_size 0x4 0001cd: 30 = 0xd (DW_TAG_member) 0001ce: DW_AT_name FrameStartCode 0001dd: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001e2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0001e5: 30 = 0xd (DW_TAG_member) 0001e6: DW_AT_name LineStartCode 0001f4: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001f9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 1 } 0001fc: 30 = 0xd (DW_TAG_member) 0001fd: DW_AT_name LineEndCode 000209: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00020e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 2 } 000211: 30 = 0xd (DW_TAG_member) 000212: DW_AT_name FrameEndCode 00021f: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000224: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 3 } 000227: 0 null 000228: 80 = 0x16 (DW_TAG_typedef) 000229: DW_AT_name DCMI_CodesInitTypeDef 00023f: DW_AT_type indirect DW_FORM_ref2 0x1c9 000242: DW_AT_decl_file 0x1 000243: DW_AT_decl_line 0x56 000244: DW_AT_decl_column 0x2 000245: 42 = 0x13 (DW_TAG_structure_type) 000246: DW_AT_sibling 0x351 000248: DW_AT_byte_size 0x30 000249: 30 = 0xd (DW_TAG_member) 00024a: DW_AT_name SynchroMode 000256: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00025b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00025e: 30 = 0xd (DW_TAG_member) 00025f: DW_AT_name PCKPolarity 00026b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000270: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000273: 30 = 0xd (DW_TAG_member) 000274: DW_AT_name VSPolarity 00027f: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000284: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000287: 30 = 0xd (DW_TAG_member) 000288: DW_AT_name HSPolarity 000293: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000298: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00029b: 30 = 0xd (DW_TAG_member) 00029c: DW_AT_name CaptureRate 0002a8: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002ad: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 0002b0: 30 = 0xd (DW_TAG_member) 0002b1: DW_AT_name ExtendedDataMode 0002c2: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002c7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 0002ca: 30 = 0xd (DW_TAG_member) 0002cb: DW_AT_name SyncroCode 0002d6: DW_AT_type indirect DW_FORM_ref2 0x228 0002d9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 0002dc: 30 = 0xd (DW_TAG_member) 0002dd: DW_AT_name JPEGMode 0002e6: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002eb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 0002ee: 30 = 0xd (DW_TAG_member) 0002ef: DW_AT_name ByteSelectMode 0002fe: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000303: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 000306: 30 = 0xd (DW_TAG_member) 000307: DW_AT_name ByteSelectStart 000317: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00031c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 00031f: 30 = 0xd (DW_TAG_member) 000320: DW_AT_name LineSelectMode 00032f: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000334: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 000337: 30 = 0xd (DW_TAG_member) 000338: DW_AT_name LineSelectStart 000348: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00034d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 000350: 0 null 000351: 80 = 0x16 (DW_TAG_typedef) 000352: DW_AT_name DCMI_InitTypeDef 000363: DW_AT_type indirect DW_FORM_ref2 0x245 000366: DW_AT_decl_file 0x1 000367: DW_AT_decl_line 0x80 000369: DW_AT_decl_column 0x2 00036a: 42 = 0x13 (DW_TAG_structure_type) 00036b: DW_AT_sibling 0x418 00036d: DW_AT_byte_size 0x50 00036e: 30 = 0xd (DW_TAG_member) 00036f: DW_AT_name Instance 000378: DW_AT_type indirect DW_FORM_ref2 0x418 00037b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00037e: 30 = 0xd (DW_TAG_member) 00037f: DW_AT_name Init 000384: DW_AT_type indirect DW_FORM_ref2 0x351 000387: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00038a: 30 = 0xd (DW_TAG_member) 00038b: DW_AT_name Lock 000390: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 000395: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 000398: 30 = 0xd (DW_TAG_member) 000399: DW_AT_name State 00039f: DW_AT_type indirect DW_FORM_ref2 0x41e 0003a2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 53 } 0003a5: 30 = 0xd (DW_TAG_member) 0003a6: DW_AT_name XferCount 0003b0: DW_AT_type indirect DW_FORM_ref2 0x422 0003b3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 0003b6: 30 = 0xd (DW_TAG_member) 0003b7: DW_AT_name XferSize 0003c0: DW_AT_type indirect DW_FORM_ref2 0x422 0003c3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 60 } 0003c6: 30 = 0xd (DW_TAG_member) 0003c7: DW_AT_name XferTransferNumber 0003da: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003df: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 64 } 0003e2: 30 = 0xd (DW_TAG_member) 0003e3: DW_AT_name pBuffPtr 0003ec: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003f1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 68 } 0003f4: 30 = 0xd (DW_TAG_member) 0003f5: DW_AT_name DMA_Handle 000400: DW_AT_type indirect DW_FORM_ref2 0x428 000403: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 72 } 000406: 30 = 0xd (DW_TAG_member) 000407: DW_AT_name ErrorCode 000411: DW_AT_type indirect DW_FORM_ref2 0x422 000414: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 76 } 000417: 0 null 000418: 34 = 0xf (DW_TAG_pointer_type) 000419: DW_AT_type indirect DW_FORM_ref_addr 0x1068+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 00041e: 116 = 0x35 (DW_TAG_volatile_type) 00041f: DW_AT_type indirect DW_FORM_ref2 0x1ac 000422: 116 = 0x35 (DW_TAG_volatile_type) 000423: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000428: 34 = 0xf (DW_TAG_pointer_type) 000429: DW_AT_type indirect DW_FORM_ref_addr 0x1a0+__ARM_grp..debug_info$stm32f7xx_hal_dma.h$.2_wD1100_gh0hnOcebnc_s10000 00042e: 80 = 0x16 (DW_TAG_typedef) 00042f: DW_AT_name DCMI_HandleTypeDef 000442: DW_AT_type indirect DW_FORM_ref2 0x36a 000445: DW_AT_decl_file 0x1 000446: DW_AT_decl_line 0x9b 000448: DW_AT_decl_column 0x2 000449: 0 null 00044a: 0 padding 00044b: 0 padding ** Section #391 '.rel.debug_info' (SHT_REL) Size : 192 bytes (alignment 4) Symbol table #343 '.symtab' 24 relocations applied to section #146 '.debug_info' ** Section #147 '__ARM_grp.stm32f7xx_hal_eth.h.2_gde100_97_7vzP0IZ2_e20000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #148 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 37288 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_ETH_H 00001c: include at line 49 - file 2 00001f: end include 000020: line 62 define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20) 000052: line 63 define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || ((CMD) == ETH_AUTONEGOTIATION_DISABLE)) 0000c2: line 65 define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || ((SPEED) == ETH_SPEED_100M)) 000114: line 67 define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || ((MODE) == ETH_MODE_HALFDUPLEX)) 000174: line 69 define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || ((MODE) == ETH_RXINTERRUPT_MODE)) 0001d0: line 71 define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || ((MODE) == ETH_CHECKSUM_BY_SOFTWARE)) 00023c: line 73 define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || ((MODE) == ETH_MEDIA_INTERFACE_RMII)) 0002a9: line 75 define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || ((CMD) == ETH_WATCHDOG_DISABLE)) 000304: line 77 define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || ((CMD) == ETH_JABBER_DISABLE)) 000359: line 79 define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || ((GAP) == ETH_INTERFRAMEGAP_88BIT) || ((GAP) == ETH_INTERFRAMEGAP_80BIT) || ((GAP) == ETH_INTERFRAMEGAP_72BIT) || ((GAP) == ETH_INTERFRAMEGAP_64BIT) || ((GAP) == ETH_INTERFRAMEGAP_56BIT) || ((GAP) == ETH_INTERFRAMEGAP_48BIT) || ((GAP) == ETH_INTERFRAMEGAP_40BIT)) 0004a6: line 87 define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || ((CMD) == ETH_CARRIERSENCE_DISABLE)) 00050e: line 89 define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || ((CMD) == ETH_RECEIVEOWN_DISABLE)) 000570: line 91 define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || ((CMD) == ETH_LOOPBACKMODE_DISABLE)) 0005d8: line 93 define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE)) 000649: line 95 define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || ((CMD) == ETH_RETRYTRANSMISSION_DISABLE)) 0006c0: line 97 define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE)) 000741: line 99 define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || ((LIMIT) == ETH_BACKOFFLIMIT_8) || ((LIMIT) == ETH_BACKOFFLIMIT_4) || ((LIMIT) == ETH_BACKOFFLIMIT_1)) 0007eb: line 103 define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || ((CMD) == ETH_DEFFERRALCHECK_DISABLE)) 000858: line 105 define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || ((CMD) == ETH_RECEIVEAll_DISABLE)) 0008ba: line 107 define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || ((CMD) == ETH_SOURCEADDRFILTER_DISABLE)) 000968: line 110 define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER)) 000a20: line 113 define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE)) 000aad: line 115 define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE)) 000b3a: line 117 define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE)) 000bad: line 119 define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE)) 000ca9: line 123 define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT)) 000d6d: line 126 define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF) 000d9a: line 127 define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE)) 000e0b: line 129 define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256)) 000efc: line 133 define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE)) 000f88: line 135 define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE)) 001003: line 137 define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE)) 001081: line 139 define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT)) 00110c: line 141 define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF) 00114f: line 142 define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || ((ADDRESS) == ETH_MAC_ADDRESS1) || ((ADDRESS) == ETH_MAC_ADDRESS2) || ((ADDRESS) == ETH_MAC_ADDRESS3)) 0011fd: line 146 define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || ((ADDRESS) == ETH_MAC_ADDRESS2) || ((ADDRESS) == ETH_MAC_ADDRESS3)) 001287: line 149 define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || ((FILTER) == ETH_MAC_ADDRESSFILTER_DA)) 0012ff: line 151 define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1)) 001415: line 157 define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE)) 0014a8: line 159 define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE)) 001527: line 161 define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE)) 0015a2: line 163 define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE)) 001624: line 165 define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES)) 00181e: line 173 define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE)) 00189a: line 175 define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE)) 001932: line 177 define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES)) 001a45: line 181 define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE)) 001ac3: line 183 define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE)) 001b42: line 185 define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || ((CMD) == ETH_FIXEDBURST_DISABLE)) 001ba5: line 187 define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT)) 001e04: line 199 define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT)) 002063: line 211 define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F) 00209d: line 212 define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX)) 0021d6: line 217 define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || ((FLAG) == ETH_DMATXDESC_IC) || ((FLAG) == ETH_DMATXDESC_LS) || ((FLAG) == ETH_DMATXDESC_FS) || ((FLAG) == ETH_DMATXDESC_DC) || ((FLAG) == ETH_DMATXDESC_DP) || ((FLAG) == ETH_DMATXDESC_TTSE) || ((FLAG) == ETH_DMATXDESC_TER) || ((FLAG) == ETH_DMATXDESC_TCH) || ((FLAG) == ETH_DMATXDESC_TTSS) || ((FLAG) == ETH_DMATXDESC_IHE) || ((FLAG) == ETH_DMATXDESC_ES) || ((FLAG) == ETH_DMATXDESC_JT) || ((FLAG) == ETH_DMATXDESC_FF) || ((FLAG) == ETH_DMATXDESC_PCE) || ((FLAG) == ETH_DMATXDESC_LCA) || ((FLAG) == ETH_DMATXDESC_NC) || ((FLAG) == ETH_DMATXDESC_LCO) || ((FLAG) == ETH_DMATXDESC_EC) || ((FLAG) == ETH_DMATXDESC_VF) || ((FLAG) == ETH_DMATXDESC_CC) || ((FLAG) == ETH_DMATXDESC_ED) || ((FLAG) == ETH_DMATXDESC_UF) || ((FLAG) == ETH_DMATXDESC_DB)) 002503: line 241 define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT)) 002582: line 243 define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL)) 002680: line 247 define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF) 0026b9: line 248 define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || ((FLAG) == ETH_DMARXDESC_AFM) || ((FLAG) == ETH_DMARXDESC_ES) || ((FLAG) == ETH_DMARXDESC_DE) || ((FLAG) == ETH_DMARXDESC_SAF) || ((FLAG) == ETH_DMARXDESC_LE) || ((FLAG) == ETH_DMARXDESC_OE) || ((FLAG) == ETH_DMARXDESC_VLAN) || ((FLAG) == ETH_DMARXDESC_FS) || ((FLAG) == ETH_DMARXDESC_LS) || ((FLAG) == ETH_DMARXDESC_IPV4HCE) || ((FLAG) == ETH_DMARXDESC_LC) || ((FLAG) == ETH_DMARXDESC_FT) || ((FLAG) == ETH_DMARXDESC_RWT) || ((FLAG) == ETH_DMARXDESC_RE) || ((FLAG) == ETH_DMARXDESC_DBE) || ((FLAG) == ETH_DMARXDESC_CE) || ((FLAG) == ETH_DMARXDESC_MAMPCE)) 00292b: line 266 define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || ((BUFFER) == ETH_DMARXDESC_BUFFER2)) 00299c: line 268 define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || ((FLAG) == ETH_PMT_FLAG_MPR)) 0029f9: line 270 define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00)) 002a52: line 271 define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || ((FLAG) == ETH_DMA_FLAG_T)) 002d27: line 282 define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00)) 002d78: line 283 define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || ((IT) == ETH_MAC_IT_PMT)) 002e1e: line 286 define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || ((FLAG) == ETH_MAC_FLAG_PMT)) 002edc: line 289 define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00)) 002f2d: line 290 define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T)) 003135: line 299 define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER)) 0031c2: line 301 define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && ((IT) != 0x00)) 003240: line 303 define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE)) 003308: line 306 define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE)) 003390: line 318 define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001U) 0033bf: line 321 define ETH_SUCCESS ((uint32_t)0U) 0033dd: line 322 define ETH_ERROR ((uint32_t)1U) 0033f9: line 325 define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3U) 00342e: line 328 define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16U) 003461: line 331 define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16U) 003494: line 334 define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16U) 0034c7: line 337 define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16) 0034f8: line 340 define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40U) 003539: line 341 define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44U) 00357a: line 344 define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3U) 0035aa: line 347 define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810FU) 0035da: line 350 define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41U) 00360b: line 353 define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23U) 00363c: line 356 define ETH_WAKEUP_REGISTER_LENGTH 8U 00365d: line 359 define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U 003692: line 665 define ETH_MAX_PACKET_SIZE ((uint32_t)1524U) 0036bb: line 666 define ETH_HEADER ((uint32_t)14U) 0036d9: line 667 define ETH_CRC ((uint32_t)4U) 0036f3: line 668 define ETH_EXTRA ((uint32_t)2U) 00370f: line 669 define ETH_VLAN_TAG ((uint32_t)4U) 00372e: line 670 define ETH_MIN_ETH_PAYLOAD ((uint32_t)46U) 003755: line 671 define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500U) 00377e: line 672 define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000U) 0037ab: line 751 define ETH_DMATXDESC_OWN ((uint32_t)0x80000000U) 0037d8: line 752 define ETH_DMATXDESC_IC ((uint32_t)0x40000000U) 003804: line 753 define ETH_DMATXDESC_LS ((uint32_t)0x20000000U) 003830: line 754 define ETH_DMATXDESC_FS ((uint32_t)0x10000000U) 00385c: line 755 define ETH_DMATXDESC_DC ((uint32_t)0x08000000U) 003888: line 756 define ETH_DMATXDESC_DP ((uint32_t)0x04000000U) 0038b4: line 757 define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000U) 0038e2: line 758 define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000U) 00390f: line 759 define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000U) 003943: line 760 define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000U) 00397b: line 761 define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000U) 0039bb: line 762 define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000U) 0039f8: line 763 define ETH_DMATXDESC_TER ((uint32_t)0x00200000U) 003a25: line 764 define ETH_DMATXDESC_TCH ((uint32_t)0x00100000U) 003a52: line 765 define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000U) 003a80: line 766 define ETH_DMATXDESC_IHE ((uint32_t)0x00010000U) 003aad: line 767 define ETH_DMATXDESC_ES ((uint32_t)0x00008000U) 003ad9: line 768 define ETH_DMATXDESC_JT ((uint32_t)0x00004000U) 003b05: line 769 define ETH_DMATXDESC_FF ((uint32_t)0x00002000U) 003b31: line 770 define ETH_DMATXDESC_PCE ((uint32_t)0x00001000U) 003b5e: line 771 define ETH_DMATXDESC_LCA ((uint32_t)0x00000800U) 003b8b: line 772 define ETH_DMATXDESC_NC ((uint32_t)0x00000400U) 003bb7: line 773 define ETH_DMATXDESC_LCO ((uint32_t)0x00000200U) 003be4: line 774 define ETH_DMATXDESC_EC ((uint32_t)0x00000100U) 003c10: line 775 define ETH_DMATXDESC_VF ((uint32_t)0x00000080U) 003c3c: line 776 define ETH_DMATXDESC_CC ((uint32_t)0x00000078U) 003c68: line 777 define ETH_DMATXDESC_ED ((uint32_t)0x00000004U) 003c94: line 778 define ETH_DMATXDESC_UF ((uint32_t)0x00000002U) 003cc0: line 779 define ETH_DMATXDESC_DB ((uint32_t)0x00000001U) 003cec: line 784 define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000U) 003d1a: line 785 define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFFU) 003d48: line 790 define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFFU) 003d76: line 795 define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFFU) 003da4: line 804 define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFFU) 003dd5: line 807 define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFFU) 003e06: line 832 define ETH_DMARXDESC_OWN ((uint32_t)0x80000000U) 003e33: line 833 define ETH_DMARXDESC_AFM ((uint32_t)0x40000000U) 003e60: line 834 define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000U) 003e8c: line 835 define ETH_DMARXDESC_ES ((uint32_t)0x00008000U) 003eb8: line 836 define ETH_DMARXDESC_DE ((uint32_t)0x00004000U) 003ee4: line 837 define ETH_DMARXDESC_SAF ((uint32_t)0x00002000U) 003f11: line 838 define ETH_DMARXDESC_LE ((uint32_t)0x00001000U) 003f3d: line 839 define ETH_DMARXDESC_OE ((uint32_t)0x00000800U) 003f69: line 840 define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400U) 003f97: line 841 define ETH_DMARXDESC_FS ((uint32_t)0x00000200U) 003fc3: line 842 define ETH_DMARXDESC_LS ((uint32_t)0x00000100U) 003fef: line 843 define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080U) 004020: line 844 define ETH_DMARXDESC_LC ((uint32_t)0x00000040U) 00404c: line 845 define ETH_DMARXDESC_FT ((uint32_t)0x00000020U) 004078: line 846 define ETH_DMARXDESC_RWT ((uint32_t)0x00000010U) 0040a5: line 847 define ETH_DMARXDESC_RE ((uint32_t)0x00000008U) 0040d1: line 848 define ETH_DMARXDESC_DBE ((uint32_t)0x00000004U) 0040fe: line 849 define ETH_DMARXDESC_CE ((uint32_t)0x00000002U) 00412a: line 850 define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001U) 00415a: line 855 define ETH_DMARXDESC_DIC ((uint32_t)0x80000000U) 004187: line 856 define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000U) 0041b5: line 857 define ETH_DMARXDESC_RER ((uint32_t)0x00008000U) 0041e2: line 858 define ETH_DMARXDESC_RCH ((uint32_t)0x00004000U) 00420f: line 859 define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFFU) 00423d: line 864 define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFFU) 00426b: line 869 define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFFU) 004299: line 882 define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000U) 0042ca: line 883 define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000U) 0042fc: line 884 define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00U) 00432e: line 885 define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100U) 004365: line 886 define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200U) 0043a0: line 887 define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300U) 0043db: line 888 define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400U) 004417: line 889 define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500U) 00445c: line 890 define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600U) 00449f: line 891 define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700U) 0044eb: line 892 define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080U) 00451e: line 893 define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040U) 004551: line 894 define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020U) 004582: line 895 define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010U) 0045b3: line 896 define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008U) 0045e4: line 897 define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007U) 004615: line 898 define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001U) 00464a: line 899 define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002U) 00467f: line 900 define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003U) 0046b5: line 903 define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFFU) 0046e6: line 906 define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFFU) 004717: line 913 define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001U) 00474d: line 914 define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000U) 004784: line 922 define ETH_SPEED_10M ((uint32_t)0x00000000U) 0047ad: line 923 define ETH_SPEED_100M ((uint32_t)0x00004000U) 0047d7: line 931 define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800U) 004806: line 932 define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000U) 004835: line 939 define ETH_RXPOLLING_MODE ((uint32_t)0x00000000U) 004863: line 940 define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001U) 004893: line 948 define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000U) 0048c7: line 949 define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001U) 0048fb: line 957 define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000U) 00492e: line 958 define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL) 00496e: line 966 define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000U) 00499d: line 967 define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000U) 0049cd: line 975 define ETH_JABBER_ENABLE ((uint32_t)0x00000000U) 0049fa: line 976 define ETH_JABBER_DISABLE ((uint32_t)0x00400000U) 004a28: line 984 define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000U) 004a5b: line 985 define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000U) 004a8e: line 986 define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000U) 004ac1: line 987 define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000U) 004af4: line 988 define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000U) 004b27: line 989 define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000U) 004b5a: line 990 define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000U) 004b8d: line 991 define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000U) 004bc0: line 999 define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000U) 004bf3: line 1000 define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000U) 004c27: line 1008 define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000U) 004c58: line 1009 define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000U) 004c8a: line 1017 define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000U) 004cbd: line 1018 define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000U) 004cf1: line 1026 define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400U) 004d27: line 1027 define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000U) 004d5e: line 1035 define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000U) 004d96: line 1036 define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200U) 004dcf: line 1044 define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080U) 004e0a: line 1045 define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000U) 004e46: line 1053 define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000U) 004e75: line 1054 define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020U) 004ea3: line 1055 define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040U) 004ed1: line 1056 define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060U) 004eff: line 1064 define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010U) 004f34: line 1065 define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000U) 004f6a: line 1073 define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000U) 004f9b: line 1074 define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000U) 004fcd: line 1082 define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200U) 00500b: line 1083 define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300U) 00504a: line 1084 define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000U) 005082: line 1092 define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040U) 0050bc: line 1093 define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080U) 0050f8: line 1094 define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0U) 005141: line 1102 define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000U) 005180: line 1103 define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020U) 0051c0: line 1111 define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000U) 0051fc: line 1112 define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008U) 005239: line 1120 define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001U) 005270: line 1121 define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000U) 0052a8: line 1129 define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404U) 0052ee: line 1130 define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004U) 00532d: line 1131 define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000U) 00536a: line 1132 define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010U) 0053a4: line 1140 define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402U) 0053e8: line 1141 define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002U) 005425: line 1142 define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000U) 005460: line 1150 define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000U) 005496: line 1151 define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080U) 0054cd: line 1159 define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000U) 005505: line 1160 define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010U) 00553e: line 1161 define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020U) 005578: line 1162 define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030U) 0055b2: line 1170 define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008U) 0055f0: line 1171 define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000U) 00562f: line 1179 define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004U) 005668: line 1180 define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000U) 0056a2: line 1188 define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002U) 0056dc: line 1189 define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000U) 005717: line 1197 define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000U) 00574e: line 1198 define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U) 005785: line 1206 define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000U) 0057b1: line 1207 define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008U) 0057dd: line 1208 define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010U) 005809: line 1209 define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018U) 005835: line 1217 define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000U) 005869: line 1218 define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008U) 00589d: line 1226 define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000U) 0058d2: line 1227 define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000U) 005907: line 1228 define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000U) 00593c: line 1229 define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000U) 005971: line 1230 define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000U) 0059a6: line 1231 define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000U) 0059db: line 1239 define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000U) 005a1d: line 1240 define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000U) 005a60: line 1248 define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000U) 005a9a: line 1249 define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000U) 005ad5: line 1257 define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000U) 005b0e: line 1258 define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000U) 005b48: line 1266 define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000U) 005b83: line 1267 define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000U) 005bbf: line 1275 define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000U) 005bff: line 1276 define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000U) 005c40: line 1277 define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000U) 005c81: line 1278 define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000U) 005cc2: line 1279 define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000U) 005d02: line 1280 define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000U) 005d42: line 1281 define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000U) 005d82: line 1282 define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000U) 005dc2: line 1290 define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080U) 005dfb: line 1291 define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000U) 005e35: line 1299 define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040U) 005e77: line 1300 define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000U) 005eba: line 1308 define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000U) 005efa: line 1309 define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008U) 005f3a: line 1310 define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010U) 005f7a: line 1311 define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018U) 005fbb: line 1319 define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004U) 005ff5: line 1320 define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000U) 006030: line 1328 define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000U) 00606a: line 1329 define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000U) 0060a5: line 1337 define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000U) 0060d6: line 1338 define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000U) 006108: line 1346 define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000U) 00613e: line 1347 define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000U) 006174: line 1348 define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000U) 0061aa: line 1349 define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000U) 0061e0: line 1350 define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000U) 006217: line 1351 define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000U) 00624e: line 1352 define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000U) 00628a: line 1353 define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000U) 0062c6: line 1354 define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000U) 006303: line 1355 define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000U) 006340: line 1356 define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000U) 00637d: line 1357 define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000U) 0063bb: line 1365 define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100U) 0063f1: line 1366 define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200U) 006427: line 1367 define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400U) 00645d: line 1368 define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800U) 006493: line 1369 define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000U) 0064ca: line 1370 define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000U) 006501: line 1371 define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100U) 00653d: line 1372 define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200U) 006579: line 1373 define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400U) 0065b6: line 1374 define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800U) 0065f3: line 1375 define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000U) 006630: line 1376 define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000U) 00666e: line 1384 define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080U) 0066aa: line 1385 define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000U) 0066e7: line 1393 define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000U) 006729: line 1394 define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000U) 00676b: line 1395 define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000U) 0067ad: line 1396 define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000U) 0067ef: line 1397 define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002U) 006827: line 1405 define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000U) 00685d: line 1406 define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000U) 006893: line 1414 define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000U) 0068cb: line 1415 define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000U) 006907: line 1416 define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000U) 00694a: line 1417 define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000U) 00698a: line 1425 define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000U) 0069bb: line 1426 define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001U) 0069ec: line 1434 define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000U) 006a1c: line 1435 define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040U) 006a49: line 1436 define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020U) 006a75: line 1444 define ETH_MMC_IT_TGF ((uint32_t)0x00200000U) 006a9f: line 1445 define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000U) 006acc: line 1446 define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000U) 006af8: line 1454 define ETH_MMC_IT_RGUF ((uint32_t)0x10020000U) 006b23: line 1455 define ETH_MMC_IT_RFAE ((uint32_t)0x10000040U) 006b4e: line 1456 define ETH_MMC_IT_RFCE ((uint32_t)0x10000020U) 006b79: line 1464 define ETH_MAC_FLAG_TST ((uint32_t)0x00000200U) 006ba5: line 1465 define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040U) 006bd2: line 1466 define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020U) 006bff: line 1467 define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010U) 006c2b: line 1468 define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008U) 006c57: line 1476 define ETH_DMA_FLAG_TST ((uint32_t)0x20000000U) 006c83: line 1477 define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000U) 006caf: line 1478 define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000U) 006cdb: line 1479 define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000U) 006d15: line 1480 define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000U) 006d4c: line 1481 define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000U) 006d80: line 1482 define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000U) 006dac: line 1483 define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000U) 006dd8: line 1484 define ETH_DMA_FLAG_ER ((uint32_t)0x00004000U) 006e03: line 1485 define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000U) 006e2f: line 1486 define ETH_DMA_FLAG_ET ((uint32_t)0x00000400U) 006e5a: line 1487 define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200U) 006e86: line 1488 define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100U) 006eb2: line 1489 define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080U) 006ede: line 1490 define ETH_DMA_FLAG_R ((uint32_t)0x00000040U) 006f08: line 1491 define ETH_DMA_FLAG_TU ((uint32_t)0x00000020U) 006f33: line 1492 define ETH_DMA_FLAG_RO ((uint32_t)0x00000010U) 006f5e: line 1493 define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008U) 006f8a: line 1494 define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004U) 006fb6: line 1495 define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002U) 006fe2: line 1496 define ETH_DMA_FLAG_T ((uint32_t)0x00000001U) 00700c: line 1504 define ETH_MAC_IT_TST ((uint32_t)0x00000200U) 007036: line 1505 define ETH_MAC_IT_MMCT ((uint32_t)0x00000040U) 007061: line 1506 define ETH_MAC_IT_MMCR ((uint32_t)0x00000020U) 00708c: line 1507 define ETH_MAC_IT_MMC ((uint32_t)0x00000010U) 0070b6: line 1508 define ETH_MAC_IT_PMT ((uint32_t)0x00000008U) 0070e0: line 1516 define ETH_DMA_IT_TST ((uint32_t)0x20000000U) 00710a: line 1517 define ETH_DMA_IT_PMT ((uint32_t)0x10000000U) 007134: line 1518 define ETH_DMA_IT_MMC ((uint32_t)0x08000000U) 00715e: line 1519 define ETH_DMA_IT_NIS ((uint32_t)0x00010000U) 007188: line 1520 define ETH_DMA_IT_AIS ((uint32_t)0x00008000U) 0071b2: line 1521 define ETH_DMA_IT_ER ((uint32_t)0x00004000U) 0071db: line 1522 define ETH_DMA_IT_FBE ((uint32_t)0x00002000U) 007205: line 1523 define ETH_DMA_IT_ET ((uint32_t)0x00000400U) 00722e: line 1524 define ETH_DMA_IT_RWT ((uint32_t)0x00000200U) 007258: line 1525 define ETH_DMA_IT_RPS ((uint32_t)0x00000100U) 007282: line 1526 define ETH_DMA_IT_RBU ((uint32_t)0x00000080U) 0072ac: line 1527 define ETH_DMA_IT_R ((uint32_t)0x00000040U) 0072d4: line 1528 define ETH_DMA_IT_TU ((uint32_t)0x00000020U) 0072fd: line 1529 define ETH_DMA_IT_RO ((uint32_t)0x00000010U) 007326: line 1530 define ETH_DMA_IT_TJT ((uint32_t)0x00000008U) 007350: line 1531 define ETH_DMA_IT_TBU ((uint32_t)0x00000004U) 00737a: line 1532 define ETH_DMA_IT_TPS ((uint32_t)0x00000002U) 0073a4: line 1533 define ETH_DMA_IT_T ((uint32_t)0x00000001U) 0073cc: line 1541 define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000U) 007407: line 1542 define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000U) 007443: line 1543 define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000U) 00747e: line 1544 define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000U) 0074b9: line 1545 define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000U) 0074f6: line 1546 define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000U) 007531: line 1556 define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000U) 00756b: line 1557 define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000U) 0075a6: line 1558 define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000U) 0075e0: line 1559 define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000U) 00761c: line 1560 define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000U) 007656: line 1561 define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000U) 007690: line 1570 define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000U) 0076ca: line 1571 define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000U) 007709: line 1579 define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000U) 007739: line 1599 define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET) 007791: line 1607 define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__)) 007800: line 1615 define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__)) 00786f: line 1622 define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC)) 0078e7: line 1629 define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC) 007954: line 1636 define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN) 0079b7: line 1643 define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT) 007a48: line 1650 define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN) 007aab: line 1657 define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC) 007b0b: line 1664 define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC) 007b6d: line 1677 define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__,__CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__)) 007be1: line 1684 define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC) 007c43: line 1691 define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC) 007ca5: line 1698 define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP) 007d17: line 1705 define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP) 007d89: line 1717 define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__)) 007df2: line 1729 define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__)) 007e5d: line 1736 define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) 007ec9: line 1743 define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA) 007f4b: line 1750 define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) 007fba: line 1757 define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA) 00802b: line 1771 define __HAL_ETH_MAC_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__)) 008098: line 1780 define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__)) 008101: line 1789 define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__)) 00816c: line 1797 define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__)) 0081d1: line 1805 define __HAL_ETH_DMA_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__)) 00823e: line 1813 define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__)) 00829c: line 1824 define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__,__OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__)) 008323: line 1832 define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__,__VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__)) 008392: line 1840 define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU) 008400: line 1848 define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU) 008470: line 1855 define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE) 0084e0: line 1862 define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) 008552: line 1869 define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE) 0085c2: line 1876 define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) 008634: line 1883 define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD) 008697: line 1890 define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD) 0086fc: line 1902 define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__)) 008774: line 1909 define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP)) 0087ea: line 1916 define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP; (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0) 00888c: line 1924 define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF) 0088f0: line 1931 define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF) 008956: line 1938 define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR) 0089bc: line 1945 define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR) 008a24: line 1952 define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR) 008a8f: line 1959 define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR) 008afa: line 1966 define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR) 008b56: line 1978 define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__,__INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF) 008bd1: line 1989 define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__,__INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF) 008c4c: line 2000 define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__)) 008cbb: line 2012 define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__)) 008d29: line 2018 define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP) 008d72: line 2024 define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP) 008dbd: line 2030 define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP) 008e09: line 2036 define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP) 008e57: line 2042 define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP) 008e9d: line 2048 define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP) 008ee5: line 2054 define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP 008f3e: line 2060 define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP) 008f9b: line 2066 define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP) 008ff7: line 2072 define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP) 009055: line 2078 define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP; EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP 0090d4: line 2085 define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP); EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP) 00915a: line 2092 define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP 0091a6: end include 0091a7: end of translation unit ** Section #149 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 120 bytes 000000: Header: length 116 (not including this field) version 3 prologue length 107 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_eth.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 65 74 68 2e 68 00 01 00 00 00005d: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000074: file "" : 00 000075: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_eth.h:1.0 ** Section #150 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 2516 bytes 000000: Header: size 0x9d0 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_eth.h 000049: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000090: DW_AT_language DW_LANG_C89 000092: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 000109: DW_AT_macro_info 0x0 00010d: DW_AT_stmt_list 0x0 000111: 19 = 0x4 (DW_TAG_enumeration_type) 000112: DW_AT_sibling 0x20a 000114: DW_AT_byte_size 0x1 000115: 20 = 0x28 (DW_TAG_enumerator) 000116: DW_AT_name HAL_ETH_STATE_RESET 00012a: DW_AT_const_value indirect DW_FORM_data1 0x0 00012c: 20 = 0x28 (DW_TAG_enumerator) 00012d: DW_AT_name HAL_ETH_STATE_READY 000141: DW_AT_const_value indirect DW_FORM_data1 0x1 000143: 20 = 0x28 (DW_TAG_enumerator) 000144: DW_AT_name HAL_ETH_STATE_BUSY 000157: DW_AT_const_value indirect DW_FORM_data1 0x2 000159: 20 = 0x28 (DW_TAG_enumerator) 00015a: DW_AT_name HAL_ETH_STATE_BUSY_TX 000170: DW_AT_const_value indirect DW_FORM_data1 0x12 000172: 20 = 0x28 (DW_TAG_enumerator) 000173: DW_AT_name HAL_ETH_STATE_BUSY_RX 000189: DW_AT_const_value indirect DW_FORM_data1 0x22 00018b: 20 = 0x28 (DW_TAG_enumerator) 00018c: DW_AT_name HAL_ETH_STATE_BUSY_TX_RX 0001a5: DW_AT_const_value indirect DW_FORM_data1 0x32 0001a7: 20 = 0x28 (DW_TAG_enumerator) 0001a8: DW_AT_name HAL_ETH_STATE_BUSY_WR 0001be: DW_AT_const_value indirect DW_FORM_data1 0x42 0001c0: 20 = 0x28 (DW_TAG_enumerator) 0001c1: DW_AT_name HAL_ETH_STATE_BUSY_RD 0001d7: DW_AT_const_value indirect DW_FORM_data1 0x82 0001d9: 20 = 0x28 (DW_TAG_enumerator) 0001da: DW_AT_name HAL_ETH_STATE_TIMEOUT 0001f0: DW_AT_const_value indirect DW_FORM_data1 0x3 0001f2: 20 = 0x28 (DW_TAG_enumerator) 0001f3: DW_AT_name HAL_ETH_STATE_ERROR 000207: DW_AT_const_value indirect DW_FORM_data1 0x4 000209: 0 null 00020a: 80 = 0x16 (DW_TAG_typedef) 00020b: DW_AT_name HAL_ETH_StateTypeDef 000220: DW_AT_type indirect DW_FORM_ref2 0x111 000223: DW_AT_decl_file 0x1 000224: DW_AT_decl_line 0x180 000226: DW_AT_decl_column 0x2 000227: 42 = 0x13 (DW_TAG_structure_type) 000228: DW_AT_sibling 0x2c9 00022a: DW_AT_byte_size 0x20 00022b: 30 = 0xd (DW_TAG_member) 00022c: DW_AT_name AutoNegotiation 00023c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000241: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000244: 30 = 0xd (DW_TAG_member) 000245: DW_AT_name Speed 00024b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000250: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000253: 30 = 0xd (DW_TAG_member) 000254: DW_AT_name DuplexMode 00025f: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000264: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000267: 30 = 0xd (DW_TAG_member) 000268: DW_AT_name PhyAddress 000273: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000278: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00027b: 30 = 0xd (DW_TAG_member) 00027c: DW_AT_name MACAddr 000284: DW_AT_type indirect DW_FORM_ref2 0x2c9 000287: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 00028a: 30 = 0xd (DW_TAG_member) 00028b: DW_AT_name RxMode 000292: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000297: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 00029a: 30 = 0xd (DW_TAG_member) 00029b: DW_AT_name ChecksumMode 0002a8: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002ad: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 0002b0: 30 = 0xd (DW_TAG_member) 0002b1: DW_AT_name MediaInterface 0002c0: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002c5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 0002c8: 0 null 0002c9: 34 = 0xf (DW_TAG_pointer_type) 0002ca: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002cf: 80 = 0x16 (DW_TAG_typedef) 0002d0: DW_AT_name ETH_InitTypeDef 0002e0: DW_AT_type indirect DW_FORM_ref2 0x227 0002e3: DW_AT_decl_file 0x1 0002e4: DW_AT_decl_line 0x1a1 0002e6: DW_AT_decl_column 0x3 0002e7: 42 = 0x13 (DW_TAG_structure_type) 0002e8: DW_AT_sibling 0x5c7 0002ea: DW_AT_byte_size 0x74 0002eb: 30 = 0xd (DW_TAG_member) 0002ec: DW_AT_name Watchdog 0002f5: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002fa: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0002fd: 30 = 0xd (DW_TAG_member) 0002fe: DW_AT_name Jabber 000305: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00030a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00030d: 30 = 0xd (DW_TAG_member) 00030e: DW_AT_name InterFrameGap 00031c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000321: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000324: 30 = 0xd (DW_TAG_member) 000325: DW_AT_name CarrierSense 000332: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000337: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00033a: 30 = 0xd (DW_TAG_member) 00033b: DW_AT_name ReceiveOwn 000346: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00034b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 00034e: 30 = 0xd (DW_TAG_member) 00034f: DW_AT_name LoopbackMode 00035c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000361: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 000364: 30 = 0xd (DW_TAG_member) 000365: DW_AT_name ChecksumOffload 000375: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00037a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 00037d: 30 = 0xd (DW_TAG_member) 00037e: DW_AT_name RetryTransmission 000390: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000395: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 000398: 30 = 0xd (DW_TAG_member) 000399: DW_AT_name AutomaticPadCRCStrip 0003ae: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003b3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 0003b6: 30 = 0xd (DW_TAG_member) 0003b7: DW_AT_name BackOffLimit 0003c4: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003c9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 0003cc: 30 = 0xd (DW_TAG_member) 0003cd: DW_AT_name DeferralCheck 0003db: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003e0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 0003e3: 30 = 0xd (DW_TAG_member) 0003e4: DW_AT_name ReceiveAll 0003ef: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003f4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 0003f7: 30 = 0xd (DW_TAG_member) 0003f8: DW_AT_name SourceAddrFilter 000409: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00040e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 000411: 30 = 0xd (DW_TAG_member) 000412: DW_AT_name PassControlFrames 000424: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000429: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 00042c: 30 = 0xd (DW_TAG_member) 00042d: DW_AT_name BroadcastFramesReception 000446: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00044b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 00044e: 30 = 0xd (DW_TAG_member) 00044f: DW_AT_name DestinationAddrFilter 000465: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00046a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 60 } 00046d: 30 = 0xd (DW_TAG_member) 00046e: DW_AT_name PromiscuousMode 00047e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000483: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 64 } 000486: 30 = 0xd (DW_TAG_member) 000487: DW_AT_name MulticastFramesFilter 00049d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004a2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 68 } 0004a5: 30 = 0xd (DW_TAG_member) 0004a6: DW_AT_name UnicastFramesFilter 0004ba: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004bf: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 72 } 0004c2: 30 = 0xd (DW_TAG_member) 0004c3: DW_AT_name HashTableHigh 0004d1: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004d6: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 76 } 0004d9: 30 = 0xd (DW_TAG_member) 0004da: DW_AT_name HashTableLow 0004e7: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004ec: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 80 } 0004ef: 30 = 0xd (DW_TAG_member) 0004f0: DW_AT_name PauseTime 0004fa: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004ff: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 84 } 000502: 30 = 0xd (DW_TAG_member) 000503: DW_AT_name ZeroQuantaPause 000513: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000518: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 88 } 00051b: 30 = 0xd (DW_TAG_member) 00051c: DW_AT_name PauseLowThreshold 00052e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000533: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 92 } 000536: 30 = 0xd (DW_TAG_member) 000537: DW_AT_name UnicastPauseFrameDetect 00054f: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000554: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 96 } 000557: 30 = 0xd (DW_TAG_member) 000558: DW_AT_name ReceiveFlowControl 00056b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000570: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 100 } 000573: 30 = 0xd (DW_TAG_member) 000574: DW_AT_name TransmitFlowControl 000588: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00058d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 104 } 000590: 30 = 0xd (DW_TAG_member) 000591: DW_AT_name VLANTagComparison 0005a3: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0005a8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 108 } 0005ab: 30 = 0xd (DW_TAG_member) 0005ac: DW_AT_name VLANTagIdentifier 0005be: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0005c3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 112 } 0005c6: 0 null 0005c7: 80 = 0x16 (DW_TAG_typedef) 0005c8: DW_AT_name ETH_MACInitTypeDef 0005db: DW_AT_type indirect DW_FORM_ref2 0x2e7 0005de: DW_AT_decl_file 0x1 0005df: DW_AT_decl_line 0x20c 0005e1: DW_AT_decl_column 0x3 0005e2: 42 = 0x13 (DW_TAG_structure_type) 0005e3: DW_AT_sibling 0x7c0 0005e5: DW_AT_byte_size 0x40 0005e6: 30 = 0xd (DW_TAG_member) 0005e7: DW_AT_name DropTCPIPChecksumErrorFrame 000603: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000608: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00060b: 30 = 0xd (DW_TAG_member) 00060c: DW_AT_name ReceiveStoreForward 000620: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000625: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000628: 30 = 0xd (DW_TAG_member) 000629: DW_AT_name FlushReceivedFrame 00063c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000641: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000644: 30 = 0xd (DW_TAG_member) 000645: DW_AT_name TransmitStoreForward 00065a: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00065f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000662: 30 = 0xd (DW_TAG_member) 000663: DW_AT_name TransmitThresholdControl 00067c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000681: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000684: 30 = 0xd (DW_TAG_member) 000685: DW_AT_name ForwardErrorFrames 000698: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00069d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 0006a0: 30 = 0xd (DW_TAG_member) 0006a1: DW_AT_name ForwardUndersizedGoodFrames 0006bd: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0006c2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 0006c5: 30 = 0xd (DW_TAG_member) 0006c6: DW_AT_name ReceiveThresholdControl 0006de: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0006e3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 0006e6: 30 = 0xd (DW_TAG_member) 0006e7: DW_AT_name SecondFrameOperate 0006fa: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0006ff: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 000702: 30 = 0xd (DW_TAG_member) 000703: DW_AT_name AddressAlignedBeats 000717: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00071c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 00071f: 30 = 0xd (DW_TAG_member) 000720: DW_AT_name FixedBurst 00072b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000730: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 000733: 30 = 0xd (DW_TAG_member) 000734: DW_AT_name RxDMABurstLength 000745: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00074a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 00074d: 30 = 0xd (DW_TAG_member) 00074e: DW_AT_name TxDMABurstLength 00075f: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000764: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 000767: 30 = 0xd (DW_TAG_member) 000768: DW_AT_name EnhancedDescriptorFormat 000781: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000786: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 000789: 30 = 0xd (DW_TAG_member) 00078a: DW_AT_name DescriptorSkipLength 00079f: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0007a4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 0007a7: 30 = 0xd (DW_TAG_member) 0007a8: DW_AT_name DMAArbitration 0007b7: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0007bc: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 60 } 0007bf: 0 null 0007c0: 80 = 0x16 (DW_TAG_typedef) 0007c1: DW_AT_name ETH_DMAInitTypeDef 0007d4: DW_AT_type indirect DW_FORM_ref2 0x5e2 0007d7: DW_AT_decl_file 0x1 0007d8: DW_AT_decl_line 0x246 0007da: DW_AT_decl_column 0x3 0007db: 42 = 0x13 (DW_TAG_structure_type) 0007dc: DW_AT_sibling 0x893 0007de: DW_AT_byte_size 0x20 0007df: 30 = 0xd (DW_TAG_member) 0007e0: DW_AT_name Status 0007e7: DW_AT_type indirect DW_FORM_ref2 0x893 0007ea: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0007ed: 30 = 0xd (DW_TAG_member) 0007ee: DW_AT_name ControlBufferSize 000800: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000805: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000808: 30 = 0xd (DW_TAG_member) 000809: DW_AT_name Buffer1Addr 000815: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00081a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 00081d: 30 = 0xd (DW_TAG_member) 00081e: DW_AT_name Buffer2NextDescAddr 000832: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000837: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00083a: 30 = 0xd (DW_TAG_member) 00083b: DW_AT_name ExtendedStatus 00084a: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00084f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000852: 30 = 0xd (DW_TAG_member) 000853: DW_AT_name Reserved1 00085d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000862: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 000865: 30 = 0xd (DW_TAG_member) 000866: DW_AT_name TimeStampLow 000873: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000878: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 00087b: 30 = 0xd (DW_TAG_member) 00087c: DW_AT_name TimeStampHigh 00088a: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00088f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 000892: 0 null 000893: 116 = 0x35 (DW_TAG_volatile_type) 000894: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000899: 80 = 0x16 (DW_TAG_typedef) 00089a: DW_AT_name ETH_DMADescTypeDef 0008ad: DW_AT_type indirect DW_FORM_ref2 0x7db 0008b0: DW_AT_decl_file 0x1 0008b1: DW_AT_decl_line 0x260 0008b3: DW_AT_decl_column 0x3 0008b4: 42 = 0x13 (DW_TAG_structure_type) 0008b5: DW_AT_sibling 0x90b 0008b7: DW_AT_byte_size 0x14 0008b8: 30 = 0xd (DW_TAG_member) 0008b9: DW_AT_name FSRxDesc 0008c2: DW_AT_type indirect DW_FORM_ref2 0x90b 0008c5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0008c8: 30 = 0xd (DW_TAG_member) 0008c9: DW_AT_name LSRxDesc 0008d2: DW_AT_type indirect DW_FORM_ref2 0x90b 0008d5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0008d8: 30 = 0xd (DW_TAG_member) 0008d9: DW_AT_name SegCount 0008e2: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0008e7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0008ea: 30 = 0xd (DW_TAG_member) 0008eb: DW_AT_name length 0008f2: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0008f7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0008fa: 30 = 0xd (DW_TAG_member) 0008fb: DW_AT_name buffer 000902: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000907: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 00090a: 0 null 00090b: 34 = 0xf (DW_TAG_pointer_type) 00090c: DW_AT_type indirect DW_FORM_ref2 0x899 00090f: 80 = 0x16 (DW_TAG_typedef) 000910: DW_AT_name ETH_DMARxFrameInfos 000924: DW_AT_type indirect DW_FORM_ref2 0x8b4 000927: DW_AT_decl_file 0x1 000928: DW_AT_decl_line 0x272 00092a: DW_AT_decl_column 0x3 00092b: 42 = 0x13 (DW_TAG_structure_type) 00092c: DW_AT_sibling 0x9ab 00092e: DW_AT_byte_size 0x48 00092f: 30 = 0xd (DW_TAG_member) 000930: DW_AT_name Instance 000939: DW_AT_type indirect DW_FORM_ref2 0x9ab 00093c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00093f: 30 = 0xd (DW_TAG_member) 000940: DW_AT_name Init 000945: DW_AT_type indirect DW_FORM_ref2 0x2cf 000948: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00094b: 30 = 0xd (DW_TAG_member) 00094c: DW_AT_name LinkStatus 000957: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00095c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 00095f: 30 = 0xd (DW_TAG_member) 000960: DW_AT_name RxDesc 000967: DW_AT_type indirect DW_FORM_ref2 0x90b 00096a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 00096d: 30 = 0xd (DW_TAG_member) 00096e: DW_AT_name TxDesc 000975: DW_AT_type indirect DW_FORM_ref2 0x90b 000978: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 00097b: 30 = 0xd (DW_TAG_member) 00097c: DW_AT_name RxFrameInfos 000989: DW_AT_type indirect DW_FORM_ref2 0x90f 00098c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 00098f: 30 = 0xd (DW_TAG_member) 000990: DW_AT_name State 000996: DW_AT_type indirect DW_FORM_ref2 0x9b1 000999: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 68 } 00099c: 30 = 0xd (DW_TAG_member) 00099d: DW_AT_name Lock 0009a2: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 0009a7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 69 } 0009aa: 0 null 0009ab: 34 = 0xf (DW_TAG_pointer_type) 0009ac: DW_AT_type indirect DW_FORM_ref_addr 0x173d+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 0009b1: 116 = 0x35 (DW_TAG_volatile_type) 0009b2: DW_AT_type indirect DW_FORM_ref2 0x20a 0009b5: 80 = 0x16 (DW_TAG_typedef) 0009b6: DW_AT_name ETH_HandleTypeDef 0009c8: DW_AT_type indirect DW_FORM_ref2 0x92b 0009cb: DW_AT_decl_file 0x1 0009cc: DW_AT_decl_line 0x28b 0009ce: DW_AT_decl_column 0x3 0009cf: 0 null 0009d0: 0 padding 0009d1: 0 padding 0009d2: 0 padding 0009d3: 0 padding ** Section #392 '.rel.debug_info' (SHT_REL) Size : 560 bytes (alignment 4) Symbol table #343 '.symtab' 70 relocations applied to section #150 '.debug_info' ** Section #151 '__ARM_grp.stm32f7xx_hal_flash_ex.h.2_Eq5000_rLtnrrAKQg1_j00000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #152 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 8392 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_FLASH_EX_H 000021: include at line 47 - file 2 000024: end include 000025: line 130 define FLASH_TYPEERASE_SECTORS ((uint32_t)0x00U) 000052: line 131 define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01U) 000081: line 139 define FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00U) 0000ac: line 140 define FLASH_VOLTAGE_RANGE_2 ((uint32_t)0x01U) 0000d7: line 141 define FLASH_VOLTAGE_RANGE_3 ((uint32_t)0x02U) 000102: line 142 define FLASH_VOLTAGE_RANGE_4 ((uint32_t)0x03U) 00012d: line 150 define OB_WRPSTATE_DISABLE ((uint32_t)0x00U) 000156: line 151 define OB_WRPSTATE_ENABLE ((uint32_t)0x01U) 00017e: line 159 define OPTIONBYTE_WRP ((uint32_t)0x01U) 0001a2: line 160 define OPTIONBYTE_RDP ((uint32_t)0x02U) 0001c6: line 161 define OPTIONBYTE_USER ((uint32_t)0x04U) 0001eb: line 162 define OPTIONBYTE_BOR ((uint32_t)0x08U) 00020f: line 163 define OPTIONBYTE_BOOTADDR_0 ((uint32_t)0x10U) 00023a: line 164 define OPTIONBYTE_BOOTADDR_1 ((uint32_t)0x20U) 000265: line 172 define OB_RDP_LEVEL_0 ((uint8_t)0xAAU) 000288: line 173 define OB_RDP_LEVEL_1 ((uint8_t)0x55U) 0002ab: line 174 define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) 0002ce: line 183 define OB_WWDG_SW ((uint32_t)0x10U) 0002ee: line 184 define OB_WWDG_HW ((uint32_t)0x00U) 00030e: line 193 define OB_IWDG_SW ((uint32_t)0x20U) 00032e: line 194 define OB_IWDG_HW ((uint32_t)0x00U) 00034e: line 202 define OB_STOP_NO_RST ((uint32_t)0x40U) 000372: line 203 define OB_STOP_RST ((uint32_t)0x00U) 000393: line 211 define OB_STDBY_NO_RST ((uint32_t)0x80U) 0003b8: line 212 define OB_STDBY_RST ((uint32_t)0x00U) 0003da: line 220 define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000000U) 000409: line 221 define OB_IWDG_STOP_ACTIVE ((uint32_t)0x80000000U) 000438: line 229 define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000000U) 000468: line 230 define OB_IWDG_STDBY_ACTIVE ((uint32_t)0x40000000U) 000498: line 238 define OB_BOR_LEVEL3 ((uint32_t)0x00U) 0004bb: line 239 define OB_BOR_LEVEL2 ((uint32_t)0x04U) 0004de: line 240 define OB_BOR_LEVEL1 ((uint32_t)0x08U) 000501: line 241 define OB_BOR_OFF ((uint32_t)0x0CU) 000521: line 250 define OB_DUAL_BOOT_DISABLE ((uint32_t)0x10000000U) 000551: line 251 define OB_DUAL_BOOT_ENABLE ((uint32_t)0x00000000U) 000580: line 262 define OB_NDBANK_SINGLE_BANK ((uint32_t)0x20000000U) 0005b1: line 263 define OB_NDBANK_DUAL_BANK ((uint32_t)0x00000000U) 0005e0: line 272 define OB_BOOTADDR_ITCM_RAM ((uint32_t)0x0000U) 00060c: line 273 define OB_BOOTADDR_SYSTEM ((uint32_t)0x0040U) 000636: line 274 define OB_BOOTADDR_ITCM_FLASH ((uint32_t)0x0080U) 000664: line 275 define OB_BOOTADDR_AXIM_FLASH ((uint32_t)0x2000U) 000692: line 276 define OB_BOOTADDR_DTCM_RAM ((uint32_t)0x8000U) 0006be: line 277 define OB_BOOTADDR_SRAM1 ((uint32_t)0x8004U) 0006e7: line 278 define OB_BOOTADDR_SRAM2 ((uint32_t)0x8013U) 000710: line 286 define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS 000739: line 287 define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS 000762: line 288 define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS 00078b: line 289 define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS 0007b4: line 290 define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS 0007dd: line 291 define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS 000806: line 292 define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS 00082f: line 293 define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS 000858: line 294 define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS 000881: line 295 define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS 0008aa: line 296 define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS 0008d5: line 297 define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS 000900: line 298 define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS 00092b: line 299 define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS 000956: line 300 define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS 000981: line 301 define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS 0009ac: line 310 define FLASH_BANK_1 ((uint32_t)0x01U) 0009ce: line 311 define FLASH_BANK_2 ((uint32_t)0x02U) 0009f0: line 312 define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) 000a2d: line 322 define FLASH_MER_BIT (FLASH_CR_MER1 | FLASH_CR_MER2) 000a5e: line 334 define FLASH_SECTOR_8 ((uint32_t)8U) 000a7f: line 335 define FLASH_SECTOR_9 ((uint32_t)9U) 000aa0: line 336 define FLASH_SECTOR_10 ((uint32_t)10U) 000ac3: line 337 define FLASH_SECTOR_11 ((uint32_t)11U) 000ae6: line 338 define FLASH_SECTOR_12 ((uint32_t)12U) 000b09: line 339 define FLASH_SECTOR_13 ((uint32_t)13U) 000b2c: line 340 define FLASH_SECTOR_14 ((uint32_t)14U) 000b4f: line 341 define FLASH_SECTOR_15 ((uint32_t)15U) 000b72: line 342 define FLASH_SECTOR_16 ((uint32_t)16U) 000b95: line 343 define FLASH_SECTOR_17 ((uint32_t)17U) 000bb8: line 344 define FLASH_SECTOR_18 ((uint32_t)18U) 000bdb: line 345 define FLASH_SECTOR_19 ((uint32_t)19U) 000bfe: line 346 define FLASH_SECTOR_20 ((uint32_t)20U) 000c21: line 347 define FLASH_SECTOR_21 ((uint32_t)21U) 000c44: line 348 define FLASH_SECTOR_22 ((uint32_t)22U) 000c67: line 349 define FLASH_SECTOR_23 ((uint32_t)23U) 000c8a: line 366 define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) 000cb5: line 367 define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) 000ce0: line 368 define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) 000d0b: line 369 define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) 000d36: line 370 define OB_WRP_SECTOR_4 ((uint32_t)0x00100000U) 000d61: line 371 define OB_WRP_SECTOR_5 ((uint32_t)0x00200000U) 000d8c: line 372 define OB_WRP_SECTOR_6 ((uint32_t)0x00400000U) 000db7: line 373 define OB_WRP_SECTOR_7 ((uint32_t)0x00800000U) 000de2: line 374 define OB_WRP_SECTOR_8 ((uint32_t)0x01000000U) 000e0d: line 375 define OB_WRP_SECTOR_9 ((uint32_t)0x02000000U) 000e38: line 376 define OB_WRP_SECTOR_10 ((uint32_t)0x04000000U) 000e64: line 377 define OB_WRP_SECTOR_11 ((uint32_t)0x08000000U) 000e90: line 378 define OB_WRP_SECTOR_All ((uint32_t)0x0FFF0000U) 000ebd: line 381 define OB_WRP_DB_SECTOR_0 ((uint32_t)0x00010000U) 000eeb: line 382 define OB_WRP_DB_SECTOR_1 ((uint32_t)0x00010000U) 000f19: line 383 define OB_WRP_DB_SECTOR_2 ((uint32_t)0x00020000U) 000f47: line 384 define OB_WRP_DB_SECTOR_3 ((uint32_t)0x00020000U) 000f75: line 385 define OB_WRP_DB_SECTOR_4 ((uint32_t)0x00040000U) 000fa3: line 386 define OB_WRP_DB_SECTOR_5 ((uint32_t)0x00040000U) 000fd1: line 387 define OB_WRP_DB_SECTOR_6 ((uint32_t)0x00080000U) 000fff: line 388 define OB_WRP_DB_SECTOR_7 ((uint32_t)0x00080000U) 00102d: line 389 define OB_WRP_DB_SECTOR_8 ((uint32_t)0x00100000U) 00105b: line 390 define OB_WRP_DB_SECTOR_9 ((uint32_t)0x00100000U) 001089: line 391 define OB_WRP_DB_SECTOR_10 ((uint32_t)0x00200000U) 0010b8: line 392 define OB_WRP_DB_SECTOR_11 ((uint32_t)0x00200000U) 0010e7: line 393 define OB_WRP_DB_SECTOR_12 ((uint32_t)0x00400000U) 001116: line 394 define OB_WRP_DB_SECTOR_13 ((uint32_t)0x00400000U) 001145: line 395 define OB_WRP_DB_SECTOR_14 ((uint32_t)0x00800000U) 001174: line 396 define OB_WRP_DB_SECTOR_15 ((uint32_t)0x00800000U) 0011a3: line 397 define OB_WRP_DB_SECTOR_16 ((uint32_t)0x01000000U) 0011d2: line 398 define OB_WRP_DB_SECTOR_17 ((uint32_t)0x01000000U) 001201: line 399 define OB_WRP_DB_SECTOR_18 ((uint32_t)0x02000000U) 001230: line 400 define OB_WRP_DB_SECTOR_19 ((uint32_t)0x02000000U) 00125f: line 401 define OB_WRP_DB_SECTOR_20 ((uint32_t)0x04000000U) 00128e: line 402 define OB_WRP_DB_SECTOR_21 ((uint32_t)0x04000000U) 0012bd: line 403 define OB_WRP_DB_SECTOR_22 ((uint32_t)0x08000000U) 0012ec: line 404 define OB_WRP_DB_SECTOR_23 ((uint32_t)0x08000000U) 00131b: line 405 define OB_WRP_DB_SECTOR_All ((uint32_t)0x0FFF0000U) 00134b: line 443 define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14) 001390: line 481 define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || ((VALUE) == FLASH_TYPEERASE_MASSERASE)) 0013fe: line 484 define IS_VOLTAGERANGE(RANGE) (((RANGE) == FLASH_VOLTAGE_RANGE_1) || ((RANGE) == FLASH_VOLTAGE_RANGE_2) || ((RANGE) == FLASH_VOLTAGE_RANGE_3) || ((RANGE) == FLASH_VOLTAGE_RANGE_4)) 0014af: line 489 define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE)) 00150b: line 492 define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1))) 0015a7: line 495 define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013) 0015dc: line 497 define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1) || ((LEVEL) == OB_RDP_LEVEL_2)) 001652: line 501 define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW)) 0016a6: line 503 define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) 0016fa: line 505 define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) 001753: line 507 define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) 0017af: line 509 define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE)) 00181a: line 511 define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE)) 001888: line 513 define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) || ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF)) 001916: line 516 define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15)) 001b58: line 533 define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) 001bad: line 535 define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL)) 001c0b: line 547 define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) || ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) || ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) || ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) || ((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) || ((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11) || ((SECTOR) == FLASH_SECTOR_12) || ((SECTOR) == FLASH_SECTOR_13) || ((SECTOR) == FLASH_SECTOR_14) || ((SECTOR) == FLASH_SECTOR_15) || ((SECTOR) == FLASH_SECTOR_16) || ((SECTOR) == FLASH_SECTOR_17) || ((SECTOR) == FLASH_SECTOR_18) || ((SECTOR) == FLASH_SECTOR_19) || ((SECTOR) == FLASH_SECTOR_20) || ((SECTOR) == FLASH_SECTOR_21) || ((SECTOR) == FLASH_SECTOR_22) || ((SECTOR) == FLASH_SECTOR_23)) 001f33: line 560 define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xF000FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U)) 001f98: line 564 define IS_OB_NDBANK(VALUE) (((VALUE) == OB_NDBANK_SINGLE_BANK) || ((VALUE) == OB_NDBANK_DUAL_BANK)) 001ff8: line 567 define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || ((BANK) == FLASH_BANK_2) || ((BANK) == FLASH_BANK_BOTH)) 002065: line 573 define IS_OB_NDBOOT(VALUE) (((VALUE) == OB_DUAL_BOOT_DISABLE) || ((VALUE) == OB_DUAL_BOOT_ENABLE)) 0020c4: end include 0020c5: end of translation unit ** Section #153 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 128 bytes 000000: Header: length 124 (not including this field) version 3 prologue length 112 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_flash_ex.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 66 6c 61 73 68 5f 65 78 2e 68 00 01 00 00 000062: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000079: file "" : 00 00007a: DW_LNS_negate_stmt : 06 00007b: DW_LNS_negate_stmt : 06 00007c: DW_LNS_negate_stmt : 06 00007d: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash_ex.h:1.0 [ ** Section #154 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 596 bytes 000000: Header: size 0x250 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash_ex.h 00004e: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000095: DW_AT_language DW_LANG_C89 000097: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010e: DW_AT_macro_info 0x0 000112: DW_AT_stmt_list 0x0 000116: 42 = 0x13 (DW_TAG_structure_type) 000117: DW_AT_sibling 0x176 000119: DW_AT_byte_size 0x14 00011a: 30 = 0xd (DW_TAG_member) 00011b: DW_AT_name TypeErase 000125: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00012a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00012d: 30 = 0xd (DW_TAG_member) 00012e: DW_AT_name Banks 000134: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000139: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00013c: 30 = 0xd (DW_TAG_member) 00013d: DW_AT_name Sector 000144: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000149: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 00014c: 30 = 0xd (DW_TAG_member) 00014d: DW_AT_name NbSectors 000157: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00015c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00015f: 30 = 0xd (DW_TAG_member) 000160: DW_AT_name VoltageRange 00016d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000172: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000175: 0 null 000176: 80 = 0x16 (DW_TAG_typedef) 000177: DW_AT_name FLASH_EraseInitTypeDef 00018e: DW_AT_type indirect DW_FORM_ref2 0x116 000191: DW_AT_decl_file 0x1 000192: DW_AT_decl_line 0x54 000193: DW_AT_decl_column 0x3 000194: 42 = 0x13 (DW_TAG_structure_type) 000195: DW_AT_sibling 0x230 000197: DW_AT_byte_size 0x20 000198: 30 = 0xd (DW_TAG_member) 000199: DW_AT_name OptionType 0001a4: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001a9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0001ac: 30 = 0xd (DW_TAG_member) 0001ad: DW_AT_name WRPState 0001b6: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001bb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0001be: 30 = 0xd (DW_TAG_member) 0001bf: DW_AT_name WRPSector 0001c9: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001ce: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0001d1: 30 = 0xd (DW_TAG_member) 0001d2: DW_AT_name RDPLevel 0001db: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001e0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0001e3: 30 = 0xd (DW_TAG_member) 0001e4: DW_AT_name BORLevel 0001ed: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001f2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 0001f5: 30 = 0xd (DW_TAG_member) 0001f6: DW_AT_name USERConfig 000201: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000206: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 000209: 30 = 0xd (DW_TAG_member) 00020a: DW_AT_name BootAddr0 000214: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000219: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 00021c: 30 = 0xd (DW_TAG_member) 00021d: DW_AT_name BootAddr1 000227: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00022c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 00022f: 0 null 000230: 80 = 0x16 (DW_TAG_typedef) 000231: DW_AT_name FLASH_OBProgramInitTypeDef 00024c: DW_AT_type indirect DW_FORM_ref2 0x194 00024f: DW_AT_decl_file 0x1 000250: DW_AT_decl_line 0x74 000251: DW_AT_decl_column 0x3 000252: 0 null 000253: 0 padding ** Section #393 '.rel.debug_info' (SHT_REL) Size : 128 bytes (alignment 4) Symbol table #343 '.symtab' 16 relocations applied to section #154 '.debug_info' ** Section #155 '__ARM_grp.stm32f7xx_hal_flash.h.2_A_2000_Jtz0qzuTtJf_c00000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #156 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 2656 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_FLASH_H 00001e: include at line 47 - file 2 000021: end include 000022: line 108 define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000U) 000051: line 109 define HAL_FLASH_ERROR_ERS ((uint32_t)0x00000002U) 00007f: line 110 define HAL_FLASH_ERROR_PGP ((uint32_t)0x00000004U) 0000ad: line 111 define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008U) 0000db: line 112 define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000010U) 000109: line 113 define HAL_FLASH_ERROR_OPERATION ((uint32_t)0x00000020U) 00013d: line 121 define FLASH_TYPEPROGRAM_BYTE ((uint32_t)0x00U) 000168: line 122 define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01U) 000197: line 123 define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02U) 0001c2: line 124 define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03U) 0001f3: line 133 define FLASH_FLAG_EOP FLASH_SR_EOP 000212: line 134 define FLASH_FLAG_OPERR FLASH_SR_OPERR 000235: line 135 define FLASH_FLAG_WRPERR FLASH_SR_WRPERR 00025a: line 136 define FLASH_FLAG_PGAERR FLASH_SR_PGAERR 00027f: line 137 define FLASH_FLAG_PGPERR FLASH_SR_PGPERR 0002a4: line 138 define FLASH_FLAG_ERSERR FLASH_SR_ERSERR 0002c9: line 139 define FLASH_FLAG_BSY FLASH_SR_BSY 0002e8: line 142 define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR) 000364: line 152 define FLASH_IT_EOP FLASH_CR_EOPIE 000383: line 153 define FLASH_IT_ERR ((uint32_t)0x02000000U) 0003ab: line 161 define FLASH_PSIZE_BYTE ((uint32_t)0x00000000U) 0003d7: line 162 define FLASH_PSIZE_HALF_WORD ((uint32_t)FLASH_CR_PSIZE_0) 00040d: line 163 define FLASH_PSIZE_WORD ((uint32_t)FLASH_CR_PSIZE_1) 00043e: line 164 define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)FLASH_CR_PSIZE) 000474: line 165 define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFFU) 00049d: line 173 define FLASH_KEY1 ((uint32_t)0x45670123U) 0004c3: line 174 define FLASH_KEY2 ((uint32_t)0xCDEF89ABU) 0004e9: line 175 define FLASH_OPT_KEY1 ((uint32_t)0x08192A3BU) 000513: line 176 define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7FU) 00053d: line 184 define FLASH_SECTOR_0 ((uint32_t)0U) 00055e: line 185 define FLASH_SECTOR_1 ((uint32_t)1U) 00057f: line 186 define FLASH_SECTOR_2 ((uint32_t)2U) 0005a0: line 187 define FLASH_SECTOR_3 ((uint32_t)3U) 0005c1: line 188 define FLASH_SECTOR_4 ((uint32_t)4U) 0005e2: line 189 define FLASH_SECTOR_5 ((uint32_t)5U) 000603: line 190 define FLASH_SECTOR_6 ((uint32_t)6U) 000624: line 191 define FLASH_SECTOR_7 ((uint32_t)7U) 000645: line 210 define __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__)) 0006b0: line 218 define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) 0006f9: line 224 define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN) 000742: line 230 define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN)) 00078f: line 237 define __HAL_FLASH_ART_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ARTEN) 0007d0: line 243 define __HAL_FLASH_ART_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTEN) 000814: line 251 define __HAL_FLASH_ART_RESET() (FLASH->ACR |= FLASH_ACR_ARTRST) 000850: line 261 define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__)) 000897: line 271 define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__)) 0008ea: line 286 define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__))) 000927: line 300 define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__)) 000964: include at line 306 - file 3 000968: end include 000969: line 371 define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15) 000997: line 385 define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_BYTE) || ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || ((VALUE) == FLASH_TYPEPROGRAM_WORD) || ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) 000a5b: end include 000a5c: end of translation unit ** Section #157 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 152 bytes 000000: Header: length 148 (not including this field) version 3 prologue length 137 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_flash.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 66 6c 61 73 68 2e 68 00 01 00 00 00005f: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000076: file "stm32f7xx_hal_flash_ex.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 66 6c 61 73 68 5f 65 78 2e 68 00 01 00 00 000092: file "" : 00 000093: DW_LNS_negate_stmt : 06 000094: DW_LNS_negate_stmt : 06 000095: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash.h:1.0 ** Section #158 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 584 bytes 000000: Header: size 0x244 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash.h 00004b: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000092: DW_AT_language DW_LANG_C89 000094: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010b: DW_AT_macro_info 0x0 00010f: DW_AT_stmt_list 0x0 000113: 19 = 0x4 (DW_TAG_enumeration_type) 000114: DW_AT_sibling 0x171 000116: DW_AT_byte_size 0x1 000117: 20 = 0x28 (DW_TAG_enumerator) 000118: DW_AT_name FLASH_PROC_NONE 000128: DW_AT_const_value indirect DW_FORM_data1 0x0 00012a: 20 = 0x28 (DW_TAG_enumerator) 00012b: DW_AT_name FLASH_PROC_SECTERASE 000140: DW_AT_const_value indirect DW_FORM_data1 0x1 000142: 20 = 0x28 (DW_TAG_enumerator) 000143: DW_AT_name FLASH_PROC_MASSERASE 000158: DW_AT_const_value indirect DW_FORM_data1 0x2 00015a: 20 = 0x28 (DW_TAG_enumerator) 00015b: DW_AT_name FLASH_PROC_PROGRAM 00016e: DW_AT_const_value indirect DW_FORM_data1 0x3 000170: 0 null 000171: 80 = 0x16 (DW_TAG_typedef) 000172: DW_AT_name FLASH_ProcedureTypeDef 000189: DW_AT_type indirect DW_FORM_ref2 0x113 00018c: DW_AT_decl_file 0x1 00018d: DW_AT_decl_line 0x47 00018e: DW_AT_decl_column 0x3 00018f: 42 = 0x13 (DW_TAG_structure_type) 000190: DW_AT_sibling 0x217 000192: DW_AT_byte_size 0x1c 000193: 30 = 0xd (DW_TAG_member) 000194: DW_AT_name ProcedureOnGoing 0001a5: DW_AT_type indirect DW_FORM_ref2 0x217 0001a8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0001ab: 30 = 0xd (DW_TAG_member) 0001ac: DW_AT_name NbSectorsToErase 0001bd: DW_AT_type indirect DW_FORM_ref2 0x21b 0001c0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0001c3: 30 = 0xd (DW_TAG_member) 0001c4: DW_AT_name VoltageForErase 0001d4: DW_AT_type indirect DW_FORM_ref2 0x221 0001d7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0001da: 30 = 0xd (DW_TAG_member) 0001db: DW_AT_name Sector 0001e2: DW_AT_type indirect DW_FORM_ref2 0x21b 0001e5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0001e8: 30 = 0xd (DW_TAG_member) 0001e9: DW_AT_name Address 0001f1: DW_AT_type indirect DW_FORM_ref2 0x21b 0001f4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 0001f7: 30 = 0xd (DW_TAG_member) 0001f8: DW_AT_name Lock 0001fd: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 000202: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 000205: 30 = 0xd (DW_TAG_member) 000206: DW_AT_name ErrorCode 000210: DW_AT_type indirect DW_FORM_ref2 0x21b 000213: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 000216: 0 null 000217: 116 = 0x35 (DW_TAG_volatile_type) 000218: DW_AT_type indirect DW_FORM_ref2 0x171 00021b: 116 = 0x35 (DW_TAG_volatile_type) 00021c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000221: 116 = 0x35 (DW_TAG_volatile_type) 000222: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000227: 80 = 0x16 (DW_TAG_typedef) 000228: DW_AT_name FLASH_ProcessTypeDef 00023d: DW_AT_type indirect DW_FORM_ref2 0x18f 000240: DW_AT_decl_file 0x1 000241: DW_AT_decl_line 0x5d 000242: DW_AT_decl_column 0x2 000243: 0 null 000244: 0 padding 000245: 0 padding 000246: 0 padding 000247: 0 padding ** Section #394 '.rel.debug_info' (SHT_REL) Size : 48 bytes (alignment 4) Symbol table #343 '.symtab' 6 relocations applied to section #158 '.debug_info' ** Section #159 '__ARM_grp.stm32f7xx_ll_fmc.h.2_om8000__ExyD6nDcTf_Y00000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #160 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 13816 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_LL_FMC_H 00001b: include at line 47 - file 2 00001e: end include 00001f: line 60 define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || ((BANK) == FMC_NORSRAM_BANK2) || ((BANK) == FMC_NORSRAM_BANK3) || ((BANK) == FMC_NORSRAM_BANK4)) 0000be: line 65 define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) 000130: line 68 define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) 0001c8: line 72 define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) 000282: line 76 define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || ((__MODE__) == FMC_ACCESS_MODE_B) || ((__MODE__) == FMC_ACCESS_MODE_C) || ((__MODE__) == FMC_ACCESS_MODE_D)) 000334: line 81 define IS_FMC_NAND_BANK(BANK) ((BANK) == FMC_NAND_BANK3) 000368: line 83 define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_WAIT_FEATURE_DISABLE) || ((FEATURE) == FMC_NAND_WAIT_FEATURE_ENABLE)) 0003e5: line 86 define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_8) || ((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_16)) 000459: line 89 define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || ((STATE) == FMC_NAND_ECC_ENABLE)) 0004bb: line 92 define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) 0005ee: line 99 define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32)) 00068c: line 103 define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE)) 00071d: line 106 define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) || ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3)) 0007c9: line 110 define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE)) 000843: line 113 define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2)) 0008e9: line 117 define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) || ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) || ((__COMMAND__) == FMC_SDRAM_CMD_PALL) || ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) || ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE)) 000a5e: line 125 define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2)) 000b13: line 132 define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255) 000b45: line 140 define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255) 000b6e: line 148 define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 254) 000b99: line 156 define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 254) 000bc3: line 164 define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 254) 000bed: line 172 define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 254) 000c16: line 177 define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) 000c97: line 180 define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) 000d25: line 183 define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) 000dab: line 186 define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) 000e3a: line 189 define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) 000eb5: line 192 define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) 000f2f: line 195 define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) 000faf: line 201 define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17)) 001002: line 206 define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || ((__BURST__) == FMC_WRITE_BURST_ENABLE)) 001079: line 209 define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) 0010fb: line 216 define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15) 001135: line 224 define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15)) 001184: line 232 define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255)) 0011d1: line 240 define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15) 001208: line 248 define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16)) 00123e: line 256 define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) 001291: line 264 define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) 0012e7: line 272 define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16)) 001335: line 280 define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) 001384: line 288 define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16)) 0013d5: line 296 define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) 00141e: line 304 define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) 001468: line 312 define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0) && ((__NUMBER__) <= 16)) 0014be: line 320 define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191) 0014fb: line 328 define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191) 001531: line 336 define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) 00157f: line 344 define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) 0015df: line 352 define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) 001627: line 360 define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE) 001671: line 365 define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || ((BANK) == FMC_SDRAM_BANK2)) 0016c9: line 368 define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) || ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) || ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11)) 0017a2: line 373 define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13)) 001837: line 377 define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4)) 0018b8: line 381 define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3)) 001954: line 385 define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || ((__SIZE__) == FMC_PAGE_SIZE_128) || ((__SIZE__) == FMC_PAGE_SIZE_256) || ((__SIZE__) == FMC_PAGE_SIZE_512) || ((__SIZE__) == FMC_PAGE_SIZE_1024)) 001a2b: line 391 define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || ((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) 001a9c: line 401 define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef 001ac5: line 402 define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef 001af8: line 403 define FMC_NAND_TypeDef FMC_Bank3_TypeDef 001b1e: line 404 define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef 001b47: line 406 define FMC_NORSRAM_DEVICE FMC_Bank1 001b67: line 407 define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E 001b91: line 408 define FMC_NAND_DEVICE FMC_Bank3 001bae: line 409 define FMC_SDRAM_DEVICE FMC_Bank5_6 001bce: line 682 define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000U) 001bfb: line 683 define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002U) 001c28: line 684 define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004U) 001c55: line 685 define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006U) 001c82: line 693 define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U) 001cba: line 694 define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U) 001cf1: line 702 define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U) 001d21: line 703 define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U) 001d52: line 704 define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U) 001d81: line 712 define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) 001db8: line 713 define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U) 001df0: line 714 define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U) 001e28: line 722 define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U) 001e63: line 723 define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U) 001e9f: line 731 define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U) 001ed8: line 732 define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U) 001f10: line 740 define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U) 001f48: line 741 define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U) 001f81: line 749 define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U) 001fb6: line 750 define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U) 001feb: line 758 define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U) 002022: line 759 define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U) 002058: line 767 define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U) 00208b: line 768 define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U) 0020bd: line 776 define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U) 0020f2: line 777 define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U) 002126: line 785 define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U) 00215f: line 786 define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U) 002197: line 794 define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U) 0021c5: line 795 define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0) 0021f8: line 796 define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1) 00222b: line 797 define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCR1_CPSIZE_0 | FMC_BCR1_CPSIZE_1)) 002274: line 798 define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2) 0022a8: line 806 define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U) 0022db: line 807 define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U) 00230d: line 815 define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U) 002347: line 816 define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U) 002382: line 824 define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS) 0023b7: line 825 define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000U) 0023e8: line 833 define FMC_ACCESS_MODE_A ((uint32_t)0x00000000U) 002415: line 834 define FMC_ACCESS_MODE_B ((uint32_t)0x10000000U) 002442: line 835 define FMC_ACCESS_MODE_C ((uint32_t)0x20000000U) 00246f: line 836 define FMC_ACCESS_MODE_D ((uint32_t)0x30000000) 00249b: line 851 define FMC_NAND_BANK3 ((uint32_t)0x00000100U) 0024c5: line 859 define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U) 0024fe: line 860 define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U) 002536: line 868 define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U) 00256a: line 876 define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) 00259e: line 877 define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U) 0025d3: line 885 define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U) 002603: line 886 define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U) 002632: line 894 define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U) 00266c: line 895 define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U) 0026a6: line 896 define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U) 0026e1: line 897 define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U) 00271c: line 898 define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U) 002757: line 899 define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U) 002792: line 914 define FMC_SDRAM_BANK1 ((uint32_t)0x00000000U) 0027bd: line 915 define FMC_SDRAM_BANK2 ((uint32_t)0x00000001U) 0027e8: line 923 define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000U) 00281f: line 924 define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001U) 002856: line 925 define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002U) 00288e: line 926 define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003U) 0028c6: line 934 define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000U) 0028fb: line 935 define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004U) 002930: line 936 define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008U) 002965: line 944 define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) 00299a: line 945 define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U) 0029d0: line 946 define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U) 002a06: line 954 define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000U) 002a3e: line 955 define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040U) 002a76: line 963 define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080U) 002aa9: line 964 define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100U) 002adc: line 965 define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180) 002b0e: line 973 define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000U) 002b4c: line 974 define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200U) 002b89: line 982 define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000U) 002bbc: line 983 define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800U) 002bf0: line 984 define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00) 002c23: line 992 define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000U) 002c57: line 993 define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000U) 002c8a: line 1001 define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000U) 002cbd: line 1002 define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000U) 002cf0: line 1003 define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000U) 002d23: line 1011 define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000U) 002d58: line 1012 define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001U) 002d8c: line 1013 define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002U) 002dba: line 1014 define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003U) 002df4: line 1015 define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004U) 002e27: line 1016 define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005U) 002e61: line 1017 define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006U) 002e99: line 1025 define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2 002ec6: line 1026 define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1 002ef3: line 1027 define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018U) 002f2b: line 1035 define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000U) 002f5c: line 1036 define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0 002f8d: line 1037 define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1 002fbc: line 1049 define FMC_IT_RISING_EDGE ((uint32_t)0x00000008U) 002fea: line 1050 define FMC_IT_LEVEL ((uint32_t)0x00000010U) 003012: line 1051 define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020U) 003041: line 1052 define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000U) 003071: line 1060 define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U) 0030a1: line 1061 define FMC_FLAG_LEVEL ((uint32_t)0x00000002U) 0030cb: line 1062 define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U) 0030fc: line 1063 define FMC_FLAG_FEMPT ((uint32_t)0x00000040U) 003126: line 1064 define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE 00314f: line 1065 define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY 003174: line 1066 define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE 0031a2: line 1094 define __FMC_NORSRAM_ENABLE(__INSTANCE__,__BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN) 003206: line 1102 define __FMC_NORSRAM_DISABLE(__INSTANCE__,__BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN) 00326c: line 1118 define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN) 0032b6: line 1125 define __FMC_NAND_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN) 003302: line 1146 define __FMC_NAND_ENABLE_IT(__INSTANCE__,__INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__)) 00335e: line 1158 define __FMC_NAND_DISABLE_IT(__INSTANCE__,__INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__)) 0033bc: line 1172 define __FMC_NAND_GET_FLAG(__INSTANCE__,__BANK__,__FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__)) 003424: line 1185 define __FMC_NAND_CLEAR_FLAG(__INSTANCE__,__FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__)) 003478: line 1195 define __FMC_SDRAM_ENABLE_IT(__INSTANCE__,__INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__)) 0034d8: line 1205 define __FMC_SDRAM_DISABLE_IT(__INSTANCE__,__INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__)) 00353a: line 1217 define __FMC_SDRAM_GET_FLAG(__INSTANCE__,__FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__)) 00359c: line 1227 define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__,__FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__)) 0035f3: end include 0035f4: end of translation unit ** Section #161 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 120 bytes 000000: Header: length 116 (not including this field) version 3 prologue length 106 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_ll_fmc.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 6c 6c 5f 66 6d 63 2e 68 00 01 00 00 00005c: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000073: file "" : 00 000074: DW_LNS_negate_stmt : 06 000075: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_fmc.h:1.0 [ ** Section #162 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 1780 bytes 000000: Header: size 0x6f0 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_fmc.h 000048: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 00008f: DW_AT_language DW_LANG_C89 000091: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 000108: DW_AT_macro_info 0x0 00010c: DW_AT_stmt_list 0x0 000110: 42 = 0x13 (DW_TAG_structure_type) 000111: DW_AT_sibling 0x267 000113: DW_AT_byte_size 0x3c 000114: 30 = 0xd (DW_TAG_member) 000115: DW_AT_name NSBank 00011c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000121: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000124: 30 = 0xd (DW_TAG_member) 000125: DW_AT_name DataAddressMux 000134: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000139: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00013c: 30 = 0xd (DW_TAG_member) 00013d: DW_AT_name MemoryType 000148: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00014d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000150: 30 = 0xd (DW_TAG_member) 000151: DW_AT_name MemoryDataWidth 000161: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000166: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000169: 30 = 0xd (DW_TAG_member) 00016a: DW_AT_name BurstAccessMode 00017a: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00017f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000182: 30 = 0xd (DW_TAG_member) 000183: DW_AT_name WaitSignalPolarity 000196: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00019b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 00019e: 30 = 0xd (DW_TAG_member) 00019f: DW_AT_name WaitSignalActive 0001b0: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001b5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 0001b8: 30 = 0xd (DW_TAG_member) 0001b9: DW_AT_name WriteOperation 0001c8: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001cd: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 0001d0: 30 = 0xd (DW_TAG_member) 0001d1: DW_AT_name WaitSignal 0001dc: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001e1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 0001e4: 30 = 0xd (DW_TAG_member) 0001e5: DW_AT_name ExtendedMode 0001f2: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001f7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 0001fa: 30 = 0xd (DW_TAG_member) 0001fb: DW_AT_name AsynchronousWait 00020c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000211: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 000214: 30 = 0xd (DW_TAG_member) 000215: DW_AT_name WriteBurst 000220: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000225: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 000228: 30 = 0xd (DW_TAG_member) 000229: DW_AT_name ContinuousClock 000239: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00023e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 000241: 30 = 0xd (DW_TAG_member) 000242: DW_AT_name WriteFifo 00024c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000251: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 000254: 30 = 0xd (DW_TAG_member) 000255: DW_AT_name PageSize 00025e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000263: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 000266: 0 null 000267: 80 = 0x16 (DW_TAG_typedef) 000268: DW_AT_name FMC_NORSRAM_InitTypeDef 000280: DW_AT_type indirect DW_FORM_ref2 0x110 000283: DW_AT_decl_file 0x1 000284: DW_AT_decl_line 0x1d9 000286: DW_AT_decl_column 0x2 000287: 42 = 0x13 (DW_TAG_structure_type) 000288: DW_AT_sibling 0x333 00028a: DW_AT_byte_size 0x1c 00028b: 30 = 0xd (DW_TAG_member) 00028c: DW_AT_name AddressSetupTime 00029d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002a2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0002a5: 30 = 0xd (DW_TAG_member) 0002a6: DW_AT_name AddressHoldTime 0002b6: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002bb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0002be: 30 = 0xd (DW_TAG_member) 0002bf: DW_AT_name DataSetupTime 0002cd: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002d2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0002d5: 30 = 0xd (DW_TAG_member) 0002d6: DW_AT_name BusTurnAroundDuration 0002ec: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002f1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0002f4: 30 = 0xd (DW_TAG_member) 0002f5: DW_AT_name CLKDivision 000301: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000306: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000309: 30 = 0xd (DW_TAG_member) 00030a: DW_AT_name DataLatency 000316: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00031b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 00031e: 30 = 0xd (DW_TAG_member) 00031f: DW_AT_name AccessMode 00032a: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00032f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 000332: 0 null 000333: 80 = 0x16 (DW_TAG_typedef) 000334: DW_AT_name FMC_NORSRAM_TimingTypeDef 00034e: DW_AT_type indirect DW_FORM_ref2 0x287 000351: DW_AT_decl_file 0x1 000352: DW_AT_decl_line 0x204 000354: DW_AT_decl_column 0x2 000355: 42 = 0x13 (DW_TAG_structure_type) 000356: DW_AT_sibling 0x3f4 000358: DW_AT_byte_size 0x1c 000359: 30 = 0xd (DW_TAG_member) 00035a: DW_AT_name NandBank 000363: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000368: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00036b: 30 = 0xd (DW_TAG_member) 00036c: DW_AT_name Waitfeature 000378: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00037d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000380: 30 = 0xd (DW_TAG_member) 000381: DW_AT_name MemoryDataWidth 000391: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000396: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000399: 30 = 0xd (DW_TAG_member) 00039a: DW_AT_name EccComputation 0003a9: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003ae: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0003b1: 30 = 0xd (DW_TAG_member) 0003b2: DW_AT_name ECCPageSize 0003be: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003c3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 0003c6: 30 = 0xd (DW_TAG_member) 0003c7: DW_AT_name TCLRSetupTime 0003d5: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003da: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 0003dd: 30 = 0xd (DW_TAG_member) 0003de: DW_AT_name TARSetupTime 0003eb: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003f0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 0003f3: 0 null 0003f4: 80 = 0x16 (DW_TAG_typedef) 0003f5: DW_AT_name FMC_NAND_InitTypeDef 00040a: DW_AT_type indirect DW_FORM_ref2 0x355 00040d: DW_AT_decl_file 0x1 00040e: DW_AT_decl_line 0x221 000410: DW_AT_decl_column 0x2 000411: 42 = 0x13 (DW_TAG_structure_type) 000412: DW_AT_sibling 0x46d 000414: DW_AT_byte_size 0x10 000415: 30 = 0xd (DW_TAG_member) 000416: DW_AT_name SetupTime 000420: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000425: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000428: 30 = 0xd (DW_TAG_member) 000429: DW_AT_name WaitSetupTime 000437: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00043c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00043f: 30 = 0xd (DW_TAG_member) 000440: DW_AT_name HoldSetupTime 00044e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000453: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000456: 30 = 0xd (DW_TAG_member) 000457: DW_AT_name HiZSetupTime 000464: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000469: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00046c: 0 null 00046d: 80 = 0x16 (DW_TAG_typedef) 00046e: DW_AT_name FMC_NAND_PCC_TimingTypeDef 000489: DW_AT_type indirect DW_FORM_ref2 0x411 00048c: DW_AT_decl_file 0x1 00048d: DW_AT_decl_line 0x240 00048f: DW_AT_decl_column 0x2 000490: 42 = 0x13 (DW_TAG_structure_type) 000491: DW_AT_sibling 0x579 000493: DW_AT_byte_size 0x28 000494: 30 = 0xd (DW_TAG_member) 000495: DW_AT_name SDBank 00049c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004a1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0004a4: 30 = 0xd (DW_TAG_member) 0004a5: DW_AT_name ColumnBitsNumber 0004b6: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004bb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0004be: 30 = 0xd (DW_TAG_member) 0004bf: DW_AT_name RowBitsNumber 0004cd: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004d2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0004d5: 30 = 0xd (DW_TAG_member) 0004d6: DW_AT_name MemoryDataWidth 0004e6: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004eb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0004ee: 30 = 0xd (DW_TAG_member) 0004ef: DW_AT_name InternalBankNumber 000502: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000507: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 00050a: 30 = 0xd (DW_TAG_member) 00050b: DW_AT_name CASLatency 000516: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00051b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 00051e: 30 = 0xd (DW_TAG_member) 00051f: DW_AT_name WriteProtection 00052f: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000534: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 000537: 30 = 0xd (DW_TAG_member) 000538: DW_AT_name SDClockPeriod 000546: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00054b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 00054e: 30 = 0xd (DW_TAG_member) 00054f: DW_AT_name ReadBurst 000559: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00055e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 000561: 30 = 0xd (DW_TAG_member) 000562: DW_AT_name ReadPipeDelay 000570: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000575: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 000578: 0 null 000579: 80 = 0x16 (DW_TAG_typedef) 00057a: DW_AT_name FMC_SDRAM_InitTypeDef 000590: DW_AT_type indirect DW_FORM_ref2 0x490 000593: DW_AT_decl_file 0x1 000594: DW_AT_decl_line 0x266 000596: DW_AT_decl_column 0x2 000597: 42 = 0x13 (DW_TAG_structure_type) 000598: DW_AT_sibling 0x643 00059a: DW_AT_byte_size 0x1c 00059b: 30 = 0xd (DW_TAG_member) 00059c: DW_AT_name LoadToActiveDelay 0005ae: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0005b3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0005b6: 30 = 0xd (DW_TAG_member) 0005b7: DW_AT_name ExitSelfRefreshDelay 0005cc: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0005d1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0005d4: 30 = 0xd (DW_TAG_member) 0005d5: DW_AT_name SelfRefreshTime 0005e5: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0005ea: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0005ed: 30 = 0xd (DW_TAG_member) 0005ee: DW_AT_name RowCycleDelay 0005fc: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000601: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000604: 30 = 0xd (DW_TAG_member) 000605: DW_AT_name WriteRecoveryTime 000617: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00061c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 00061f: 30 = 0xd (DW_TAG_member) 000620: DW_AT_name RPDelay 000628: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00062d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 000630: 30 = 0xd (DW_TAG_member) 000631: DW_AT_name RCDDelay 00063a: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00063f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 000642: 0 null 000643: 80 = 0x16 (DW_TAG_typedef) 000644: DW_AT_name FMC_SDRAM_TimingTypeDef 00065c: DW_AT_type indirect DW_FORM_ref2 0x597 00065f: DW_AT_decl_file 0x1 000660: DW_AT_decl_line 0x288 000662: DW_AT_decl_column 0x2 000663: 42 = 0x13 (DW_TAG_structure_type) 000664: DW_AT_sibling 0x6cf 000666: DW_AT_byte_size 0x10 000667: 30 = 0xd (DW_TAG_member) 000668: DW_AT_name CommandMode 000674: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000679: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00067c: 30 = 0xd (DW_TAG_member) 00067d: DW_AT_name CommandTarget 00068b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000690: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000693: 30 = 0xd (DW_TAG_member) 000694: DW_AT_name AutoRefreshNumber 0006a6: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0006ab: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0006ae: 30 = 0xd (DW_TAG_member) 0006af: DW_AT_name ModeRegisterDefinition 0006c6: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0006cb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0006ce: 0 null 0006cf: 80 = 0x16 (DW_TAG_typedef) 0006d0: DW_AT_name FMC_SDRAM_CommandTypeDef 0006e9: DW_AT_type indirect DW_FORM_ref2 0x663 0006ec: DW_AT_decl_file 0x1 0006ed: DW_AT_decl_line 0x299 0006ef: DW_AT_decl_column 0x2 0006f0: 0 null 0006f1: 0 padding 0006f2: 0 padding 0006f3: 0 padding ** Section #395 '.rel.debug_info' (SHT_REL) Size : 456 bytes (alignment 4) Symbol table #343 '.symtab' 57 relocations applied to section #162 '.debug_info' ** Section #163 '__ARM_grp.stm32f7xx_hal_sram.h.2_0M2100_3M8HgbfHLH4_t20000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #164 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 124 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_SRAM_H 00001d: include at line 47 - file 2 000020: end include 000021: line 108 define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET) 00007a: end include 00007b: end of translation unit ** Section #165 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 120 bytes 000000: Header: length 116 (not including this field) version 3 prologue length 107 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_sram.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 73 72 61 6d 2e 68 00 01 00 00 00005e: file "stm32f7xx_ll_fmc.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 6c 6c 5f 66 6d 63 2e 68 00 01 00 00 000074: file "" : 00 000075: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_sram.h:1.0 ** Section #166 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 572 bytes 000000: Header: size 0x238 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_sram.h 00004a: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000091: DW_AT_language DW_LANG_C89 000093: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010a: DW_AT_macro_info 0x0 00010e: DW_AT_stmt_list 0x0 000112: 19 = 0x4 (DW_TAG_enumeration_type) 000113: DW_AT_sibling 0x192 000115: DW_AT_byte_size 0x1 000116: 20 = 0x28 (DW_TAG_enumerator) 000117: DW_AT_name HAL_SRAM_STATE_RESET 00012c: DW_AT_const_value indirect DW_FORM_data1 0x0 00012e: 20 = 0x28 (DW_TAG_enumerator) 00012f: DW_AT_name HAL_SRAM_STATE_READY 000144: DW_AT_const_value indirect DW_FORM_data1 0x1 000146: 20 = 0x28 (DW_TAG_enumerator) 000147: DW_AT_name HAL_SRAM_STATE_BUSY 00015b: DW_AT_const_value indirect DW_FORM_data1 0x2 00015d: 20 = 0x28 (DW_TAG_enumerator) 00015e: DW_AT_name HAL_SRAM_STATE_ERROR 000173: DW_AT_const_value indirect DW_FORM_data1 0x3 000175: 20 = 0x28 (DW_TAG_enumerator) 000176: DW_AT_name HAL_SRAM_STATE_PROTECTED 00018f: DW_AT_const_value indirect DW_FORM_data1 0x4 000191: 0 null 000192: 80 = 0x16 (DW_TAG_typedef) 000193: DW_AT_name HAL_SRAM_StateTypeDef 0001a9: DW_AT_type indirect DW_FORM_ref2 0x112 0001ac: DW_AT_decl_file 0x1 0001ad: DW_AT_decl_line 0x48 0001ae: DW_AT_decl_column 0x2 0001af: 42 = 0x13 (DW_TAG_structure_type) 0001b0: DW_AT_sibling 0x209 0001b2: DW_AT_byte_size 0x4c 0001b3: 30 = 0xd (DW_TAG_member) 0001b4: DW_AT_name Instance 0001bd: DW_AT_type indirect DW_FORM_ref2 0x209 0001c0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0001c3: 30 = 0xd (DW_TAG_member) 0001c4: DW_AT_name Extended 0001cd: DW_AT_type indirect DW_FORM_ref2 0x20f 0001d0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0001d3: 30 = 0xd (DW_TAG_member) 0001d4: DW_AT_name Init 0001d9: DW_AT_type indirect DW_FORM_ref_addr 0x267+__ARM_grp..debug_info$stm32f7xx_ll_fmc.h$.2_om8000__ExyD6nDcTf_Y00000 0001de: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0001e1: 30 = 0xd (DW_TAG_member) 0001e2: DW_AT_name Lock 0001e7: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 0001ec: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 68 } 0001ef: 30 = 0xd (DW_TAG_member) 0001f0: DW_AT_name State 0001f6: DW_AT_type indirect DW_FORM_ref2 0x215 0001f9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 69 } 0001fc: 30 = 0xd (DW_TAG_member) 0001fd: DW_AT_name hdma 000202: DW_AT_type indirect DW_FORM_ref2 0x219 000205: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 72 } 000208: 0 null 000209: 34 = 0xf (DW_TAG_pointer_type) 00020a: DW_AT_type indirect DW_FORM_ref_addr 0x183a+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 00020f: 34 = 0xf (DW_TAG_pointer_type) 000210: DW_AT_type indirect DW_FORM_ref_addr 0x186e+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 000215: 116 = 0x35 (DW_TAG_volatile_type) 000216: DW_AT_type indirect DW_FORM_ref2 0x192 000219: 34 = 0xf (DW_TAG_pointer_type) 00021a: DW_AT_type indirect DW_FORM_ref_addr 0x1a0+__ARM_grp..debug_info$stm32f7xx_hal_dma.h$.2_wD1100_gh0hnOcebnc_s10000 00021f: 80 = 0x16 (DW_TAG_typedef) 000220: DW_AT_name SRAM_HandleTypeDef 000233: DW_AT_type indirect DW_FORM_ref2 0x1af 000236: DW_AT_decl_file 0x1 000237: DW_AT_decl_line 0x5b 000238: DW_AT_decl_column 0x2 000239: 0 null 00023a: 0 padding 00023b: 0 padding ** Section #396 '.rel.debug_info' (SHT_REL) Size : 64 bytes (alignment 4) Symbol table #343 '.symtab' 8 relocations applied to section #166 '.debug_info' ** Section #167 '__ARM_grp.stm32f7xx_hal_nor.h.2_EY$000_kQSX135Z2Jc_g20000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #168 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 1040 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_NOR_H 00001c: include at line 47 - file 2 00001f: end include 000020: line 150 define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET) 000078: line 227 define MC_ADDRESS ((uint16_t)0x0000U) 00009a: line 228 define DEVICE_CODE1_ADDR ((uint16_t)0x0001U) 0000c3: line 229 define DEVICE_CODE2_ADDR ((uint16_t)0x000EU) 0000ec: line 230 define DEVICE_CODE3_ADDR ((uint16_t)0x000FU) 000115: line 233 define CFI1_ADDRESS ((uint16_t)0x61U) 000137: line 234 define CFI2_ADDRESS ((uint16_t)0x62U) 000159: line 235 define CFI3_ADDRESS ((uint16_t)0x63U) 00017b: line 236 define CFI4_ADDRESS ((uint16_t)0x64U) 00019d: line 239 define NOR_TMEOUT ((uint16_t)0xFFFFU) 0001bf: line 242 define NOR_MEMORY_8B ((uint8_t)0x0U) 0001e0: line 243 define NOR_MEMORY_16B ((uint8_t)0x1U) 000202: line 246 define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000U) 000230: line 247 define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000U) 00025e: line 248 define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000U) 00028c: line 249 define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000U) 0002ba: line 265 define NOR_ADDR_SHIFT(__NOR_ADDRESS,__NOR_MEMORY_WIDTH_,__ADDRESS__) ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))): ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__))))) 000397: line 276 define NOR_WRITE(__ADDRESS__,__DATA__) do{ (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); __DSB(); } while(0) 00040e: end include 00040f: end of translation unit ** Section #169 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 120 bytes 000000: Header: length 116 (not including this field) version 3 prologue length 106 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_nor.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 6e 6f 72 2e 68 00 01 00 00 00005d: file "stm32f7xx_ll_fmc.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 6c 6c 5f 66 6d 63 2e 68 00 01 00 00 000073: file "" : 00 000074: DW_LNS_negate_stmt : 06 000075: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_nor.h:1.0 [ ** Section #170 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 888 bytes 000000: Header: size 0x374 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_nor.h 000049: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000090: DW_AT_language DW_LANG_C89 000092: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 000109: DW_AT_macro_info 0x0 00010d: DW_AT_stmt_list 0x0 000111: 19 = 0x4 (DW_TAG_enumeration_type) 000112: DW_AT_sibling 0x18c 000114: DW_AT_byte_size 0x1 000115: 20 = 0x28 (DW_TAG_enumerator) 000116: DW_AT_name HAL_NOR_STATE_RESET 00012a: DW_AT_const_value indirect DW_FORM_data1 0x0 00012c: 20 = 0x28 (DW_TAG_enumerator) 00012d: DW_AT_name HAL_NOR_STATE_READY 000141: DW_AT_const_value indirect DW_FORM_data1 0x1 000143: 20 = 0x28 (DW_TAG_enumerator) 000144: DW_AT_name HAL_NOR_STATE_BUSY 000157: DW_AT_const_value indirect DW_FORM_data1 0x2 000159: 20 = 0x28 (DW_TAG_enumerator) 00015a: DW_AT_name HAL_NOR_STATE_ERROR 00016e: DW_AT_const_value indirect DW_FORM_data1 0x3 000170: 20 = 0x28 (DW_TAG_enumerator) 000171: DW_AT_name HAL_NOR_STATE_PROTECTED 000189: DW_AT_const_value indirect DW_FORM_data1 0x4 00018b: 0 null 00018c: 80 = 0x16 (DW_TAG_typedef) 00018d: DW_AT_name HAL_NOR_StateTypeDef 0001a2: DW_AT_type indirect DW_FORM_ref2 0x111 0001a5: DW_AT_decl_file 0x1 0001a6: DW_AT_decl_line 0x49 0001a7: DW_AT_decl_column 0x2 0001a8: 19 = 0x4 (DW_TAG_enumeration_type) 0001a9: DW_AT_sibling 0x213 0001ab: DW_AT_byte_size 0x1 0001ac: 20 = 0x28 (DW_TAG_enumerator) 0001ad: DW_AT_name HAL_NOR_STATUS_SUCCESS 0001c4: DW_AT_const_value indirect DW_FORM_data1 0x0 0001c6: 20 = 0x28 (DW_TAG_enumerator) 0001c7: DW_AT_name HAL_NOR_STATUS_ONGOING 0001de: DW_AT_const_value indirect DW_FORM_data1 0x1 0001e0: 20 = 0x28 (DW_TAG_enumerator) 0001e1: DW_AT_name HAL_NOR_STATUS_ERROR 0001f6: DW_AT_const_value indirect DW_FORM_data1 0x2 0001f8: 20 = 0x28 (DW_TAG_enumerator) 0001f9: DW_AT_name HAL_NOR_STATUS_TIMEOUT 000210: DW_AT_const_value indirect DW_FORM_data1 0x3 000212: 0 null 000213: 80 = 0x16 (DW_TAG_typedef) 000214: DW_AT_name HAL_NOR_StatusTypeDef 00022a: DW_AT_type indirect DW_FORM_ref2 0x1a8 00022d: DW_AT_decl_file 0x1 00022e: DW_AT_decl_line 0x54 00022f: DW_AT_decl_column 0x2 000230: 42 = 0x13 (DW_TAG_structure_type) 000231: DW_AT_sibling 0x292 000233: DW_AT_byte_size 0x8 000234: 30 = 0xd (DW_TAG_member) 000235: DW_AT_name Manufacturer_Code 000247: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00024c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00024f: 30 = 0xd (DW_TAG_member) 000250: DW_AT_name Device_Code1 00025d: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000262: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 2 } 000265: 30 = 0xd (DW_TAG_member) 000266: DW_AT_name Device_Code2 000273: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000278: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00027b: 30 = 0xd (DW_TAG_member) 00027c: DW_AT_name Device_Code3 000289: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00028e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 6 } 000291: 0 null 000292: 80 = 0x16 (DW_TAG_typedef) 000293: DW_AT_name NOR_IDTypeDef 0002a1: DW_AT_type indirect DW_FORM_ref2 0x230 0002a4: DW_AT_decl_file 0x1 0002a5: DW_AT_decl_line 0x65 0002a6: DW_AT_decl_column 0x2 0002a7: 42 = 0x13 (DW_TAG_structure_type) 0002a8: DW_AT_sibling 0x2e8 0002aa: DW_AT_byte_size 0x8 0002ab: 30 = 0xd (DW_TAG_member) 0002ac: DW_AT_name CFI_1 0002b2: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002b7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0002ba: 30 = 0xd (DW_TAG_member) 0002bb: DW_AT_name CFI_2 0002c1: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002c6: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 2 } 0002c9: 30 = 0xd (DW_TAG_member) 0002ca: DW_AT_name CFI_3 0002d0: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002d5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0002d8: 30 = 0xd (DW_TAG_member) 0002d9: DW_AT_name CFI_4 0002df: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002e4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 6 } 0002e7: 0 null 0002e8: 80 = 0x16 (DW_TAG_typedef) 0002e9: DW_AT_name NOR_CFITypeDef 0002f8: DW_AT_type indirect DW_FORM_ref2 0x2a7 0002fb: DW_AT_decl_file 0x1 0002fc: DW_AT_decl_line 0x77 0002fd: DW_AT_decl_column 0x2 0002fe: 42 = 0x13 (DW_TAG_structure_type) 0002ff: DW_AT_sibling 0x34c 000301: DW_AT_byte_size 0x48 000302: 30 = 0xd (DW_TAG_member) 000303: DW_AT_name Instance 00030c: DW_AT_type indirect DW_FORM_ref2 0x34c 00030f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000312: 30 = 0xd (DW_TAG_member) 000313: DW_AT_name Extended 00031c: DW_AT_type indirect DW_FORM_ref2 0x352 00031f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000322: 30 = 0xd (DW_TAG_member) 000323: DW_AT_name Init 000328: DW_AT_type indirect DW_FORM_ref_addr 0x267+__ARM_grp..debug_info$stm32f7xx_ll_fmc.h$.2_om8000__ExyD6nDcTf_Y00000 00032d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000330: 30 = 0xd (DW_TAG_member) 000331: DW_AT_name Lock 000336: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 00033b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 68 } 00033e: 30 = 0xd (DW_TAG_member) 00033f: DW_AT_name State 000345: DW_AT_type indirect DW_FORM_ref2 0x358 000348: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 69 } 00034b: 0 null 00034c: 34 = 0xf (DW_TAG_pointer_type) 00034d: DW_AT_type indirect DW_FORM_ref_addr 0x183a+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 000352: 34 = 0xf (DW_TAG_pointer_type) 000353: DW_AT_type indirect DW_FORM_ref_addr 0x186e+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 000358: 116 = 0x35 (DW_TAG_volatile_type) 000359: DW_AT_type indirect DW_FORM_ref2 0x18c 00035c: 80 = 0x16 (DW_TAG_typedef) 00035d: DW_AT_name NOR_HandleTypeDef 00036f: DW_AT_type indirect DW_FORM_ref2 0x2fe 000372: DW_AT_decl_file 0x1 000373: DW_AT_decl_line 0x88 000375: DW_AT_decl_column 0x2 000376: 0 null 000377: 0 padding ** Section #397 '.rel.debug_info' (SHT_REL) Size : 120 bytes (alignment 4) Symbol table #343 '.symtab' 15 relocations applied to section #170 '.debug_info' ** Section #171 '__ARM_grp.stm32f7xx_hal_nand.h.2_A60100_PwQdbRJ0jo0_j20000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #172 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 1392 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_NAND_H 00001d: include at line 47 - file 2 000020: end include 000021: line 148 define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET) 00007b: line 231 define NAND_DEVICE ((uint32_t)0x80000000U) 0000a2: line 232 define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000U) 0000d0: line 234 define CMD_AREA ((uint32_t)(1<<16)) 0000f0: line 235 define ADDR_AREA ((uint32_t)(1<<17)) 000111: line 237 define NAND_CMD_AREA_A ((uint8_t)0x00U) 000135: line 238 define NAND_CMD_AREA_B ((uint8_t)0x01U) 000159: line 239 define NAND_CMD_AREA_C ((uint8_t)0x50U) 00017d: line 240 define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U) 0001a5: line 242 define NAND_CMD_WRITE0 ((uint8_t)0x80U) 0001c9: line 243 define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U) 0001f2: line 244 define NAND_CMD_ERASE0 ((uint8_t)0x60U) 000216: line 245 define NAND_CMD_ERASE1 ((uint8_t)0xD0U) 00023a: line 246 define NAND_CMD_READID ((uint8_t)0x90U) 00025e: line 247 define NAND_CMD_STATUS ((uint8_t)0x70U) 000282: line 248 define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU) 0002ab: line 249 define NAND_CMD_RESET ((uint8_t)0xFFU) 0002ce: line 252 define NAND_VALID_ADDRESS ((uint32_t)0x00000100U) 0002fc: line 253 define NAND_INVALID_ADDRESS ((uint32_t)0x00000200U) 00032c: line 254 define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400U) 00035a: line 255 define NAND_BUSY ((uint32_t)0x00000000U) 00037f: line 256 define NAND_ERROR ((uint32_t)0x00000001U) 0003a5: line 257 define NAND_READY ((uint32_t)0x00000040U) 0003cb: line 273 define ARRAY_ADDRESS(__ADDRESS__,__HANDLE__) ((__ADDRESS__)->Page + (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize))) 00047f: line 281 define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) 0004b5: line 282 define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) 0004f2: line 283 define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) 000530: line 284 define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) 00056e: end include 00056f: end of translation unit ** Section #173 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 120 bytes 000000: Header: length 116 (not including this field) version 3 prologue length 107 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_nand.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 6e 61 6e 64 2e 68 00 01 00 00 00005e: file "stm32f7xx_ll_fmc.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 6c 6c 5f 66 6d 63 2e 68 00 01 00 00 000074: file "" : 00 000075: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_nand.h:1.0 ** Section #174 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 820 bytes 000000: Header: size 0x330 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_nand.h 00004a: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000091: DW_AT_language DW_LANG_C89 000093: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010a: DW_AT_macro_info 0x0 00010e: DW_AT_stmt_list 0x0 000112: 19 = 0x4 (DW_TAG_enumeration_type) 000113: DW_AT_sibling 0x176 000115: DW_AT_byte_size 0x1 000116: 20 = 0x28 (DW_TAG_enumerator) 000117: DW_AT_name HAL_NAND_STATE_RESET 00012c: DW_AT_const_value indirect DW_FORM_data1 0x0 00012e: 20 = 0x28 (DW_TAG_enumerator) 00012f: DW_AT_name HAL_NAND_STATE_READY 000144: DW_AT_const_value indirect DW_FORM_data1 0x1 000146: 20 = 0x28 (DW_TAG_enumerator) 000147: DW_AT_name HAL_NAND_STATE_BUSY 00015b: DW_AT_const_value indirect DW_FORM_data1 0x2 00015d: 20 = 0x28 (DW_TAG_enumerator) 00015e: DW_AT_name HAL_NAND_STATE_ERROR 000173: DW_AT_const_value indirect DW_FORM_data1 0x3 000175: 0 null 000176: 80 = 0x16 (DW_TAG_typedef) 000177: DW_AT_name HAL_NAND_StateTypeDef 00018d: DW_AT_type indirect DW_FORM_ref2 0x112 000190: DW_AT_decl_file 0x1 000191: DW_AT_decl_line 0x48 000192: DW_AT_decl_column 0x2 000193: 42 = 0x13 (DW_TAG_structure_type) 000194: DW_AT_sibling 0x1e2 000196: DW_AT_byte_size 0x4 000197: 30 = 0xd (DW_TAG_member) 000198: DW_AT_name Maker_Id 0001a1: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001a6: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0001a9: 30 = 0xd (DW_TAG_member) 0001aa: DW_AT_name Device_Id 0001b4: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001b9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 1 } 0001bc: 30 = 0xd (DW_TAG_member) 0001bd: DW_AT_name Third_Id 0001c6: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001cb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 2 } 0001ce: 30 = 0xd (DW_TAG_member) 0001cf: DW_AT_name Fourth_Id 0001d9: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001de: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 3 } 0001e1: 0 null 0001e2: 80 = 0x16 (DW_TAG_typedef) 0001e3: DW_AT_name NAND_IDTypeDef 0001f2: DW_AT_type indirect DW_FORM_ref2 0x193 0001f5: DW_AT_decl_file 0x1 0001f6: DW_AT_decl_line 0x58 0001f7: DW_AT_decl_column 0x2 0001f8: 42 = 0x13 (DW_TAG_structure_type) 0001f9: DW_AT_sibling 0x228 0001fb: DW_AT_byte_size 0x6 0001fc: 30 = 0xd (DW_TAG_member) 0001fd: DW_AT_name Page 000202: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000207: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00020a: 30 = 0xd (DW_TAG_member) 00020b: DW_AT_name Zone 000210: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000215: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 2 } 000218: 30 = 0xd (DW_TAG_member) 000219: DW_AT_name Block 00021f: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000224: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000227: 0 null 000228: 80 = 0x16 (DW_TAG_typedef) 000229: DW_AT_name NAND_AddressTypeDef 00023d: DW_AT_type indirect DW_FORM_ref2 0x1f8 000240: DW_AT_decl_file 0x1 000241: DW_AT_decl_line 0x65 000242: DW_AT_decl_column 0x2 000243: 42 = 0x13 (DW_TAG_structure_type) 000244: DW_AT_sibling 0x2a8 000246: DW_AT_byte_size 0x14 000247: 30 = 0xd (DW_TAG_member) 000248: DW_AT_name PageSize 000251: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000256: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000259: 30 = 0xd (DW_TAG_member) 00025a: DW_AT_name SpareAreaSize 000268: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00026d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000270: 30 = 0xd (DW_TAG_member) 000271: DW_AT_name BlockSize 00027b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000280: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000283: 30 = 0xd (DW_TAG_member) 000284: DW_AT_name BlockNbr 00028d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000292: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000295: 30 = 0xd (DW_TAG_member) 000296: DW_AT_name ZoneSize 00029f: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002a4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 0002a7: 0 null 0002a8: 80 = 0x16 (DW_TAG_typedef) 0002a9: DW_AT_name NAND_InfoTypeDef 0002ba: DW_AT_type indirect DW_FORM_ref2 0x243 0002bd: DW_AT_decl_file 0x1 0002be: DW_AT_decl_line 0x75 0002bf: DW_AT_decl_column 0x2 0002c0: 42 = 0x13 (DW_TAG_structure_type) 0002c1: DW_AT_sibling 0x30a 0002c3: DW_AT_byte_size 0x38 0002c4: 30 = 0xd (DW_TAG_member) 0002c5: DW_AT_name Instance 0002ce: DW_AT_type indirect DW_FORM_ref2 0x30a 0002d1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0002d4: 30 = 0xd (DW_TAG_member) 0002d5: DW_AT_name Init 0002da: DW_AT_type indirect DW_FORM_ref_addr 0x3f4+__ARM_grp..debug_info$stm32f7xx_ll_fmc.h$.2_om8000__ExyD6nDcTf_Y00000 0002df: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0002e2: 30 = 0xd (DW_TAG_member) 0002e3: DW_AT_name Lock 0002e8: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 0002ed: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 0002f0: 30 = 0xd (DW_TAG_member) 0002f1: DW_AT_name State 0002f7: DW_AT_type indirect DW_FORM_ref2 0x310 0002fa: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 33 } 0002fd: 30 = 0xd (DW_TAG_member) 0002fe: DW_AT_name Info 000303: DW_AT_type indirect DW_FORM_ref2 0x2a8 000306: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 000309: 0 null 00030a: 34 = 0xf (DW_TAG_pointer_type) 00030b: DW_AT_type indirect DW_FORM_ref_addr 0x18da+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 000310: 116 = 0x35 (DW_TAG_volatile_type) 000311: DW_AT_type indirect DW_FORM_ref2 0x176 000314: 80 = 0x16 (DW_TAG_typedef) 000315: DW_AT_name NAND_HandleTypeDef 000328: DW_AT_type indirect DW_FORM_ref2 0x2c0 00032b: DW_AT_decl_file 0x1 00032c: DW_AT_decl_line 0x85 00032e: DW_AT_decl_column 0x2 00032f: 0 null 000330: 0 padding 000331: 0 padding 000332: 0 padding 000333: 0 padding ** Section #398 '.rel.debug_info' (SHT_REL) Size : 144 bytes (alignment 4) Symbol table #343 '.symtab' 18 relocations applied to section #174 '.debug_info' ** Section #175 '__ARM_grp.stm32f7xx_hal_sdram.h.2_EM2100_KpVfMDmBB64_s20000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #176 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 128 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_SDRAM_H 00001e: include at line 47 - file 2 000021: end include 000022: line 108 define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET) 00007d: end include 00007e: end of translation unit ** Section #177 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 124 bytes 000000: Header: length 120 (not including this field) version 3 prologue length 108 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_sdram.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 73 64 72 61 6d 2e 68 00 01 00 00 00005f: file "stm32f7xx_ll_fmc.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 6c 6c 5f 66 6d 63 2e 68 00 01 00 00 000075: file "" : 00 000076: DW_LNS_negate_stmt : 06 000077: DW_LNS_negate_stmt : 06 000078: DW_LNS_negate_stmt : 06 000079: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_sdram.h:1.0 [ ** Section #178 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 596 bytes 000000: Header: size 0x250 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_sdram.h 00004b: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000092: DW_AT_language DW_LANG_C89 000094: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010b: DW_AT_macro_info 0x0 00010f: DW_AT_stmt_list 0x0 000113: 19 = 0x4 (DW_TAG_enumeration_type) 000114: DW_AT_sibling 0x1bc 000116: DW_AT_byte_size 0x1 000117: 20 = 0x28 (DW_TAG_enumerator) 000118: DW_AT_name HAL_SDRAM_STATE_RESET 00012e: DW_AT_const_value indirect DW_FORM_data1 0x0 000130: 20 = 0x28 (DW_TAG_enumerator) 000131: DW_AT_name HAL_SDRAM_STATE_READY 000147: DW_AT_const_value indirect DW_FORM_data1 0x1 000149: 20 = 0x28 (DW_TAG_enumerator) 00014a: DW_AT_name HAL_SDRAM_STATE_BUSY 00015f: DW_AT_const_value indirect DW_FORM_data1 0x2 000161: 20 = 0x28 (DW_TAG_enumerator) 000162: DW_AT_name HAL_SDRAM_STATE_ERROR 000178: DW_AT_const_value indirect DW_FORM_data1 0x3 00017a: 20 = 0x28 (DW_TAG_enumerator) 00017b: DW_AT_name HAL_SDRAM_STATE_WRITE_PROTECTED 00019b: DW_AT_const_value indirect DW_FORM_data1 0x4 00019d: 20 = 0x28 (DW_TAG_enumerator) 00019e: DW_AT_name HAL_SDRAM_STATE_PRECHARGED 0001b9: DW_AT_const_value indirect DW_FORM_data1 0x5 0001bb: 0 null 0001bc: 80 = 0x16 (DW_TAG_typedef) 0001bd: DW_AT_name HAL_SDRAM_StateTypeDef 0001d4: DW_AT_type indirect DW_FORM_ref2 0x113 0001d7: DW_AT_decl_file 0x1 0001d8: DW_AT_decl_line 0x4b 0001d9: DW_AT_decl_column 0x2 0001da: 42 = 0x13 (DW_TAG_structure_type) 0001db: DW_AT_sibling 0x224 0001dd: DW_AT_byte_size 0x34 0001de: 30 = 0xd (DW_TAG_member) 0001df: DW_AT_name Instance 0001e8: DW_AT_type indirect DW_FORM_ref2 0x224 0001eb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0001ee: 30 = 0xd (DW_TAG_member) 0001ef: DW_AT_name Init 0001f4: DW_AT_type indirect DW_FORM_ref_addr 0x579+__ARM_grp..debug_info$stm32f7xx_ll_fmc.h$.2_om8000__ExyD6nDcTf_Y00000 0001f9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0001fc: 30 = 0xd (DW_TAG_member) 0001fd: DW_AT_name State 000203: DW_AT_type indirect DW_FORM_ref2 0x22a 000206: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 000209: 30 = 0xd (DW_TAG_member) 00020a: DW_AT_name Lock 00020f: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 000214: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 45 } 000217: 30 = 0xd (DW_TAG_member) 000218: DW_AT_name hdma 00021d: DW_AT_type indirect DW_FORM_ref2 0x22e 000220: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 000223: 0 null 000224: 34 = 0xf (DW_TAG_pointer_type) 000225: DW_AT_type indirect DW_FORM_ref_addr 0x1949+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 00022a: 116 = 0x35 (DW_TAG_volatile_type) 00022b: DW_AT_type indirect DW_FORM_ref2 0x1bc 00022e: 34 = 0xf (DW_TAG_pointer_type) 00022f: DW_AT_type indirect DW_FORM_ref_addr 0x1a0+__ARM_grp..debug_info$stm32f7xx_hal_dma.h$.2_wD1100_gh0hnOcebnc_s10000 000234: 80 = 0x16 (DW_TAG_typedef) 000235: DW_AT_name SDRAM_HandleTypeDef 000249: DW_AT_type indirect DW_FORM_ref2 0x1da 00024c: DW_AT_decl_file 0x1 00024d: DW_AT_decl_line 0x5c 00024e: DW_AT_decl_column 0x2 00024f: 0 null 000250: 0 padding 000251: 0 padding 000252: 0 padding 000253: 0 padding ** Section #399 '.rel.debug_info' (SHT_REL) Size : 56 bytes (alignment 4) Symbol table #343 '.symtab' 7 relocations applied to section #178 '.debug_info' ** Section #179 '__ARM_grp.stm32f7xx_hal_hash.h.2_0v0000_6dfCvthvqQ9_300000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #180 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 32 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_HASH_H 00001d: end include 00001e: end of translation unit ** Section #181 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 100 bytes 000000: Header: length 96 (not including this field) version 3 prologue length 85 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_hash.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 68 61 73 68 2e 68 00 01 00 00 00005e: file "" : 00 00005f: DW_LNS_negate_stmt : 06 000060: DW_LNS_negate_stmt : 06 000061: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_hash.h:1.0 ** Section #182 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 276 bytes 000000: Header: size 0x110 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_hash.h 00004a: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000091: DW_AT_language DW_LANG_C89 000093: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010a: DW_AT_macro_info 0x0 00010e: DW_AT_stmt_list 0x0 000112: 0 null 000113: 0 padding ** Section #400 '.rel.debug_info' (SHT_REL) Size : 24 bytes (alignment 4) Symbol table #343 '.symtab' 3 relocations applied to section #182 '.debug_info' ** Section #183 '__ARM_grp.stm32f7xx_hal_i2c_ex.h.2_A51000_IGg_yFrxfYd_300000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #184 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 1240 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_I2C_EX_H 00001f: include at line 47 - file 2 000022: end include 000023: line 67 define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U) 000055: line 68 define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF 00007f: line 78 define I2C_FASTMODEPLUS_PB6 SYSCFG_PMC_I2C_PB6_FMP 0000ad: line 79 define I2C_FASTMODEPLUS_PB7 SYSCFG_PMC_I2C_PB7_FMP 0000db: line 80 define I2C_FASTMODEPLUS_PB8 SYSCFG_PMC_I2C_PB8_FMP 000109: line 81 define I2C_FASTMODEPLUS_PB9 SYSCFG_PMC_I2C_PB9_FMP 000137: line 83 define I2C_FASTMODEPLUS_I2C1 SYSCFG_PMC_I2C1_FMP 000163: line 84 define I2C_FASTMODEPLUS_I2C2 SYSCFG_PMC_I2C2_FMP 00018f: line 85 define I2C_FASTMODEPLUS_I2C3 SYSCFG_PMC_I2C3_FMP 0001bb: line 86 define I2C_FASTMODEPLUS_I2C4 SYSCFG_PMC_I2C4_FMP 0001e7: line 121 define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || ((FILTER) == I2C_ANALOGFILTER_DISABLE)) 000258: line 124 define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) 000292: line 127 define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4)) 0004d3: end include 0004d4: end of translation unit ** Section #185 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 124 bytes 000000: Header: length 120 (not including this field) version 3 prologue length 110 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_i2c_ex.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 69 32 63 5f 65 78 2e 68 00 01 00 00 000060: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000077: file "" : 00 000078: DW_LNS_negate_stmt : 06 000079: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c_ex.h:1.0 [ ** Section #186 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 280 bytes 000000: Header: size 0x114 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c_ex.h 00004c: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000093: DW_AT_language DW_LANG_C89 000095: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010c: DW_AT_macro_info 0x0 000110: DW_AT_stmt_list 0x0 000114: 0 null 000115: 0 padding 000116: 0 padding 000117: 0 padding ** Section #401 '.rel.debug_info' (SHT_REL) Size : 24 bytes (alignment 4) Symbol table #343 '.symtab' 3 relocations applied to section #186 '.debug_info' ** Section #187 '__ARM_grp.stm32f7xx_hal_i2c.h.2_Q22100_NRb4U6uQAaa_N10000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #188 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 6156 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_I2C_H 00001c: include at line 47 - file 2 00001f: end include 000020: line 184 define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000U) 00004e: line 185 define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001U) 00007c: line 186 define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002U) 0000aa: line 187 define HAL_I2C_ERROR_AF ((uint32_t)0x00000004U) 0000d6: line 188 define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008U) 000103: line 189 define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010U) 000130: line 190 define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020U) 000161: line 191 define HAL_I2C_ERROR_SIZE ((uint32_t)0x00000040U) 00018f: line 192 define HAL_I2C_ERROR_ABORT ((uint32_t)0x00000080U) 0001be: line 250 define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE) 0001ee: line 251 define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) 00023b: line 252 define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) 00027e: line 253 define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) 0002b7: line 254 define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) 0002e6: line 262 define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001U) 000319: line 263 define I2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002U) 00034d: line 271 define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000U) 000380: line 272 define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN 0003a9: line 280 define I2C_OA2_NOMASK ((uint8_t)0x00U) 0003cc: line 281 define I2C_OA2_MASK01 ((uint8_t)0x01U) 0003ef: line 282 define I2C_OA2_MASK02 ((uint8_t)0x02U) 000412: line 283 define I2C_OA2_MASK03 ((uint8_t)0x03U) 000435: line 284 define I2C_OA2_MASK04 ((uint8_t)0x04U) 000458: line 285 define I2C_OA2_MASK05 ((uint8_t)0x05U) 00047b: line 286 define I2C_OA2_MASK06 ((uint8_t)0x06U) 00049e: line 287 define I2C_OA2_MASK07 ((uint8_t)0x07U) 0004c1: line 295 define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000U) 0004f4: line 296 define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN 00051b: line 304 define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000U) 00054c: line 305 define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH 000576: line 313 define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001U) 0005a6: line 314 define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002U) 0005d7: line 322 define I2C_DIRECTION_TRANSMIT ((uint32_t)0x00000000U) 000609: line 323 define I2C_DIRECTION_RECEIVE ((uint32_t)0x00000001U) 00063a: line 331 define I2C_RELOAD_MODE I2C_CR2_RELOAD 00065c: line 332 define I2C_AUTOEND_MODE I2C_CR2_AUTOEND 000680: line 333 define I2C_SOFTEND_MODE ((uint32_t)0x00000000U) 0006ac: line 341 define I2C_NO_STARTSTOP ((uint32_t)0x00000000U) 0006d8: line 342 define I2C_GENERATE_STOP I2C_CR2_STOP 0006fa: line 343 define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) 000740: line 344 define I2C_GENERATE_START_WRITE I2C_CR2_START 00076a: line 355 define I2C_IT_ERRI I2C_CR1_ERRIE 000787: line 356 define I2C_IT_TCI I2C_CR1_TCIE 0007a2: line 357 define I2C_IT_STOPI I2C_CR1_STOPIE 0007c1: line 358 define I2C_IT_NACKI I2C_CR1_NACKIE 0007e0: line 359 define I2C_IT_ADDRI I2C_CR1_ADDRIE 0007ff: line 360 define I2C_IT_RXI I2C_CR1_RXIE 00081a: line 361 define I2C_IT_TXI I2C_CR1_TXIE 000835: line 369 define I2C_FLAG_TXE I2C_ISR_TXE 000851: line 370 define I2C_FLAG_TXIS I2C_ISR_TXIS 00086f: line 371 define I2C_FLAG_RXNE I2C_ISR_RXNE 00088d: line 372 define I2C_FLAG_ADDR I2C_ISR_ADDR 0008ab: line 373 define I2C_FLAG_AF I2C_ISR_NACKF 0008c8: line 374 define I2C_FLAG_STOPF I2C_ISR_STOPF 0008e8: line 375 define I2C_FLAG_TC I2C_ISR_TC 000902: line 376 define I2C_FLAG_TCR I2C_ISR_TCR 00091e: line 377 define I2C_FLAG_BERR I2C_ISR_BERR 00093c: line 378 define I2C_FLAG_ARLO I2C_ISR_ARLO 00095a: line 379 define I2C_FLAG_OVR I2C_ISR_OVR 000976: line 380 define I2C_FLAG_PECERR I2C_ISR_PECERR 000998: line 381 define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT 0009bc: line 382 define I2C_FLAG_ALERT I2C_ISR_ALERT 0009dc: line 383 define I2C_FLAG_BUSY I2C_ISR_BUSY 0009fa: line 384 define I2C_FLAG_DIR I2C_ISR_DIR 000a16: line 403 define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) 000a6e: line 419 define __HAL_I2C_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) 000ad0: line 435 define __HAL_I2C_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) 000b36: line 451 define __HAL_I2C_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 000bc0: line 476 define __HAL_I2C_GET_FLAG(__HANDLE__,__FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) 000c38: line 495 define __HAL_I2C_CLEAR_FLAG(__HANDLE__,__FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : ((__HANDLE__)->Instance->ICR = (__FLAG__))) 000cdf: line 502 define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) 000d32: line 508 define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) 000d88: line 514 define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) 000de4: include at line 520 - file 3 000de8: end include 000de9: line 629 define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || ((MODE) == I2C_ADDRESSINGMODE_10BIT)) 000e57: line 632 define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) 000ec9: line 635 define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || ((MASK) == I2C_OA2_MASK01) || ((MASK) == I2C_OA2_MASK02) || ((MASK) == I2C_OA2_MASK03) || ((MASK) == I2C_OA2_MASK04) || ((MASK) == I2C_OA2_MASK05) || ((MASK) == I2C_OA2_MASK06) || ((MASK) == I2C_OA2_MASK07)) 000fda: line 644 define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || ((CALL) == I2C_GENERALCALL_ENABLE)) 001043: line 647 define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || ((STRETCH) == I2C_NOSTRETCH_ENABLE)) 0010af: line 650 define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || ((SIZE) == I2C_MEMADD_SIZE_16BIT)) 001113: line 653 define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || ((MODE) == I2C_AUTOEND_MODE) || ((MODE) == I2C_SOFTEND_MODE)) 00118b: line 657 define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || ((REQUEST) == I2C_GENERATE_START_READ) || ((REQUEST) == I2C_GENERATE_START_WRITE) || ((REQUEST) == I2C_NO_STARTSTOP)) 001246: line 662 define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || ((REQUEST) == I2C_NEXT_FRAME) || ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || ((REQUEST) == I2C_LAST_FRAME)) 00132b: line 668 define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) 0013d4: line 670 define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16) 00142e: line 671 define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16) 00147d: line 672 define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) 0014ce: line 673 define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1) 001520: line 674 define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2) 001572: line 676 define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF) 0015b8: line 677 define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF) 0015fa: line 679 define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8))) 001669: line 680 define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) 0016c5: line 682 define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) 001809: end include 00180a: end of translation unit ** Section #189 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 148 bytes 000000: Header: length 144 (not including this field) version 3 prologue length 133 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_i2c.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 69 32 63 2e 68 00 01 00 00 00005d: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000074: file "stm32f7xx_hal_i2c_ex.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 69 32 63 5f 65 78 2e 68 00 01 00 00 00008e: file "" : 00 00008f: DW_LNS_negate_stmt : 06 000090: DW_LNS_negate_stmt : 06 000091: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c.h:1.0 ** Section #190 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 1276 bytes 000000: Header: size 0x4f8 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c.h 000049: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000090: DW_AT_language DW_LANG_C89 000092: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 000109: DW_AT_macro_info 0x0 00010d: DW_AT_stmt_list 0x0 000111: 42 = 0x13 (DW_TAG_structure_type) 000112: DW_AT_sibling 0x1cb 000114: DW_AT_byte_size 0x20 000115: 30 = 0xd (DW_TAG_member) 000116: DW_AT_name Timing 00011d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000122: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000125: 30 = 0xd (DW_TAG_member) 000126: DW_AT_name OwnAddress1 000132: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000137: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00013a: 30 = 0xd (DW_TAG_member) 00013b: DW_AT_name AddressingMode 00014a: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00014f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000152: 30 = 0xd (DW_TAG_member) 000153: DW_AT_name DualAddressMode 000163: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000168: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00016b: 30 = 0xd (DW_TAG_member) 00016c: DW_AT_name OwnAddress2 000178: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00017d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000180: 30 = 0xd (DW_TAG_member) 000181: DW_AT_name OwnAddress2Masks 000192: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000197: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 00019a: 30 = 0xd (DW_TAG_member) 00019b: DW_AT_name GeneralCallMode 0001ab: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001b0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 0001b3: 30 = 0xd (DW_TAG_member) 0001b4: DW_AT_name NoStretchMode 0001c2: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001c7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 0001ca: 0 null 0001cb: 80 = 0x16 (DW_TAG_typedef) 0001cc: DW_AT_name I2C_InitTypeDef 0001dc: DW_AT_type indirect DW_FORM_ref2 0x111 0001df: DW_AT_decl_file 0x1 0001e0: DW_AT_decl_line 0x5d 0001e1: DW_AT_decl_column 0x2 0001e2: 19 = 0x4 (DW_TAG_enumeration_type) 0001e3: DW_AT_sibling 0x2fc 0001e5: DW_AT_byte_size 0x1 0001e6: 20 = 0x28 (DW_TAG_enumerator) 0001e7: DW_AT_name HAL_I2C_STATE_RESET 0001fb: DW_AT_const_value indirect DW_FORM_data1 0x0 0001fd: 20 = 0x28 (DW_TAG_enumerator) 0001fe: DW_AT_name HAL_I2C_STATE_READY 000212: DW_AT_const_value indirect DW_FORM_data1 0x20 000214: 20 = 0x28 (DW_TAG_enumerator) 000215: DW_AT_name HAL_I2C_STATE_BUSY 000228: DW_AT_const_value indirect DW_FORM_data1 0x24 00022a: 20 = 0x28 (DW_TAG_enumerator) 00022b: DW_AT_name HAL_I2C_STATE_BUSY_TX 000241: DW_AT_const_value indirect DW_FORM_data1 0x21 000243: 20 = 0x28 (DW_TAG_enumerator) 000244: DW_AT_name HAL_I2C_STATE_BUSY_RX 00025a: DW_AT_const_value indirect DW_FORM_data1 0x22 00025c: 20 = 0x28 (DW_TAG_enumerator) 00025d: DW_AT_name HAL_I2C_STATE_LISTEN 000272: DW_AT_const_value indirect DW_FORM_data1 0x28 000274: 20 = 0x28 (DW_TAG_enumerator) 000275: DW_AT_name HAL_I2C_STATE_BUSY_TX_LISTEN 000292: DW_AT_const_value indirect DW_FORM_data1 0x29 000294: 20 = 0x28 (DW_TAG_enumerator) 000295: DW_AT_name HAL_I2C_STATE_BUSY_RX_LISTEN 0002b2: DW_AT_const_value indirect DW_FORM_data1 0x2a 0002b4: 20 = 0x28 (DW_TAG_enumerator) 0002b5: DW_AT_name HAL_I2C_STATE_ABORT 0002c9: DW_AT_const_value indirect DW_FORM_data1 0x60 0002cb: 20 = 0x28 (DW_TAG_enumerator) 0002cc: DW_AT_name HAL_I2C_STATE_TIMEOUT 0002e2: DW_AT_const_value indirect DW_FORM_data1 0xa0 0002e4: 20 = 0x28 (DW_TAG_enumerator) 0002e5: DW_AT_name HAL_I2C_STATE_ERROR 0002f9: DW_AT_const_value indirect DW_FORM_data1 0xe0 0002fb: 0 null 0002fc: 80 = 0x16 (DW_TAG_typedef) 0002fd: DW_AT_name HAL_I2C_StateTypeDef 000312: DW_AT_type indirect DW_FORM_ref2 0x1e2 000315: DW_AT_decl_file 0x1 000316: DW_AT_decl_line 0x8f 000318: DW_AT_decl_column 0x2 000319: 19 = 0x4 (DW_TAG_enumeration_type) 00031a: DW_AT_sibling 0x374 00031c: DW_AT_byte_size 0x1 00031d: 20 = 0x28 (DW_TAG_enumerator) 00031e: DW_AT_name HAL_I2C_MODE_NONE 000330: DW_AT_const_value indirect DW_FORM_data1 0x0 000332: 20 = 0x28 (DW_TAG_enumerator) 000333: DW_AT_name HAL_I2C_MODE_MASTER 000347: DW_AT_const_value indirect DW_FORM_data1 0x10 000349: 20 = 0x28 (DW_TAG_enumerator) 00034a: DW_AT_name HAL_I2C_MODE_SLAVE 00035d: DW_AT_const_value indirect DW_FORM_data1 0x20 00035f: 20 = 0x28 (DW_TAG_enumerator) 000360: DW_AT_name HAL_I2C_MODE_MEM 000371: DW_AT_const_value indirect DW_FORM_data1 0x40 000373: 0 null 000374: 80 = 0x16 (DW_TAG_typedef) 000375: DW_AT_name HAL_I2C_ModeTypeDef 000389: DW_AT_type indirect DW_FORM_ref2 0x319 00038c: DW_AT_decl_file 0x1 00038d: DW_AT_decl_line 0xae 00038f: DW_AT_decl_column 0x2 000390: 41 = 0x13 (DW_TAG_structure_type) 000391: DW_AT_sibling 0x4b6 000393: DW_AT_name __I2C_HandleTypeDef 0003a7: DW_AT_byte_size 0x4c 0003a8: 30 = 0xd (DW_TAG_member) 0003a9: DW_AT_name Instance 0003b2: DW_AT_type indirect DW_FORM_ref2 0x4b6 0003b5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0003b8: 30 = 0xd (DW_TAG_member) 0003b9: DW_AT_name Init 0003be: DW_AT_type indirect DW_FORM_ref2 0x1cb 0003c1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0003c4: 30 = 0xd (DW_TAG_member) 0003c5: DW_AT_name pBuffPtr 0003ce: DW_AT_type indirect DW_FORM_ref2 0x4bc 0003d1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 0003d4: 30 = 0xd (DW_TAG_member) 0003d5: DW_AT_name XferSize 0003de: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003e3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 0003e6: 30 = 0xd (DW_TAG_member) 0003e7: DW_AT_name XferCount 0003f1: DW_AT_type indirect DW_FORM_ref2 0x4c2 0003f4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 42 } 0003f7: 30 = 0xd (DW_TAG_member) 0003f8: DW_AT_name XferOptions 000404: DW_AT_type indirect DW_FORM_ref2 0x4c8 000407: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 00040a: 30 = 0xd (DW_TAG_member) 00040b: DW_AT_name PreviousState 000419: DW_AT_type indirect DW_FORM_ref2 0x4c8 00041c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 00041f: 78 = 0x15 (DW_TAG_subroutine_type) 000420: DW_AT_sibling 0x438 000422: DW_AT_type indirect DW_FORM_ref_addr 0x148+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 000427: 37 = 0x5 (DW_TAG_formal_parameter) 000428: DW_AT_type indirect DW_FORM_ref2 0x4ce 00042b: 37 = 0x5 (DW_TAG_formal_parameter) 00042c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000431: 37 = 0x5 (DW_TAG_formal_parameter) 000432: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000437: 0 null 000438: 34 = 0xf (DW_TAG_pointer_type) 000439: DW_AT_type indirect DW_FORM_ref2 0x41f 00043c: 30 = 0xd (DW_TAG_member) 00043d: DW_AT_name XferISR 000445: DW_AT_type indirect DW_FORM_ref2 0x438 000448: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 00044b: 30 = 0xd (DW_TAG_member) 00044c: DW_AT_name hdmatx 000453: DW_AT_type indirect DW_FORM_ref2 0x4d2 000456: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 000459: 30 = 0xd (DW_TAG_member) 00045a: DW_AT_name hdmarx 000461: DW_AT_type indirect DW_FORM_ref2 0x4d2 000464: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 60 } 000467: 30 = 0xd (DW_TAG_member) 000468: DW_AT_name Lock 00046d: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 000472: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 64 } 000475: 30 = 0xd (DW_TAG_member) 000476: DW_AT_name State 00047c: DW_AT_type indirect DW_FORM_ref2 0x4d8 00047f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 65 } 000482: 30 = 0xd (DW_TAG_member) 000483: DW_AT_name Mode 000488: DW_AT_type indirect DW_FORM_ref2 0x4dc 00048b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 66 } 00048e: 30 = 0xd (DW_TAG_member) 00048f: DW_AT_name ErrorCode 000499: DW_AT_type indirect DW_FORM_ref2 0x4c8 00049c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 68 } 00049f: 30 = 0xd (DW_TAG_member) 0004a0: DW_AT_name AddrEventCount 0004af: DW_AT_type indirect DW_FORM_ref2 0x4c8 0004b2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 72 } 0004b5: 0 null 0004b6: 34 = 0xf (DW_TAG_pointer_type) 0004b7: DW_AT_type indirect DW_FORM_ref_addr 0x1afa+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 0004bc: 34 = 0xf (DW_TAG_pointer_type) 0004bd: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004c2: 116 = 0x35 (DW_TAG_volatile_type) 0004c3: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004c8: 116 = 0x35 (DW_TAG_volatile_type) 0004c9: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004ce: 34 = 0xf (DW_TAG_pointer_type) 0004cf: DW_AT_type indirect DW_FORM_ref2 0x390 0004d2: 34 = 0xf (DW_TAG_pointer_type) 0004d3: DW_AT_type indirect DW_FORM_ref_addr 0x1a0+__ARM_grp..debug_info$stm32f7xx_hal_dma.h$.2_wD1100_gh0hnOcebnc_s10000 0004d8: 116 = 0x35 (DW_TAG_volatile_type) 0004d9: DW_AT_type indirect DW_FORM_ref2 0x2fc 0004dc: 116 = 0x35 (DW_TAG_volatile_type) 0004dd: DW_AT_type indirect DW_FORM_ref2 0x374 0004e0: 80 = 0x16 (DW_TAG_typedef) 0004e1: DW_AT_name I2C_HandleTypeDef 0004f3: DW_AT_type indirect DW_FORM_ref2 0x390 0004f6: DW_AT_decl_file 0x1 0004f7: DW_AT_decl_line 0xe9 0004f9: DW_AT_decl_column 0x2 0004fa: 0 null 0004fb: 0 padding ** Section #402 '.rel.debug_info' (SHT_REL) Size : 168 bytes (alignment 4) Symbol table #343 '.symtab' 21 relocations applied to section #190 '.debug_info' ** Section #191 '__ARM_grp.stm32f7xx_hal_i2s.h.2_wQ0100_fkUZfwg3SD7_I10000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #192 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 3848 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_I2S_H 00001c: include at line 47 - file 2 00001f: end include 000020: line 155 define HAL_I2S_ERROR_NONE ((uint32_t)0x00000000U) 00004e: line 156 define HAL_I2S_ERROR_TIMEOUT ((uint32_t)0x00000001U) 00007f: line 157 define HAL_I2S_ERROR_OVR ((uint32_t)0x00000002U) 0000ac: line 158 define HAL_I2S_ERROR_UDR ((uint32_t)0x00000004U) 0000d9: line 159 define HAL_I2S_ERROR_DMA ((uint32_t)0x00000008U) 000106: line 160 define HAL_I2S_ERROR_UNKNOW ((uint32_t)0x00000010U) 000136: line 168 define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001U) 000164: line 169 define I2S_CLOCK_PLL ((uint32_t)0x00000002U) 00018d: line 177 define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000U) 0001ba: line 178 define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100U) 0001e7: line 179 define I2S_MODE_MASTER_TX ((uint32_t)0x00000200U) 000215: line 180 define I2S_MODE_MASTER_RX ((uint32_t)0x00000300U) 000243: line 188 define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000U) 000273: line 189 define I2S_STANDARD_MSB ((uint32_t)0x00000010U) 00029f: line 190 define I2S_STANDARD_LSB ((uint32_t)0x00000020U) 0002cb: line 191 define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030U) 0002fd: line 192 define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0U) 00032e: line 200 define I2S_DATAFORMAT_16B ((uint32_t)0x00000000U) 00035c: line 201 define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001U) 000393: line 202 define I2S_DATAFORMAT_24B ((uint32_t)0x00000003U) 0003c1: line 203 define I2S_DATAFORMAT_32B ((uint32_t)0x00000005U) 0003ef: line 211 define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE) 000424: line 212 define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000U) 000456: line 220 define I2S_AUDIOFREQ_192K ((uint32_t)192000U) 000480: line 221 define I2S_AUDIOFREQ_96K ((uint32_t)96000U) 0004a8: line 222 define I2S_AUDIOFREQ_48K ((uint32_t)48000U) 0004d0: line 223 define I2S_AUDIOFREQ_44K ((uint32_t)44100U) 0004f8: line 224 define I2S_AUDIOFREQ_32K ((uint32_t)32000U) 000520: line 225 define I2S_AUDIOFREQ_22K ((uint32_t)22050U) 000548: line 226 define I2S_AUDIOFREQ_16K ((uint32_t)16000U) 000570: line 227 define I2S_AUDIOFREQ_11K ((uint32_t)11025U) 000598: line 228 define I2S_AUDIOFREQ_8K ((uint32_t)8000U) 0005be: line 229 define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2U) 0005e6: line 238 define I2S_CPOL_LOW ((uint32_t)0x00000000U) 00060e: line 239 define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL) 00063d: line 247 define I2S_IT_TXE SPI_CR2_TXEIE 000659: line 248 define I2S_IT_RXNE SPI_CR2_RXNEIE 000677: line 249 define I2S_IT_ERR SPI_CR2_ERRIE 000693: line 257 define I2S_FLAG_TXE SPI_SR_TXE 0006ae: line 258 define I2S_FLAG_RXNE SPI_SR_RXNE 0006cb: line 260 define I2S_FLAG_UDR SPI_SR_UDR 0006e6: line 261 define I2S_FLAG_OVR SPI_SR_OVR 000701: line 262 define I2S_FLAG_FRE SPI_SR_FRE 00071c: line 264 define I2S_FLAG_CHSIDE SPI_SR_CHSIDE 00073d: line 265 define I2S_FLAG_BSY SPI_SR_BSY 000758: line 283 define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET) 0007b0: line 289 define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE) 000806: line 290 define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= ~SPI_I2SCFGR_I2SE) 00085e: line 301 define __HAL_I2S_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__)) 0008c0: line 302 define __HAL_I2S_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= ~(__INTERRUPT__)) 000924: line 314 define __HAL_I2S_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 0009ae: line 329 define __HAL_I2S_GET_FLAG(__HANDLE__,__FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 000a15: line 335 define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ __IO uint32_t tmpreg; tmpreg = (__HANDLE__)->Instance->DR; tmpreg = (__HANDLE__)->Instance->SR; UNUSED(tmpreg); } while(0) 000abb: line 347 define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{ __IO uint32_t tmpreg; tmpreg = (__HANDLE__)->Instance->SR; UNUSED(tmpreg); } while(0) 000b3c: line 436 define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || ((CLOCK) == I2S_CLOCK_PLL)) 000b99: line 439 define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || ((MODE) == I2S_MODE_SLAVE_RX) || ((MODE) == I2S_MODE_MASTER_TX)|| ((MODE) == I2S_MODE_MASTER_RX)) 000c32: line 444 define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || ((STANDARD) == I2S_STANDARD_MSB) || ((STANDARD) == I2S_STANDARD_LSB) || ((STANDARD) == I2S_STANDARD_PCM_SHORT) || ((STANDARD) == I2S_STANDARD_PCM_LONG)) 000d11: line 450 define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || ((FORMAT) == I2S_DATAFORMAT_24B) || ((FORMAT) == I2S_DATAFORMAT_32B)) 000dc7: line 455 define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE)) 000e33: line 458 define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && ((FREQ) <= I2S_AUDIOFREQ_192K)) || ((FREQ) == I2S_AUDIOFREQ_DEFAULT)) 000eb6: line 462 define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || ((CPOL) == I2S_CPOL_HIGH)) 000f03: end include 000f04: end of translation unit ** Section #193 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 120 bytes 000000: Header: length 116 (not including this field) version 3 prologue length 107 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_i2s.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 69 32 73 2e 68 00 01 00 00 00005d: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000074: file "" : 00 000075: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2s.h:1.0 ** Section #194 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 936 bytes 000000: Header: size 0x3a4 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2s.h 000049: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000090: DW_AT_language DW_LANG_C89 000092: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 000109: DW_AT_macro_info 0x0 00010d: DW_AT_stmt_list 0x0 000111: 42 = 0x13 (DW_TAG_structure_type) 000112: DW_AT_sibling 0x194 000114: DW_AT_byte_size 0x1c 000115: 30 = 0xd (DW_TAG_member) 000116: DW_AT_name Mode 00011b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000120: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000123: 30 = 0xd (DW_TAG_member) 000124: DW_AT_name Standard 00012d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000132: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000135: 30 = 0xd (DW_TAG_member) 000136: DW_AT_name DataFormat 000141: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000146: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000149: 30 = 0xd (DW_TAG_member) 00014a: DW_AT_name MCLKOutput 000155: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00015a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00015d: 30 = 0xd (DW_TAG_member) 00015e: DW_AT_name AudioFreq 000168: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00016d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000170: 30 = 0xd (DW_TAG_member) 000171: DW_AT_name CPOL 000176: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00017b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 00017e: 30 = 0xd (DW_TAG_member) 00017f: DW_AT_name ClockSource 00018b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000190: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 000193: 0 null 000194: 80 = 0x16 (DW_TAG_typedef) 000195: DW_AT_name I2S_InitTypeDef 0001a5: DW_AT_type indirect DW_FORM_ref2 0x111 0001a8: DW_AT_decl_file 0x1 0001a9: DW_AT_decl_line 0x57 0001aa: DW_AT_decl_column 0x2 0001ab: 19 = 0x4 (DW_TAG_enumeration_type) 0001ac: DW_AT_sibling 0x272 0001ae: DW_AT_byte_size 0x1 0001af: 20 = 0x28 (DW_TAG_enumerator) 0001b0: DW_AT_name HAL_I2S_STATE_RESET 0001c4: DW_AT_const_value indirect DW_FORM_data1 0x0 0001c6: 20 = 0x28 (DW_TAG_enumerator) 0001c7: DW_AT_name HAL_I2S_STATE_READY 0001db: DW_AT_const_value indirect DW_FORM_data1 0x1 0001dd: 20 = 0x28 (DW_TAG_enumerator) 0001de: DW_AT_name HAL_I2S_STATE_BUSY 0001f1: DW_AT_const_value indirect DW_FORM_data1 0x2 0001f3: 20 = 0x28 (DW_TAG_enumerator) 0001f4: DW_AT_name HAL_I2S_STATE_BUSY_TX 00020a: DW_AT_const_value indirect DW_FORM_data1 0x3 00020c: 20 = 0x28 (DW_TAG_enumerator) 00020d: DW_AT_name HAL_I2S_STATE_BUSY_RX 000223: DW_AT_const_value indirect DW_FORM_data1 0x4 000225: 20 = 0x28 (DW_TAG_enumerator) 000226: DW_AT_name HAL_I2S_STATE_BUSY_TX_RX 00023f: DW_AT_const_value indirect DW_FORM_data1 0x5 000241: 20 = 0x28 (DW_TAG_enumerator) 000242: DW_AT_name HAL_I2S_STATE_TIMEOUT 000258: DW_AT_const_value indirect DW_FORM_data1 0x6 00025a: 20 = 0x28 (DW_TAG_enumerator) 00025b: DW_AT_name HAL_I2S_STATE_ERROR 00026f: DW_AT_const_value indirect DW_FORM_data1 0x7 000271: 0 null 000272: 80 = 0x16 (DW_TAG_typedef) 000273: DW_AT_name HAL_I2S_StateTypeDef 000288: DW_AT_type indirect DW_FORM_ref2 0x1ab 00028b: DW_AT_decl_file 0x1 00028c: DW_AT_decl_line 0x67 00028d: DW_AT_decl_column 0x2 00028e: 42 = 0x13 (DW_TAG_structure_type) 00028f: DW_AT_sibling 0x363 000291: DW_AT_byte_size 0x40 000292: 30 = 0xd (DW_TAG_member) 000293: DW_AT_name Instance 00029c: DW_AT_type indirect DW_FORM_ref2 0x363 00029f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0002a2: 30 = 0xd (DW_TAG_member) 0002a3: DW_AT_name Init 0002a8: DW_AT_type indirect DW_FORM_ref2 0x194 0002ab: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0002ae: 30 = 0xd (DW_TAG_member) 0002af: DW_AT_name pTxBuffPtr 0002ba: DW_AT_type indirect DW_FORM_ref2 0x369 0002bd: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 0002c0: 30 = 0xd (DW_TAG_member) 0002c1: DW_AT_name TxXferSize 0002cc: DW_AT_type indirect DW_FORM_ref2 0x36f 0002cf: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 0002d2: 30 = 0xd (DW_TAG_member) 0002d3: DW_AT_name TxXferCount 0002df: DW_AT_type indirect DW_FORM_ref2 0x36f 0002e2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 38 } 0002e5: 30 = 0xd (DW_TAG_member) 0002e6: DW_AT_name pRxBuffPtr 0002f1: DW_AT_type indirect DW_FORM_ref2 0x369 0002f4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 0002f7: 30 = 0xd (DW_TAG_member) 0002f8: DW_AT_name RxXferSize 000303: DW_AT_type indirect DW_FORM_ref2 0x36f 000306: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 000309: 30 = 0xd (DW_TAG_member) 00030a: DW_AT_name RxXferCount 000316: DW_AT_type indirect DW_FORM_ref2 0x36f 000319: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 46 } 00031c: 30 = 0xd (DW_TAG_member) 00031d: DW_AT_name hdmatx 000324: DW_AT_type indirect DW_FORM_ref2 0x375 000327: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 00032a: 30 = 0xd (DW_TAG_member) 00032b: DW_AT_name hdmarx 000332: DW_AT_type indirect DW_FORM_ref2 0x375 000335: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 000338: 30 = 0xd (DW_TAG_member) 000339: DW_AT_name Lock 00033e: DW_AT_type indirect DW_FORM_ref2 0x37b 000341: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 000344: 30 = 0xd (DW_TAG_member) 000345: DW_AT_name State 00034b: DW_AT_type indirect DW_FORM_ref2 0x381 00034e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 57 } 000351: 30 = 0xd (DW_TAG_member) 000352: DW_AT_name ErrorCode 00035c: DW_AT_type indirect DW_FORM_ref2 0x385 00035f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 60 } 000362: 0 null 000363: 34 = 0xf (DW_TAG_pointer_type) 000364: DW_AT_type indirect DW_FORM_ref_addr 0x25a3+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 000369: 34 = 0xf (DW_TAG_pointer_type) 00036a: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00036f: 116 = 0x35 (DW_TAG_volatile_type) 000370: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000375: 34 = 0xf (DW_TAG_pointer_type) 000376: DW_AT_type indirect DW_FORM_ref_addr 0x1a0+__ARM_grp..debug_info$stm32f7xx_hal_dma.h$.2_wD1100_gh0hnOcebnc_s10000 00037b: 116 = 0x35 (DW_TAG_volatile_type) 00037c: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 000381: 116 = 0x35 (DW_TAG_volatile_type) 000382: DW_AT_type indirect DW_FORM_ref2 0x272 000385: 116 = 0x35 (DW_TAG_volatile_type) 000386: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00038b: 80 = 0x16 (DW_TAG_typedef) 00038c: DW_AT_name I2S_HandleTypeDef 00039e: DW_AT_type indirect DW_FORM_ref2 0x28e 0003a1: DW_AT_decl_file 0x1 0003a2: DW_AT_decl_line 0x8d 0003a4: DW_AT_decl_column 0x2 0003a5: 0 null 0003a6: 0 padding 0003a7: 0 padding ** Section #403 '.rel.debug_info' (SHT_REL) Size : 128 bytes (alignment 4) Symbol table #343 '.symtab' 16 relocations applied to section #194 '.debug_info' ** Section #195 '__ARM_grp.stm32f7xx_hal_iwdg.h.2_cPX000_D7cU_o0Pih8_c10000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #196 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 1356 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_IWDG_H 00001d: include at line 47 - file 2 000020: end include 000021: line 101 define IWDG_PRESCALER_4 0x00000000u 000040: line 102 define IWDG_PRESCALER_8 IWDG_PR_PR_0 000060: line 103 define IWDG_PRESCALER_16 IWDG_PR_PR_1 000081: line 104 define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) 0000b3: line 105 define IWDG_PRESCALER_64 IWDG_PR_PR_2 0000d4: line 106 define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) 000107: line 107 define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) 00013a: line 115 define IWDG_WINDOW_DISABLE IWDG_WINR_WIN 00015e: line 134 define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE) 0001b5: line 142 define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD) 000215: line 183 define IWDG_KEY_RELOAD 0x0000AAAAu 000234: line 184 define IWDG_KEY_ENABLE 0x0000CCCCu 000253: line 185 define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u 00027f: line 186 define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u 0002ac: line 202 define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE) 000318: line 209 define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE) 000386: line 216 define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || ((__PRESCALER__) == IWDG_PRESCALER_8) || ((__PRESCALER__) == IWDG_PRESCALER_16) || ((__PRESCALER__) == IWDG_PRESCALER_32) || ((__PRESCALER__) == IWDG_PRESCALER_64) || ((__PRESCALER__) == IWDG_PRESCALER_128)|| ((__PRESCALER__) == IWDG_PRESCALER_256)) 0004ce: line 229 define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL) 00050a: line 236 define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN) 000548: end include 000549: end of translation unit ** Section #197 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 124 bytes 000000: Header: length 120 (not including this field) version 3 prologue length 108 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_iwdg.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 69 77 64 67 2e 68 00 01 00 00 00005e: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000075: file "" : 00 000076: DW_LNS_negate_stmt : 06 000077: DW_LNS_negate_stmt : 06 000078: DW_LNS_negate_stmt : 06 000079: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_iwdg.h:1.0 [ ** Section #198 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 424 bytes 000000: Header: size 0x1a4 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_iwdg.h 00004a: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000091: DW_AT_language DW_LANG_C89 000093: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010a: DW_AT_macro_info 0x0 00010e: DW_AT_stmt_list 0x0 000112: 42 = 0x13 (DW_TAG_structure_type) 000113: DW_AT_sibling 0x14a 000115: DW_AT_byte_size 0xc 000116: 30 = 0xd (DW_TAG_member) 000117: DW_AT_name Prescaler 000121: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000126: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000129: 30 = 0xd (DW_TAG_member) 00012a: DW_AT_name Reload 000131: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000136: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000139: 30 = 0xd (DW_TAG_member) 00013a: DW_AT_name Window 000141: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000146: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000149: 0 null 00014a: 80 = 0x16 (DW_TAG_typedef) 00014b: DW_AT_name IWDG_InitTypeDef 00015c: DW_AT_type indirect DW_FORM_ref2 0x112 00015f: DW_AT_decl_file 0x1 000160: DW_AT_decl_line 0x4c 000161: DW_AT_decl_column 0x3 000162: 42 = 0x13 (DW_TAG_structure_type) 000163: DW_AT_sibling 0x183 000165: DW_AT_byte_size 0x10 000166: 30 = 0xd (DW_TAG_member) 000167: DW_AT_name Instance 000170: DW_AT_type indirect DW_FORM_ref2 0x183 000173: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000176: 30 = 0xd (DW_TAG_member) 000177: DW_AT_name Init 00017c: DW_AT_type indirect DW_FORM_ref2 0x14a 00017f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000182: 0 null 000183: 34 = 0xf (DW_TAG_pointer_type) 000184: DW_AT_type indirect DW_FORM_ref_addr 0x1b48+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 000189: 80 = 0x16 (DW_TAG_typedef) 00018a: DW_AT_name IWDG_HandleTypeDef 00019d: DW_AT_type indirect DW_FORM_ref2 0x162 0001a0: DW_AT_decl_file 0x1 0001a1: DW_AT_decl_line 0x57 0001a2: DW_AT_decl_column 0x2 0001a3: 0 null 0001a4: 0 padding 0001a5: 0 padding 0001a6: 0 padding 0001a7: 0 padding ** Section #404 '.rel.debug_info' (SHT_REL) Size : 56 bytes (alignment 4) Symbol table #343 '.symtab' 7 relocations applied to section #198 '.debug_info' ** Section #199 '__ARM_grp.stm32f7xx_hal_lptim.h.2_sr$000_kXHxATbBSqb_o10000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #200 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 7788 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_LPTIM_H 00001e: include at line 47 - file 2 000021: end include 000022: line 66 define LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR23) 000060: line 184 define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00U) 000096: line 185 define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL 0000c3: line 193 define LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000U) 0000f1: line 194 define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 00011c: line 195 define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 000147: line 196 define LPTIM_PRESCALER_DIV8 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)) 000195: line 197 define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 0001c1: line 198 define LPTIM_PRESCALER_DIV32 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)) 000210: line 199 define LPTIM_PRESCALER_DIV64 ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)) 00025f: line 200 define LPTIM_PRESCALER_DIV128 ((uint32_t)LPTIM_CFGR_PRESC) 000296: line 209 define LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000U) 0002cb: line 210 define LPTIM_OUTPUTPOLARITY_LOW (LPTIM_CFGR_WAVPOL) 0002fb: line 218 define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U) 00033d: line 219 define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0 000376: line 220 define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1 0003af: line 221 define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT 0003e6: line 230 define LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000U) 00041c: line 231 define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0 00044e: line 232 define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 000487: line 240 define LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFFU) 0004bc: line 241 define LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000U) 0004ea: line 242 define LPTIM_TRIGSOURCE_1 ((uint32_t)LPTIM_CFGR_TRIGSEL_0) 000521: line 243 define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1 00054c: line 244 define LPTIM_TRIGSOURCE_3 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1) 00059a: line 245 define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2 0005c5: line 246 define LPTIM_TRIGSOURCE_5 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2) 000613: line 254 define LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0 000642: line 255 define LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1 000672: line 256 define LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN 0006a7: line 264 define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U) 0006e8: line 265 define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0 000721: line 266 define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1 00075a: line 267 define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT 000791: line 276 define LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000U) 0007c3: line 277 define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD 0007f2: line 286 define LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000U) 00082a: line 287 define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE 00085f: line 296 define LPTIM_FLAG_DOWN LPTIM_ISR_DOWN 000881: line 297 define LPTIM_FLAG_UP LPTIM_ISR_UP 00089f: line 298 define LPTIM_FLAG_ARROK LPTIM_ISR_ARROK 0008c3: line 299 define LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK 0008e7: line 300 define LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG 00090f: line 301 define LPTIM_FLAG_ARRM LPTIM_ISR_ARRM 000931: line 302 define LPTIM_FLAG_CMPM LPTIM_ISR_CMPM 000953: line 311 define LPTIM_IT_DOWN LPTIM_IER_DOWNIE 000975: line 312 define LPTIM_IT_UP LPTIM_IER_UPIE 000993: line 313 define LPTIM_IT_ARROK LPTIM_IER_ARROKIE 0009b7: line 314 define LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE 0009db: line 315 define LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE 000a03: line 316 define LPTIM_IT_ARRM LPTIM_IER_ARRMIE 000a25: line 317 define LPTIM_IT_CMPM LPTIM_IER_CMPMIE 000a47: line 335 define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET) 000aa3: line 342 define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE)) 000af7: line 343 define __HAL_LPTIM_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(LPTIM_CR_ENABLE)) 000b4d: line 350 define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT) 000baa: line 351 define __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT) 000c03: line 360 define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__,__VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__)) 000c63: line 368 define __HAL_LPTIM_COMPARE_SET(__HANDLE__,__VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__)) 000cc0: line 384 define __HAL_LPTIM_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__)) 000d27: line 400 define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) 000d81: line 416 define __HAL_LPTIM_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) 000de5: line 432 define __HAL_LPTIM_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) 000e4d: line 449 define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 000ed9: line 455 define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) 000f36: line 461 define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) 000f97: line 467 define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) 000ff7: line 473 define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) 00105b: line 479 define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) 0010c3: line 485 define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) 00112f: line 491 define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) 001196: line 497 define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) 001201: line 503 define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); }while(0) 0012b2: line 512 define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE(); __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); }while(0) 001366: line 520 define __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) 0013c0: line 526 define __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) 00141c: line 532 define __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) 00147f: line 656 define IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)) 001507: line 659 define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_PRESCALER_DIV1 ) || ((__PRESCALER__) == LPTIM_PRESCALER_DIV2 ) || ((__PRESCALER__) == LPTIM_PRESCALER_DIV4 ) || ((__PRESCALER__) == LPTIM_PRESCALER_DIV8 ) || ((__PRESCALER__) == LPTIM_PRESCALER_DIV16 ) || ((__PRESCALER__) == LPTIM_PRESCALER_DIV32 ) || ((__PRESCALER__) == LPTIM_PRESCALER_DIV64 ) || ((__PRESCALER__) == LPTIM_PRESCALER_DIV128)) 0016a5: line 667 define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1) 0016fe: line 669 define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH)) 001789: line 672 define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS) || ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS) || ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS)) 0018aa: line 677 define IS_LPTIM_CLOCK_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING) || ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING)) 001971: line 681 define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || ((__TRIG__) == LPTIM_TRIGSOURCE_0) || ((__TRIG__) == LPTIM_TRIGSOURCE_1) || ((__TRIG__) == LPTIM_TRIGSOURCE_2) || ((__TRIG__) == LPTIM_TRIGSOURCE_3) || ((__TRIG__) == LPTIM_TRIGSOURCE_4) || ((__TRIG__) == LPTIM_TRIGSOURCE_5)) 001aa2: line 689 define IS_LPTIM_EXT_TRG_POLARITY(__POLAR__) (((__POLAR__) == LPTIM_ACTIVEEDGE_RISING ) || ((__POLAR__) == LPTIM_ACTIVEEDGE_FALLING ) || ((__POLAR__) == LPTIM_ACTIVEEDGE_RISING_FALLING )) 001b59: line 693 define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS ) || ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS ) || ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS )) 001c78: line 698 define IS_LPTIM_UPDATE_MODE(__MODE__) (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD)) 001cef: line 701 define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL)) 001d79: line 704 define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFU) 001dc2: line 706 define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFU) 001e02: line 708 define IS_LPTIM_PERIOD(PERIOD) ((PERIOD) <= 0x0000FFFFU) 001e37: line 710 define IS_LPTIM_PULSE(PULSE) ((PULSE) <= 0x0000FFFFU) 001e69: end include 001e6a: end of translation unit ** Section #201 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 124 bytes 000000: Header: length 120 (not including this field) version 3 prologue length 109 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_lptim.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 6c 70 74 69 6d 2e 68 00 01 00 00 00005f: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000076: file "" : 00 000077: DW_LNS_negate_stmt : 06 000078: DW_LNS_negate_stmt : 06 000079: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_lptim.h:1.0 ** Section #202 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 976 bytes 000000: Header: size 0x3cc bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_lptim.h 00004b: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000092: DW_AT_language DW_LANG_C89 000094: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010b: DW_AT_macro_info 0x0 00010f: DW_AT_stmt_list 0x0 000113: 42 = 0x13 (DW_TAG_structure_type) 000114: DW_AT_sibling 0x13b 000116: DW_AT_byte_size 0x8 000117: 30 = 0xd (DW_TAG_member) 000118: DW_AT_name Source 00011f: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000124: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000127: 30 = 0xd (DW_TAG_member) 000128: DW_AT_name Prescaler 000132: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000137: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00013a: 0 null 00013b: 80 = 0x16 (DW_TAG_typedef) 00013c: DW_AT_name LPTIM_ClockConfigTypeDef 000155: DW_AT_type indirect DW_FORM_ref2 0x113 000158: DW_AT_decl_file 0x1 000159: DW_AT_decl_line 0x52 00015a: DW_AT_decl_column 0x2 00015b: 42 = 0x13 (DW_TAG_structure_type) 00015c: DW_AT_sibling 0x186 00015e: DW_AT_byte_size 0x8 00015f: 30 = 0xd (DW_TAG_member) 000160: DW_AT_name Polarity 000169: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00016e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000171: 30 = 0xd (DW_TAG_member) 000172: DW_AT_name SampleTime 00017d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000182: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000185: 0 null 000186: 80 = 0x16 (DW_TAG_typedef) 000187: DW_AT_name LPTIM_ULPClockConfigTypeDef 0001a3: DW_AT_type indirect DW_FORM_ref2 0x15b 0001a6: DW_AT_decl_file 0x1 0001a7: DW_AT_decl_line 0x64 0001a8: DW_AT_decl_column 0x2 0001a9: 42 = 0x13 (DW_TAG_structure_type) 0001aa: DW_AT_sibling 0x1e6 0001ac: DW_AT_byte_size 0xc 0001ad: 30 = 0xd (DW_TAG_member) 0001ae: DW_AT_name Source 0001b5: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001ba: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0001bd: 30 = 0xd (DW_TAG_member) 0001be: DW_AT_name ActiveEdge 0001c9: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001ce: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0001d1: 30 = 0xd (DW_TAG_member) 0001d2: DW_AT_name SampleTime 0001dd: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001e2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0001e5: 0 null 0001e6: 80 = 0x16 (DW_TAG_typedef) 0001e7: DW_AT_name LPTIM_TriggerConfigTypeDef 000202: DW_AT_type indirect DW_FORM_ref2 0x1a9 000205: DW_AT_decl_file 0x1 000206: DW_AT_decl_line 0x75 000207: DW_AT_decl_column 0x2 000208: 42 = 0x13 (DW_TAG_structure_type) 000209: DW_AT_sibling 0x286 00020b: DW_AT_byte_size 0x28 00020c: 30 = 0xd (DW_TAG_member) 00020d: DW_AT_name Clock 000213: DW_AT_type indirect DW_FORM_ref2 0x13b 000216: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000219: 30 = 0xd (DW_TAG_member) 00021a: DW_AT_name UltraLowPowerClock 00022d: DW_AT_type indirect DW_FORM_ref2 0x186 000230: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000233: 30 = 0xd (DW_TAG_member) 000234: DW_AT_name Trigger 00023c: DW_AT_type indirect DW_FORM_ref2 0x1e6 00023f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000242: 30 = 0xd (DW_TAG_member) 000243: DW_AT_name OutputPolarity 000252: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000257: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 00025a: 30 = 0xd (DW_TAG_member) 00025b: DW_AT_name UpdateMode 000266: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00026b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 00026e: 30 = 0xd (DW_TAG_member) 00026f: DW_AT_name CounterSource 00027d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000282: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 000285: 0 null 000286: 80 = 0x16 (DW_TAG_typedef) 000287: DW_AT_name LPTIM_InitTypeDef 000299: DW_AT_type indirect DW_FORM_ref2 0x208 00029c: DW_AT_decl_file 0x1 00029d: DW_AT_decl_line 0x8d 00029f: DW_AT_decl_column 0x2 0002a0: 18 = 0x4 (DW_TAG_enumeration_type) 0002a1: DW_AT_sibling 0x33c 0002a3: DW_AT_name __HAL_LPTIM_StateTypeDef 0002bc: DW_AT_byte_size 0x1 0002bd: 20 = 0x28 (DW_TAG_enumerator) 0002be: DW_AT_name HAL_LPTIM_STATE_RESET 0002d4: DW_AT_const_value indirect DW_FORM_data1 0x0 0002d6: 20 = 0x28 (DW_TAG_enumerator) 0002d7: DW_AT_name HAL_LPTIM_STATE_READY 0002ed: DW_AT_const_value indirect DW_FORM_data1 0x1 0002ef: 20 = 0x28 (DW_TAG_enumerator) 0002f0: DW_AT_name HAL_LPTIM_STATE_BUSY 000305: DW_AT_const_value indirect DW_FORM_data1 0x2 000307: 20 = 0x28 (DW_TAG_enumerator) 000308: DW_AT_name HAL_LPTIM_STATE_TIMEOUT 000320: DW_AT_const_value indirect DW_FORM_data1 0x3 000322: 20 = 0x28 (DW_TAG_enumerator) 000323: DW_AT_name HAL_LPTIM_STATE_ERROR 000339: DW_AT_const_value indirect DW_FORM_data1 0x4 00033b: 0 null 00033c: 80 = 0x16 (DW_TAG_typedef) 00033d: DW_AT_name HAL_LPTIM_StateTypeDef 000354: DW_AT_type indirect DW_FORM_ref2 0x2a0 000357: DW_AT_decl_file 0x1 000358: DW_AT_decl_line 0x99 00035a: DW_AT_decl_column 0x2 00035b: 42 = 0x13 (DW_TAG_structure_type) 00035c: DW_AT_sibling 0x3a7 00035e: DW_AT_byte_size 0x30 00035f: 30 = 0xd (DW_TAG_member) 000360: DW_AT_name Instance 000369: DW_AT_type indirect DW_FORM_ref2 0x3a7 00036c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00036f: 30 = 0xd (DW_TAG_member) 000370: DW_AT_name Init 000375: DW_AT_type indirect DW_FORM_ref2 0x286 000378: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00037b: 30 = 0xd (DW_TAG_member) 00037c: DW_AT_name Status 000383: DW_AT_type indirect DW_FORM_ref_addr 0x148+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 000388: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 00038b: 30 = 0xd (DW_TAG_member) 00038c: DW_AT_name Lock 000391: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 000396: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 45 } 000399: 30 = 0xd (DW_TAG_member) 00039a: DW_AT_name State 0003a0: DW_AT_type indirect DW_FORM_ref2 0x3ad 0003a3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 46 } 0003a6: 0 null 0003a7: 34 = 0xf (DW_TAG_pointer_type) 0003a8: DW_AT_type indirect DW_FORM_ref_addr 0x2807+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 0003ad: 116 = 0x35 (DW_TAG_volatile_type) 0003ae: DW_AT_type indirect DW_FORM_ref2 0x33c 0003b1: 80 = 0x16 (DW_TAG_typedef) 0003b2: DW_AT_name LPTIM_HandleTypeDef 0003c6: DW_AT_type indirect DW_FORM_ref2 0x35b 0003c9: DW_AT_decl_file 0x1 0003ca: DW_AT_decl_line 0xaa 0003cc: DW_AT_decl_column 0x2 0003cd: 0 null 0003ce: 0 padding 0003cf: 0 padding ** Section #405 '.rel.debug_info' (SHT_REL) Size : 128 bytes (alignment 4) Symbol table #343 '.symtab' 16 relocations applied to section #202 '.debug_info' ** Section #203 '__ARM_grp.stm32f7xx_hal_ltdc.h.2_wm_000_Ywckgy$Kbs4_G10000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #204 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 5432 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_LTDC_H 00001d: include at line 49 - file 2 000020: end include 000021: line 65 define MAX_LAYER 2 00002f: line 213 define HAL_LTDC_ERROR_NONE ((uint32_t)0x00000000U) 00005e: line 214 define HAL_LTDC_ERROR_TE ((uint32_t)0x00000001U) 00008b: line 215 define HAL_LTDC_ERROR_FU ((uint32_t)0x00000002U) 0000b8: line 216 define HAL_LTDC_ERROR_TIMEOUT ((uint32_t)0x00000020U) 0000ea: line 224 define LTDC_HSPOLARITY_AL ((uint32_t)0x00000000U) 000118: line 225 define LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL 00013d: line 233 define LTDC_VSPOLARITY_AL ((uint32_t)0x00000000U) 00016b: line 234 define LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL 000190: line 242 define LTDC_DEPOLARITY_AL ((uint32_t)0x00000000U) 0001be: line 243 define LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL 0001e3: line 251 define LTDC_PCPOLARITY_IPC ((uint32_t)0x00000000U) 000212: line 252 define LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL 000239: line 260 define LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16) 000266: line 261 define LTDC_VERTICALSYNC LTDC_SSCR_VSH 000289: line 269 define LTDC_COLOR ((uint32_t)0x000000FFU) 0002af: line 277 define LTDC_BLENDING_FACTOR1_CA ((uint32_t)0x00000400U) 0002e3: line 278 define LTDC_BLENDING_FACTOR1_PAxCA ((uint32_t)0x00000600U) 00031a: line 286 define LTDC_BLENDING_FACTOR2_CA ((uint32_t)0x00000005U) 00034e: line 287 define LTDC_BLENDING_FACTOR2_PAxCA ((uint32_t)0x00000007U) 000385: line 295 define LTDC_PIXEL_FORMAT_ARGB8888 ((uint32_t)0x00000000U) 0003bb: line 296 define LTDC_PIXEL_FORMAT_RGB888 ((uint32_t)0x00000001U) 0003ef: line 297 define LTDC_PIXEL_FORMAT_RGB565 ((uint32_t)0x00000002U) 000423: line 298 define LTDC_PIXEL_FORMAT_ARGB1555 ((uint32_t)0x00000003U) 000459: line 299 define LTDC_PIXEL_FORMAT_ARGB4444 ((uint32_t)0x00000004U) 00048f: line 300 define LTDC_PIXEL_FORMAT_L8 ((uint32_t)0x00000005U) 0004bf: line 301 define LTDC_PIXEL_FORMAT_AL44 ((uint32_t)0x00000006U) 0004f1: line 302 define LTDC_PIXEL_FORMAT_AL88 ((uint32_t)0x00000007U) 000523: line 310 define LTDC_ALPHA LTDC_LxCACR_CONSTA 000544: line 318 define LTDC_STOPPOSITION (LTDC_LxWHPCR_WHSPPOS >> 16) 000576: line 319 define LTDC_STARTPOSITION LTDC_LxWHPCR_WHSTPOS 0005a1: line 321 define LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL 0005cf: line 322 define LTDC_LINE_NUMBER LTDC_LxCFBLNR_CFBLNBR 0005f9: line 330 define LTDC_IT_LI LTDC_IER_LIE 000614: line 331 define LTDC_IT_FU LTDC_IER_FUIE 000630: line 332 define LTDC_IT_TE LTDC_IER_TERRIE 00064e: line 333 define LTDC_IT_RR LTDC_IER_RRIE 00066a: line 341 define LTDC_FLAG_LI LTDC_ISR_LIF 000687: line 342 define LTDC_FLAG_FU LTDC_ISR_FUIF 0006a5: line 343 define LTDC_FLAG_TE LTDC_ISR_TERRIF 0006c5: line 344 define LTDC_FLAG_RR LTDC_ISR_RRIF 0006e3: line 352 define LTDC_RELOAD_IMMEDIATE LTDC_SRCR_IMR 00070a: line 353 define LTDC_RELOAD_VERTICAL_BLANKING LTDC_SRCR_VBR 000739: line 371 define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET) 000793: line 378 define __HAL_LTDC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN) 0007e5: line 385 define __HAL_LTDC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN)) 00083b: line 394 define __HAL_LTDC_LAYER_ENABLE(__HANDLE__,__LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN) 0008b5: line 403 define __HAL_LTDC_LAYER_DISABLE(__HANDLE__,__LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN) 000931: line 410 define __HAL_LTDC_RELOAD_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR) 000989: line 424 define __HAL_LTDC_GET_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) 0009e0: line 437 define __HAL_LTDC_CLEAR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) 000a39: line 450 define __HAL_LTDC_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) 000a9c: line 463 define __HAL_LTDC_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__)) 000b01: line 476 define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->ISR & (__INTERRUPT__)) 000b67: line 596 define LTDC_LAYER(__HANDLE__,__LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84 + (0x80*(__LAYER__))))) 000bf2: line 597 define IS_LTDC_LAYER(LAYER) ((LAYER) <= MAX_LAYER) 000c21: line 598 define IS_LTDC_HSPOL(HSPOL) (((HSPOL) == LTDC_HSPOLARITY_AL) || ((HSPOL) == LTDC_HSPOLARITY_AH)) 000c7e: line 600 define IS_LTDC_VSPOL(VSPOL) (((VSPOL) == LTDC_VSPOLARITY_AL) || ((VSPOL) == LTDC_VSPOLARITY_AH)) 000cdb: line 602 define IS_LTDC_DEPOL(DEPOL) (((DEPOL) == LTDC_DEPOLARITY_AL) || ((DEPOL) == LTDC_DEPOLARITY_AH)) 000d38: line 604 define IS_LTDC_PCPOL(PCPOL) (((PCPOL) == LTDC_PCPOLARITY_IPC) || ((PCPOL) == LTDC_PCPOLARITY_IIPC)) 000d98: line 606 define IS_LTDC_HSYNC(HSYNC) ((HSYNC) <= LTDC_HORIZONTALSYNC) 000dd1: line 607 define IS_LTDC_VSYNC(VSYNC) ((VSYNC) <= LTDC_VERTICALSYNC) 000e08: line 608 define IS_LTDC_AHBP(AHBP) ((AHBP) <= LTDC_HORIZONTALSYNC) 000e3e: line 609 define IS_LTDC_AVBP(AVBP) ((AVBP) <= LTDC_VERTICALSYNC) 000e72: line 610 define IS_LTDC_AAW(AAW) ((AAW) <= LTDC_HORIZONTALSYNC) 000ea5: line 611 define IS_LTDC_AAH(AAH) ((AAH) <= LTDC_VERTICALSYNC) 000ed6: line 612 define IS_LTDC_TOTALW(TOTALW) ((TOTALW) <= LTDC_HORIZONTALSYNC) 000f12: line 613 define IS_LTDC_TOTALH(TOTALH) ((TOTALH) <= LTDC_VERTICALSYNC) 000f4c: line 614 define IS_LTDC_BLUEVALUE(BBLUE) ((BBLUE) <= LTDC_COLOR) 000f80: line 615 define IS_LTDC_GREENVALUE(BGREEN) ((BGREEN) <= LTDC_COLOR) 000fb7: line 616 define IS_LTDC_REDVALUE(BRED) ((BRED) <= LTDC_COLOR) 000fe8: line 617 define IS_LTDC_BLENDING_FACTOR1(BlendingFactor1) (((BlendingFactor1) == LTDC_BLENDING_FACTOR1_CA) || ((BlendingFactor1) == LTDC_BLENDING_FACTOR1_PAxCA)) 00107d: line 619 define IS_LTDC_BLENDING_FACTOR2(BlendingFactor2) (((BlendingFactor2) == LTDC_BLENDING_FACTOR2_CA) || ((BlendingFactor2) == LTDC_BLENDING_FACTOR2_PAxCA)) 001112: line 621 define IS_LTDC_PIXEL_FORMAT(Pixelformat) (((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB8888) || ((Pixelformat) == LTDC_PIXEL_FORMAT_RGB888) || ((Pixelformat) == LTDC_PIXEL_FORMAT_RGB565) || ((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB1555) || ((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB4444) || ((Pixelformat) == LTDC_PIXEL_FORMAT_L8) || ((Pixelformat) == LTDC_PIXEL_FORMAT_AL44) || ((Pixelformat) == LTDC_PIXEL_FORMAT_AL88)) 0012ac: line 625 define IS_LTDC_ALPHA(ALPHA) ((ALPHA) <= LTDC_ALPHA) 0012dc: line 626 define IS_LTDC_HCONFIGST(HCONFIGST) ((HCONFIGST) <= LTDC_STARTPOSITION) 001320: line 627 define IS_LTDC_HCONFIGSP(HCONFIGSP) ((HCONFIGSP) <= LTDC_STOPPOSITION) 001363: line 628 define IS_LTDC_VCONFIGST(VCONFIGST) ((VCONFIGST) <= LTDC_STARTPOSITION) 0013a7: line 629 define IS_LTDC_VCONFIGSP(VCONFIGSP) ((VCONFIGSP) <= LTDC_STOPPOSITION) 0013ea: line 630 define IS_LTDC_CFBP(CFBP) ((CFBP) <= LTDC_COLOR_FRAME_BUFFER) 001424: line 631 define IS_LTDC_CFBLL(CFBLL) ((CFBLL) <= LTDC_COLOR_FRAME_BUFFER) 001461: line 632 define IS_LTDC_CFBLNBR(CFBLNBR) ((CFBLNBR) <= LTDC_LINE_NUMBER) 00149d: line 633 define IS_LTDC_LIPOS(LIPOS) ((LIPOS) <= 0x7FF) 0014c8: line 634 define IS_LTDC_RELAOD(RELOADTYPE) (((RELOADTYPE) == LTDC_RELOAD_IMMEDIATE) || ((RELOADTYPE) == LTDC_SRCR_VBR)) 001533: end include 001534: end of translation unit ** Section #205 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 124 bytes 000000: Header: length 120 (not including this field) version 3 prologue length 108 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_ltdc.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 6c 74 64 63 2e 68 00 01 00 00 00005e: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000075: file "" : 00 000076: DW_LNS_negate_stmt : 06 000077: DW_LNS_negate_stmt : 06 000078: DW_LNS_negate_stmt : 06 000079: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_ltdc.h:1.0 [ ** Section #206 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 1276 bytes 000000: Header: size 0x4f8 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_ltdc.h 00004a: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000091: DW_AT_language DW_LANG_C89 000093: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010a: DW_AT_macro_info 0x0 00010e: DW_AT_stmt_list 0x0 000112: 42 = 0x13 (DW_TAG_structure_type) 000113: DW_AT_sibling 0x153 000115: DW_AT_byte_size 0x4 000116: 30 = 0xd (DW_TAG_member) 000117: DW_AT_name Blue 00011c: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000121: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000124: 30 = 0xd (DW_TAG_member) 000125: DW_AT_name Green 00012b: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000130: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 1 } 000133: 30 = 0xd (DW_TAG_member) 000134: DW_AT_name Red 000138: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00013d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 2 } 000140: 30 = 0xd (DW_TAG_member) 000141: DW_AT_name Reserved 00014a: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00014f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 3 } 000152: 0 null 000153: 80 = 0x16 (DW_TAG_typedef) 000154: DW_AT_name LTDC_ColorTypeDef 000166: DW_AT_type indirect DW_FORM_ref2 0x112 000169: DW_AT_decl_file 0x1 00016a: DW_AT_decl_line 0x52 00016b: DW_AT_decl_column 0x3 00016c: 42 = 0x13 (DW_TAG_structure_type) 00016d: DW_AT_sibling 0x290 00016f: DW_AT_byte_size 0x34 000170: 30 = 0xd (DW_TAG_member) 000171: DW_AT_name HSPolarity 00017c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000181: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000184: 30 = 0xd (DW_TAG_member) 000185: DW_AT_name VSPolarity 000190: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000195: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000198: 30 = 0xd (DW_TAG_member) 000199: DW_AT_name DEPolarity 0001a4: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001a9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0001ac: 30 = 0xd (DW_TAG_member) 0001ad: DW_AT_name PCPolarity 0001b8: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001bd: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0001c0: 30 = 0xd (DW_TAG_member) 0001c1: DW_AT_name HorizontalSync 0001d0: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001d5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 0001d8: 30 = 0xd (DW_TAG_member) 0001d9: DW_AT_name VerticalSync 0001e6: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001eb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 0001ee: 30 = 0xd (DW_TAG_member) 0001ef: DW_AT_name AccumulatedHBP 0001fe: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000203: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 000206: 30 = 0xd (DW_TAG_member) 000207: DW_AT_name AccumulatedVBP 000216: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00021b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 00021e: 30 = 0xd (DW_TAG_member) 00021f: DW_AT_name AccumulatedActiveW 000232: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000237: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 00023a: 30 = 0xd (DW_TAG_member) 00023b: DW_AT_name AccumulatedActiveH 00024e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000253: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 000256: 30 = 0xd (DW_TAG_member) 000257: DW_AT_name TotalWidth 000262: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000267: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 00026a: 30 = 0xd (DW_TAG_member) 00026b: DW_AT_name TotalHeigh 000276: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00027b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 00027e: 30 = 0xd (DW_TAG_member) 00027f: DW_AT_name Backcolor 000289: DW_AT_type indirect DW_FORM_ref2 0x153 00028c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 00028f: 0 null 000290: 80 = 0x16 (DW_TAG_typedef) 000291: DW_AT_name LTDC_InitTypeDef 0002a2: DW_AT_type indirect DW_FORM_ref2 0x16c 0002a5: DW_AT_decl_file 0x1 0002a6: DW_AT_decl_line 0x7e 0002a7: DW_AT_decl_column 0x3 0002a8: 42 = 0x13 (DW_TAG_structure_type) 0002a9: DW_AT_sibling 0x3ac 0002ab: DW_AT_byte_size 0x34 0002ac: 30 = 0xd (DW_TAG_member) 0002ad: DW_AT_name WindowX0 0002b6: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002bb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0002be: 30 = 0xd (DW_TAG_member) 0002bf: DW_AT_name WindowX1 0002c8: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002cd: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0002d0: 30 = 0xd (DW_TAG_member) 0002d1: DW_AT_name WindowY0 0002da: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002df: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0002e2: 30 = 0xd (DW_TAG_member) 0002e3: DW_AT_name WindowY1 0002ec: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002f1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0002f4: 30 = 0xd (DW_TAG_member) 0002f5: DW_AT_name PixelFormat 000301: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000306: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000309: 30 = 0xd (DW_TAG_member) 00030a: DW_AT_name Alpha 000310: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000315: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 000318: 30 = 0xd (DW_TAG_member) 000319: DW_AT_name Alpha0 000320: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000325: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 000328: 30 = 0xd (DW_TAG_member) 000329: DW_AT_name BlendingFactor1 000339: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00033e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 000341: 30 = 0xd (DW_TAG_member) 000342: DW_AT_name BlendingFactor2 000352: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000357: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 00035a: 30 = 0xd (DW_TAG_member) 00035b: DW_AT_name FBStartAdress 000369: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00036e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 000371: 30 = 0xd (DW_TAG_member) 000372: DW_AT_name ImageWidth 00037d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000382: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 000385: 30 = 0xd (DW_TAG_member) 000386: DW_AT_name ImageHeight 000392: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000397: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 00039a: 30 = 0xd (DW_TAG_member) 00039b: DW_AT_name Backcolor 0003a5: DW_AT_type indirect DW_FORM_ref2 0x153 0003a8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 0003ab: 0 null 0003ac: 80 = 0x16 (DW_TAG_typedef) 0003ad: DW_AT_name LTDC_LayerCfgTypeDef 0003c2: DW_AT_type indirect DW_FORM_ref2 0x2a8 0003c5: DW_AT_decl_file 0x1 0003c6: DW_AT_decl_line 0xa9 0003c8: DW_AT_decl_column 0x3 0003c9: 19 = 0x4 (DW_TAG_enumeration_type) 0003ca: DW_AT_sibling 0x447 0003cc: DW_AT_byte_size 0x1 0003cd: 20 = 0x28 (DW_TAG_enumerator) 0003ce: DW_AT_name HAL_LTDC_STATE_RESET 0003e3: DW_AT_const_value indirect DW_FORM_data1 0x0 0003e5: 20 = 0x28 (DW_TAG_enumerator) 0003e6: DW_AT_name HAL_LTDC_STATE_READY 0003fb: DW_AT_const_value indirect DW_FORM_data1 0x1 0003fd: 20 = 0x28 (DW_TAG_enumerator) 0003fe: DW_AT_name HAL_LTDC_STATE_BUSY 000412: DW_AT_const_value indirect DW_FORM_data1 0x2 000414: 20 = 0x28 (DW_TAG_enumerator) 000415: DW_AT_name HAL_LTDC_STATE_TIMEOUT 00042c: DW_AT_const_value indirect DW_FORM_data1 0x3 00042e: 20 = 0x28 (DW_TAG_enumerator) 00042f: DW_AT_name HAL_LTDC_STATE_ERROR 000444: DW_AT_const_value indirect DW_FORM_data1 0x4 000446: 0 null 000447: 80 = 0x16 (DW_TAG_typedef) 000448: DW_AT_name HAL_LTDC_StateTypeDef 00045e: DW_AT_type indirect DW_FORM_ref2 0x3c9 000461: DW_AT_decl_file 0x1 000462: DW_AT_decl_line 0xb5 000464: DW_AT_decl_column 0x2 000465: 42 = 0x13 (DW_TAG_structure_type) 000466: DW_AT_sibling 0x4cf 000468: DW_AT_byte_size 0xa8 00046a: 30 = 0xd (DW_TAG_member) 00046b: DW_AT_name Instance 000474: DW_AT_type indirect DW_FORM_ref2 0x4cf 000477: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00047a: 30 = 0xd (DW_TAG_member) 00047b: DW_AT_name Init 000480: DW_AT_type indirect DW_FORM_ref2 0x290 000483: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000486: 3 = 0x1 (DW_TAG_array_type) 000487: DW_AT_sibling 0x48f 000489: DW_AT_type indirect DW_FORM_ref2 0x3ac 00048c: 1 = 0x21 (DW_TAG_subrange_type) 00048d: DW_AT_upper_bound 0x1 00048e: 0 null 00048f: 30 = 0xd (DW_TAG_member) 000490: DW_AT_name LayerCfg 000499: DW_AT_type indirect DW_FORM_ref2 0x486 00049c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 00049f: 30 = 0xd (DW_TAG_member) 0004a0: DW_AT_name Lock 0004a5: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 0004aa: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 160 } 0004ae: 30 = 0xd (DW_TAG_member) 0004af: DW_AT_name State 0004b5: DW_AT_type indirect DW_FORM_ref2 0x4d5 0004b8: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 161 } 0004bc: 30 = 0xd (DW_TAG_member) 0004bd: DW_AT_name ErrorCode 0004c7: DW_AT_type indirect DW_FORM_ref2 0x4d9 0004ca: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 164 } 0004ce: 0 null 0004cf: 34 = 0xf (DW_TAG_pointer_type) 0004d0: DW_AT_type indirect DW_FORM_ref_addr 0x1c6b+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 0004d5: 116 = 0x35 (DW_TAG_volatile_type) 0004d6: DW_AT_type indirect DW_FORM_ref2 0x447 0004d9: 116 = 0x35 (DW_TAG_volatile_type) 0004da: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004df: 80 = 0x16 (DW_TAG_typedef) 0004e0: DW_AT_name LTDC_HandleTypeDef 0004f3: DW_AT_type indirect DW_FORM_ref2 0x465 0004f6: DW_AT_decl_file 0x1 0004f7: DW_AT_decl_line 0xc8 0004f9: DW_AT_decl_column 0x3 0004fa: 0 null 0004fb: 0 padding ** Section #406 '.rel.debug_info' (SHT_REL) Size : 272 bytes (alignment 4) Symbol table #343 '.symtab' 34 relocations applied to section #206 '.debug_info' ** Section #207 '__ARM_grp.stm32f7xx_hal_pwr_ex.h.2_YV1000_M8lfIaWYms4_300000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #208 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 2916 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_PWR_EX_H 00001f: include at line 47 - file 2 000022: end include 000023: line 65 define PWR_WAKEUP_PIN1 PWR_CSR2_EWUP1 000044: line 66 define PWR_WAKEUP_PIN2 PWR_CSR2_EWUP2 000065: line 67 define PWR_WAKEUP_PIN3 PWR_CSR2_EWUP3 000086: line 68 define PWR_WAKEUP_PIN4 PWR_CSR2_EWUP4 0000a7: line 69 define PWR_WAKEUP_PIN5 PWR_CSR2_EWUP5 0000c8: line 70 define PWR_WAKEUP_PIN6 PWR_CSR2_EWUP6 0000e9: line 71 define PWR_WAKEUP_PIN1_HIGH PWR_CSR2_EWUP1 00010f: line 72 define PWR_WAKEUP_PIN2_HIGH PWR_CSR2_EWUP2 000135: line 73 define PWR_WAKEUP_PIN3_HIGH PWR_CSR2_EWUP3 00015b: line 74 define PWR_WAKEUP_PIN4_HIGH PWR_CSR2_EWUP4 000181: line 75 define PWR_WAKEUP_PIN5_HIGH PWR_CSR2_EWUP5 0001a7: line 76 define PWR_WAKEUP_PIN6_HIGH PWR_CSR2_EWUP6 0001cd: line 77 define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR2_WUPP1<<6) | PWR_CSR2_EWUP1) 000213: line 78 define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR2_WUPP2<<6) | PWR_CSR2_EWUP2) 000259: line 79 define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR2_WUPP3<<6) | PWR_CSR2_EWUP3) 00029f: line 80 define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR2_WUPP4<<6) | PWR_CSR2_EWUP4) 0002e5: line 81 define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR2_WUPP5<<6) | PWR_CSR2_EWUP5) 00032b: line 82 define PWR_WAKEUP_PIN6_LOW (uint32_t)((PWR_CR2_WUPP6<<6) | PWR_CSR2_EWUP6) 000371: line 91 define PWR_MAINREGULATOR_UNDERDRIVE_ON PWR_CR1_MRUDS 0003a1: line 92 define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON ((uint32_t)(PWR_CR1_LPDS | PWR_CR1_LPUDS)) 0003f2: line 100 define PWR_FLAG_ODRDY PWR_CSR1_ODRDY 000412: line 101 define PWR_FLAG_ODSWRDY PWR_CSR1_ODSWRDY 000436: line 102 define PWR_FLAG_UDRDY PWR_CSR1_UDRDY 000456: line 110 define PWR_WAKEUP_PIN_FLAG1 PWR_CSR2_WUPF1 00047c: line 111 define PWR_WAKEUP_PIN_FLAG2 PWR_CSR2_WUPF2 0004a2: line 112 define PWR_WAKEUP_PIN_FLAG3 PWR_CSR2_WUPF3 0004c8: line 113 define PWR_WAKEUP_PIN_FLAG4 PWR_CSR2_WUPF4 0004ee: line 114 define PWR_WAKEUP_PIN_FLAG5 PWR_CSR2_WUPF5 000514: line 115 define PWR_WAKEUP_PIN_FLAG6 PWR_CSR2_WUPF6 00053a: line 130 define __HAL_PWR_OVERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODEN) 00057f: line 131 define __HAL_PWR_OVERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODEN)) 0005c8: line 135 define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODSWEN) 000618: line 136 define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODSWEN)) 00066c: line 148 define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_UDEN) 0006b2: line 149 define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_UDEN)) 0006fc: line 162 define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__)) 00074c: line 166 define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR1 |= PWR_FLAG_UDRDY) 00078b: line 178 define __HAL_PWR_GET_WAKEUP_FLAG(__WUFLAG__) (PWR->CSR2 & (__WUFLAG__)) 0007cf: line 190 define __HAL_PWR_CLEAR_WAKEUP_FLAG(__WUFLAG__) (PWR->CR2 |= (__WUFLAG__)) 000815: line 237 define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON)) 0008aa: line 239 define IS_PWR_WAKEUP_PIN(__PIN__) (((__PIN__) == PWR_WAKEUP_PIN1) || ((__PIN__) == PWR_WAKEUP_PIN2) || ((__PIN__) == PWR_WAKEUP_PIN3) || ((__PIN__) == PWR_WAKEUP_PIN4) || ((__PIN__) == PWR_WAKEUP_PIN5) || ((__PIN__) == PWR_WAKEUP_PIN6) || ((__PIN__) == PWR_WAKEUP_PIN1_HIGH) || ((__PIN__) == PWR_WAKEUP_PIN2_HIGH) || ((__PIN__) == PWR_WAKEUP_PIN3_HIGH) || ((__PIN__) == PWR_WAKEUP_PIN4_HIGH) || ((__PIN__) == PWR_WAKEUP_PIN5_HIGH) || ((__PIN__) == PWR_WAKEUP_PIN6_HIGH) || ((__PIN__) == PWR_WAKEUP_PIN1_LOW) || ((__PIN__) == PWR_WAKEUP_PIN2_LOW) || ((__PIN__) == PWR_WAKEUP_PIN3_LOW) || ((__PIN__) == PWR_WAKEUP_PIN4_LOW) || ((__PIN__) == PWR_WAKEUP_PIN5_LOW) || ((__PIN__) == PWR_WAKEUP_PIN6_LOW)) 000b61: end include 000b62: end of translation unit ** Section #209 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 124 bytes 000000: Header: length 120 (not including this field) version 3 prologue length 110 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_pwr_ex.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 70 77 72 5f 65 78 2e 68 00 01 00 00 000060: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000077: file "" : 00 000078: DW_LNS_negate_stmt : 06 000079: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr_ex.h:1.0 [ ** Section #210 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 280 bytes 000000: Header: size 0x114 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr_ex.h 00004c: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000093: DW_AT_language DW_LANG_C89 000095: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010c: DW_AT_macro_info 0x0 000110: DW_AT_stmt_list 0x0 000114: 0 null 000115: 0 padding 000116: 0 padding 000117: 0 padding ** Section #407 '.rel.debug_info' (SHT_REL) Size : 24 bytes (alignment 4) Symbol table #343 '.symtab' 3 relocations applied to section #210 '.debug_info' ** Section #211 '__ARM_grp.stm32f7xx_hal_pwr.h.2_s63000_kPAZSEmXgQ4_800000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #212 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 3760 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_PWR_H 00001c: include at line 47 - file 2 00001f: end include 000020: line 87 define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 000042: line 88 define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 000064: line 89 define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 000086: line 90 define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 0000a8: line 91 define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 0000ca: line 92 define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 0000ec: line 93 define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 00010e: line 94 define PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7 000130: line 104 define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U) 00015e: line 105 define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U) 00018f: line 106 define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U) 0001c1: line 107 define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) 0001fa: line 108 define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) 00022e: line 109 define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) 000263: line 110 define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) 00029f: line 118 define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U) 0002ce: line 119 define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS 0002f6: line 127 define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U) 00031c: line 128 define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U) 000343: line 136 define PWR_STOPENTRY_WFI ((uint8_t)0x01U) 000369: line 137 define PWR_STOPENTRY_WFE ((uint8_t)0x02U) 00038f: line 145 define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS 0003bb: line 146 define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 0003e9: line 147 define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR1_VOS_0 000417: line 155 define PWR_FLAG_WU PWR_CSR1_WUIF 000434: line 156 define PWR_FLAG_SB PWR_CSR1_SBF 000450: line 157 define PWR_FLAG_PVDO PWR_CSR1_PVDO 00046f: line 158 define PWR_FLAG_BRR PWR_CSR1_BRR 00048c: line 159 define PWR_FLAG_VOSRDY PWR_CSR1_VOSRDY 0004af: line 183 define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { __IO uint32_t tmpreg; MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); UNUSED(tmpreg); } while(0) 000575: line 210 define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__)) 0005be: line 217 define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR1 |= (__FLAG__) << 2) 0005fe: line 223 define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD)) 000643: line 229 define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD)) 00068a: line 235 define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD)) 0006d2: line 241 define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD)) 00071c: line 247 define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) 00076e: line 253 define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) 0007c3: line 259 define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) 000816: line 266 define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) 00086c: line 273 define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); 0008f1: line 279 define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); 000979: line 285 define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) 0009bb: line 291 define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) 0009ff: line 297 define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD)) 000a4a: include at line 304 - file 3 000a4e: end include 000a4f: line 367 define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_IM16) 000a7e: line 383 define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) 000b8d: line 387 define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_NORMAL)) 000cc6: line 391 define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) 000d3a: line 393 define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) 000d9c: line 394 define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) 000dfb: line 395 define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) 000eac: end include 000ead: end of translation unit ** Section #213 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 148 bytes 000000: Header: length 144 (not including this field) version 3 prologue length 133 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_pwr.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 70 77 72 2e 68 00 01 00 00 00005d: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000074: file "stm32f7xx_hal_pwr_ex.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 70 77 72 5f 65 78 2e 68 00 01 00 00 00008e: file "" : 00 00008f: DW_LNS_negate_stmt : 06 000090: DW_LNS_negate_stmt : 06 000091: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr.h:1.0 ** Section #214 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 336 bytes 000000: Header: size 0x14c bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr.h 000049: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000090: DW_AT_language DW_LANG_C89 000092: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 000109: DW_AT_macro_info 0x0 00010d: DW_AT_stmt_list 0x0 000111: 42 = 0x13 (DW_TAG_structure_type) 000112: DW_AT_sibling 0x136 000114: DW_AT_byte_size 0x8 000115: 30 = 0xd (DW_TAG_member) 000116: DW_AT_name PVDLevel 00011f: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000124: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000127: 30 = 0xd (DW_TAG_member) 000128: DW_AT_name Mode 00012d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000132: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000135: 0 null 000136: 80 = 0x16 (DW_TAG_typedef) 000137: DW_AT_name PWR_PVDTypeDef 000146: DW_AT_type indirect DW_FORM_ref2 0x111 000149: DW_AT_decl_file 0x1 00014a: DW_AT_decl_line 0x49 00014b: DW_AT_decl_column 0x2 00014c: 0 null 00014d: 0 padding 00014e: 0 padding 00014f: 0 padding ** Section #408 '.rel.debug_info' (SHT_REL) Size : 40 bytes (alignment 4) Symbol table #343 '.symtab' 5 relocations applied to section #214 '.debug_info' ** Section #215 '__ARM_grp.stm32f7xx_hal_qspi.h.2_0W2100_mYL1ArJf_Y6_420000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #216 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 7772 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_QSPI_H 00001d: include at line 47 - file 2 000020: end include 000021: line 211 define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000U) 000050: line 212 define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) 000082: line 213 define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) 0000b5: line 214 define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004U) 0000e3: line 215 define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) 00011b: line 223 define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) 000150: line 224 define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) 000190: line 232 define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000U) 0001c5: line 233 define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) 000201: line 234 define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) 00023d: line 235 define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) 00028e: line 236 define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) 0002ca: line 237 define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) 00031b: line 238 define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) 00036c: line 239 define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) 0003a6: line 247 define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000U) 0003d3: line 248 define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) 000407: line 256 define QSPI_FLASH_ID_1 ((uint32_t)0x00000000U) 000432: line 257 define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) 000461: line 265 define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) 000495: line 266 define QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000U) 0004c7: line 274 define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000U) 0004f6: line 275 define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) 00052f: line 276 define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) 000568: line 277 define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) 00059f: line 285 define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000U) 0005d6: line 286 define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) 000617: line 287 define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) 000658: line 288 define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) 000697: line 296 define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000U) 0006c8: line 297 define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) 000703: line 298 define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) 00073f: line 299 define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) 000779: line 307 define QSPI_ADDRESS_NONE ((uint32_t)0x00000000U) 0007a6: line 308 define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) 0007de: line 309 define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) 000817: line 310 define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) 00084e: line 318 define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000U) 000883: line 319 define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) 0008c3: line 320 define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) 000904: line 321 define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) 000943: line 329 define QSPI_DATA_NONE ((uint32_t)0X00000000) 00096c: line 330 define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) 0009a0: line 331 define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) 0009d5: line 332 define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) 000a08: line 340 define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000U) 000a39: line 341 define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) 000a6e: line 349 define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000U) 000aa3: line 350 define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) 000adf: line 358 define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000U) 000b13: line 359 define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) 000b51: line 367 define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000U) 000b80: line 368 define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) 000bb1: line 376 define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000U) 000be8: line 377 define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) 000c22: line 385 define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000U) 000c5a: line 386 define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) 000c95: line 394 define QSPI_FLAG_BUSY QUADSPI_SR_BUSY 000cb7: line 395 define QSPI_FLAG_TO QUADSPI_SR_TOF 000cd6: line 396 define QSPI_FLAG_SM QUADSPI_SR_SMF 000cf5: line 397 define QSPI_FLAG_FT QUADSPI_SR_FTF 000d14: line 398 define QSPI_FLAG_TC QUADSPI_SR_TCF 000d33: line 399 define QSPI_FLAG_TE QUADSPI_SR_TEF 000d52: line 407 define QSPI_IT_TO QUADSPI_CR_TOIE 000d70: line 408 define QSPI_IT_SM QUADSPI_CR_SMIE 000d8e: line 409 define QSPI_IT_FT QUADSPI_CR_FTIE 000dac: line 410 define QSPI_IT_TC QUADSPI_CR_TCIE 000dca: line 411 define QSPI_IT_TE QUADSPI_CR_TEIE 000de8: line 419 define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000) 000e1b: line 437 define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET) 000e75: line 443 define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) 000ec9: line 449 define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) 000f20: line 462 define __HAL_QSPI_ENABLE_IT(__HANDLE__,__INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 000f87: line 476 define __HAL_QSPI_DISABLE_IT(__HANDLE__,__INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 000ff1: line 489 define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) 001072: line 504 define __HAL_QSPI_GET_FLAG(__HANDLE__,__FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0) 0010d6: line 516 define __HAL_QSPI_CLEAR_FLAG(__HANDLE__,__FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) 001137: line 615 define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF) 001173: line 623 define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 32)) 0011b1: line 628 define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) 001225: line 634 define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31)) 001254: line 639 define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE)) 0013d4: line 648 define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || ((CLKMODE) == QSPI_CLOCK_MODE_3)) 00143a: line 651 define IS_QSPI_FLASH_ID(FLA) (((FLA) == QSPI_FLASH_ID_1) || ((FLA) == QSPI_FLASH_ID_2)) 00148e: line 654 define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || ((MODE) == QSPI_DUALFLASH_DISABLE)) 0014f9: line 661 define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF) 001535: line 666 define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS)) 0015fa: line 671 define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS)) 0016ce: line 680 define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31) 0016f9: line 685 define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || ((MODE) == QSPI_INSTRUCTION_1_LINE) || ((MODE) == QSPI_INSTRUCTION_2_LINES) || ((MODE) == QSPI_INSTRUCTION_4_LINES)) 0017b6: line 690 define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || ((MODE) == QSPI_ADDRESS_1_LINE) || ((MODE) == QSPI_ADDRESS_2_LINES) || ((MODE) == QSPI_ADDRESS_4_LINES)) 00185f: line 695 define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES)) 001930: line 700 define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || ((MODE) == QSPI_DATA_1_LINE) || ((MODE) == QSPI_DATA_2_LINES) || ((MODE) == QSPI_DATA_4_LINES)) 0019ca: line 705 define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || ((DDR_MODE) == QSPI_DDR_MODE_ENABLE)) 001a38: line 708 define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY)) 001aad: line 711 define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD)) 001b2b: line 717 define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) 001b6e: line 725 define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4)) 001bb2: line 729 define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || ((MODE) == QSPI_MATCH_MODE_OR)) 001c12: line 732 define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) 001c86: line 735 define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) 001d00: line 741 define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF) 001d37: line 746 define IS_QSPI_GET_FLAG(FLAG) (((FLAG) == QSPI_FLAG_BUSY) || ((FLAG) == QSPI_FLAG_TO) || ((FLAG) == QSPI_FLAG_SM) || ((FLAG) == QSPI_FLAG_FT) || ((FLAG) == QSPI_FLAG_TC) || ((FLAG) == QSPI_FLAG_TE)) 001dfa: line 753 define IS_QSPI_IT(IT) ((((IT) & (uint32_t)0xFFE0FFFFU) == 0x00000000U) && ((IT) != 0x00000000U)) 001e57: end include 001e58: end of translation unit ** Section #217 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 124 bytes 000000: Header: length 120 (not including this field) version 3 prologue length 108 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_qspi.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 71 73 70 69 2e 68 00 01 00 00 00005e: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000075: file "" : 00 000076: DW_LNS_negate_stmt : 06 000077: DW_LNS_negate_stmt : 06 000078: DW_LNS_negate_stmt : 06 000079: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_qspi.h:1.0 [ ** Section #218 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 1624 bytes 000000: Header: size 0x654 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_qspi.h 00004a: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000091: DW_AT_language DW_LANG_C89 000093: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010a: DW_AT_macro_info 0x0 00010e: DW_AT_stmt_list 0x0 000112: 42 = 0x13 (DW_TAG_structure_type) 000113: DW_AT_sibling 0x1c4 000115: DW_AT_byte_size 0x20 000116: 30 = 0xd (DW_TAG_member) 000117: DW_AT_name ClockPrescaler 000126: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00012b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00012e: 30 = 0xd (DW_TAG_member) 00012f: DW_AT_name FifoThreshold 00013d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000142: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000145: 30 = 0xd (DW_TAG_member) 000146: DW_AT_name SampleShifting 000155: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00015a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 00015d: 30 = 0xd (DW_TAG_member) 00015e: DW_AT_name FlashSize 000168: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00016d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000170: 30 = 0xd (DW_TAG_member) 000171: DW_AT_name ChipSelectHighTime 000184: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000189: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 00018c: 30 = 0xd (DW_TAG_member) 00018d: DW_AT_name ClockMode 000197: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00019c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 00019f: 30 = 0xd (DW_TAG_member) 0001a0: DW_AT_name FlashID 0001a8: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001ad: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 0001b0: 30 = 0xd (DW_TAG_member) 0001b1: DW_AT_name DualFlash 0001bb: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001c0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 0001c3: 0 null 0001c4: 80 = 0x16 (DW_TAG_typedef) 0001c5: DW_AT_name QSPI_InitTypeDef 0001d6: DW_AT_type indirect DW_FORM_ref2 0x112 0001d9: DW_AT_decl_file 0x1 0001da: DW_AT_decl_line 0x60 0001db: DW_AT_decl_column 0x2 0001dc: 19 = 0x4 (DW_TAG_enumeration_type) 0001dd: DW_AT_sibling 0x2e4 0001df: DW_AT_byte_size 0x1 0001e0: 20 = 0x28 (DW_TAG_enumerator) 0001e1: DW_AT_name HAL_QSPI_STATE_RESET 0001f6: DW_AT_const_value indirect DW_FORM_data1 0x0 0001f8: 20 = 0x28 (DW_TAG_enumerator) 0001f9: DW_AT_name HAL_QSPI_STATE_READY 00020e: DW_AT_const_value indirect DW_FORM_data1 0x1 000210: 20 = 0x28 (DW_TAG_enumerator) 000211: DW_AT_name HAL_QSPI_STATE_BUSY 000225: DW_AT_const_value indirect DW_FORM_data1 0x2 000227: 20 = 0x28 (DW_TAG_enumerator) 000228: DW_AT_name HAL_QSPI_STATE_BUSY_INDIRECT_TX 000248: DW_AT_const_value indirect DW_FORM_data1 0x12 00024a: 20 = 0x28 (DW_TAG_enumerator) 00024b: DW_AT_name HAL_QSPI_STATE_BUSY_INDIRECT_RX 00026b: DW_AT_const_value indirect DW_FORM_data1 0x22 00026d: 20 = 0x28 (DW_TAG_enumerator) 00026e: DW_AT_name HAL_QSPI_STATE_BUSY_AUTO_POLLING 00028f: DW_AT_const_value indirect DW_FORM_data1 0x42 000291: 20 = 0x28 (DW_TAG_enumerator) 000292: DW_AT_name HAL_QSPI_STATE_BUSY_MEM_MAPPED 0002b1: DW_AT_const_value indirect DW_FORM_data1 0x82 0002b3: 20 = 0x28 (DW_TAG_enumerator) 0002b4: DW_AT_name HAL_QSPI_STATE_ABORT 0002c9: DW_AT_const_value indirect DW_FORM_data1 0x8 0002cb: 20 = 0x28 (DW_TAG_enumerator) 0002cc: DW_AT_name HAL_QSPI_STATE_ERROR 0002e1: DW_AT_const_value indirect DW_FORM_data1 0x4 0002e3: 0 null 0002e4: 80 = 0x16 (DW_TAG_typedef) 0002e5: DW_AT_name HAL_QSPI_StateTypeDef 0002fb: DW_AT_type indirect DW_FORM_ref2 0x1dc 0002fe: DW_AT_decl_file 0x1 0002ff: DW_AT_decl_line 0x70 000300: DW_AT_decl_column 0x2 000301: 42 = 0x13 (DW_TAG_structure_type) 000302: DW_AT_sibling 0x3d7 000304: DW_AT_byte_size 0x44 000305: 30 = 0xd (DW_TAG_member) 000306: DW_AT_name Instance 00030f: DW_AT_type indirect DW_FORM_ref2 0x3d7 000312: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000315: 30 = 0xd (DW_TAG_member) 000316: DW_AT_name Init 00031b: DW_AT_type indirect DW_FORM_ref2 0x1c4 00031e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000321: 30 = 0xd (DW_TAG_member) 000322: DW_AT_name pTxBuffPtr 00032d: DW_AT_type indirect DW_FORM_ref2 0x3dd 000330: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 000333: 30 = 0xd (DW_TAG_member) 000334: DW_AT_name TxXferSize 00033f: DW_AT_type indirect DW_FORM_ref2 0x3e3 000342: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 000345: 30 = 0xd (DW_TAG_member) 000346: DW_AT_name TxXferCount 000352: DW_AT_type indirect DW_FORM_ref2 0x3e3 000355: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 42 } 000358: 30 = 0xd (DW_TAG_member) 000359: DW_AT_name pRxBuffPtr 000364: DW_AT_type indirect DW_FORM_ref2 0x3dd 000367: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 00036a: 30 = 0xd (DW_TAG_member) 00036b: DW_AT_name RxXferSize 000376: DW_AT_type indirect DW_FORM_ref2 0x3e3 000379: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 00037c: 30 = 0xd (DW_TAG_member) 00037d: DW_AT_name RxXferCount 000389: DW_AT_type indirect DW_FORM_ref2 0x3e3 00038c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 50 } 00038f: 30 = 0xd (DW_TAG_member) 000390: DW_AT_name hdma 000395: DW_AT_type indirect DW_FORM_ref2 0x3e9 000398: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 00039b: 30 = 0xd (DW_TAG_member) 00039c: DW_AT_name Lock 0003a1: DW_AT_type indirect DW_FORM_ref2 0x3ef 0003a4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 0003a7: 30 = 0xd (DW_TAG_member) 0003a8: DW_AT_name State 0003ae: DW_AT_type indirect DW_FORM_ref2 0x3f5 0003b1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 57 } 0003b4: 30 = 0xd (DW_TAG_member) 0003b5: DW_AT_name ErrorCode 0003bf: DW_AT_type indirect DW_FORM_ref2 0x3f9 0003c2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 60 } 0003c5: 30 = 0xd (DW_TAG_member) 0003c6: DW_AT_name Timeout 0003ce: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003d3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 64 } 0003d6: 0 null 0003d7: 34 = 0xf (DW_TAG_pointer_type) 0003d8: DW_AT_type indirect DW_FORM_ref_addr 0x264c+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 0003dd: 34 = 0xf (DW_TAG_pointer_type) 0003de: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003e3: 116 = 0x35 (DW_TAG_volatile_type) 0003e4: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003e9: 34 = 0xf (DW_TAG_pointer_type) 0003ea: DW_AT_type indirect DW_FORM_ref_addr 0x1a0+__ARM_grp..debug_info$stm32f7xx_hal_dma.h$.2_wD1100_gh0hnOcebnc_s10000 0003ef: 116 = 0x35 (DW_TAG_volatile_type) 0003f0: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 0003f5: 116 = 0x35 (DW_TAG_volatile_type) 0003f6: DW_AT_type indirect DW_FORM_ref2 0x2e4 0003f9: 116 = 0x35 (DW_TAG_volatile_type) 0003fa: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003ff: 80 = 0x16 (DW_TAG_typedef) 000400: DW_AT_name QSPI_HandleTypeDef 000413: DW_AT_type indirect DW_FORM_ref2 0x301 000416: DW_AT_decl_file 0x1 000417: DW_AT_decl_line 0x84 000419: DW_AT_decl_column 0x2 00041a: 42 = 0x13 (DW_TAG_structure_type) 00041b: DW_AT_sibling 0x54b 00041d: DW_AT_byte_size 0x38 00041e: 30 = 0xd (DW_TAG_member) 00041f: DW_AT_name Instruction 00042b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000430: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000433: 30 = 0xd (DW_TAG_member) 000434: DW_AT_name Address 00043c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000441: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000444: 30 = 0xd (DW_TAG_member) 000445: DW_AT_name AlternateBytes 000454: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000459: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 00045c: 30 = 0xd (DW_TAG_member) 00045d: DW_AT_name AddressSize 000469: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00046e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000471: 30 = 0xd (DW_TAG_member) 000472: DW_AT_name AlternateBytesSize 000485: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00048a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 00048d: 30 = 0xd (DW_TAG_member) 00048e: DW_AT_name DummyCycles 00049a: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00049f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 0004a2: 30 = 0xd (DW_TAG_member) 0004a3: DW_AT_name InstructionMode 0004b3: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004b8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 0004bb: 30 = 0xd (DW_TAG_member) 0004bc: DW_AT_name AddressMode 0004c8: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004cd: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 0004d0: 30 = 0xd (DW_TAG_member) 0004d1: DW_AT_name AlternateByteMode 0004e3: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004e8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 0004eb: 30 = 0xd (DW_TAG_member) 0004ec: DW_AT_name DataMode 0004f5: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004fa: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 0004fd: 30 = 0xd (DW_TAG_member) 0004fe: DW_AT_name NbData 000505: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00050a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 00050d: 30 = 0xd (DW_TAG_member) 00050e: DW_AT_name DdrMode 000516: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00051b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 00051e: 30 = 0xd (DW_TAG_member) 00051f: DW_AT_name DdrHoldHalfCycle 000530: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000535: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 000538: 30 = 0xd (DW_TAG_member) 000539: DW_AT_name SIOOMode 000542: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000547: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 00054a: 0 null 00054b: 80 = 0x16 (DW_TAG_typedef) 00054c: DW_AT_name QSPI_CommandTypeDef 000560: DW_AT_type indirect DW_FORM_ref2 0x41a 000563: DW_AT_decl_file 0x1 000564: DW_AT_decl_line 0xa9 000566: DW_AT_decl_column 0x2 000567: 42 = 0x13 (DW_TAG_structure_type) 000568: DW_AT_sibling 0x5de 00056a: DW_AT_byte_size 0x18 00056b: 30 = 0xd (DW_TAG_member) 00056c: DW_AT_name Match 000572: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000577: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00057a: 30 = 0xd (DW_TAG_member) 00057b: DW_AT_name Mask 000580: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000585: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000588: 30 = 0xd (DW_TAG_member) 000589: DW_AT_name Interval 000592: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000597: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 00059a: 30 = 0xd (DW_TAG_member) 00059b: DW_AT_name StatusBytesSize 0005ab: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0005b0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0005b3: 30 = 0xd (DW_TAG_member) 0005b4: DW_AT_name MatchMode 0005be: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0005c3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 0005c6: 30 = 0xd (DW_TAG_member) 0005c7: DW_AT_name AutomaticStop 0005d5: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0005da: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 0005dd: 0 null 0005de: 80 = 0x16 (DW_TAG_typedef) 0005df: DW_AT_name QSPI_AutoPollingTypeDef 0005f7: DW_AT_type indirect DW_FORM_ref2 0x567 0005fa: DW_AT_decl_file 0x1 0005fb: DW_AT_decl_line 0xbc 0005fd: DW_AT_decl_column 0x2 0005fe: 42 = 0x13 (DW_TAG_structure_type) 0005ff: DW_AT_sibling 0x635 000601: DW_AT_byte_size 0x8 000602: 30 = 0xd (DW_TAG_member) 000603: DW_AT_name TimeOutPeriod 000611: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000616: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000619: 30 = 0xd (DW_TAG_member) 00061a: DW_AT_name TimeOutActivation 00062c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000631: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000634: 0 null 000635: 80 = 0x16 (DW_TAG_typedef) 000636: DW_AT_name QSPI_MemoryMappedTypeDef 00064f: DW_AT_type indirect DW_FORM_ref2 0x5fe 000652: DW_AT_decl_file 0x1 000653: DW_AT_decl_line 0xc7 000655: DW_AT_decl_column 0x2 000656: 0 null 000657: 0 padding ** Section #409 '.rel.debug_info' (SHT_REL) Size : 320 bytes (alignment 4) Symbol table #343 '.symtab' 40 relocations applied to section #218 '.debug_info' ** Section #219 '__ARM_grp.stm32f7xx_hal_rng.h.2_84Y000__p8$n132UG9_e10000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #220 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 1124 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_RNG_H 00001c: include at line 47 - file 2 00001f: end include 000020: line 113 define RNG_IT_DRDY RNG_SR_DRDY 00003a: line 114 define RNG_IT_CEI RNG_SR_CEIS 000053: line 115 define RNG_IT_SEI RNG_SR_SEIS 00006c: line 123 define RNG_FLAG_DRDY RNG_SR_DRDY 000088: line 124 define RNG_FLAG_CECS RNG_SR_CECS 0000a4: line 125 define RNG_FLAG_SECS RNG_SR_SECS 0000c0: line 145 define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET) 000118: line 152 define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN) 000165: line 159 define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN) 0001b4: line 171 define __HAL_RNG_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) 000219: line 181 define __HAL_RNG_CLEAR_FLAG(__HANDLE__,__FLAG__) 000247: line 190 define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE) 000294: line 197 define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE) 0002e3: line 209 define __HAL_RNG_GET_IT(__HANDLE__,__INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__)) 000355: line 221 define __HAL_RNG_CLEAR_IT(__HANDLE__,__INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__)) 0003b7: line 315 define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || ((IT) == RNG_IT_SEI)) 0003f7: line 318 define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || ((FLAG) == RNG_FLAG_CECS) || ((FLAG) == RNG_FLAG_SECS)) 000462: end include 000463: end of translation unit ** Section #221 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 120 bytes 000000: Header: length 116 (not including this field) version 3 prologue length 107 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_rng.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 72 6e 67 2e 68 00 01 00 00 00005d: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000074: file "" : 00 000075: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rng.h:1.0 ** Section #222 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 532 bytes 000000: Header: size 0x210 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rng.h 000049: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000090: DW_AT_language DW_LANG_C89 000092: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 000109: DW_AT_macro_info 0x0 00010d: DW_AT_stmt_list 0x0 000111: 19 = 0x4 (DW_TAG_enumeration_type) 000112: DW_AT_sibling 0x18a 000114: DW_AT_byte_size 0x1 000115: 20 = 0x28 (DW_TAG_enumerator) 000116: DW_AT_name HAL_RNG_STATE_RESET 00012a: DW_AT_const_value indirect DW_FORM_data1 0x0 00012c: 20 = 0x28 (DW_TAG_enumerator) 00012d: DW_AT_name HAL_RNG_STATE_READY 000141: DW_AT_const_value indirect DW_FORM_data1 0x1 000143: 20 = 0x28 (DW_TAG_enumerator) 000144: DW_AT_name HAL_RNG_STATE_BUSY 000157: DW_AT_const_value indirect DW_FORM_data1 0x2 000159: 20 = 0x28 (DW_TAG_enumerator) 00015a: DW_AT_name HAL_RNG_STATE_TIMEOUT 000170: DW_AT_const_value indirect DW_FORM_data1 0x3 000172: 20 = 0x28 (DW_TAG_enumerator) 000173: DW_AT_name HAL_RNG_STATE_ERROR 000187: DW_AT_const_value indirect DW_FORM_data1 0x4 000189: 0 null 00018a: 80 = 0x16 (DW_TAG_typedef) 00018b: DW_AT_name HAL_RNG_StateTypeDef 0001a0: DW_AT_type indirect DW_FORM_ref2 0x111 0001a3: DW_AT_decl_file 0x1 0001a4: DW_AT_decl_line 0x4b 0001a5: DW_AT_decl_column 0x2 0001a6: 42 = 0x13 (DW_TAG_structure_type) 0001a7: DW_AT_sibling 0x1ec 0001a9: DW_AT_byte_size 0xc 0001aa: 30 = 0xd (DW_TAG_member) 0001ab: DW_AT_name Instance 0001b4: DW_AT_type indirect DW_FORM_ref2 0x1ec 0001b7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0001ba: 30 = 0xd (DW_TAG_member) 0001bb: DW_AT_name RandomNumber 0001c8: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001cd: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0001d0: 30 = 0xd (DW_TAG_member) 0001d1: DW_AT_name Lock 0001d6: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 0001db: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0001de: 30 = 0xd (DW_TAG_member) 0001df: DW_AT_name State 0001e5: DW_AT_type indirect DW_FORM_ref2 0x1f2 0001e8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 9 } 0001eb: 0 null 0001ec: 34 = 0xf (DW_TAG_pointer_type) 0001ed: DW_AT_type indirect DW_FORM_ref_addr 0x290f+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 0001f2: 116 = 0x35 (DW_TAG_volatile_type) 0001f3: DW_AT_type indirect DW_FORM_ref2 0x18a 0001f6: 80 = 0x16 (DW_TAG_typedef) 0001f7: DW_AT_name RNG_HandleTypeDef 000209: DW_AT_type indirect DW_FORM_ref2 0x1a6 00020c: DW_AT_decl_file 0x1 00020d: DW_AT_decl_line 0x5e 00020e: DW_AT_decl_column 0x2 00020f: 0 null 000210: 0 padding 000211: 0 padding 000212: 0 padding 000213: 0 padding ** Section #410 '.rel.debug_info' (SHT_REL) Size : 48 bytes (alignment 4) Symbol table #343 '.symtab' 6 relocations applied to section #222 '.debug_info' ** Section #223 '__ARM_grp.stm32f7xx_hal_rtc_ex.h.2_019000__zZ1wvi7KFb_g00000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #224 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 15804 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_RTC_EX_H 00001f: include at line 47 - file 2 000022: end include 000023: line 109 define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000U) 000050: line 110 define RTC_OUTPUT_ALARMA ((uint32_t)0x00200000U) 00007c: line 111 define RTC_OUTPUT_ALARMB ((uint32_t)0x00400000U) 0000a8: line 112 define RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000U) 0000d4: line 120 define RTC_BKP_DR0 ((uint32_t)0x00000000U) 0000fa: line 121 define RTC_BKP_DR1 ((uint32_t)0x00000001U) 000120: line 122 define RTC_BKP_DR2 ((uint32_t)0x00000002U) 000146: line 123 define RTC_BKP_DR3 ((uint32_t)0x00000003U) 00016c: line 124 define RTC_BKP_DR4 ((uint32_t)0x00000004U) 000192: line 125 define RTC_BKP_DR5 ((uint32_t)0x00000005U) 0001b8: line 126 define RTC_BKP_DR6 ((uint32_t)0x00000006U) 0001de: line 127 define RTC_BKP_DR7 ((uint32_t)0x00000007U) 000204: line 128 define RTC_BKP_DR8 ((uint32_t)0x00000008U) 00022b: line 129 define RTC_BKP_DR9 ((uint32_t)0x00000009U) 000252: line 130 define RTC_BKP_DR10 ((uint32_t)0x0000000AU) 00027a: line 131 define RTC_BKP_DR11 ((uint32_t)0x0000000BU) 0002a2: line 132 define RTC_BKP_DR12 ((uint32_t)0x0000000CU) 0002ca: line 133 define RTC_BKP_DR13 ((uint32_t)0x0000000DU) 0002f2: line 134 define RTC_BKP_DR14 ((uint32_t)0x0000000EU) 00031a: line 135 define RTC_BKP_DR15 ((uint32_t)0x0000000FU) 000342: line 136 define RTC_BKP_DR16 ((uint32_t)0x00000010U) 00036a: line 137 define RTC_BKP_DR17 ((uint32_t)0x00000011U) 000392: line 138 define RTC_BKP_DR18 ((uint32_t)0x00000012U) 0003ba: line 139 define RTC_BKP_DR19 ((uint32_t)0x00000013U) 0003e2: line 140 define RTC_BKP_DR20 ((uint32_t)0x00000014U) 00040a: line 141 define RTC_BKP_DR21 ((uint32_t)0x00000015U) 000432: line 142 define RTC_BKP_DR22 ((uint32_t)0x00000016U) 00045a: line 143 define RTC_BKP_DR23 ((uint32_t)0x00000017U) 000482: line 144 define RTC_BKP_DR24 ((uint32_t)0x00000018U) 0004aa: line 145 define RTC_BKP_DR25 ((uint32_t)0x00000019U) 0004d2: line 146 define RTC_BKP_DR26 ((uint32_t)0x0000001AU) 0004fa: line 147 define RTC_BKP_DR27 ((uint32_t)0x0000001BU) 000522: line 148 define RTC_BKP_DR28 ((uint32_t)0x0000001CU) 00054a: line 149 define RTC_BKP_DR29 ((uint32_t)0x0000001DU) 000572: line 150 define RTC_BKP_DR30 ((uint32_t)0x0000001EU) 00059a: line 151 define RTC_BKP_DR31 ((uint32_t)0x0000001FU) 0005c2: line 159 define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000U) 0005f6: line 160 define RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008U) 00062b: line 168 define RTC_TAMPER_1 RTC_TAMPCR_TAMP1E 00064d: line 169 define RTC_TAMPER_2 RTC_TAMPCR_TAMP2E 00066f: line 170 define RTC_TAMPER_3 RTC_TAMPCR_TAMP3E 000691: line 178 define RTC_TAMPER1_INTERRUPT RTC_TAMPCR_TAMP1IE 0006bd: line 179 define RTC_TAMPER2_INTERRUPT RTC_TAMPCR_TAMP2IE 0006e9: line 180 define RTC_TAMPER3_INTERRUPT RTC_TAMPCR_TAMP3IE 000715: line 181 define RTC_ALL_TAMPER_INTERRUPT RTC_TAMPCR_TAMPIE 000743: line 189 define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000U) 000777: line 190 define RTC_TIMESTAMPPIN_POS1 ((uint32_t)0x00000002U) 0007a8: line 191 define RTC_TIMESTAMPPIN_POS2 ((uint32_t)0x00000004U) 0007d9: line 199 define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000U) 000811: line 200 define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002U) 00084a: line 201 define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE 000885: line 202 define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE 0008c2: line 210 define RTC_TAMPER_ERASE_BACKUP_ENABLE ((uint32_t)0x00000000U) 0008fc: line 211 define RTC_TAMPER_ERASE_BACKUP_DISABLE ((uint32_t)0x00020000U) 000937: line 219 define RTC_TAMPERMASK_FLAG_DISABLE ((uint32_t)0x00000000U) 00096e: line 220 define RTC_TAMPERMASK_FLAG_ENABLE ((uint32_t)0x00040000U) 0009a4: line 228 define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000U) 0009d8: line 230 define RTC_TAMPERFILTER_2SAMPLE ((uint32_t)0x00000800U) 000a0c: line 232 define RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000U) 000a40: line 234 define RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800U) 000a74: line 243 define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000U) 000ab6: line 245 define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 ((uint32_t)0x00000100U) 000af8: line 247 define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 ((uint32_t)0x00000200U) 000b39: line 249 define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t)0x00000300U) 000b7a: line 251 define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 ((uint32_t)0x00000400U) 000bbb: line 253 define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t)0x00000500U) 000bfc: line 255 define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t)0x00000600U) 000c3c: line 257 define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700U) 000c7c: line 266 define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000U) 000cbb: line 268 define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000U) 000cfa: line 270 define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000U) 000d39: line 272 define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000U) 000d78: line 281 define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAMPCR_TAMPTS) 000dbf: line 282 define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000U) 000e01: line 290 define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000U) 000e35: line 291 define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAMPCR_TAMPPUDIS) 000e73: line 299 define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000U) 000eab: line 300 define RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001U) 000ee2: line 301 define RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002U) 000f19: line 302 define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003U) 000f50: line 303 define RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004U) 000f8a: line 304 define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006U) 000fc4: line 312 define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000U) 000ffc: line 314 define RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000U) 001034: line 316 define RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000U) 00106b: line 325 define RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000U) 0010a5: line 328 define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000U) 0010e1: line 337 define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000U) 001111: line 338 define RTC_SHIFTADD1S_SET ((uint32_t)0x80000000U) 00113f: line 346 define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000U) 001170: line 347 define RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000U) 00119f: line 366 define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE)) 0011f9: line 373 define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE)) 001255: line 383 define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) 0012c2: line 393 define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) 001331: line 403 define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__,__INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET) 0013be: line 413 define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) 00144b: line 424 define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__,__FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) 0014ca: line 434 define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) 00156f: line 441 define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E)) 0015cf: line 448 define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E)) 001631: line 455 define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E)) 001691: line 462 define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E)) 0016f3: line 469 define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E)) 001753: line 476 define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E)) 0017b5: line 489 define __HAL_RTC_TAMPER_GET_IT(__HANDLE__,__INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3)) != RESET) ? SET : RESET) : ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET) : (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7)) != RESET) ? SET : RESET)) 001931: line 504 define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != RESET) ? SET : RESET) 0019bd: line 516 define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__,__FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) 001a37: line 528 define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) 001ad7: line 535 define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE)) 001b2e: line 542 define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE)) 001b87: line 552 define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) 001bf2: line 562 define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) 001c5f: line 572 define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__,__INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET) 001cea: line 582 define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) 001d75: line 593 define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__,__FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) 001df2: line 604 define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) 001e95: line 611 define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE)) 001ef6: line 618 define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE)) 001f59: line 628 define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__,__FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) 001fdf: line 638 define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0003FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) 002099: line 645 define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE)) 0020f9: line 652 define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE)) 00215b: line 659 define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON)) 0021bf: line 666 define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON)) 002225: line 676 define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__,__FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) 00229e: line 682 define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) 0022f7: line 688 define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) 002354: line 694 define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) 0023b0: line 700 define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) 002410: line 706 define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) 002474: line 712 define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) 0024dc: line 718 define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) 00253f: line 724 define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) 0025a6: line 730 define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); 002643: line 737 define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); 0026e3: line 743 define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT) 002739: line 749 define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT) 002791: line 755 define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) 0027f0: line 761 define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) 002853: line 767 define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) 0028ba: line 773 define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) 002920: line 779 define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) 00298a: line 785 define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) 0029f8: line 791 define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) 002a6a: line 797 define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) 002ad7: line 803 define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) 002b48: line 809 define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); 002bf4: line 816 define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); 002ca3: line 822 define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) 002d03: line 828 define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) 002d65: line 834 define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) 002dce: line 927 define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)EXTI_IMR_IM21) 002e10: line 928 define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_IM22) 002e4d: line 938 define RTC_TAMPCR_TAMPXE ((uint32_t) (RTC_TAMPCR_TAMP3E | RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP1E)) 002eab: line 939 define RTC_TAMPCR_TAMPXIE ((uint32_t) (RTC_TAMPER1_INTERRUPT | RTC_TAMPER2_INTERRUPT | RTC_TAMPER3_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT)) 002f31: line 952 define IS_RTC_OUTPUT(__OUTPUT__) (((__OUTPUT__) == RTC_OUTPUT_DISABLE) || ((__OUTPUT__) == RTC_OUTPUT_ALARMA) || ((__OUTPUT__) == RTC_OUTPUT_ALARMB) || ((__OUTPUT__) == RTC_OUTPUT_WAKEUP)) 002fea: line 956 define IS_RTC_BKP(__BKP__) ((__BKP__) < (uint32_t) RTC_BKP_NUMBER) 003029: line 957 define IS_TIMESTAMP_EDGE(__EDGE__) (((__EDGE__) == RTC_TIMESTAMPEDGE_RISING) || ((__EDGE__) == RTC_TIMESTAMPEDGE_FALLING)) 0030a0: line 959 define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & ((uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXE))) == 0x00U) && ((__TAMPER__) != (uint32_t)RESET)) 00312e: line 961 define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & (uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXIE)) == 0x00U) && ((__INTERRUPT__) != (uint32_t)RESET)) 0031ce: line 963 define IS_RTC_TIMESTAMP_PIN(__PIN__) (((__PIN__) == RTC_TIMESTAMPPIN_DEFAULT) || ((__PIN__) == RTC_TIMESTAMPPIN_POS1) || ((__PIN__) == RTC_TIMESTAMPPIN_POS2)) 003269: line 966 define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE) || ((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE) || ((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL)) 003358: line 970 define IS_RTC_TAMPER_ERASE_MODE(__MODE__) (((__MODE__) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || ((__MODE__) == RTC_TAMPER_ERASE_BACKUP_DISABLE)) 0033e2: line 972 define IS_RTC_TAMPER_MASKFLAG_STATE(__STATE__) (((__STATE__) == RTC_TAMPERMASK_FLAG_ENABLE) || ((__STATE__) == RTC_TAMPERMASK_FLAG_DISABLE)) 00346b: line 974 define IS_RTC_TAMPER_FILTER(__FILTER__) (((__FILTER__) == RTC_TAMPERFILTER_DISABLE) || ((__FILTER__) == RTC_TAMPERFILTER_2SAMPLE) || ((__FILTER__) == RTC_TAMPERFILTER_4SAMPLE) || ((__FILTER__) == RTC_TAMPERFILTER_8SAMPLE)) 003546: line 978 define IS_RTC_TAMPER_SAMPLING_FREQ(__FREQ__) (((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256)) 003734: line 986 define IS_RTC_TAMPER_PRECHARGE_DURATION(__DURATION__) (((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK)) 003851: line 990 define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(__DETECTION__) (((__DETECTION__) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || ((__DETECTION__) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE)) 003909: line 992 define IS_RTC_TAMPER_PULLUP_STATE(__STATE__) (((__STATE__) == RTC_TAMPER_PULLUP_ENABLE) || ((__STATE__) == RTC_TAMPER_PULLUP_DISABLE)) 00398c: line 994 define IS_RTC_WAKEUP_CLOCK(__CLOCK__) (((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || ((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || ((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || ((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || ((__CLOCK__) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || ((__CLOCK__) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS)) 003ad4: line 1001 define IS_RTC_WAKEUP_COUNTER(__COUNTER__) ((__COUNTER__) <= 0xFFFF) 003b14: line 1002 define IS_RTC_SMOOTH_CALIB_PERIOD(__PERIOD__) (((__PERIOD__) == RTC_SMOOTHCALIB_PERIOD_32SEC) || ((__PERIOD__) == RTC_SMOOTHCALIB_PERIOD_16SEC) || ((__PERIOD__) == RTC_SMOOTHCALIB_PERIOD_8SEC)) 003bd2: line 1005 define IS_RTC_SMOOTH_CALIB_PLUS(__PLUS__) (((__PLUS__) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || ((__PLUS__) == RTC_SMOOTHCALIB_PLUSPULSES_RESET)) 003c5d: line 1007 define IS_RTC_SMOOTH_CALIB_MINUS(__VALUE__) ((__VALUE__) <= 0x000001FF) 003ca1: line 1008 define IS_RTC_SHIFT_ADD1S(__SEL__) (((__SEL__) == RTC_SHIFTADD1S_RESET) || ((__SEL__) == RTC_SHIFTADD1S_SET)) 003d0b: line 1010 define IS_RTC_SHIFT_SUBFS(__FS__) ((__FS__) <= 0x00007FFF) 003d42: line 1011 define IS_RTC_CALIB_OUTPUT(__OUTPUT__) (((__OUTPUT__) == RTC_CALIBOUTPUT_512HZ) || ((__OUTPUT__) == RTC_CALIBOUTPUT_1HZ)) 003db8: end include 003db9: end of translation unit ** Section #225 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 124 bytes 000000: Header: length 120 (not including this field) version 3 prologue length 110 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_rtc_ex.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 72 74 63 5f 65 78 2e 68 00 01 00 00 000060: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000077: file "" : 00 000078: DW_LNS_negate_stmt : 06 000079: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rtc_ex.h:1.0 [ ** Section #226 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 524 bytes 000000: Header: size 0x208 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rtc_ex.h 00004c: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000093: DW_AT_language DW_LANG_C89 000095: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010c: DW_AT_macro_info 0x0 000110: DW_AT_stmt_list 0x0 000114: 42 = 0x13 (DW_TAG_structure_type) 000115: DW_AT_sibling 0x1f0 000117: DW_AT_byte_size 0x28 000118: 30 = 0xd (DW_TAG_member) 000119: DW_AT_name Tamper 000120: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000125: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000128: 30 = 0xd (DW_TAG_member) 000129: DW_AT_name Interrupt 000133: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000138: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00013b: 30 = 0xd (DW_TAG_member) 00013c: DW_AT_name Trigger 000144: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000149: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 00014c: 30 = 0xd (DW_TAG_member) 00014d: DW_AT_name NoErase 000155: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00015a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00015d: 30 = 0xd (DW_TAG_member) 00015e: DW_AT_name MaskFlag 000167: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00016c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 00016f: 30 = 0xd (DW_TAG_member) 000170: DW_AT_name Filter 000177: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00017c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 00017f: 30 = 0xd (DW_TAG_member) 000180: DW_AT_name SamplingFrequency 000192: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000197: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 00019a: 30 = 0xd (DW_TAG_member) 00019b: DW_AT_name PrechargeDuration 0001ad: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001b2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 0001b5: 30 = 0xd (DW_TAG_member) 0001b6: DW_AT_name TamperPullUp 0001c3: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001c8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 0001cb: 30 = 0xd (DW_TAG_member) 0001cc: DW_AT_name TimeStampOnTamperDetection 0001e7: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001ec: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 0001ef: 0 null 0001f0: 80 = 0x16 (DW_TAG_typedef) 0001f1: DW_AT_name RTC_TamperTypeDef 000203: DW_AT_type indirect DW_FORM_ref2 0x114 000206: DW_AT_decl_file 0x1 000207: DW_AT_decl_line 0x60 000208: DW_AT_decl_column 0x2 000209: 0 null 00020a: 0 padding 00020b: 0 padding ** Section #411 '.rel.debug_info' (SHT_REL) Size : 104 bytes (alignment 4) Symbol table #343 '.symtab' 13 relocations applied to section #226 '.debug_info' ** Section #227 '__ARM_grp.stm32f7xx_hal_rtc.h.2_0J0100_Z1cqTI6tfs6_A10000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #228 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 10304 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_RTC_H 00001c: include at line 47 - file 2 00001f: end include 000020: line 205 define RTC_HOURFORMAT_24 ((uint32_t)0x00000000U) 00004d: line 206 define RTC_HOURFORMAT_12 ((uint32_t)0x00000040U) 00007a: line 215 define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000U) 0000ae: line 216 define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000U) 0000e1: line 224 define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000U) 000116: line 225 define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)RTC_OR_ALARMTYPE) 00014f: line 233 define RTC_HOURFORMAT12_AM ((uint8_t)0x00U) 000177: line 234 define RTC_HOURFORMAT12_PM ((uint8_t)0x40U) 00019f: line 242 define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000U) 0001d3: line 243 define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000U) 000207: line 244 define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000U) 00023a: line 252 define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000U) 00026e: line 253 define RTC_STOREOPERATION_SET ((uint32_t)0x00040000U) 0002a0: line 261 define RTC_FORMAT_BIN ((uint32_t)0x00000000U) 0002ca: line 262 define RTC_FORMAT_BCD ((uint32_t)0x00000001U) 0002f4: line 271 define RTC_MONTH_JANUARY ((uint8_t)0x01U) 00031a: line 272 define RTC_MONTH_FEBRUARY ((uint8_t)0x02U) 000341: line 273 define RTC_MONTH_MARCH ((uint8_t)0x03U) 000365: line 274 define RTC_MONTH_APRIL ((uint8_t)0x04U) 000389: line 275 define RTC_MONTH_MAY ((uint8_t)0x05U) 0003ab: line 276 define RTC_MONTH_JUNE ((uint8_t)0x06U) 0003ce: line 277 define RTC_MONTH_JULY ((uint8_t)0x07U) 0003f1: line 278 define RTC_MONTH_AUGUST ((uint8_t)0x08U) 000416: line 279 define RTC_MONTH_SEPTEMBER ((uint8_t)0x09U) 00043e: line 280 define RTC_MONTH_OCTOBER ((uint8_t)0x10U) 000464: line 281 define RTC_MONTH_NOVEMBER ((uint8_t)0x11U) 00048b: line 282 define RTC_MONTH_DECEMBER ((uint8_t)0x12U) 0004b2: line 290 define RTC_WEEKDAY_MONDAY ((uint8_t)0x01U) 0004d9: line 291 define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U) 000501: line 292 define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U) 00052b: line 293 define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U) 000554: line 294 define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U) 00057b: line 295 define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U) 0005a4: line 296 define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U) 0005cb: line 304 define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000U) 000603: line 305 define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000U) 00063e: line 313 define RTC_ALARMMASK_NONE ((uint32_t)0x00000000U) 00066c: line 314 define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4 000699: line 315 define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 0006c0: line 316 define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 0006e9: line 317 define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1 000712: line 318 define RTC_ALARMMASK_ALL ((uint32_t)0x80808080U) 00073f: line 326 define RTC_ALARM_A RTC_CR_ALRAE 00075b: line 327 define RTC_ALARM_B RTC_CR_ALRBE 000777: line 335 define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000U) 0007ad: line 338 define RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000U) 0007e6: line 340 define RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000U) 00081f: line 342 define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000U) 000858: line 344 define RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000U) 000891: line 346 define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000U) 0008ca: line 348 define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000U) 000903: line 350 define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000U) 00093c: line 352 define RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000U) 000975: line 354 define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000U) 0009ae: line 356 define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000U) 0009e8: line 358 define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000U) 000a22: line 360 define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000U) 000a5c: line 362 define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000U) 000a96: line 364 define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000U) 000acd: line 366 define RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000U) 000b04: line 375 define RTC_IT_TS ((uint32_t)RTC_CR_TSIE) 000b29: line 376 define RTC_IT_WUT ((uint32_t)RTC_CR_WUTIE) 000b50: line 377 define RTC_IT_ALRA ((uint32_t)RTC_CR_ALRAIE) 000b79: line 378 define RTC_IT_ALRB ((uint32_t)RTC_CR_ALRBIE) 000ba2: line 379 define RTC_IT_TAMP ((uint32_t)RTC_TAMPCR_TAMPIE) 000bcf: line 380 define RTC_IT_TAMP1 ((uint32_t)RTC_TAMPCR_TAMP1IE) 000bfe: line 381 define RTC_IT_TAMP2 ((uint32_t)RTC_TAMPCR_TAMP2IE) 000c2d: line 382 define RTC_IT_TAMP3 ((uint32_t)RTC_TAMPCR_TAMP3IE) 000c5c: line 390 define RTC_FLAG_RECALPF ((uint32_t)RTC_ISR_RECALPF) 000c8c: line 391 define RTC_FLAG_TAMP3F ((uint32_t)RTC_ISR_TAMP3F) 000cba: line 392 define RTC_FLAG_TAMP2F ((uint32_t)RTC_ISR_TAMP2F) 000ce8: line 393 define RTC_FLAG_TAMP1F ((uint32_t)RTC_ISR_TAMP1F) 000d16: line 394 define RTC_FLAG_TSOVF ((uint32_t)RTC_ISR_TSOVF) 000d42: line 395 define RTC_FLAG_TSF ((uint32_t)RTC_ISR_TSF) 000d6a: line 396 define RTC_FLAG_ITSF ((uint32_t)RTC_ISR_ITSF) 000d94: line 397 define RTC_FLAG_WUTF ((uint32_t)RTC_ISR_WUTF) 000dbe: line 398 define RTC_FLAG_ALRBF ((uint32_t)RTC_ISR_ALRBF) 000dea: line 399 define RTC_FLAG_ALRAF ((uint32_t)RTC_ISR_ALRAF) 000e16: line 400 define RTC_FLAG_INITF ((uint32_t)RTC_ISR_INITF) 000e42: line 401 define RTC_FLAG_RSF ((uint32_t)RTC_ISR_RSF) 000e6a: line 402 define RTC_FLAG_INITS ((uint32_t)RTC_ISR_INITS) 000e96: line 403 define RTC_FLAG_SHPF ((uint32_t)RTC_ISR_SHPF) 000ec0: line 404 define RTC_FLAG_WUTWF ((uint32_t)RTC_ISR_WUTWF) 000eec: line 405 define RTC_FLAG_ALRBWF ((uint32_t)RTC_ISR_ALRBWF) 000f1a: line 406 define RTC_FLAG_ALRAWF ((uint32_t)RTC_ISR_ALRAWF) 000f48: line 424 define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET) 000fa0: line 431 define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) do{ (__HANDLE__)->Instance->WPR = 0xCA; (__HANDLE__)->Instance->WPR = 0x53; } while(0) 001028: line 442 define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) do{ (__HANDLE__)->Instance->WPR = 0xFF; } while(0) 00108b: line 452 define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE)) 0010e1: line 459 define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE)) 001139: line 466 define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE)) 00118f: line 473 define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE)) 0011e7: line 484 define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) 00124e: line 495 define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) 0012b7: line 506 define __HAL_RTC_ALARM_GET_IT(__HANDLE__,__INTERRUPT__) ((((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) & 0x0000FFFF) != RESET)? SET : RESET) 00134b: line 519 define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__,__FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) 0013c3: line 530 define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) 001470: line 541 define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) 0014f7: line 547 define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT) 001544: line 553 define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) 001595: line 559 define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT) 0015e5: line 565 define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) 001639: line 571 define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT) 001691: line 577 define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) 0016ed: line 583 define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT) 001744: line 589 define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) 00179f: line 595 define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); 00182a: line 601 define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); 0018b8: line 607 define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT) 001902: line 613 define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT) 00194e: line 619 define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT) 0019a1: include at line 625 - file 3 0019a5: end include 0019a6: line 700 define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7FU) 0019d6: line 701 define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3FU) 001a06: line 702 define RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU) 001a2f: line 703 define RTC_RSF_MASK ((uint32_t)0xFFFFFF5FU) 001a57: line 705 define RTC_TIMEOUT_VALUE 1000 001a71: line 707 define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_IM17) 001aa8: line 720 define IS_RTC_HOUR_FORMAT(__FORMAT__) (((__FORMAT__) == RTC_HOURFORMAT_12) || ((__FORMAT__) == RTC_HOURFORMAT_24)) 001b17: line 722 define IS_RTC_OUTPUT_POL(__POL__) (((__POL__) == RTC_OUTPUT_POLARITY_HIGH) || ((__POL__) == RTC_OUTPUT_POLARITY_LOW)) 001b89: line 724 define IS_RTC_OUTPUT_TYPE(__TYPE__) (((__TYPE__) == RTC_OUTPUT_TYPE_OPENDRAIN) || ((__TYPE__) == RTC_OUTPUT_TYPE_PUSHPULL)) 001c01: line 726 define IS_RTC_ASYNCH_PREDIV(__PREDIV__) ((__PREDIV__) <= (uint32_t)0x7F) 001c46: line 727 define IS_RTC_SYNCH_PREDIV(__PREDIV__) ((__PREDIV__) <= (uint32_t)0x7FFF) 001c8c: line 728 define IS_RTC_HOUR12(__HOUR__) (((__HOUR__) > (uint32_t)0) && ((__HOUR__) <= (uint32_t)12)) 001ce4: line 729 define IS_RTC_HOUR24(__HOUR__) ((__HOUR__) <= (uint32_t)23) 001d1c: line 730 define IS_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= (uint32_t)59) 001d5b: line 731 define IS_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= (uint32_t)59) 001d9a: line 732 define IS_RTC_HOURFORMAT12(__PM__) (((__PM__) == RTC_HOURFORMAT12_AM) || ((__PM__) == RTC_HOURFORMAT12_PM)) 001e02: line 733 define IS_RTC_DAYLIGHT_SAVING(__SAVE__) (((__SAVE__) == RTC_DAYLIGHTSAVING_SUB1H) || ((__SAVE__) == RTC_DAYLIGHTSAVING_ADD1H) || ((__SAVE__) == RTC_DAYLIGHTSAVING_NONE)) 001ea8: line 736 define IS_RTC_STORE_OPERATION(__OPERATION__) (((__OPERATION__) == RTC_STOREOPERATION_RESET) || ((__OPERATION__) == RTC_STOREOPERATION_SET)) 001f30: line 738 define IS_RTC_FORMAT(__FORMAT__) (((__FORMAT__) == RTC_FORMAT_BIN) || ((__FORMAT__) == RTC_FORMAT_BCD)) 001f94: line 739 define IS_RTC_YEAR(__YEAR__) ((__YEAR__) <= (uint32_t)99) 001fca: line 740 define IS_RTC_MONTH(__MONTH__) (((__MONTH__) >= (uint32_t)1) && ((__MONTH__) <= (uint32_t)12)) 002025: line 741 define IS_RTC_DATE(__DATE__) (((__DATE__) >= (uint32_t)1) && ((__DATE__) <= (uint32_t)31)) 00207c: line 742 define IS_RTC_WEEKDAY(__WEEKDAY__) (((__WEEKDAY__) == RTC_WEEKDAY_MONDAY) || ((__WEEKDAY__) == RTC_WEEKDAY_TUESDAY) || ((__WEEKDAY__) == RTC_WEEKDAY_WEDNESDAY) || ((__WEEKDAY__) == RTC_WEEKDAY_THURSDAY) || ((__WEEKDAY__) == RTC_WEEKDAY_FRIDAY) || ((__WEEKDAY__) == RTC_WEEKDAY_SATURDAY) || ((__WEEKDAY__) == RTC_WEEKDAY_SUNDAY)) 0021c1: line 750 define IS_RTC_ALARM_DATE_WEEKDAY_DATE(__DATE__) (((__DATE__) >(uint32_t) 0) && ((__DATE__) <= (uint32_t)31)) 00222a: line 751 define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(__WEEKDAY__) (((__WEEKDAY__) == RTC_WEEKDAY_MONDAY) || ((__WEEKDAY__) == RTC_WEEKDAY_TUESDAY) || ((__WEEKDAY__) == RTC_WEEKDAY_WEDNESDAY) || ((__WEEKDAY__) == RTC_WEEKDAY_THURSDAY) || ((__WEEKDAY__) == RTC_WEEKDAY_FRIDAY) || ((__WEEKDAY__) == RTC_WEEKDAY_SATURDAY) || ((__WEEKDAY__) == RTC_WEEKDAY_SUNDAY)) 002382: line 758 define IS_RTC_ALARM_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == RTC_ALARMDATEWEEKDAYSEL_DATE) || ((__SEL__) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY)) 00240c: line 760 define IS_RTC_ALARM_MASK(__MASK__) (((__MASK__) & 0x7F7F7F7F) == (uint32_t)RESET) 00245a: line 761 define IS_RTC_ALARM(__ALARM__) (((__ALARM__) == RTC_ALARM_A) || ((__ALARM__) == RTC_ALARM_B)) 0024b4: line 762 define IS_RTC_ALARM_SUB_SECOND_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)0x00007FFF) 002506: line 763 define IS_RTC_ALARM_SUB_SECOND_MASK(__MASK__) (((__MASK__) == RTC_ALARMSUBSECONDMASK_ALL) || ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_1) || ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_2) || ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_3) || ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_4) || ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_5) || ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_6) || ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_7) || ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_8) || ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_9) || ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_10) || ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_11) || ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_12) || ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_13) || ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14) || ((__MASK__) == RTC_ALARMSUBSECONDMASK_NONE)) 00283c: end include 00283d: end of translation unit ** Section #229 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 148 bytes 000000: Header: length 144 (not including this field) version 3 prologue length 133 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_rtc.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 72 74 63 2e 68 00 01 00 00 00005d: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000074: file "stm32f7xx_hal_rtc_ex.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 72 74 63 5f 65 78 2e 68 00 01 00 00 00008e: file "" : 00 00008f: DW_LNS_negate_stmt : 06 000090: DW_LNS_negate_stmt : 06 000091: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rtc.h:1.0 ** Section #230 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 1116 bytes 000000: Header: size 0x458 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rtc.h 000049: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000090: DW_AT_language DW_LANG_C89 000092: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 000109: DW_AT_macro_info 0x0 00010d: DW_AT_stmt_list 0x0 000111: 19 = 0x4 (DW_TAG_enumeration_type) 000112: DW_AT_sibling 0x18a 000114: DW_AT_byte_size 0x1 000115: 20 = 0x28 (DW_TAG_enumerator) 000116: DW_AT_name HAL_RTC_STATE_RESET 00012a: DW_AT_const_value indirect DW_FORM_data1 0x0 00012c: 20 = 0x28 (DW_TAG_enumerator) 00012d: DW_AT_name HAL_RTC_STATE_READY 000141: DW_AT_const_value indirect DW_FORM_data1 0x1 000143: 20 = 0x28 (DW_TAG_enumerator) 000144: DW_AT_name HAL_RTC_STATE_BUSY 000157: DW_AT_const_value indirect DW_FORM_data1 0x2 000159: 20 = 0x28 (DW_TAG_enumerator) 00015a: DW_AT_name HAL_RTC_STATE_TIMEOUT 000170: DW_AT_const_value indirect DW_FORM_data1 0x3 000172: 20 = 0x28 (DW_TAG_enumerator) 000173: DW_AT_name HAL_RTC_STATE_ERROR 000187: DW_AT_const_value indirect DW_FORM_data1 0x4 000189: 0 null 00018a: 80 = 0x16 (DW_TAG_typedef) 00018b: DW_AT_name HAL_RTCStateTypeDef 00019f: DW_AT_type indirect DW_FORM_ref2 0x111 0001a2: DW_AT_decl_file 0x1 0001a3: DW_AT_decl_line 0x49 0001a4: DW_AT_decl_column 0x2 0001a5: 42 = 0x13 (DW_TAG_structure_type) 0001a6: DW_AT_sibling 0x225 0001a8: DW_AT_byte_size 0x18 0001a9: 30 = 0xd (DW_TAG_member) 0001aa: DW_AT_name HourFormat 0001b5: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001ba: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0001bd: 30 = 0xd (DW_TAG_member) 0001be: DW_AT_name AsynchPrediv 0001cb: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001d0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0001d3: 30 = 0xd (DW_TAG_member) 0001d4: DW_AT_name SynchPrediv 0001e0: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001e5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0001e8: 30 = 0xd (DW_TAG_member) 0001e9: DW_AT_name OutPut 0001f0: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001f5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0001f8: 30 = 0xd (DW_TAG_member) 0001f9: DW_AT_name OutPutPolarity 000208: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00020d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000210: 30 = 0xd (DW_TAG_member) 000211: DW_AT_name OutPutType 00021c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000221: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 000224: 0 null 000225: 80 = 0x16 (DW_TAG_typedef) 000226: DW_AT_name RTC_InitTypeDef 000236: DW_AT_type indirect DW_FORM_ref2 0x1a5 000239: DW_AT_decl_file 0x1 00023a: DW_AT_decl_line 0x61 00023b: DW_AT_decl_column 0x2 00023c: 42 = 0x13 (DW_TAG_structure_type) 00023d: DW_AT_sibling 0x2e2 00023f: DW_AT_byte_size 0x18 000240: 30 = 0xd (DW_TAG_member) 000241: DW_AT_name Hours 000247: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00024c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00024f: 30 = 0xd (DW_TAG_member) 000250: DW_AT_name Minutes 000258: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00025d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 1 } 000260: 30 = 0xd (DW_TAG_member) 000261: DW_AT_name Seconds 000269: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00026e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 2 } 000271: 30 = 0xd (DW_TAG_member) 000272: DW_AT_name SubSeconds 00027d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000282: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000285: 30 = 0xd (DW_TAG_member) 000286: DW_AT_name SecondFraction 000295: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00029a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 00029d: 30 = 0xd (DW_TAG_member) 00029e: DW_AT_name TimeFormat 0002a9: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002ae: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0002b1: 30 = 0xd (DW_TAG_member) 0002b2: DW_AT_name DayLightSaving 0002c1: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002c6: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 0002c9: 30 = 0xd (DW_TAG_member) 0002ca: DW_AT_name StoreOperation 0002d9: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002de: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 0002e1: 0 null 0002e2: 80 = 0x16 (DW_TAG_typedef) 0002e3: DW_AT_name RTC_TimeTypeDef 0002f3: DW_AT_type indirect DW_FORM_ref2 0x23c 0002f6: DW_AT_decl_file 0x1 0002f7: DW_AT_decl_line 0x85 0002f9: DW_AT_decl_column 0x2 0002fa: 42 = 0x13 (DW_TAG_structure_type) 0002fb: DW_AT_sibling 0x33b 0002fd: DW_AT_byte_size 0x4 0002fe: 30 = 0xd (DW_TAG_member) 0002ff: DW_AT_name WeekDay 000307: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00030c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00030f: 30 = 0xd (DW_TAG_member) 000310: DW_AT_name Month 000316: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00031b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 1 } 00031e: 30 = 0xd (DW_TAG_member) 00031f: DW_AT_name Date 000324: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000329: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 2 } 00032c: 30 = 0xd (DW_TAG_member) 00032d: DW_AT_name Year 000332: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000337: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 3 } 00033a: 0 null 00033b: 80 = 0x16 (DW_TAG_typedef) 00033c: DW_AT_name RTC_DateTypeDef 00034c: DW_AT_type indirect DW_FORM_ref2 0x2fa 00034f: DW_AT_decl_file 0x1 000350: DW_AT_decl_line 0x98 000352: DW_AT_decl_column 0x2 000353: 42 = 0x13 (DW_TAG_structure_type) 000354: DW_AT_sibling 0x3de 000356: DW_AT_byte_size 0x2c 000357: 30 = 0xd (DW_TAG_member) 000358: DW_AT_name AlarmTime 000362: DW_AT_type indirect DW_FORM_ref2 0x2e2 000365: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000368: 30 = 0xd (DW_TAG_member) 000369: DW_AT_name AlarmMask 000373: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000378: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 00037b: 30 = 0xd (DW_TAG_member) 00037c: DW_AT_name AlarmSubSecondMask 00038f: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000394: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 000397: 30 = 0xd (DW_TAG_member) 000398: DW_AT_name AlarmDateWeekDaySel 0003ac: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003b1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 0003b4: 30 = 0xd (DW_TAG_member) 0003b5: DW_AT_name AlarmDateWeekDay 0003c6: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003cb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 0003ce: 30 = 0xd (DW_TAG_member) 0003cf: DW_AT_name Alarm 0003d5: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003da: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 0003dd: 0 null 0003de: 80 = 0x16 (DW_TAG_typedef) 0003df: DW_AT_name RTC_AlarmTypeDef 0003f0: DW_AT_type indirect DW_FORM_ref2 0x353 0003f3: DW_AT_decl_file 0x1 0003f4: DW_AT_decl_line 0xb0 0003f6: DW_AT_decl_column 0x2 0003f7: 42 = 0x13 (DW_TAG_structure_type) 0003f8: DW_AT_sibling 0x433 0003fa: DW_AT_byte_size 0x20 0003fb: 30 = 0xd (DW_TAG_member) 0003fc: DW_AT_name Instance 000405: DW_AT_type indirect DW_FORM_ref2 0x433 000408: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00040b: 30 = 0xd (DW_TAG_member) 00040c: DW_AT_name Init 000411: DW_AT_type indirect DW_FORM_ref2 0x225 000414: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000417: 30 = 0xd (DW_TAG_member) 000418: DW_AT_name Lock 00041d: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 000422: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 000425: 30 = 0xd (DW_TAG_member) 000426: DW_AT_name State 00042c: DW_AT_type indirect DW_FORM_ref2 0x439 00042f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 29 } 000432: 0 null 000433: 34 = 0xf (DW_TAG_pointer_type) 000434: DW_AT_type indirect DW_FORM_ref_addr 0x22d1+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 000439: 116 = 0x35 (DW_TAG_volatile_type) 00043a: DW_AT_type indirect DW_FORM_ref2 0x18a 00043d: 80 = 0x16 (DW_TAG_typedef) 00043e: DW_AT_name RTC_HandleTypeDef 000450: DW_AT_type indirect DW_FORM_ref2 0x3f7 000453: DW_AT_decl_file 0x1 000454: DW_AT_decl_line 0xbf 000456: DW_AT_decl_column 0x2 000457: 0 null 000458: 0 padding 000459: 0 padding 00045a: 0 padding 00045b: 0 padding ** Section #412 '.rel.debug_info' (SHT_REL) Size : 224 bytes (alignment 4) Symbol table #343 '.symtab' 28 relocations applied to section #230 '.debug_info' ** Section #231 '__ARM_grp.stm32f7xx_hal_sai.h.2_w54100_49cUBdmiwda__10000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #232 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 10316 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_SAI_H 00001c: include at line 48 - file 2 00001f: end include 000020: line 255 define HAL_SAI_ERROR_NONE ((uint32_t)0x00000000U) 00004e: line 256 define HAL_SAI_ERROR_OVR ((uint32_t)0x00000001U) 00007b: line 257 define HAL_SAI_ERROR_UDR ((uint32_t)0x00000002U) 0000a8: line 258 define HAL_SAI_ERROR_AFSDET ((uint32_t)0x00000004U) 0000d8: line 259 define HAL_SAI_ERROR_LFSDET ((uint32_t)0x00000008U) 000108: line 260 define HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010U) 000139: line 261 define HAL_SAI_ERROR_WCKCFG ((uint32_t)0x00000020U) 000169: line 262 define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040U) 00019a: line 263 define HAL_SAI_ERROR_DMA ((uint32_t)0x00000080U) 0001c7: line 271 define SAI_SYNCEXT_DISABLE 0 0001e0: line 272 define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1 000202: line 273 define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2 000224: line 281 define SAI_I2S_STANDARD 0 00023a: line 282 define SAI_I2S_MSBJUSTIFIED 1 000254: line 283 define SAI_I2S_LSBJUSTIFIED 2 00026e: line 284 define SAI_PCM_LONG 3 000280: line 285 define SAI_PCM_SHORT 4 000293: line 293 define SAI_PROTOCOL_DATASIZE_16BIT 0 0002b4: line 294 define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1 0002dd: line 295 define SAI_PROTOCOL_DATASIZE_24BIT 2 0002fe: line 296 define SAI_PROTOCOL_DATASIZE_32BIT 3 00031f: line 304 define SAI_AUDIO_FREQUENCY_192K ((uint32_t)192000U) 00034f: line 305 define SAI_AUDIO_FREQUENCY_96K ((uint32_t)96000U) 00037d: line 306 define SAI_AUDIO_FREQUENCY_48K ((uint32_t)48000U) 0003ab: line 307 define SAI_AUDIO_FREQUENCY_44K ((uint32_t)44100U) 0003d9: line 308 define SAI_AUDIO_FREQUENCY_32K ((uint32_t)32000U) 000407: line 309 define SAI_AUDIO_FREQUENCY_22K ((uint32_t)22050U) 000435: line 310 define SAI_AUDIO_FREQUENCY_16K ((uint32_t)16000U) 000463: line 311 define SAI_AUDIO_FREQUENCY_11K ((uint32_t)11025U) 000491: line 312 define SAI_AUDIO_FREQUENCY_8K ((uint32_t)8000U) 0004bd: line 313 define SAI_AUDIO_FREQUENCY_MCKDIV ((uint32_t)0U) 0004ea: line 321 define SAI_MODEMASTER_TX ((uint32_t)0x00000000U) 000517: line 322 define SAI_MODEMASTER_RX ((uint32_t)SAI_xCR1_MODE_0) 000548: line 323 define SAI_MODESLAVE_TX ((uint32_t)SAI_xCR1_MODE_1) 000578: line 324 define SAI_MODESLAVE_RX ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0)) 0005bc: line 333 define SAI_FREE_PROTOCOL ((uint32_t)0x00000000U) 0005e9: line 334 define SAI_SPDIF_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_0) 00061d: line 335 define SAI_AC97_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_1) 000650: line 343 define SAI_DATASIZE_8 ((uint32_t)SAI_xCR1_DS_1) 00067c: line 344 define SAI_DATASIZE_10 ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0)) 0006bb: line 345 define SAI_DATASIZE_16 ((uint32_t)SAI_xCR1_DS_2) 0006e8: line 346 define SAI_DATASIZE_20 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0)) 000727: line 347 define SAI_DATASIZE_24 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1)) 000766: line 348 define SAI_DATASIZE_32 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0)) 0007b5: line 356 define SAI_FIRSTBIT_MSB ((uint32_t)0x00000000U) 0007e1: line 357 define SAI_FIRSTBIT_LSB ((uint32_t)SAI_xCR1_LSBFIRST) 000813: line 365 define SAI_CLOCKSTROBING_FALLINGEDGE 0 000836: line 366 define SAI_CLOCKSTROBING_RISINGEDGE 1 000858: line 374 define SAI_ASYNCHRONOUS 0 00086e: line 375 define SAI_SYNCHRONOUS 1 000883: line 376 define SAI_SYNCHRONOUS_EXT_SAI1 2 0008a1: line 377 define SAI_SYNCHRONOUS_EXT_SAI2 3 0008bf: line 385 define SAI_OUTPUTDRIVE_DISABLE ((uint32_t)0x00000000U) 0008f2: line 386 define SAI_OUTPUTDRIVE_ENABLE ((uint32_t)SAI_xCR1_OUTDRIV) 000929: line 394 define SAI_MASTERDIVIDER_ENABLE ((uint32_t)0x00000000U) 00095d: line 395 define SAI_MASTERDIVIDER_DISABLE ((uint32_t)SAI_xCR1_NODIV) 000995: line 404 define SAI_FS_STARTFRAME ((uint32_t)0x00000000U) 0009c2: line 405 define SAI_FS_CHANNEL_IDENTIFICATION ((uint32_t)SAI_xFRCR_FSDEF) 0009ff: line 413 define SAI_FS_ACTIVE_LOW ((uint32_t)0x00000000U) 000a2c: line 414 define SAI_FS_ACTIVE_HIGH ((uint32_t)SAI_xFRCR_FSPOL) 000a5e: line 422 define SAI_FS_FIRSTBIT ((uint32_t)0x00000000U) 000a89: line 423 define SAI_FS_BEFOREFIRSTBIT ((uint32_t)SAI_xFRCR_FSOFF) 000abe: line 432 define SAI_SLOTSIZE_DATASIZE ((uint32_t)0x00000000U) 000aef: line 433 define SAI_SLOTSIZE_16B ((uint32_t)SAI_xSLOTR_SLOTSZ_0) 000b23: line 434 define SAI_SLOTSIZE_32B ((uint32_t)SAI_xSLOTR_SLOTSZ_1) 000b57: line 442 define SAI_SLOT_NOTACTIVE ((uint32_t)0x00000000U) 000b85: line 443 define SAI_SLOTACTIVE_0 ((uint32_t)0x00000001U) 000bb1: line 444 define SAI_SLOTACTIVE_1 ((uint32_t)0x00000002U) 000bdd: line 445 define SAI_SLOTACTIVE_2 ((uint32_t)0x00000004U) 000c09: line 446 define SAI_SLOTACTIVE_3 ((uint32_t)0x00000008U) 000c35: line 447 define SAI_SLOTACTIVE_4 ((uint32_t)0x00000010U) 000c61: line 448 define SAI_SLOTACTIVE_5 ((uint32_t)0x00000020U) 000c8d: line 449 define SAI_SLOTACTIVE_6 ((uint32_t)0x00000040U) 000cb9: line 450 define SAI_SLOTACTIVE_7 ((uint32_t)0x00000080U) 000ce5: line 451 define SAI_SLOTACTIVE_8 ((uint32_t)0x00000100U) 000d11: line 452 define SAI_SLOTACTIVE_9 ((uint32_t)0x00000200U) 000d3d: line 453 define SAI_SLOTACTIVE_10 ((uint32_t)0x00000400U) 000d6a: line 454 define SAI_SLOTACTIVE_11 ((uint32_t)0x00000800U) 000d97: line 455 define SAI_SLOTACTIVE_12 ((uint32_t)0x00001000U) 000dc4: line 456 define SAI_SLOTACTIVE_13 ((uint32_t)0x00002000U) 000df1: line 457 define SAI_SLOTACTIVE_14 ((uint32_t)0x00004000U) 000e1e: line 458 define SAI_SLOTACTIVE_15 ((uint32_t)0x00008000U) 000e4b: line 459 define SAI_SLOTACTIVE_ALL ((uint32_t)0x0000FFFFU) 000e79: line 467 define SAI_STEREOMODE ((uint32_t)0x00000000U) 000ea3: line 468 define SAI_MONOMODE ((uint32_t)SAI_xCR1_MONO) 000ecd: line 476 define SAI_OUTPUT_NOTRELEASED ((uint32_t)0x00000000U) 000eff: line 477 define SAI_OUTPUT_RELEASED ((uint32_t)SAI_xCR2_TRIS) 000f30: line 485 define SAI_FIFOTHRESHOLD_EMPTY ((uint32_t)0x00000000U) 000f63: line 486 define SAI_FIFOTHRESHOLD_1QF ((uint32_t)(SAI_xCR2_FTH_0)) 000f99: line 487 define SAI_FIFOTHRESHOLD_HF ((uint32_t)(SAI_xCR2_FTH_1)) 000fce: line 488 define SAI_FIFOTHRESHOLD_3QF ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0)) 001015: line 489 define SAI_FIFOTHRESHOLD_FULL ((uint32_t)(SAI_xCR2_FTH_2)) 00104c: line 497 define SAI_NOCOMPANDING ((uint32_t)0x00000000U) 001078: line 498 define SAI_ULAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1)) 0010b2: line 499 define SAI_ALAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0)) 0010fe: line 500 define SAI_ULAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL)) 001147: line 501 define SAI_ALAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL)) 0011a2: line 509 define SAI_ZERO_VALUE ((uint32_t)0x00000000U) 0011cc: line 510 define SAI_LAST_SENT_VALUE ((uint32_t)SAI_xCR2_MUTEVAL) 001200: line 518 define SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE) 00122f: line 519 define SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE) 001260: line 520 define SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE) 00128f: line 521 define SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE) 0012ba: line 522 define SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE) 0012e7: line 523 define SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE) 001316: line 524 define SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE) 001345: line 532 define SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR) 001373: line 533 define SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET) 0013a3: line 534 define SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG) 0013d1: line 535 define SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ) 0013fb: line 536 define SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY) 001427: line 537 define SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET) 001455: line 538 define SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET) 001483: line 546 define SAI_FIFOSTATUS_EMPTY ((uint32_t)0x00000000U) 0014b3: line 547 define SAI_FIFOSTATUS_LESS1QUARTERFULL ((uint32_t)0x00010000U) 0014ee: line 548 define SAI_FIFOSTATUS_1QUARTERFULL ((uint32_t)0x00020000U) 001525: line 549 define SAI_FIFOSTATUS_HALFFULL ((uint32_t)0x00030000U) 001558: line 550 define SAI_FIFOSTATUS_3QUARTERFULL ((uint32_t)0x00040000U) 00158f: line 551 define SAI_FIFOSTATUS_FULL ((uint32_t)0x00050000U) 0015be: line 571 define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET) 001616: line 586 define __HAL_SAI_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__)) 001678: line 587 define __HAL_SAI_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__))) 0016de: line 602 define __HAL_SAI_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 001768: line 617 define __HAL_SAI_GET_FLAG(__HANDLE__,__FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 0017cf: line 633 define __HAL_SAI_CLEAR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__)) 001829: line 635 define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN) 001879: line 636 define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN) 0018cb: line 721 define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) || ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) || ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE)) 001967: line 725 define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_I2S_STANDARD) || ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) || ((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) || ((PROTOCOL) == SAI_PCM_LONG) || ((PROTOCOL) == SAI_PCM_SHORT)) 001a42: line 731 define IS_SAI_PROTOCOL_DATASIZE(DATASIZE) (((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT) || ((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) || ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT) || ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT)) 001b2b: line 736 define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_48K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_32K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_16K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_8K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV)) 001cde: line 742 define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_MODEMASTER_TX) || ((MODE) == SAI_MODEMASTER_RX) || ((MODE) == SAI_MODESLAVE_TX) || ((MODE) == SAI_MODESLAVE_RX)) 001d7a: line 747 define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL) || ((PROTOCOL) == SAI_AC97_PROTOCOL) || ((PROTOCOL) == SAI_SPDIF_PROTOCOL)) 001e0c: line 751 define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8) || ((DATASIZE) == SAI_DATASIZE_10) || ((DATASIZE) == SAI_DATASIZE_16) || ((DATASIZE) == SAI_DATASIZE_20) || ((DATASIZE) == SAI_DATASIZE_24) || ((DATASIZE) == SAI_DATASIZE_32)) 001eff: line 758 define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || ((BIT) == SAI_FIRSTBIT_LSB)) 001f5b: line 761 define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE)) 001fdb: line 764 define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || ((SYNCHRO) == SAI_SYNCHRONOUS) || ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2)) 002096: line 769 define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE)) 002108: line 772 define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE)) 002187: line 775 define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63) 0021bf: line 777 define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZERO_VALUE) || ((VALUE) == SAI_LAST_SENT_VALUE)) 002223: line 780 define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NOCOMPANDING) || ((MODE) == SAI_ULAW_1CPL_COMPANDING) || ((MODE) == SAI_ALAW_1CPL_COMPANDING) || ((MODE) == SAI_ULAW_2CPL_COMPANDING) || ((MODE) == SAI_ALAW_2CPL_COMPANDING)) 002308: line 786 define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY) || ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF) || ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF) || ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF) || ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL)) 002405: line 792 define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) || ((STATE) == SAI_OUTPUT_RELEASED)) 00247a: line 795 define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) || ((MODE) == SAI_STEREOMODE)) 0024d4: line 798 define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL) 002513: line 800 define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16)) 00255d: line 802 define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || ((SIZE) == SAI_SLOTSIZE_16B) || ((SIZE) == SAI_SLOTSIZE_32B)) 0025e1: line 806 define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24) 00261a: line 808 define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || ((OFFSET) == SAI_FS_BEFOREFIRSTBIT)) 002683: line 811 define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || ((POLARITY) == SAI_FS_ACTIVE_HIGH)) 0026f3: line 814 define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION)) 002776: line 817 define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15) 0027b0: line 819 define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256)) 0027fc: line 821 define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128)) 002848: end include 002849: end of translation unit ** Section #233 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 120 bytes 000000: Header: length 116 (not including this field) version 3 prologue length 107 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_sai.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 73 61 69 2e 68 00 01 00 00 00005d: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000074: file "" : 00 000075: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_sai.h:1.0 ** Section #234 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 1376 bytes 000000: Header: size 0x55c bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_sai.h 000049: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000090: DW_AT_language DW_LANG_C89 000092: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 000109: DW_AT_macro_info 0x0 00010d: DW_AT_stmt_list 0x0 000111: 19 = 0x4 (DW_TAG_enumeration_type) 000112: DW_AT_sibling 0x18c 000114: DW_AT_byte_size 0x1 000115: 20 = 0x28 (DW_TAG_enumerator) 000116: DW_AT_name HAL_SAI_STATE_RESET 00012a: DW_AT_const_value indirect DW_FORM_data1 0x0 00012c: 20 = 0x28 (DW_TAG_enumerator) 00012d: DW_AT_name HAL_SAI_STATE_READY 000141: DW_AT_const_value indirect DW_FORM_data1 0x1 000143: 20 = 0x28 (DW_TAG_enumerator) 000144: DW_AT_name HAL_SAI_STATE_BUSY 000157: DW_AT_const_value indirect DW_FORM_data1 0x2 000159: 20 = 0x28 (DW_TAG_enumerator) 00015a: DW_AT_name HAL_SAI_STATE_BUSY_TX 000170: DW_AT_const_value indirect DW_FORM_data1 0x12 000172: 20 = 0x28 (DW_TAG_enumerator) 000173: DW_AT_name HAL_SAI_STATE_BUSY_RX 000189: DW_AT_const_value indirect DW_FORM_data1 0x22 00018b: 0 null 00018c: 80 = 0x16 (DW_TAG_typedef) 00018d: DW_AT_name HAL_SAI_StateTypeDef 0001a2: DW_AT_type indirect DW_FORM_ref2 0x111 0001a5: DW_AT_decl_file 0x1 0001a6: DW_AT_decl_line 0x49 0001a7: DW_AT_decl_column 0x2 0001a8: 79 = 0x15 (DW_TAG_subroutine_type) 0001a9: DW_AT_sibling 0x1ac 0001ab: 0 null 0001ac: 34 = 0xf (DW_TAG_pointer_type) 0001ad: DW_AT_type indirect DW_FORM_ref2 0x1a8 0001b0: 80 = 0x16 (DW_TAG_typedef) 0001b1: DW_AT_name SAIcallback 0001bd: DW_AT_type indirect DW_FORM_ref2 0x1ac 0001c0: DW_AT_decl_file 0x1 0001c1: DW_AT_decl_line 0x4e 0001c2: DW_AT_decl_column 0x10 0001c3: 42 = 0x13 (DW_TAG_structure_type) 0001c4: DW_AT_sibling 0x2f6 0001c6: DW_AT_byte_size 0x3c 0001c7: 30 = 0xd (DW_TAG_member) 0001c8: DW_AT_name AudioMode 0001d2: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001d7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0001da: 30 = 0xd (DW_TAG_member) 0001db: DW_AT_name Synchro 0001e3: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001e8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0001eb: 30 = 0xd (DW_TAG_member) 0001ec: DW_AT_name SynchroExt 0001f7: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001fc: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0001ff: 30 = 0xd (DW_TAG_member) 000200: DW_AT_name OutputDrive 00020c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000211: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000214: 30 = 0xd (DW_TAG_member) 000215: DW_AT_name NoDivider 00021f: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000224: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000227: 30 = 0xd (DW_TAG_member) 000228: DW_AT_name FIFOThreshold 000236: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00023b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 00023e: 30 = 0xd (DW_TAG_member) 00023f: DW_AT_name AudioFrequency 00024e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000253: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 000256: 30 = 0xd (DW_TAG_member) 000257: DW_AT_name Mckdiv 00025e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000263: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 000266: 30 = 0xd (DW_TAG_member) 000267: DW_AT_name MonoStereoMode 000276: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00027b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 00027e: 30 = 0xd (DW_TAG_member) 00027f: DW_AT_name CompandingMode 00028e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000293: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 000296: 30 = 0xd (DW_TAG_member) 000297: DW_AT_name TriState 0002a0: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002a5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 0002a8: 30 = 0xd (DW_TAG_member) 0002a9: DW_AT_name Protocol 0002b2: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002b7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 0002ba: 30 = 0xd (DW_TAG_member) 0002bb: DW_AT_name DataSize 0002c4: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002c9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 0002cc: 30 = 0xd (DW_TAG_member) 0002cd: DW_AT_name FirstBit 0002d6: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002db: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 0002de: 30 = 0xd (DW_TAG_member) 0002df: DW_AT_name ClockStrobing 0002ed: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002f2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 0002f5: 0 null 0002f6: 80 = 0x16 (DW_TAG_typedef) 0002f7: DW_AT_name SAI_InitTypeDef 000307: DW_AT_type indirect DW_FORM_ref2 0x1c3 00030a: DW_AT_decl_file 0x1 00030b: DW_AT_decl_line 0x91 00030d: DW_AT_decl_column 0x2 00030e: 42 = 0x13 (DW_TAG_structure_type) 00030f: DW_AT_sibling 0x37f 000311: DW_AT_byte_size 0x14 000312: 30 = 0xd (DW_TAG_member) 000313: DW_AT_name FrameLength 00031f: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000324: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000327: 30 = 0xd (DW_TAG_member) 000328: DW_AT_name ActiveFrameLength 00033a: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00033f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000342: 30 = 0xd (DW_TAG_member) 000343: DW_AT_name FSDefinition 000350: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000355: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000358: 30 = 0xd (DW_TAG_member) 000359: DW_AT_name FSPolarity 000364: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000369: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00036c: 30 = 0xd (DW_TAG_member) 00036d: DW_AT_name FSOffset 000376: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00037b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 00037e: 0 null 00037f: 80 = 0x16 (DW_TAG_typedef) 000380: DW_AT_name SAI_FrameInitTypeDef 000395: DW_AT_type indirect DW_FORM_ref2 0x30e 000398: DW_AT_decl_file 0x1 000399: DW_AT_decl_line 0xb1 00039b: DW_AT_decl_column 0x2 00039c: 42 = 0x13 (DW_TAG_structure_type) 00039d: DW_AT_sibling 0x3f3 00039f: DW_AT_byte_size 0x10 0003a0: 30 = 0xd (DW_TAG_member) 0003a1: DW_AT_name FirstBitOffset 0003b0: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003b5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0003b8: 30 = 0xd (DW_TAG_member) 0003b9: DW_AT_name SlotSize 0003c2: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003c7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0003ca: 30 = 0xd (DW_TAG_member) 0003cb: DW_AT_name SlotNumber 0003d6: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003db: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0003de: 30 = 0xd (DW_TAG_member) 0003df: DW_AT_name SlotActive 0003ea: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003ef: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0003f2: 0 null 0003f3: 80 = 0x16 (DW_TAG_typedef) 0003f4: DW_AT_name SAI_SlotInitTypeDef 000408: DW_AT_type indirect DW_FORM_ref2 0x39c 00040b: DW_AT_decl_file 0x1 00040c: DW_AT_decl_line 0xc7 00040e: DW_AT_decl_column 0x2 00040f: 41 = 0x13 (DW_TAG_structure_type) 000410: DW_AT_sibling 0x523 000412: DW_AT_name __SAI_HandleTypeDef 000426: DW_AT_byte_size 0x84 000428: 30 = 0xd (DW_TAG_member) 000429: DW_AT_name Instance 000432: DW_AT_type indirect DW_FORM_ref2 0x523 000435: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000438: 30 = 0xd (DW_TAG_member) 000439: DW_AT_name Init 00043e: DW_AT_type indirect DW_FORM_ref2 0x2f6 000441: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000444: 30 = 0xd (DW_TAG_member) 000445: DW_AT_name FrameInit 00044f: DW_AT_type indirect DW_FORM_ref2 0x37f 000452: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 64 } 000455: 30 = 0xd (DW_TAG_member) 000456: DW_AT_name SlotInit 00045f: DW_AT_type indirect DW_FORM_ref2 0x3f3 000462: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 84 } 000465: 30 = 0xd (DW_TAG_member) 000466: DW_AT_name pBuffPtr 00046f: DW_AT_type indirect DW_FORM_ref2 0x529 000472: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 100 } 000475: 30 = 0xd (DW_TAG_member) 000476: DW_AT_name XferSize 00047f: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000484: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 104 } 000487: 30 = 0xd (DW_TAG_member) 000488: DW_AT_name XferCount 000492: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000497: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 106 } 00049a: 30 = 0xd (DW_TAG_member) 00049b: DW_AT_name hdmatx 0004a2: DW_AT_type indirect DW_FORM_ref2 0x52f 0004a5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 108 } 0004a8: 30 = 0xd (DW_TAG_member) 0004a9: DW_AT_name hdmarx 0004b0: DW_AT_type indirect DW_FORM_ref2 0x52f 0004b3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 112 } 0004b6: 30 = 0xd (DW_TAG_member) 0004b7: DW_AT_name mutecallback 0004c4: DW_AT_type indirect DW_FORM_ref2 0x1b0 0004c7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 116 } 0004ca: 79 = 0x15 (DW_TAG_subroutine_type) 0004cb: DW_AT_sibling 0x4d2 0004cd: 37 = 0x5 (DW_TAG_formal_parameter) 0004ce: DW_AT_type indirect DW_FORM_ref2 0x535 0004d1: 0 null 0004d2: 34 = 0xf (DW_TAG_pointer_type) 0004d3: DW_AT_type indirect DW_FORM_ref2 0x4ca 0004d6: 30 = 0xd (DW_TAG_member) 0004d7: DW_AT_name InterruptServiceRoutine 0004ef: DW_AT_type indirect DW_FORM_ref2 0x4d2 0004f2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 120 } 0004f5: 30 = 0xd (DW_TAG_member) 0004f6: DW_AT_name Lock 0004fb: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 000500: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 124 } 000503: 30 = 0xd (DW_TAG_member) 000504: DW_AT_name State 00050a: DW_AT_type indirect DW_FORM_ref2 0x539 00050d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 125 } 000510: 30 = 0xd (DW_TAG_member) 000511: DW_AT_name ErrorCode 00051b: DW_AT_type indirect DW_FORM_ref2 0x53d 00051e: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 128 } 000522: 0 null 000523: 34 = 0xf (DW_TAG_pointer_type) 000524: DW_AT_type indirect DW_FORM_ref_addr 0x2369+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 000529: 34 = 0xf (DW_TAG_pointer_type) 00052a: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00052f: 34 = 0xf (DW_TAG_pointer_type) 000530: DW_AT_type indirect DW_FORM_ref_addr 0x1a0+__ARM_grp..debug_info$stm32f7xx_hal_dma.h$.2_wD1100_gh0hnOcebnc_s10000 000535: 34 = 0xf (DW_TAG_pointer_type) 000536: DW_AT_type indirect DW_FORM_ref2 0x40f 000539: 116 = 0x35 (DW_TAG_volatile_type) 00053a: DW_AT_type indirect DW_FORM_ref2 0x18c 00053d: 116 = 0x35 (DW_TAG_volatile_type) 00053e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000543: 80 = 0x16 (DW_TAG_typedef) 000544: DW_AT_name SAI_HandleTypeDef 000556: DW_AT_type indirect DW_FORM_ref2 0x40f 000559: DW_AT_decl_file 0x1 00055a: DW_AT_decl_line 0xed 00055c: DW_AT_decl_column 0x2 00055d: 0 null 00055e: 0 padding 00055f: 0 padding ** Section #413 '.rel.debug_info' (SHT_REL) Size : 272 bytes (alignment 4) Symbol table #343 '.symtab' 34 relocations applied to section #234 '.debug_info' ** Section #235 '__ARM_grp.stm32f7xx_ll_sdmmc.h.2_QE5000_TMZRSJjRpce_n00000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #236 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 8788 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_LL_SDMMC_H 00001d: include at line 47 - file 2 000020: end include 000021: line 152 define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000U) 000054: line 153 define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE 000084: line 155 define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || ((EDGE) == SDMMC_CLOCK_EDGE_FALLING)) 0000ef: line 164 define SDMMC_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000U) 000125: line 165 define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS 000155: line 167 define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE)) 0001cc: line 176 define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U) 000206: line 177 define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV 00023a: line 179 define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE)) 0002b7: line 188 define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000U) 0002e4: line 189 define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0 00030e: line 190 define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1 000338: line 192 define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || ((WIDE) == SDMMC_BUS_WIDE_4B) || ((WIDE) == SDMMC_BUS_WIDE_8B)) 0003b5: line 202 define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U) 0003f4: line 203 define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN 00042e: line 205 define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE)) 0004c3: line 214 define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFF) 0004eb: line 222 define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40) 000519: line 230 define SDMMC_RESPONSE_NO ((uint32_t)0x00000000U) 000546: line 231 define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0 000573: line 232 define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP 00059d: line 234 define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || ((RESPONSE) == SDMMC_RESPONSE_SHORT) || ((RESPONSE) == SDMMC_RESPONSE_LONG)) 00062f: line 244 define SDMMC_WAIT_NO ((uint32_t)0x00000000U) 000658: line 245 define SDMMC_WAIT_IT SDMMC_CMD_WAITINT 00067b: line 246 define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND 0006a1: line 248 define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || ((WAIT) == SDMMC_WAIT_IT) || ((WAIT) == SDMMC_WAIT_PEND)) 000710: line 258 define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000U) 00073e: line 259 define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN 000764: line 261 define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || ((CPSM) == SDMMC_CPSM_ENABLE)) 0007bd: line 270 define SDMMC_RESP1 ((uint32_t)0x00000000U) 0007e4: line 271 define SDMMC_RESP2 ((uint32_t)0x00000004U) 00080b: line 272 define SDMMC_RESP3 ((uint32_t)0x00000008U) 000832: line 273 define SDMMC_RESP4 ((uint32_t)0x0000000C) 000858: line 275 define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || ((RESP) == SDMMC_RESP2) || ((RESP) == SDMMC_RESP3) || ((RESP) == SDMMC_RESP4)) 0008da: line 286 define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) 000913: line 294 define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U) 000946: line 295 define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0 00097a: line 296 define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1 0009ae: line 297 define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1) 0009fd: line 298 define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2 000a32: line 299 define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2) 000a82: line 300 define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) 000ad2: line 301 define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) 000b3c: line 302 define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3 000b72: line 303 define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3) 000bc3: line 304 define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) 000c15: line 305 define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) 000c80: line 306 define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 000cd2: line 307 define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 000d3d: line 308 define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 000da9: line 310 define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) 001027: line 332 define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U) 00105d: line 333 define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR 00108e: line 335 define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)) 0010fe: line 344 define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U) 001133: line 345 define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE 001164: line 347 define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || ((MODE) == SDMMC_TRANSFER_MODE_STREAM)) 0011d6: line 356 define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000U) 001204: line 357 define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN 00122a: line 359 define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) || ((DPSM) == SDMMC_DPSM_ENABLE)) 001283: line 368 define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U) 0012b9: line 369 define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD) 0012e9: line 371 define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || ((MODE) == SDMMC_READ_WAIT_MODE_DATA2)) 00135a: line 380 define SDMMC_IT_CCRCFAIL SDMMC_STA_CCRCFAIL 001382: line 381 define SDMMC_IT_DCRCFAIL SDMMC_STA_DCRCFAIL 0013aa: line 382 define SDMMC_IT_CTIMEOUT SDMMC_STA_CTIMEOUT 0013d2: line 383 define SDMMC_IT_DTIMEOUT SDMMC_STA_DTIMEOUT 0013fa: line 384 define SDMMC_IT_TXUNDERR SDMMC_STA_TXUNDERR 001422: line 385 define SDMMC_IT_RXOVERR SDMMC_STA_RXOVERR 001448: line 386 define SDMMC_IT_CMDREND SDMMC_STA_CMDREND 00146e: line 387 define SDMMC_IT_CMDSENT SDMMC_STA_CMDSENT 001494: line 388 define SDMMC_IT_DATAEND SDMMC_STA_DATAEND 0014ba: line 389 define SDMMC_IT_DBCKEND SDMMC_STA_DBCKEND 0014e0: line 390 define SDMMC_IT_CMDACT SDMMC_STA_CMDACT 001504: line 391 define SDMMC_IT_TXACT SDMMC_STA_TXACT 001526: line 392 define SDMMC_IT_RXACT SDMMC_STA_RXACT 001548: line 393 define SDMMC_IT_TXFIFOHE SDMMC_STA_TXFIFOHE 001570: line 394 define SDMMC_IT_RXFIFOHF SDMMC_STA_RXFIFOHF 001598: line 395 define SDMMC_IT_TXFIFOF SDMMC_STA_TXFIFOF 0015be: line 396 define SDMMC_IT_RXFIFOF SDMMC_STA_RXFIFOF 0015e4: line 397 define SDMMC_IT_TXFIFOE SDMMC_STA_TXFIFOE 00160a: line 398 define SDMMC_IT_RXFIFOE SDMMC_STA_RXFIFOE 001630: line 399 define SDMMC_IT_TXDAVL SDMMC_STA_TXDAVL 001654: line 400 define SDMMC_IT_RXDAVL SDMMC_STA_RXDAVL 001678: line 401 define SDMMC_IT_SDIOIT SDMMC_STA_SDIOIT 00169c: line 409 define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL 0016c6: line 410 define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL 0016f0: line 411 define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT 00171a: line 412 define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT 001744: line 413 define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR 00176e: line 414 define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR 001796: line 415 define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND 0017be: line 416 define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT 0017e6: line 417 define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND 00180e: line 418 define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND 001836: line 419 define SDMMC_FLAG_CMDACT SDMMC_STA_CMDACT 00185c: line 420 define SDMMC_FLAG_TXACT SDMMC_STA_TXACT 001880: line 421 define SDMMC_FLAG_RXACT SDMMC_STA_RXACT 0018a4: line 422 define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE 0018ce: line 423 define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF 0018f8: line 424 define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF 001920: line 425 define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF 001948: line 426 define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE 001970: line 427 define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE 001998: line 428 define SDMMC_FLAG_TXDAVL SDMMC_STA_TXDAVL 0019be: line 429 define SDMMC_FLAG_RXDAVL SDMMC_STA_RXDAVL 0019e4: line 430 define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT 001a0a: line 451 define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV | SDMMC_CLKCR_BYPASS | SDMMC_CLKCR_WIDBUS | SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN)) 001aaa: line 457 define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN | SDMMC_DCTRL_DTDIR | SDMMC_DCTRL_DTMODE | SDMMC_DCTRL_DBLOCKSIZE)) 001b1f: line 462 define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP | SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND | SDMMC_CMD_CPSMEN | SDMMC_CMD_SDIOSUSPEND)) 001bbb: line 467 define SDMMC_INIT_CLK_DIV ((uint8_t)0x76) 001be1: line 470 define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0) 001c0a: line 486 define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN) 001c57: line 493 define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN) 001ca6: line 500 define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN) 001cf7: line 506 define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN) 001d4a: line 537 define __SDMMC_ENABLE_IT(__INSTANCE__,__INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) 001da5: line 568 define __SDMMC_DISABLE_IT(__INSTANCE__,__INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) 001e02: line 599 define __SDMMC_GET_FLAG(__INSTANCE__,__FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET) 001e5a: line 620 define __SDMMC_CLEAR_FLAG(__INSTANCE__,__FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) 001eaa: line 651 define __SDMMC_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) 001f16: line 670 define __SDMMC_CLEAR_IT(__INSTANCE__,__INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) 001f6e: line 677 define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART) 001fcc: line 684 define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART) 00202c: line 691 define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP) 002088: line 698 define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP) 0020e6: line 705 define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN) 00213e: line 712 define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN) 002198: line 719 define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND) 0021f3: line 726 define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND) 002250: end include 002251: end of translation unit ** Section #237 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 124 bytes 000000: Header: length 120 (not including this field) version 3 prologue length 108 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_ll_sdmmc.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 6c 6c 5f 73 64 6d 6d 63 2e 68 00 01 00 00 00005e: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000075: file "" : 00 000076: DW_LNS_negate_stmt : 06 000077: DW_LNS_negate_stmt : 06 000078: DW_LNS_negate_stmt : 06 000079: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_sdmmc.h:1.0 [ ** Section #238 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 720 bytes 000000: Header: size 0x2cc bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_sdmmc.h 00004a: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000091: DW_AT_language DW_LANG_C89 000093: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010a: DW_AT_macro_info 0x0 00010e: DW_AT_stmt_list 0x0 000112: 42 = 0x13 (DW_TAG_structure_type) 000113: DW_AT_sibling 0x197 000115: DW_AT_byte_size 0x18 000116: 30 = 0xd (DW_TAG_member) 000117: DW_AT_name ClockEdge 000121: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000126: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000129: 30 = 0xd (DW_TAG_member) 00012a: DW_AT_name ClockBypass 000136: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00013b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00013e: 30 = 0xd (DW_TAG_member) 00013f: DW_AT_name ClockPowerSave 00014e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000153: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000156: 30 = 0xd (DW_TAG_member) 000157: DW_AT_name BusWide 00015f: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000164: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000167: 30 = 0xd (DW_TAG_member) 000168: DW_AT_name HardwareFlowControl 00017c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000181: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000184: 30 = 0xd (DW_TAG_member) 000185: DW_AT_name ClockDiv 00018e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000193: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 000196: 0 null 000197: 80 = 0x16 (DW_TAG_typedef) 000198: DW_AT_name SDMMC_InitTypeDef 0001aa: DW_AT_type indirect DW_FORM_ref2 0x112 0001ad: DW_AT_decl_file 0x1 0001ae: DW_AT_decl_line 0x57 0001af: DW_AT_decl_column 0x2 0001b0: 42 = 0x13 (DW_TAG_structure_type) 0001b1: DW_AT_sibling 0x213 0001b3: DW_AT_byte_size 0x14 0001b4: 30 = 0xd (DW_TAG_member) 0001b5: DW_AT_name Argument 0001be: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001c3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0001c6: 30 = 0xd (DW_TAG_member) 0001c7: DW_AT_name CmdIndex 0001d0: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001d5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0001d8: 30 = 0xd (DW_TAG_member) 0001d9: DW_AT_name Response 0001e2: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001e7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0001ea: 30 = 0xd (DW_TAG_member) 0001eb: DW_AT_name WaitForInterrupt 0001fc: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000201: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000204: 30 = 0xd (DW_TAG_member) 000205: DW_AT_name CPSM 00020a: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00020f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000212: 0 null 000213: 80 = 0x16 (DW_TAG_typedef) 000214: DW_AT_name SDMMC_CmdInitTypeDef 000229: DW_AT_type indirect DW_FORM_ref2 0x1b0 00022c: DW_AT_decl_file 0x1 00022d: DW_AT_decl_line 0x71 00022e: DW_AT_decl_column 0x2 00022f: 42 = 0x13 (DW_TAG_structure_type) 000230: DW_AT_sibling 0x2ad 000232: DW_AT_byte_size 0x18 000233: 30 = 0xd (DW_TAG_member) 000234: DW_AT_name DataTimeOut 000240: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000245: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000248: 30 = 0xd (DW_TAG_member) 000249: DW_AT_name DataLength 000254: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000259: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00025c: 30 = 0xd (DW_TAG_member) 00025d: DW_AT_name DataBlockSize 00026b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000270: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000273: 30 = 0xd (DW_TAG_member) 000274: DW_AT_name TransferDir 000280: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000285: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000288: 30 = 0xd (DW_TAG_member) 000289: DW_AT_name TransferMode 000296: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00029b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 00029e: 30 = 0xd (DW_TAG_member) 00029f: DW_AT_name DPSM 0002a4: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002a9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 0002ac: 0 null 0002ad: 80 = 0x16 (DW_TAG_typedef) 0002ae: DW_AT_name SDMMC_DataInitTypeDef 0002c4: DW_AT_type indirect DW_FORM_ref2 0x22f 0002c7: DW_AT_decl_file 0x1 0002c8: DW_AT_decl_line 0x8a 0002ca: DW_AT_decl_column 0x2 0002cb: 0 null 0002cc: 0 padding 0002cd: 0 padding 0002ce: 0 padding 0002cf: 0 padding ** Section #414 '.rel.debug_info' (SHT_REL) Size : 160 bytes (alignment 4) Symbol table #343 '.symtab' 20 relocations applied to section #238 '.debug_info' ** Section #239 '__ARM_grp.stm32f7xx_hal_sd.h.2_0O3100_i3HjtthYjXd_220000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #240 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 3896 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_SD_H 00001b: include at line 47 - file 2 00001e: end include 00001f: line 66 define SD_InitTypeDef SDMMC_InitTypeDef 000042: line 67 define SD_TypeDef SDMMC_TypeDef 00005d: line 330 define SD_CMD_GO_IDLE_STATE ((uint8_t)0U) 000083: line 331 define SD_CMD_SEND_OP_COND ((uint8_t)1U) 0000a8: line 332 define SD_CMD_ALL_SEND_CID ((uint8_t)2U) 0000cd: line 333 define SD_CMD_SET_REL_ADDR ((uint8_t)3U) 0000f2: line 334 define SD_CMD_SET_DSR ((uint8_t)4U) 000112: line 335 define SD_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) 00013c: line 337 define SD_CMD_HS_SWITCH ((uint8_t)6U) 00015e: line 338 define SD_CMD_SEL_DESEL_CARD ((uint8_t)7U) 000185: line 339 define SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) 0001ad: line 341 define SD_CMD_SEND_CSD ((uint8_t)9U) 0001ce: line 342 define SD_CMD_SEND_CID ((uint8_t)10U) 0001f0: line 343 define SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11U) 00021d: line 344 define SD_CMD_STOP_TRANSMISSION ((uint8_t)12U) 000248: line 345 define SD_CMD_SEND_STATUS ((uint8_t)13U) 00026d: line 346 define SD_CMD_HS_BUSTEST_READ ((uint8_t)14U) 000296: line 347 define SD_CMD_GO_INACTIVE_STATE ((uint8_t)15U) 0002c1: line 348 define SD_CMD_SET_BLOCKLEN ((uint8_t)16U) 0002e7: line 351 define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) 000312: line 353 define SD_CMD_READ_MULT_BLOCK ((uint8_t)18U) 00033b: line 355 define SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) 000365: line 356 define SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) 000393: line 357 define SD_CMD_SET_BLOCK_COUNT ((uint8_t)23U) 0003bc: line 358 define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) 0003e8: line 360 define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) 000412: line 361 define SD_CMD_PROG_CID ((uint8_t)26U) 000434: line 362 define SD_CMD_PROG_CSD ((uint8_t)27U) 000456: line 363 define SD_CMD_SET_WRITE_PROT ((uint8_t)28U) 00047e: line 364 define SD_CMD_CLR_WRITE_PROT ((uint8_t)29U) 0004a6: line 365 define SD_CMD_SEND_WRITE_PROT ((uint8_t)30U) 0004cf: line 366 define SD_CMD_SD_ERASE_GRP_START ((uint8_t)32U) 0004fb: line 367 define SD_CMD_SD_ERASE_GRP_END ((uint8_t)33U) 000525: line 368 define SD_CMD_ERASE_GRP_START ((uint8_t)35U) 00054e: line 370 define SD_CMD_ERASE_GRP_END ((uint8_t)36U) 000575: line 372 define SD_CMD_ERASE ((uint8_t)38U) 000594: line 373 define SD_CMD_FAST_IO ((uint8_t)39U) 0005b5: line 374 define SD_CMD_GO_IRQ_STATE ((uint8_t)40U) 0005db: line 375 define SD_CMD_LOCK_UNLOCK ((uint8_t)42U) 000600: line 377 define SD_CMD_APP_CMD ((uint8_t)55U) 000621: line 379 define SD_CMD_GEN_CMD ((uint8_t)56U) 000642: line 381 define SD_CMD_NO_CMD ((uint8_t)64U) 000662: line 387 define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) 00068e: line 389 define SD_CMD_SD_APP_STATUS ((uint8_t)13U) 0006b5: line 390 define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) 0006eb: line 392 define SD_CMD_SD_APP_OP_COND ((uint8_t)41U) 000713: line 394 define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) 000747: line 395 define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51U) 000770: line 396 define SD_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) 000799: line 397 define SD_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) 0007c4: line 403 define SD_CMD_SD_APP_GET_MKB ((uint8_t)43U) 0007ec: line 404 define SD_CMD_SD_APP_GET_MID ((uint8_t)44U) 000814: line 405 define SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U) 000840: line 406 define SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U) 00086c: line 407 define SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U) 000899: line 408 define SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U) 0008c6: line 409 define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U) 000901: line 410 define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U) 00093d: line 411 define SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U) 00096a: line 412 define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U) 00099d: line 413 define SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U) 0009ce: line 418 define STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000U) 000a03: line 419 define STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001U) 000a38: line 420 define HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002U) 000a69: line 421 define MULTIMEDIA_CARD ((uint32_t)0x00000003U) 000a94: line 422 define SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004U) 000ac6: line 423 define HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005U) 000afc: line 424 define SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006U) 000b34: line 425 define HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007U) 000b66: line 440 define __HAL_SD_SDMMC_ENABLE(__HANDLE__) __SDMMC_ENABLE((__HANDLE__)->Instance) 000bb2: line 446 define __HAL_SD_SDMMC_DISABLE(__HANDLE__) __SDMMC_DISABLE((__HANDLE__)->Instance) 000c00: line 452 define __HAL_SD_SDMMC_DMA_ENABLE(__HANDLE__) __SDMMC_DMA_ENABLE((__HANDLE__)->Instance) 000c54: line 458 define __HAL_SD_SDMMC_DMA_DISABLE(__HANDLE__) __SDMMC_DMA_DISABLE((__HANDLE__)->Instance) 000caa: line 489 define __HAL_SD_SDMMC_ENABLE_IT(__HANDLE__,__INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) 000d1b: line 520 define __HAL_SD_SDMMC_DISABLE_IT(__HANDLE__,__INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) 000d8e: line 551 define __HAL_SD_SDMMC_GET_FLAG(__HANDLE__,__FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__)) 000df3: line 571 define __HAL_SD_SDMMC_CLEAR_FLAG(__HANDLE__,__FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__)) 000e5c: line 602 define __HAL_SD_SDMMC_GET_IT(__HANDLE__,__INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__)) 000ec7: line 621 define __HAL_SD_SDMMC_CLEAR_IT(__HANDLE__,__INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__)) 000f36: end include 000f37: end of translation unit ** Section #241 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 120 bytes 000000: Header: length 116 (not including this field) version 3 prologue length 107 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_sd.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 73 64 2e 68 00 01 00 00 00005c: file "stm32f7xx_ll_sdmmc.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 6c 6c 5f 73 64 6d 6d 63 2e 68 00 01 00 00 000074: file "" : 00 000075: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_sd.h:1.0 ** Section #242 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 3336 bytes 000000: Header: size 0xd04 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_sd.h 000048: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 00008f: DW_AT_language DW_LANG_C89 000091: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 000108: DW_AT_macro_info 0x0 00010c: DW_AT_stmt_list 0x0 000110: 42 = 0x13 (DW_TAG_structure_type) 000111: DW_AT_sibling 0x1fd 000113: DW_AT_byte_size 0x60 000114: 30 = 0xd (DW_TAG_member) 000115: DW_AT_name Instance 00011e: DW_AT_type indirect DW_FORM_ref2 0x1fd 000121: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000124: 30 = 0xd (DW_TAG_member) 000125: DW_AT_name Init 00012a: DW_AT_type indirect DW_FORM_ref_addr 0x197+__ARM_grp..debug_info$stm32f7xx_ll_sdmmc.h$.2_QE5000_TMZRSJjRpce_n00000 00012f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000132: 30 = 0xd (DW_TAG_member) 000133: DW_AT_name Lock 000138: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 00013d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 000140: 30 = 0xd (DW_TAG_member) 000141: DW_AT_name CardType 00014a: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00014f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 000152: 30 = 0xd (DW_TAG_member) 000153: DW_AT_name RCA 000157: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00015c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 00015f: 3 = 0x1 (DW_TAG_array_type) 000160: DW_AT_sibling 0x16a 000162: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000167: 1 = 0x21 (DW_TAG_subrange_type) 000168: DW_AT_upper_bound 0x3 000169: 0 null 00016a: 30 = 0xd (DW_TAG_member) 00016b: DW_AT_name CSD 00016f: DW_AT_type indirect DW_FORM_ref2 0x15f 000172: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 000175: 3 = 0x1 (DW_TAG_array_type) 000176: DW_AT_sibling 0x180 000178: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00017d: 1 = 0x21 (DW_TAG_subrange_type) 00017e: DW_AT_upper_bound 0x3 00017f: 0 null 000180: 30 = 0xd (DW_TAG_member) 000181: DW_AT_name CID 000185: DW_AT_type indirect DW_FORM_ref2 0x175 000188: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 00018b: 30 = 0xd (DW_TAG_member) 00018c: DW_AT_name SdTransferCplt 00019b: DW_AT_type indirect DW_FORM_ref2 0x203 00019e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 72 } 0001a1: 30 = 0xd (DW_TAG_member) 0001a2: DW_AT_name SdTransferErr 0001b0: DW_AT_type indirect DW_FORM_ref2 0x203 0001b3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 76 } 0001b6: 30 = 0xd (DW_TAG_member) 0001b7: DW_AT_name DmaTransferCplt 0001c7: DW_AT_type indirect DW_FORM_ref2 0x203 0001ca: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 80 } 0001cd: 30 = 0xd (DW_TAG_member) 0001ce: DW_AT_name SdOperation 0001da: DW_AT_type indirect DW_FORM_ref2 0x203 0001dd: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 84 } 0001e0: 30 = 0xd (DW_TAG_member) 0001e1: DW_AT_name hdmarx 0001e8: DW_AT_type indirect DW_FORM_ref2 0x209 0001eb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 88 } 0001ee: 30 = 0xd (DW_TAG_member) 0001ef: DW_AT_name hdmatx 0001f6: DW_AT_type indirect DW_FORM_ref2 0x209 0001f9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 92 } 0001fc: 0 null 0001fd: 34 = 0xf (DW_TAG_pointer_type) 0001fe: DW_AT_type indirect DW_FORM_ref_addr 0x2519+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 000203: 116 = 0x35 (DW_TAG_volatile_type) 000204: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000209: 34 = 0xf (DW_TAG_pointer_type) 00020a: DW_AT_type indirect DW_FORM_ref_addr 0x1a0+__ARM_grp..debug_info$stm32f7xx_hal_dma.h$.2_wD1100_gh0hnOcebnc_s10000 00020f: 80 = 0x16 (DW_TAG_typedef) 000210: DW_AT_name SD_HandleTypeDef 000221: DW_AT_type indirect DW_FORM_ref2 0x110 000224: DW_AT_decl_file 0x1 000225: DW_AT_decl_line 0x61 000226: DW_AT_decl_column 0x2 000227: 42 = 0x13 (DW_TAG_structure_type) 000228: DW_AT_sibling 0x511 00022a: DW_AT_byte_size 0x2c 00022b: 30 = 0xd (DW_TAG_member) 00022c: DW_AT_name CSDStruct 000236: DW_AT_type indirect DW_FORM_ref2 0x511 000239: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00023c: 30 = 0xd (DW_TAG_member) 00023d: DW_AT_name SysSpecVersion 00024c: DW_AT_type indirect DW_FORM_ref2 0x511 00024f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 1 } 000252: 30 = 0xd (DW_TAG_member) 000253: DW_AT_name Reserved1 00025d: DW_AT_type indirect DW_FORM_ref2 0x511 000260: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 2 } 000263: 30 = 0xd (DW_TAG_member) 000264: DW_AT_name TAAC 000269: DW_AT_type indirect DW_FORM_ref2 0x511 00026c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 3 } 00026f: 30 = 0xd (DW_TAG_member) 000270: DW_AT_name NSAC 000275: DW_AT_type indirect DW_FORM_ref2 0x511 000278: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00027b: 30 = 0xd (DW_TAG_member) 00027c: DW_AT_name MaxBusClkFrec 00028a: DW_AT_type indirect DW_FORM_ref2 0x511 00028d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 5 } 000290: 30 = 0xd (DW_TAG_member) 000291: DW_AT_name CardComdClasses 0002a1: DW_AT_type indirect DW_FORM_ref2 0x517 0002a4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 6 } 0002a7: 30 = 0xd (DW_TAG_member) 0002a8: DW_AT_name RdBlockLen 0002b3: DW_AT_type indirect DW_FORM_ref2 0x511 0002b6: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0002b9: 30 = 0xd (DW_TAG_member) 0002ba: DW_AT_name PartBlockRead 0002c8: DW_AT_type indirect DW_FORM_ref2 0x511 0002cb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 9 } 0002ce: 30 = 0xd (DW_TAG_member) 0002cf: DW_AT_name WrBlockMisalign 0002df: DW_AT_type indirect DW_FORM_ref2 0x511 0002e2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 10 } 0002e5: 30 = 0xd (DW_TAG_member) 0002e6: DW_AT_name RdBlockMisalign 0002f6: DW_AT_type indirect DW_FORM_ref2 0x511 0002f9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 11 } 0002fc: 30 = 0xd (DW_TAG_member) 0002fd: DW_AT_name DSRImpl 000305: DW_AT_type indirect DW_FORM_ref2 0x511 000308: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00030b: 30 = 0xd (DW_TAG_member) 00030c: DW_AT_name Reserved2 000316: DW_AT_type indirect DW_FORM_ref2 0x511 000319: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 13 } 00031c: 30 = 0xd (DW_TAG_member) 00031d: DW_AT_name DeviceSize 000328: DW_AT_type indirect DW_FORM_ref2 0x203 00032b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 00032e: 30 = 0xd (DW_TAG_member) 00032f: DW_AT_name MaxRdCurrentVDDMin 000342: DW_AT_type indirect DW_FORM_ref2 0x511 000345: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 000348: 30 = 0xd (DW_TAG_member) 000349: DW_AT_name MaxRdCurrentVDDMax 00035c: DW_AT_type indirect DW_FORM_ref2 0x511 00035f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 21 } 000362: 30 = 0xd (DW_TAG_member) 000363: DW_AT_name MaxWrCurrentVDDMin 000376: DW_AT_type indirect DW_FORM_ref2 0x511 000379: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 22 } 00037c: 30 = 0xd (DW_TAG_member) 00037d: DW_AT_name MaxWrCurrentVDDMax 000390: DW_AT_type indirect DW_FORM_ref2 0x511 000393: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 23 } 000396: 30 = 0xd (DW_TAG_member) 000397: DW_AT_name DeviceSizeMul 0003a5: DW_AT_type indirect DW_FORM_ref2 0x511 0003a8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 0003ab: 30 = 0xd (DW_TAG_member) 0003ac: DW_AT_name EraseGrSize 0003b8: DW_AT_type indirect DW_FORM_ref2 0x511 0003bb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 25 } 0003be: 30 = 0xd (DW_TAG_member) 0003bf: DW_AT_name EraseGrMul 0003ca: DW_AT_type indirect DW_FORM_ref2 0x511 0003cd: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 26 } 0003d0: 30 = 0xd (DW_TAG_member) 0003d1: DW_AT_name WrProtectGrSize 0003e1: DW_AT_type indirect DW_FORM_ref2 0x511 0003e4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 27 } 0003e7: 30 = 0xd (DW_TAG_member) 0003e8: DW_AT_name WrProtectGrEnable 0003fa: DW_AT_type indirect DW_FORM_ref2 0x511 0003fd: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 000400: 30 = 0xd (DW_TAG_member) 000401: DW_AT_name ManDeflECC 00040c: DW_AT_type indirect DW_FORM_ref2 0x511 00040f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 29 } 000412: 30 = 0xd (DW_TAG_member) 000413: DW_AT_name WrSpeedFact 00041f: DW_AT_type indirect DW_FORM_ref2 0x511 000422: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 30 } 000425: 30 = 0xd (DW_TAG_member) 000426: DW_AT_name MaxWrBlockLen 000434: DW_AT_type indirect DW_FORM_ref2 0x511 000437: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 31 } 00043a: 30 = 0xd (DW_TAG_member) 00043b: DW_AT_name WriteBlockPaPartial 00044f: DW_AT_type indirect DW_FORM_ref2 0x511 000452: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 000455: 30 = 0xd (DW_TAG_member) 000456: DW_AT_name Reserved3 000460: DW_AT_type indirect DW_FORM_ref2 0x511 000463: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 33 } 000466: 30 = 0xd (DW_TAG_member) 000467: DW_AT_name ContentProtectAppli 00047b: DW_AT_type indirect DW_FORM_ref2 0x511 00047e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 34 } 000481: 30 = 0xd (DW_TAG_member) 000482: DW_AT_name FileFormatGrouop 000493: DW_AT_type indirect DW_FORM_ref2 0x511 000496: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 35 } 000499: 30 = 0xd (DW_TAG_member) 00049a: DW_AT_name CopyFlag 0004a3: DW_AT_type indirect DW_FORM_ref2 0x511 0004a6: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 0004a9: 30 = 0xd (DW_TAG_member) 0004aa: DW_AT_name PermWrProtect 0004b8: DW_AT_type indirect DW_FORM_ref2 0x511 0004bb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 37 } 0004be: 30 = 0xd (DW_TAG_member) 0004bf: DW_AT_name TempWrProtect 0004cd: DW_AT_type indirect DW_FORM_ref2 0x511 0004d0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 38 } 0004d3: 30 = 0xd (DW_TAG_member) 0004d4: DW_AT_name FileFormat 0004df: DW_AT_type indirect DW_FORM_ref2 0x511 0004e2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 39 } 0004e5: 30 = 0xd (DW_TAG_member) 0004e6: DW_AT_name ECC 0004ea: DW_AT_type indirect DW_FORM_ref2 0x511 0004ed: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 0004f0: 30 = 0xd (DW_TAG_member) 0004f1: DW_AT_name CSD_CRC 0004f9: DW_AT_type indirect DW_FORM_ref2 0x511 0004fc: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 41 } 0004ff: 30 = 0xd (DW_TAG_member) 000500: DW_AT_name Reserved4 00050a: DW_AT_type indirect DW_FORM_ref2 0x511 00050d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 42 } 000510: 0 null 000511: 116 = 0x35 (DW_TAG_volatile_type) 000512: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000517: 116 = 0x35 (DW_TAG_volatile_type) 000518: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00051d: 80 = 0x16 (DW_TAG_typedef) 00051e: DW_AT_name HAL_SD_CSDTypedef 000530: DW_AT_type indirect DW_FORM_ref2 0x227 000533: DW_AT_decl_file 0x1 000534: DW_AT_decl_line 0x91 000536: DW_AT_decl_column 0x2 000537: 42 = 0x13 (DW_TAG_structure_type) 000538: DW_AT_sibling 0x5e9 00053a: DW_AT_byte_size 0x18 00053b: 30 = 0xd (DW_TAG_member) 00053c: DW_AT_name ManufacturerID 00054b: DW_AT_type indirect DW_FORM_ref2 0x511 00054e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000551: 30 = 0xd (DW_TAG_member) 000552: DW_AT_name OEM_AppliID 00055e: DW_AT_type indirect DW_FORM_ref2 0x517 000561: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 2 } 000564: 30 = 0xd (DW_TAG_member) 000565: DW_AT_name ProdName1 00056f: DW_AT_type indirect DW_FORM_ref2 0x203 000572: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000575: 30 = 0xd (DW_TAG_member) 000576: DW_AT_name ProdName2 000580: DW_AT_type indirect DW_FORM_ref2 0x511 000583: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000586: 30 = 0xd (DW_TAG_member) 000587: DW_AT_name ProdRev 00058f: DW_AT_type indirect DW_FORM_ref2 0x511 000592: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 9 } 000595: 30 = 0xd (DW_TAG_member) 000596: DW_AT_name ProdSN 00059d: DW_AT_type indirect DW_FORM_ref2 0x203 0005a0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0005a3: 30 = 0xd (DW_TAG_member) 0005a4: DW_AT_name Reserved1 0005ae: DW_AT_type indirect DW_FORM_ref2 0x511 0005b1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 0005b4: 30 = 0xd (DW_TAG_member) 0005b5: DW_AT_name ManufactDate 0005c2: DW_AT_type indirect DW_FORM_ref2 0x517 0005c5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 18 } 0005c8: 30 = 0xd (DW_TAG_member) 0005c9: DW_AT_name CID_CRC 0005d1: DW_AT_type indirect DW_FORM_ref2 0x511 0005d4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 0005d7: 30 = 0xd (DW_TAG_member) 0005d8: DW_AT_name Reserved2 0005e2: DW_AT_type indirect DW_FORM_ref2 0x511 0005e5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 21 } 0005e8: 0 null 0005e9: 80 = 0x16 (DW_TAG_typedef) 0005ea: DW_AT_name HAL_SD_CIDTypedef 0005fc: DW_AT_type indirect DW_FORM_ref2 0x537 0005ff: DW_AT_decl_file 0x1 000600: DW_AT_decl_line 0xa6 000602: DW_AT_decl_column 0x2 000603: 42 = 0x13 (DW_TAG_structure_type) 000604: DW_AT_sibling 0x6d8 000606: DW_AT_byte_size 0x10 000607: 30 = 0xd (DW_TAG_member) 000608: DW_AT_name DAT_BUS_WIDTH 000616: DW_AT_type indirect DW_FORM_ref2 0x511 000619: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00061c: 30 = 0xd (DW_TAG_member) 00061d: DW_AT_name SECURED_MODE 00062a: DW_AT_type indirect DW_FORM_ref2 0x511 00062d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 1 } 000630: 30 = 0xd (DW_TAG_member) 000631: DW_AT_name SD_CARD_TYPE 00063e: DW_AT_type indirect DW_FORM_ref2 0x517 000641: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 2 } 000644: 30 = 0xd (DW_TAG_member) 000645: DW_AT_name SIZE_OF_PROTECTED_AREA 00065c: DW_AT_type indirect DW_FORM_ref2 0x203 00065f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000662: 30 = 0xd (DW_TAG_member) 000663: DW_AT_name SPEED_CLASS 00066f: DW_AT_type indirect DW_FORM_ref2 0x511 000672: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000675: 30 = 0xd (DW_TAG_member) 000676: DW_AT_name PERFORMANCE_MOVE 000687: DW_AT_type indirect DW_FORM_ref2 0x511 00068a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 9 } 00068d: 30 = 0xd (DW_TAG_member) 00068e: DW_AT_name AU_SIZE 000696: DW_AT_type indirect DW_FORM_ref2 0x511 000699: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 10 } 00069c: 30 = 0xd (DW_TAG_member) 00069d: DW_AT_name ERASE_SIZE 0006a8: DW_AT_type indirect DW_FORM_ref2 0x517 0006ab: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0006ae: 30 = 0xd (DW_TAG_member) 0006af: DW_AT_name ERASE_TIMEOUT 0006bd: DW_AT_type indirect DW_FORM_ref2 0x511 0006c0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 14 } 0006c3: 30 = 0xd (DW_TAG_member) 0006c4: DW_AT_name ERASE_OFFSET 0006d1: DW_AT_type indirect DW_FORM_ref2 0x511 0006d4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 15 } 0006d7: 0 null 0006d8: 80 = 0x16 (DW_TAG_typedef) 0006d9: DW_AT_name HAL_SD_CardStatusTypedef 0006f2: DW_AT_type indirect DW_FORM_ref2 0x603 0006f5: DW_AT_decl_file 0x1 0006f6: DW_AT_decl_line 0xbb 0006f8: DW_AT_decl_column 0x2 0006f9: 42 = 0x13 (DW_TAG_structure_type) 0006fa: DW_AT_sibling 0x766 0006fc: DW_AT_byte_size 0x58 0006fd: 30 = 0xd (DW_TAG_member) 0006fe: DW_AT_name SD_csd 000705: DW_AT_type indirect DW_FORM_ref2 0x51d 000708: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00070b: 30 = 0xd (DW_TAG_member) 00070c: DW_AT_name SD_cid 000713: DW_AT_type indirect DW_FORM_ref2 0x5e9 000716: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 000719: 30 = 0xd (DW_TAG_member) 00071a: DW_AT_name CardCapacity 000727: DW_AT_type indirect DW_FORM_ref_addr 0x17d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00072c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 72 } 00072f: 30 = 0xd (DW_TAG_member) 000730: DW_AT_name CardBlockSize 00073e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000743: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 80 } 000746: 30 = 0xd (DW_TAG_member) 000747: DW_AT_name RCA 00074b: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000750: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 84 } 000753: 30 = 0xd (DW_TAG_member) 000754: DW_AT_name CardType 00075d: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000762: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 86 } 000765: 0 null 000766: 80 = 0x16 (DW_TAG_typedef) 000767: DW_AT_name HAL_SD_CardInfoTypedef 00077e: DW_AT_type indirect DW_FORM_ref2 0x6f9 000781: DW_AT_decl_file 0x1 000782: DW_AT_decl_line 0xcc 000784: DW_AT_decl_column 0x2 000785: 19 = 0x4 (DW_TAG_enumeration_type) 000786: DW_AT_sibling 0xb1c 000788: DW_AT_byte_size 0x1 000789: 20 = 0x28 (DW_TAG_enumerator) 00078a: DW_AT_name SD_CMD_CRC_FAIL 00079a: DW_AT_const_value indirect DW_FORM_data1 0x1 00079c: 20 = 0x28 (DW_TAG_enumerator) 00079d: DW_AT_name SD_DATA_CRC_FAIL 0007ae: DW_AT_const_value indirect DW_FORM_data1 0x2 0007b0: 20 = 0x28 (DW_TAG_enumerator) 0007b1: DW_AT_name SD_CMD_RSP_TIMEOUT 0007c4: DW_AT_const_value indirect DW_FORM_data1 0x3 0007c6: 20 = 0x28 (DW_TAG_enumerator) 0007c7: DW_AT_name SD_DATA_TIMEOUT 0007d7: DW_AT_const_value indirect DW_FORM_data1 0x4 0007d9: 20 = 0x28 (DW_TAG_enumerator) 0007da: DW_AT_name SD_TX_UNDERRUN 0007e9: DW_AT_const_value indirect DW_FORM_data1 0x5 0007eb: 20 = 0x28 (DW_TAG_enumerator) 0007ec: DW_AT_name SD_RX_OVERRUN 0007fa: DW_AT_const_value indirect DW_FORM_data1 0x6 0007fc: 20 = 0x28 (DW_TAG_enumerator) 0007fd: DW_AT_name SD_START_BIT_ERR 00080e: DW_AT_const_value indirect DW_FORM_data1 0x7 000810: 20 = 0x28 (DW_TAG_enumerator) 000811: DW_AT_name SD_CMD_OUT_OF_RANGE 000825: DW_AT_const_value indirect DW_FORM_data1 0x8 000827: 20 = 0x28 (DW_TAG_enumerator) 000828: DW_AT_name SD_ADDR_MISALIGNED 00083b: DW_AT_const_value indirect DW_FORM_data1 0x9 00083d: 20 = 0x28 (DW_TAG_enumerator) 00083e: DW_AT_name SD_BLOCK_LEN_ERR 00084f: DW_AT_const_value indirect DW_FORM_data1 0xa 000851: 20 = 0x28 (DW_TAG_enumerator) 000852: DW_AT_name SD_ERASE_SEQ_ERR 000863: DW_AT_const_value indirect DW_FORM_data1 0xb 000865: 20 = 0x28 (DW_TAG_enumerator) 000866: DW_AT_name SD_BAD_ERASE_PARAM 000879: DW_AT_const_value indirect DW_FORM_data1 0xc 00087b: 20 = 0x28 (DW_TAG_enumerator) 00087c: DW_AT_name SD_WRITE_PROT_VIOLATION 000894: DW_AT_const_value indirect DW_FORM_data1 0xd 000896: 20 = 0x28 (DW_TAG_enumerator) 000897: DW_AT_name SD_LOCK_UNLOCK_FAILED 0008ad: DW_AT_const_value indirect DW_FORM_data1 0xe 0008af: 20 = 0x28 (DW_TAG_enumerator) 0008b0: DW_AT_name SD_COM_CRC_FAILED 0008c2: DW_AT_const_value indirect DW_FORM_data1 0xf 0008c4: 20 = 0x28 (DW_TAG_enumerator) 0008c5: DW_AT_name SD_ILLEGAL_CMD 0008d4: DW_AT_const_value indirect DW_FORM_data1 0x10 0008d6: 20 = 0x28 (DW_TAG_enumerator) 0008d7: DW_AT_name SD_CARD_ECC_FAILED 0008ea: DW_AT_const_value indirect DW_FORM_data1 0x11 0008ec: 20 = 0x28 (DW_TAG_enumerator) 0008ed: DW_AT_name SD_CC_ERROR 0008f9: DW_AT_const_value indirect DW_FORM_data1 0x12 0008fb: 20 = 0x28 (DW_TAG_enumerator) 0008fc: DW_AT_name SD_GENERAL_UNKNOWN_ERROR 000915: DW_AT_const_value indirect DW_FORM_data1 0x13 000917: 20 = 0x28 (DW_TAG_enumerator) 000918: DW_AT_name SD_STREAM_READ_UNDERRUN 000930: DW_AT_const_value indirect DW_FORM_data1 0x14 000932: 20 = 0x28 (DW_TAG_enumerator) 000933: DW_AT_name SD_STREAM_WRITE_OVERRUN 00094b: DW_AT_const_value indirect DW_FORM_data1 0x15 00094d: 20 = 0x28 (DW_TAG_enumerator) 00094e: DW_AT_name SD_CID_CSD_OVERWRITE 000963: DW_AT_const_value indirect DW_FORM_data1 0x16 000965: 20 = 0x28 (DW_TAG_enumerator) 000966: DW_AT_name SD_WP_ERASE_SKIP 000977: DW_AT_const_value indirect DW_FORM_data1 0x17 000979: 20 = 0x28 (DW_TAG_enumerator) 00097a: DW_AT_name SD_CARD_ECC_DISABLED 00098f: DW_AT_const_value indirect DW_FORM_data1 0x18 000991: 20 = 0x28 (DW_TAG_enumerator) 000992: DW_AT_name SD_ERASE_RESET 0009a1: DW_AT_const_value indirect DW_FORM_data1 0x19 0009a3: 20 = 0x28 (DW_TAG_enumerator) 0009a4: DW_AT_name SD_AKE_SEQ_ERROR 0009b5: DW_AT_const_value indirect DW_FORM_data1 0x1a 0009b7: 20 = 0x28 (DW_TAG_enumerator) 0009b8: DW_AT_name SD_INVALID_VOLTRANGE 0009cd: DW_AT_const_value indirect DW_FORM_data1 0x1b 0009cf: 20 = 0x28 (DW_TAG_enumerator) 0009d0: DW_AT_name SD_ADDR_OUT_OF_RANGE 0009e5: DW_AT_const_value indirect DW_FORM_data1 0x1c 0009e7: 20 = 0x28 (DW_TAG_enumerator) 0009e8: DW_AT_name SD_SWITCH_ERROR 0009f8: DW_AT_const_value indirect DW_FORM_data1 0x1d 0009fa: 20 = 0x28 (DW_TAG_enumerator) 0009fb: DW_AT_name SD_SDMMC_DISABLED 000a0d: DW_AT_const_value indirect DW_FORM_data1 0x1e 000a0f: 20 = 0x28 (DW_TAG_enumerator) 000a10: DW_AT_name SD_SDMMC_FUNCTION_BUSY 000a27: DW_AT_const_value indirect DW_FORM_data1 0x1f 000a29: 20 = 0x28 (DW_TAG_enumerator) 000a2a: DW_AT_name SD_SDMMC_FUNCTION_FAILED 000a43: DW_AT_const_value indirect DW_FORM_data1 0x20 000a45: 20 = 0x28 (DW_TAG_enumerator) 000a46: DW_AT_name SD_SDMMC_UNKNOWN_FUNCTION 000a60: DW_AT_const_value indirect DW_FORM_data1 0x21 000a62: 20 = 0x28 (DW_TAG_enumerator) 000a63: DW_AT_name SD_INTERNAL_ERROR 000a75: DW_AT_const_value indirect DW_FORM_data1 0x22 000a77: 20 = 0x28 (DW_TAG_enumerator) 000a78: DW_AT_name SD_NOT_CONFIGURED 000a8a: DW_AT_const_value indirect DW_FORM_data1 0x23 000a8c: 20 = 0x28 (DW_TAG_enumerator) 000a8d: DW_AT_name SD_REQUEST_PENDING 000aa0: DW_AT_const_value indirect DW_FORM_data1 0x24 000aa2: 20 = 0x28 (DW_TAG_enumerator) 000aa3: DW_AT_name SD_REQUEST_NOT_APPLICABLE 000abd: DW_AT_const_value indirect DW_FORM_data1 0x25 000abf: 20 = 0x28 (DW_TAG_enumerator) 000ac0: DW_AT_name SD_INVALID_PARAMETER 000ad5: DW_AT_const_value indirect DW_FORM_data1 0x26 000ad7: 20 = 0x28 (DW_TAG_enumerator) 000ad8: DW_AT_name SD_UNSUPPORTED_FEATURE 000aef: DW_AT_const_value indirect DW_FORM_data1 0x27 000af1: 20 = 0x28 (DW_TAG_enumerator) 000af2: DW_AT_name SD_UNSUPPORTED_HW 000b04: DW_AT_const_value indirect DW_FORM_data1 0x28 000b06: 20 = 0x28 (DW_TAG_enumerator) 000b07: DW_AT_name SD_ERROR 000b10: DW_AT_const_value indirect DW_FORM_data1 0x29 000b12: 20 = 0x28 (DW_TAG_enumerator) 000b13: DW_AT_name SD_OK 000b19: DW_AT_const_value indirect DW_FORM_data1 0x0 000b1b: 0 null 000b1c: 80 = 0x16 (DW_TAG_typedef) 000b1d: DW_AT_name HAL_SD_ErrorTypedef 000b31: DW_AT_type indirect DW_FORM_ref2 0x785 000b34: DW_AT_decl_file 0x1 000b35: DW_AT_decl_line 0x108 000b37: DW_AT_decl_column 0x2 000b38: 19 = 0x4 (DW_TAG_enumeration_type) 000b39: DW_AT_sibling 0xb78 000b3b: DW_AT_byte_size 0x1 000b3c: 20 = 0x28 (DW_TAG_enumerator) 000b3d: DW_AT_name SD_TRANSFER_OK 000b4c: DW_AT_const_value indirect DW_FORM_data1 0x0 000b4e: 20 = 0x28 (DW_TAG_enumerator) 000b4f: DW_AT_name SD_TRANSFER_BUSY 000b60: DW_AT_const_value indirect DW_FORM_data1 0x1 000b62: 20 = 0x28 (DW_TAG_enumerator) 000b63: DW_AT_name SD_TRANSFER_ERROR 000b75: DW_AT_const_value indirect DW_FORM_data1 0x2 000b77: 0 null 000b78: 80 = 0x16 (DW_TAG_typedef) 000b79: DW_AT_name HAL_SD_TransferStateTypedef 000b95: DW_AT_type indirect DW_FORM_ref2 0xb38 000b98: DW_AT_decl_file 0x1 000b99: DW_AT_decl_line 0x116 000b9b: DW_AT_decl_column 0x2 000b9c: 19 = 0x4 (DW_TAG_enumeration_type) 000b9d: DW_AT_sibling 0xc5b 000b9f: DW_AT_byte_size 0x1 000ba0: 20 = 0x28 (DW_TAG_enumerator) 000ba1: DW_AT_name SD_CARD_READY 000baf: DW_AT_const_value indirect DW_FORM_data1 0x1 000bb1: 20 = 0x28 (DW_TAG_enumerator) 000bb2: DW_AT_name SD_CARD_IDENTIFICATION 000bc9: DW_AT_const_value indirect DW_FORM_data1 0x2 000bcb: 20 = 0x28 (DW_TAG_enumerator) 000bcc: DW_AT_name SD_CARD_STANDBY 000bdc: DW_AT_const_value indirect DW_FORM_data1 0x3 000bde: 20 = 0x28 (DW_TAG_enumerator) 000bdf: DW_AT_name SD_CARD_TRANSFER 000bf0: DW_AT_const_value indirect DW_FORM_data1 0x4 000bf2: 20 = 0x28 (DW_TAG_enumerator) 000bf3: DW_AT_name SD_CARD_SENDING 000c03: DW_AT_const_value indirect DW_FORM_data1 0x5 000c05: 20 = 0x28 (DW_TAG_enumerator) 000c06: DW_AT_name SD_CARD_RECEIVING 000c18: DW_AT_const_value indirect DW_FORM_data1 0x6 000c1a: 20 = 0x28 (DW_TAG_enumerator) 000c1b: DW_AT_name SD_CARD_PROGRAMMING 000c2f: DW_AT_const_value indirect DW_FORM_data1 0x7 000c31: 20 = 0x28 (DW_TAG_enumerator) 000c32: DW_AT_name SD_CARD_DISCONNECTED 000c47: DW_AT_const_value indirect DW_FORM_data1 0x8 000c49: 20 = 0x28 (DW_TAG_enumerator) 000c4a: DW_AT_name SD_CARD_ERROR 000c58: DW_AT_const_value indirect DW_FORM_data1 0xff 000c5a: 0 null 000c5b: 80 = 0x16 (DW_TAG_typedef) 000c5c: DW_AT_name HAL_SD_CardStateTypedef 000c74: DW_AT_type indirect DW_FORM_ref2 0xb9c 000c77: DW_AT_decl_file 0x1 000c78: DW_AT_decl_line 0x12a 000c7a: DW_AT_decl_column 0x2 000c7b: 19 = 0x4 (DW_TAG_enumeration_type) 000c7c: DW_AT_sibling 0xce6 000c7e: DW_AT_byte_size 0x1 000c7f: 20 = 0x28 (DW_TAG_enumerator) 000c80: DW_AT_name SD_READ_SINGLE_BLOCK 000c95: DW_AT_const_value indirect DW_FORM_data1 0x0 000c97: 20 = 0x28 (DW_TAG_enumerator) 000c98: DW_AT_name SD_READ_MULTIPLE_BLOCK 000caf: DW_AT_const_value indirect DW_FORM_data1 0x1 000cb1: 20 = 0x28 (DW_TAG_enumerator) 000cb2: DW_AT_name SD_WRITE_SINGLE_BLOCK 000cc8: DW_AT_const_value indirect DW_FORM_data1 0x2 000cca: 20 = 0x28 (DW_TAG_enumerator) 000ccb: DW_AT_name SD_WRITE_MULTIPLE_BLOCK 000ce3: DW_AT_const_value indirect DW_FORM_data1 0x3 000ce5: 0 null 000ce6: 80 = 0x16 (DW_TAG_typedef) 000ce7: DW_AT_name HAL_SD_OperationTypedef 000cff: DW_AT_type indirect DW_FORM_ref2 0xc7b 000d02: DW_AT_decl_file 0x1 000d03: DW_AT_decl_line 0x139 000d05: DW_AT_decl_column 0x2 000d06: 0 null 000d07: 0 padding ** Section #415 '.rel.debug_info' (SHT_REL) Size : 144 bytes (alignment 4) Symbol table #343 '.symtab' 18 relocations applied to section #242 '.debug_info' ** Section #243 '__ARM_grp.stm32f7xx_hal_spdifrx.h.2_4m1100_B9vfbf75J1a_R10000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #244 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 4776 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_SPDIFRX_H 000020: include at line 49 - file 2 000023: end include 000024: line 192 define HAL_SPDIFRX_ERROR_NONE ((uint32_t)0x00000000U) 000056: line 193 define HAL_SPDIFRX_ERROR_TIMEOUT ((uint32_t)0x00000001U) 00008b: line 194 define HAL_SPDIFRX_ERROR_OVR ((uint32_t)0x00000002U) 0000bc: line 195 define HAL_SPDIFRX_ERROR_PE ((uint32_t)0x00000004U) 0000ec: line 196 define HAL_SPDIFRX_ERROR_DMA ((uint32_t)0x00000008U) 00011d: line 197 define HAL_SPDIFRX_ERROR_UNKNOWN ((uint32_t)0x00000010U) 000152: line 205 define SPDIFRX_INPUT_IN0 ((uint32_t)0x00000000U) 00017f: line 206 define SPDIFRX_INPUT_IN1 ((uint32_t)0x00010000U) 0001ac: line 207 define SPDIFRX_INPUT_IN2 ((uint32_t)0x00020000U) 0001d9: line 208 define SPDIFRX_INPUT_IN3 ((uint32_t)0x00030000U) 000206: line 216 define SPDIFRX_MAXRETRIES_NONE ((uint32_t)0x00000000U) 000239: line 217 define SPDIFRX_MAXRETRIES_3 ((uint32_t)0x00001000U) 000269: line 218 define SPDIFRX_MAXRETRIES_15 ((uint32_t)0x00002000U) 00029a: line 219 define SPDIFRX_MAXRETRIES_63 ((uint32_t)0x00003000U) 0002cb: line 227 define SPDIFRX_WAITFORACTIVITY_OFF ((uint32_t)0x00000000U) 000302: line 228 define SPDIFRX_WAITFORACTIVITY_ON ((uint32_t)SPDIFRX_CR_WFA) 00033b: line 236 define SPDIFRX_PREAMBLETYPEMASK_OFF ((uint32_t)0x00000000U) 000373: line 237 define SPDIFRX_PREAMBLETYPEMASK_ON ((uint32_t)SPDIFRX_CR_PTMSK) 0003af: line 245 define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000U) 0003e4: line 246 define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) 00041d: line 254 define SPDIFRX_VALIDITYMASK_OFF ((uint32_t)0x00000000U) 000451: line 255 define SPDIFRX_VALIDITYMASK_ON ((uint32_t)SPDIFRX_CR_VMSK) 000488: line 263 define SPDIFRX_PARITYERRORMASK_OFF ((uint32_t)0x00000000U) 0004bf: line 264 define SPDIFRX_PARITYERRORMASK_ON ((uint32_t)SPDIFRX_CR_PMSK) 0004f9: line 272 define SPDIFRX_CHANNEL_A ((uint32_t)0x00000000U) 000526: line 273 define SPDIFRX_CHANNEL_B ((uint32_t)SPDIFRX_CR_CHSEL) 000558: line 281 define SPDIFRX_DATAFORMAT_LSB ((uint32_t)0x00000000U) 00058a: line 282 define SPDIFRX_DATAFORMAT_MSB ((uint32_t)0x00000010U) 0005bc: line 283 define SPDIFRX_DATAFORMAT_32BITS ((uint32_t)0x00000020U) 0005f1: line 291 define SPDIFRX_STEREOMODE_DISABLE ((uint32_t)0x00000000U) 000627: line 292 define SPDIFRX_STEREOMODE_ENABLE ((uint32_t)SPDIFRX_CR_RXSTEO) 000662: line 301 define SPDIFRX_STATE_IDLE ((uint32_t)0xFFFFFFFCU) 000690: line 302 define SPDIFRX_STATE_SYNC ((uint32_t)0x00000001U) 0006be: line 303 define SPDIFRX_STATE_RCV ((uint32_t)SPDIFRX_CR_SPDIFEN) 0006f2: line 311 define SPDIFRX_IT_RXNE ((uint32_t)SPDIFRX_IMR_RXNEIE) 000724: line 312 define SPDIFRX_IT_CSRNE ((uint32_t)SPDIFRX_IMR_CSRNEIE) 000758: line 313 define SPDIFRX_IT_PERRIE ((uint32_t)SPDIFRX_IMR_PERRIE) 00078c: line 314 define SPDIFRX_IT_OVRIE ((uint32_t)SPDIFRX_IMR_OVRIE) 0007be: line 315 define SPDIFRX_IT_SBLKIE ((uint32_t)SPDIFRX_IMR_SBLKIE) 0007f2: line 316 define SPDIFRX_IT_SYNCDIE ((uint32_t)SPDIFRX_IMR_SYNCDIE) 000828: line 317 define SPDIFRX_IT_IFEIE ((uint32_t)SPDIFRX_IMR_IFEIE ) 00085b: line 325 define SPDIFRX_FLAG_RXNE ((uint32_t)SPDIFRX_SR_RXNE) 00088c: line 326 define SPDIFRX_FLAG_CSRNE ((uint32_t)SPDIFRX_SR_CSRNE) 0008bf: line 327 define SPDIFRX_FLAG_PERR ((uint32_t)SPDIFRX_SR_PERR) 0008f0: line 328 define SPDIFRX_FLAG_OVR ((uint32_t)SPDIFRX_SR_OVR) 00091f: line 329 define SPDIFRX_FLAG_SBD ((uint32_t)SPDIFRX_SR_SBD) 00094e: line 330 define SPDIFRX_FLAG_SYNCD ((uint32_t)SPDIFRX_SR_SYNCD) 000981: line 331 define SPDIFRX_FLAG_FERR ((uint32_t)SPDIFRX_SR_FERR) 0009b2: line 332 define SPDIFRX_FLAG_SERR ((uint32_t)SPDIFRX_SR_SERR) 0009e3: line 333 define SPDIFRX_FLAG_TERR ((uint32_t)SPDIFRX_SR_TERR) 000a14: line 351 define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = (uint16_t)SPDIFRX_CR_SPDIFEN) 000a79: line 357 define __HAL_SPDIFRX_IDLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE) 000ace: line 363 define __HAL_SPDIFRX_SYNC(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC) 000b23: line 370 define __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV) 000b76: line 386 define __HAL_SPDIFRX_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__)) 000bdc: line 387 define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__))) 000c50: line 402 define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 000cde: line 419 define __HAL_SPDIFRX_GET_FLAG(__HANDLE__,__FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 000d49: line 432 define __HAL_SPDIFRX_CLEAR_IT(__HANDLE__,__IT_CLEAR__) ((__HANDLE__)->Instance->IFCR = (uint32_t)(__IT_CLEAR__)) 000db6: line 505 define IS_SPDIFRX_INPUT_SELECT(INPUT) (((INPUT) == SPDIFRX_INPUT_IN1) || ((INPUT) == SPDIFRX_INPUT_IN2) || ((INPUT) == SPDIFRX_INPUT_IN3) || ((INPUT) == SPDIFRX_INPUT_IN0)) 000e5f: line 509 define IS_SPDIFRX_MAX_RETRIES(RET) (((RET) == SPDIFRX_MAXRETRIES_NONE) || ((RET) == SPDIFRX_MAXRETRIES_3) || ((RET) == SPDIFRX_MAXRETRIES_15) || ((RET) == SPDIFRX_MAXRETRIES_63)) 000f0e: line 513 define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL) (((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF)) 000f85: line 515 define IS_PREAMBLE_TYPE_MASK(VAL) (((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF)) 000ff7: line 517 define IS_VALIDITY_MASK(VAL) (((VAL) == SPDIFRX_VALIDITYMASK_OFF) || ((VAL) == SPDIFRX_VALIDITYMASK_ON)) 00105c: line 519 define IS_PARITY_ERROR_MASK(VAL) (((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || ((VAL) == SPDIFRX_PARITYERRORMASK_ON)) 0010cb: line 521 define IS_SPDIFRX_CHANNEL(CHANNEL) (((CHANNEL) == SPDIFRX_CHANNEL_A) || ((CHANNEL) == SPDIFRX_CHANNEL_B)) 001131: line 523 define IS_SPDIFRX_DATA_FORMAT(FORMAT) (((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || ((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS)) 0011cd: line 526 define IS_STEREO_MODE(MODE) (((MODE) == SPDIFRX_STEREOMODE_DISABLE) || ((MODE) == SPDIFRX_STEREOMODE_ENABLE)) 001237: line 529 define IS_CHANNEL_STATUS_MASK(VAL) (((VAL) == SPDIFRX_CHANNELSTATUS_ON) || ((VAL) == SPDIFRX_CHANNELSTATUS_OFF)) 0012a4: end include 0012a5: end of translation unit ** Section #245 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 124 bytes 000000: Header: length 120 (not including this field) version 3 prologue length 111 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_spdifrx.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 73 70 64 69 66 72 78 2e 68 00 01 00 00 000061: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000078: file "" : 00 000079: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_spdifrx.h:1.0 ** Section #246 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 1220 bytes 000000: Header: size 0x4c0 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_spdifrx.h 00004d: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000094: DW_AT_language DW_LANG_C89 000096: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010d: DW_AT_macro_info 0x0 000111: DW_AT_stmt_list 0x0 000115: 42 = 0x13 (DW_TAG_structure_type) 000116: DW_AT_sibling 0x205 000118: DW_AT_byte_size 0x28 000119: 30 = 0xd (DW_TAG_member) 00011a: DW_AT_name InputSelection 000129: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00012e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000131: 30 = 0xd (DW_TAG_member) 000132: DW_AT_name Retries 00013a: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00013f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000142: 30 = 0xd (DW_TAG_member) 000143: DW_AT_name WaitForActivity 000153: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000158: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 00015b: 30 = 0xd (DW_TAG_member) 00015c: DW_AT_name ChannelSelection 00016d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000172: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000175: 30 = 0xd (DW_TAG_member) 000176: DW_AT_name DataFormat 000181: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000186: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000189: 30 = 0xd (DW_TAG_member) 00018a: DW_AT_name StereoMode 000195: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00019a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 00019d: 30 = 0xd (DW_TAG_member) 00019e: DW_AT_name PreambleTypeMask 0001af: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001b4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 0001b7: 30 = 0xd (DW_TAG_member) 0001b8: DW_AT_name ChannelStatusMask 0001ca: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001cf: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 0001d2: 30 = 0xd (DW_TAG_member) 0001d3: DW_AT_name ValidityBitMask 0001e3: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001e8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 0001eb: 30 = 0xd (DW_TAG_member) 0001ec: DW_AT_name ParityErrorMask 0001fc: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000201: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 000204: 0 null 000205: 80 = 0x16 (DW_TAG_typedef) 000206: DW_AT_name SPDIFRX_InitTypeDef 00021a: DW_AT_type indirect DW_FORM_ref2 0x115 00021d: DW_AT_decl_file 0x1 00021e: DW_AT_decl_line 0x63 00021f: DW_AT_decl_column 0x2 000220: 42 = 0x13 (DW_TAG_structure_type) 000221: DW_AT_sibling 0x2b4 000223: DW_AT_byte_size 0x18 000224: 30 = 0xd (DW_TAG_member) 000225: DW_AT_name DataFormat 000230: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000235: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000238: 30 = 0xd (DW_TAG_member) 000239: DW_AT_name StereoMode 000244: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000249: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00024c: 30 = 0xd (DW_TAG_member) 00024d: DW_AT_name PreambleTypeMask 00025e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000263: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000266: 30 = 0xd (DW_TAG_member) 000267: DW_AT_name ChannelStatusMask 000279: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00027e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000281: 30 = 0xd (DW_TAG_member) 000282: DW_AT_name ValidityBitMask 000292: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000297: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 00029a: 30 = 0xd (DW_TAG_member) 00029b: DW_AT_name ParityErrorMask 0002ab: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002b0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 0002b3: 0 null 0002b4: 80 = 0x16 (DW_TAG_typedef) 0002b5: DW_AT_name SPDIFRX_SetDataFormatTypeDef 0002d2: DW_AT_type indirect DW_FORM_ref2 0x220 0002d5: DW_AT_decl_file 0x1 0002d6: DW_AT_decl_line 0x7c 0002d7: DW_AT_decl_column 0x2 0002d8: 19 = 0x4 (DW_TAG_enumeration_type) 0002d9: DW_AT_sibling 0x382 0002db: DW_AT_byte_size 0x1 0002dc: 20 = 0x28 (DW_TAG_enumerator) 0002dd: DW_AT_name HAL_SPDIFRX_STATE_RESET 0002f5: DW_AT_const_value indirect DW_FORM_data1 0x0 0002f7: 20 = 0x28 (DW_TAG_enumerator) 0002f8: DW_AT_name HAL_SPDIFRX_STATE_READY 000310: DW_AT_const_value indirect DW_FORM_data1 0x1 000312: 20 = 0x28 (DW_TAG_enumerator) 000313: DW_AT_name HAL_SPDIFRX_STATE_BUSY 00032a: DW_AT_const_value indirect DW_FORM_data1 0x2 00032c: 20 = 0x28 (DW_TAG_enumerator) 00032d: DW_AT_name HAL_SPDIFRX_STATE_BUSY_RX 000347: DW_AT_const_value indirect DW_FORM_data1 0x3 000349: 20 = 0x28 (DW_TAG_enumerator) 00034a: DW_AT_name HAL_SPDIFRX_STATE_BUSY_CX 000364: DW_AT_const_value indirect DW_FORM_data1 0x4 000366: 20 = 0x28 (DW_TAG_enumerator) 000367: DW_AT_name HAL_SPDIFRX_STATE_ERROR 00037f: DW_AT_const_value indirect DW_FORM_data1 0x7 000381: 0 null 000382: 80 = 0x16 (DW_TAG_typedef) 000383: DW_AT_name HAL_SPDIFRX_StateTypeDef 00039c: DW_AT_type indirect DW_FORM_ref2 0x2d8 00039f: DW_AT_decl_file 0x1 0003a0: DW_AT_decl_line 0x89 0003a2: DW_AT_decl_column 0x2 0003a3: 42 = 0x13 (DW_TAG_structure_type) 0003a4: DW_AT_sibling 0x47c 0003a6: DW_AT_byte_size 0x4c 0003a7: 30 = 0xd (DW_TAG_member) 0003a8: DW_AT_name Instance 0003b1: DW_AT_type indirect DW_FORM_ref2 0x47c 0003b4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0003b7: 30 = 0xd (DW_TAG_member) 0003b8: DW_AT_name Init 0003bd: DW_AT_type indirect DW_FORM_ref2 0x205 0003c0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0003c3: 30 = 0xd (DW_TAG_member) 0003c4: DW_AT_name pRxBuffPtr 0003cf: DW_AT_type indirect DW_FORM_ref2 0x482 0003d2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 0003d5: 30 = 0xd (DW_TAG_member) 0003d6: DW_AT_name pCsBuffPtr 0003e1: DW_AT_type indirect DW_FORM_ref2 0x482 0003e4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 0003e7: 30 = 0xd (DW_TAG_member) 0003e8: DW_AT_name RxXferSize 0003f3: DW_AT_type indirect DW_FORM_ref2 0x488 0003f6: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 0003f9: 30 = 0xd (DW_TAG_member) 0003fa: DW_AT_name RxXferCount 000406: DW_AT_type indirect DW_FORM_ref2 0x488 000409: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 54 } 00040c: 30 = 0xd (DW_TAG_member) 00040d: DW_AT_name CsXferSize 000418: DW_AT_type indirect DW_FORM_ref2 0x488 00041b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 00041e: 30 = 0xd (DW_TAG_member) 00041f: DW_AT_name CsXferCount 00042b: DW_AT_type indirect DW_FORM_ref2 0x488 00042e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 58 } 000431: 30 = 0xd (DW_TAG_member) 000432: DW_AT_name hdmaCsRx 00043b: DW_AT_type indirect DW_FORM_ref2 0x48e 00043e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 60 } 000441: 30 = 0xd (DW_TAG_member) 000442: DW_AT_name hdmaDrRx 00044b: DW_AT_type indirect DW_FORM_ref2 0x48e 00044e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 64 } 000451: 30 = 0xd (DW_TAG_member) 000452: DW_AT_name Lock 000457: DW_AT_type indirect DW_FORM_ref2 0x494 00045a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 68 } 00045d: 30 = 0xd (DW_TAG_member) 00045e: DW_AT_name State 000464: DW_AT_type indirect DW_FORM_ref2 0x49a 000467: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 69 } 00046a: 30 = 0xd (DW_TAG_member) 00046b: DW_AT_name ErrorCode 000475: DW_AT_type indirect DW_FORM_ref2 0x49e 000478: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 72 } 00047b: 0 null 00047c: 34 = 0xf (DW_TAG_pointer_type) 00047d: DW_AT_type indirect DW_FORM_ref_addr 0x23d3+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 000482: 34 = 0xf (DW_TAG_pointer_type) 000483: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000488: 116 = 0x35 (DW_TAG_volatile_type) 000489: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00048e: 34 = 0xf (DW_TAG_pointer_type) 00048f: DW_AT_type indirect DW_FORM_ref_addr 0x1a0+__ARM_grp..debug_info$stm32f7xx_hal_dma.h$.2_wD1100_gh0hnOcebnc_s10000 000494: 116 = 0x35 (DW_TAG_volatile_type) 000495: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 00049a: 116 = 0x35 (DW_TAG_volatile_type) 00049b: DW_AT_type indirect DW_FORM_ref2 0x382 00049e: 116 = 0x35 (DW_TAG_volatile_type) 00049f: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004a4: 80 = 0x16 (DW_TAG_typedef) 0004a5: DW_AT_name SPDIFRX_HandleTypeDef 0004bb: DW_AT_type indirect DW_FORM_ref2 0x3a3 0004be: DW_AT_decl_file 0x1 0004bf: DW_AT_decl_line 0xb4 0004c1: DW_AT_decl_column 0x2 0004c2: 0 null 0004c3: 0 padding ** Section #416 '.rel.debug_info' (SHT_REL) Size : 200 bytes (alignment 4) Symbol table #343 '.symtab' 25 relocations applied to section #246 '.debug_info' ** Section #247 '__ARM_grp.stm32f7xx_hal_spi.h.2_4u2100_23dnc8DW6ic_R10000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #248 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 7120 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_SPI_H 00001c: include at line 47 - file 2 00001f: end include 000020: line 183 define HAL_SPI_ERROR_NONE ((uint32_t)0x00000000U) 00004e: line 184 define HAL_SPI_ERROR_MODF ((uint32_t)0x00000001U) 00007c: line 185 define HAL_SPI_ERROR_CRC ((uint32_t)0x00000002U) 0000a9: line 186 define HAL_SPI_ERROR_OVR ((uint32_t)0x00000004U) 0000d6: line 187 define HAL_SPI_ERROR_FRE ((uint32_t)0x00000008U) 000103: line 188 define HAL_SPI_ERROR_DMA ((uint32_t)0x00000010U) 000130: line 189 define HAL_SPI_ERROR_FLAG ((uint32_t)0x00000020U) 00015e: line 190 define HAL_SPI_ERROR_ABORT ((uint32_t)0x00000040U) 00018d: line 198 define SPI_MODE_SLAVE ((uint32_t)0x00000000U) 0001b7: line 199 define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) 0001e7: line 207 define SPI_DIRECTION_2LINES ((uint32_t)0x00000000U) 000217: line 208 define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY 000245: line 209 define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE 00026d: line 217 define SPI_DATASIZE_4BIT ((uint32_t)0x00000300U) 00029a: line 218 define SPI_DATASIZE_5BIT ((uint32_t)0x00000400U) 0002c7: line 219 define SPI_DATASIZE_6BIT ((uint32_t)0x00000500U) 0002f4: line 220 define SPI_DATASIZE_7BIT ((uint32_t)0x00000600U) 000321: line 221 define SPI_DATASIZE_8BIT ((uint32_t)0x00000700U) 00034e: line 222 define SPI_DATASIZE_9BIT ((uint32_t)0x00000800U) 00037b: line 223 define SPI_DATASIZE_10BIT ((uint32_t)0x00000900U) 0003a9: line 224 define SPI_DATASIZE_11BIT ((uint32_t)0x00000A00U) 0003d7: line 225 define SPI_DATASIZE_12BIT ((uint32_t)0x00000B00U) 000405: line 226 define SPI_DATASIZE_13BIT ((uint32_t)0x00000C00U) 000433: line 227 define SPI_DATASIZE_14BIT ((uint32_t)0x00000D00U) 000461: line 228 define SPI_DATASIZE_15BIT ((uint32_t)0x00000E00U) 00048f: line 229 define SPI_DATASIZE_16BIT ((uint32_t)0x00000F00U) 0004bd: line 237 define SPI_POLARITY_LOW ((uint32_t)0x00000000U) 0004e9: line 238 define SPI_POLARITY_HIGH SPI_CR1_CPOL 00050b: line 246 define SPI_PHASE_1EDGE ((uint32_t)0x00000000U) 000536: line 247 define SPI_PHASE_2EDGE SPI_CR1_CPHA 000556: line 255 define SPI_NSS_SOFT SPI_CR1_SSM 000572: line 256 define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000U) 0005a0: line 257 define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000U) 0005cf: line 265 define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP 0005f4: line 266 define SPI_NSS_PULSE_DISABLE ((uint32_t)0x00000000U) 000625: line 274 define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000U) 000658: line 275 define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008U) 00068b: line 276 define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010U) 0006be: line 277 define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018U) 0006f2: line 278 define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020U) 000726: line 279 define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028U) 00075a: line 280 define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030U) 00078f: line 281 define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038U) 0007c4: line 289 define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000U) 0007f0: line 290 define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST 000815: line 298 define SPI_TIMODE_DISABLE ((uint32_t)0x00000000U) 000843: line 299 define SPI_TIMODE_ENABLE SPI_CR2_FRF 000864: line 307 define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000U) 00089a: line 308 define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN 0008c5: line 320 define SPI_CRC_LENGTH_DATASIZE ((uint32_t)0x00000000U) 0008f8: line 321 define SPI_CRC_LENGTH_8BIT ((uint32_t)0x00000001U) 000927: line 322 define SPI_CRC_LENGTH_16BIT ((uint32_t)0x00000002U) 000957: line 335 define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH 00097d: line 336 define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH 0009a6: line 337 define SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x00000000U) 0009d9: line 346 define SPI_IT_TXE SPI_CR2_TXEIE 0009f5: line 347 define SPI_IT_RXNE SPI_CR2_RXNEIE 000a13: line 348 define SPI_IT_ERR SPI_CR2_ERRIE 000a2f: line 356 define SPI_FLAG_RXNE SPI_SR_RXNE 000a4c: line 357 define SPI_FLAG_TXE SPI_SR_TXE 000a67: line 358 define SPI_FLAG_BSY SPI_SR_BSY 000a82: line 359 define SPI_FLAG_CRCERR SPI_SR_CRCERR 000aa3: line 360 define SPI_FLAG_MODF SPI_SR_MODF 000ac0: line 361 define SPI_FLAG_OVR SPI_SR_OVR 000adb: line 362 define SPI_FLAG_FRE SPI_SR_FRE 000af6: line 363 define SPI_FLAG_FTLVL SPI_SR_FTLVL 000b15: line 364 define SPI_FLAG_FRLVL SPI_SR_FRLVL 000b34: line 372 define SPI_FTLVL_EMPTY ((uint32_t)0x00000000U) 000b5f: line 373 define SPI_FTLVL_QUARTER_FULL ((uint32_t)0x00000800U) 000b91: line 374 define SPI_FTLVL_HALF_FULL ((uint32_t)0x00001000U) 000bc0: line 375 define SPI_FTLVL_FULL ((uint32_t)0x00001800U) 000bea: line 384 define SPI_FRLVL_EMPTY ((uint32_t)0x00000000U) 000c15: line 385 define SPI_FRLVL_QUARTER_FULL ((uint32_t)0x00000200U) 000c47: line 386 define SPI_FRLVL_HALF_FULL ((uint32_t)0x00000400U) 000c76: line 387 define SPI_FRLVL_FULL ((uint32_t)0x00000600U) 000ca0: line 402 define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) 000cf8: line 414 define __HAL_SPI_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__)) 000d5a: line 415 define __HAL_SPI_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__))) 000dc0: line 427 define __HAL_SPI_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 000e4a: line 445 define __HAL_SPI_GET_FLAG(__HANDLE__,__FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 000eb1: line 452 define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) 000f17: line 459 define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{ __IO uint32_t tmpreg_modf = 0x00U; tmpreg_modf = (__HANDLE__)->Instance->SR; (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); UNUSED(tmpreg_modf); } while(0) 000fdf: line 472 define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{ __IO uint32_t tmpreg_ovr = 0x00U; tmpreg_ovr = (__HANDLE__)->Instance->DR; tmpreg_ovr = (__HANDLE__)->Instance->SR; UNUSED(tmpreg_ovr); } while(0) 00109d: line 485 define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) do{ __IO uint32_t tmpreg_fre = 0x00U; tmpreg_fre = (__HANDLE__)->Instance->SR; UNUSED(tmpreg_fre); }while(0) 001131: line 497 define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE) 00117e: line 504 define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE)) 0011cf: line 520 define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE) 00121b: line 527 define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE)) 00126a: line 534 define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN); (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0) 0012fc: line 537 define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || ((MODE) == SPI_MODE_MASTER)) 00134d: line 540 define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || ((MODE) == SPI_DIRECTION_1LINE)) 0013d8: line 544 define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES) 00141a: line 546 define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || ((MODE) == SPI_DIRECTION_1LINE)) 00148a: line 549 define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || ((DATASIZE) == SPI_DATASIZE_15BIT) || ((DATASIZE) == SPI_DATASIZE_14BIT) || ((DATASIZE) == SPI_DATASIZE_13BIT) || ((DATASIZE) == SPI_DATASIZE_12BIT) || ((DATASIZE) == SPI_DATASIZE_11BIT) || ((DATASIZE) == SPI_DATASIZE_10BIT) || ((DATASIZE) == SPI_DATASIZE_9BIT) || ((DATASIZE) == SPI_DATASIZE_8BIT) || ((DATASIZE) == SPI_DATASIZE_7BIT) || ((DATASIZE) == SPI_DATASIZE_6BIT) || ((DATASIZE) == SPI_DATASIZE_5BIT) || ((DATASIZE) == SPI_DATASIZE_4BIT)) 00168e: line 563 define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || ((CPOL) == SPI_POLARITY_HIGH)) 0016e3: line 566 define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || ((CPHA) == SPI_PHASE_2EDGE)) 001735: line 569 define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || ((NSS) == SPI_NSS_HARD_INPUT) || ((NSS) == SPI_NSS_HARD_OUTPUT)) 0017a5: line 573 define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || ((NSSP) == SPI_NSS_PULSE_DISABLE)) 001802: line 576 define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || ((PRESCALER) == SPI_BAUDRATEPRESCALER_256)) 001990: line 585 define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || ((BIT) == SPI_FIRSTBIT_LSB)) 0019e6: line 588 define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || ((MODE) == SPI_TIMODE_ENABLE)) 001a3f: line 591 define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || ((CALCULATION) == SPI_CRCCALCULATION_ENABLE)) 001ac6: line 594 define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) || ((LENGTH) == SPI_CRC_LENGTH_8BIT) || ((LENGTH) == SPI_CRC_LENGTH_16BIT)) 001b56: line 598 define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0)) 001bce: end include 001bcf: end of translation unit ** Section #249 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 120 bytes 000000: Header: length 116 (not including this field) version 3 prologue length 107 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_spi.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 73 70 69 2e 68 00 01 00 00 00005d: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000074: file "" : 00 000075: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_spi.h:1.0 ** Section #250 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 1148 bytes 000000: Header: size 0x478 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_spi.h 000049: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000090: DW_AT_language DW_LANG_C89 000092: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 000109: DW_AT_macro_info 0x0 00010d: DW_AT_stmt_list 0x0 000111: 42 = 0x13 (DW_TAG_structure_type) 000112: DW_AT_sibling 0x20e 000114: DW_AT_byte_size 0x34 000115: 30 = 0xd (DW_TAG_member) 000116: DW_AT_name Mode 00011b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000120: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000123: 30 = 0xd (DW_TAG_member) 000124: DW_AT_name Direction 00012e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000133: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000136: 30 = 0xd (DW_TAG_member) 000137: DW_AT_name DataSize 000140: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000145: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000148: 30 = 0xd (DW_TAG_member) 000149: DW_AT_name CLKPolarity 000155: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00015a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00015d: 30 = 0xd (DW_TAG_member) 00015e: DW_AT_name CLKPhase 000167: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00016c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 00016f: 30 = 0xd (DW_TAG_member) 000170: DW_AT_name NSS 000174: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000179: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 00017c: 30 = 0xd (DW_TAG_member) 00017d: DW_AT_name BaudRatePrescaler 00018f: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000194: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 000197: 30 = 0xd (DW_TAG_member) 000198: DW_AT_name FirstBit 0001a1: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001a6: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 0001a9: 30 = 0xd (DW_TAG_member) 0001aa: DW_AT_name TIMode 0001b1: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001b6: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 0001b9: 30 = 0xd (DW_TAG_member) 0001ba: DW_AT_name CRCCalculation 0001c9: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001ce: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 0001d1: 30 = 0xd (DW_TAG_member) 0001d2: DW_AT_name CRCPolynomial 0001e0: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001e5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 0001e8: 30 = 0xd (DW_TAG_member) 0001e9: DW_AT_name CRCLength 0001f3: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001f8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 0001fb: 30 = 0xd (DW_TAG_member) 0001fc: DW_AT_name NSSPMode 000205: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00020a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 00020d: 0 null 00020e: 80 = 0x16 (DW_TAG_typedef) 00020f: DW_AT_name SPI_InitTypeDef 00021f: DW_AT_type indirect DW_FORM_ref2 0x111 000222: DW_AT_decl_file 0x1 000223: DW_AT_decl_line 0x72 000224: DW_AT_decl_column 0x3 000225: 19 = 0x4 (DW_TAG_enumeration_type) 000226: DW_AT_sibling 0x2ea 000228: DW_AT_byte_size 0x1 000229: 20 = 0x28 (DW_TAG_enumerator) 00022a: DW_AT_name HAL_SPI_STATE_RESET 00023e: DW_AT_const_value indirect DW_FORM_data1 0x0 000240: 20 = 0x28 (DW_TAG_enumerator) 000241: DW_AT_name HAL_SPI_STATE_READY 000255: DW_AT_const_value indirect DW_FORM_data1 0x1 000257: 20 = 0x28 (DW_TAG_enumerator) 000258: DW_AT_name HAL_SPI_STATE_BUSY 00026b: DW_AT_const_value indirect DW_FORM_data1 0x2 00026d: 20 = 0x28 (DW_TAG_enumerator) 00026e: DW_AT_name HAL_SPI_STATE_BUSY_TX 000284: DW_AT_const_value indirect DW_FORM_data1 0x3 000286: 20 = 0x28 (DW_TAG_enumerator) 000287: DW_AT_name HAL_SPI_STATE_BUSY_RX 00029d: DW_AT_const_value indirect DW_FORM_data1 0x4 00029f: 20 = 0x28 (DW_TAG_enumerator) 0002a0: DW_AT_name HAL_SPI_STATE_BUSY_TX_RX 0002b9: DW_AT_const_value indirect DW_FORM_data1 0x5 0002bb: 20 = 0x28 (DW_TAG_enumerator) 0002bc: DW_AT_name HAL_SPI_STATE_ERROR 0002d0: DW_AT_const_value indirect DW_FORM_data1 0x6 0002d2: 20 = 0x28 (DW_TAG_enumerator) 0002d3: DW_AT_name HAL_SPI_STATE_ABORT 0002e7: DW_AT_const_value indirect DW_FORM_data1 0x7 0002e9: 0 null 0002ea: 80 = 0x16 (DW_TAG_typedef) 0002eb: DW_AT_name HAL_SPI_StateTypeDef 000300: DW_AT_type indirect DW_FORM_ref2 0x225 000303: DW_AT_decl_file 0x1 000304: DW_AT_decl_line 0x81 000306: DW_AT_decl_column 0x3 000307: 41 = 0x13 (DW_TAG_structure_type) 000308: DW_AT_sibling 0x439 00030a: DW_AT_name __SPI_HandleTypeDef 00031e: DW_AT_byte_size 0x64 00031f: 30 = 0xd (DW_TAG_member) 000320: DW_AT_name Instance 000329: DW_AT_type indirect DW_FORM_ref2 0x439 00032c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00032f: 30 = 0xd (DW_TAG_member) 000330: DW_AT_name Init 000335: DW_AT_type indirect DW_FORM_ref2 0x20e 000338: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00033b: 30 = 0xd (DW_TAG_member) 00033c: DW_AT_name pTxBuffPtr 000347: DW_AT_type indirect DW_FORM_ref2 0x43f 00034a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 00034d: 30 = 0xd (DW_TAG_member) 00034e: DW_AT_name TxXferSize 000359: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00035e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 60 } 000361: 30 = 0xd (DW_TAG_member) 000362: DW_AT_name TxXferCount 00036e: DW_AT_type indirect DW_FORM_ref2 0x445 000371: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 62 } 000374: 30 = 0xd (DW_TAG_member) 000375: DW_AT_name pRxBuffPtr 000380: DW_AT_type indirect DW_FORM_ref2 0x43f 000383: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 64 } 000386: 30 = 0xd (DW_TAG_member) 000387: DW_AT_name RxXferSize 000392: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000397: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 68 } 00039a: 30 = 0xd (DW_TAG_member) 00039b: DW_AT_name RxXferCount 0003a7: DW_AT_type indirect DW_FORM_ref2 0x445 0003aa: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 70 } 0003ad: 30 = 0xd (DW_TAG_member) 0003ae: DW_AT_name CRCSize 0003b6: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003bb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 72 } 0003be: 79 = 0x15 (DW_TAG_subroutine_type) 0003bf: DW_AT_sibling 0x3c6 0003c1: 37 = 0x5 (DW_TAG_formal_parameter) 0003c2: DW_AT_type indirect DW_FORM_ref2 0x44b 0003c5: 0 null 0003c6: 34 = 0xf (DW_TAG_pointer_type) 0003c7: DW_AT_type indirect DW_FORM_ref2 0x3be 0003ca: 30 = 0xd (DW_TAG_member) 0003cb: DW_AT_name RxISR 0003d1: DW_AT_type indirect DW_FORM_ref2 0x3c6 0003d4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 76 } 0003d7: 79 = 0x15 (DW_TAG_subroutine_type) 0003d8: DW_AT_sibling 0x3df 0003da: 37 = 0x5 (DW_TAG_formal_parameter) 0003db: DW_AT_type indirect DW_FORM_ref2 0x44b 0003de: 0 null 0003df: 34 = 0xf (DW_TAG_pointer_type) 0003e0: DW_AT_type indirect DW_FORM_ref2 0x3d7 0003e3: 30 = 0xd (DW_TAG_member) 0003e4: DW_AT_name TxISR 0003ea: DW_AT_type indirect DW_FORM_ref2 0x3df 0003ed: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 80 } 0003f0: 30 = 0xd (DW_TAG_member) 0003f1: DW_AT_name hdmatx 0003f8: DW_AT_type indirect DW_FORM_ref2 0x44f 0003fb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 84 } 0003fe: 30 = 0xd (DW_TAG_member) 0003ff: DW_AT_name hdmarx 000406: DW_AT_type indirect DW_FORM_ref2 0x44f 000409: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 88 } 00040c: 30 = 0xd (DW_TAG_member) 00040d: DW_AT_name Lock 000412: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 000417: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 92 } 00041a: 30 = 0xd (DW_TAG_member) 00041b: DW_AT_name State 000421: DW_AT_type indirect DW_FORM_ref2 0x455 000424: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 93 } 000427: 30 = 0xd (DW_TAG_member) 000428: DW_AT_name ErrorCode 000432: DW_AT_type indirect DW_FORM_ref2 0x459 000435: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 96 } 000438: 0 null 000439: 34 = 0xf (DW_TAG_pointer_type) 00043a: DW_AT_type indirect DW_FORM_ref_addr 0x25a3+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 00043f: 34 = 0xf (DW_TAG_pointer_type) 000440: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000445: 116 = 0x35 (DW_TAG_volatile_type) 000446: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00044b: 34 = 0xf (DW_TAG_pointer_type) 00044c: DW_AT_type indirect DW_FORM_ref2 0x307 00044f: 34 = 0xf (DW_TAG_pointer_type) 000450: DW_AT_type indirect DW_FORM_ref_addr 0x1a0+__ARM_grp..debug_info$stm32f7xx_hal_dma.h$.2_wD1100_gh0hnOcebnc_s10000 000455: 116 = 0x35 (DW_TAG_volatile_type) 000456: DW_AT_type indirect DW_FORM_ref2 0x2ea 000459: 116 = 0x35 (DW_TAG_volatile_type) 00045a: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00045f: 80 = 0x16 (DW_TAG_typedef) 000460: DW_AT_name SPI_HandleTypeDef 000472: DW_AT_type indirect DW_FORM_ref2 0x307 000475: DW_AT_decl_file 0x1 000476: DW_AT_decl_line 0xa8 000478: DW_AT_decl_column 0x3 000479: 0 null 00047a: 0 padding 00047b: 0 padding ** Section #417 '.rel.debug_info' (SHT_REL) Size : 200 bytes (alignment 4) Symbol table #343 '.symtab' 25 relocations applied to section #250 '.debug_info' ** Section #251 '__ARM_grp.stm32f7xx_hal_tim_ex.h.2_kC5000_pNBuEpmOGV2_q00000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #252 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 8624 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_TIM_EX_H 00001f: include at line 47 - file 2 000022: end include 000023: line 147 define TIM_CHANNEL_1 ((uint32_t)0x0000U) 000048: line 148 define TIM_CHANNEL_2 ((uint32_t)0x0004U) 00006d: line 149 define TIM_CHANNEL_3 ((uint32_t)0x0008U) 000092: line 150 define TIM_CHANNEL_4 ((uint32_t)0x000CU) 0000b7: line 151 define TIM_CHANNEL_5 ((uint32_t)0x0010U) 0000dc: line 152 define TIM_CHANNEL_6 ((uint32_t)0x0014U) 000101: line 153 define TIM_CHANNEL_ALL ((uint32_t)0x003CU) 000128: line 162 define TIM_OCMODE_TIMING ((uint32_t)0x0000U) 000151: line 163 define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0) 000183: line 164 define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1) 0001b7: line 165 define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) 0001fc: line 166 define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) 00023f: line 167 define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) 000295: line 168 define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) 0002e1: line 169 define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2) 00031c: line 171 define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3) 00035a: line 172 define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) 0003ab: line 173 define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) 0003f7: line 174 define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) 000456: line 175 define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) 0004b7: line 176 define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) 000503: line 184 define TIM_TIM2_TIM8_TRGO (0x00000000U) 000527: line 185 define TIM_TIM2_ETH_PTP (0x00000400U) 000549: line 186 define TIM_TIM2_USBFS_SOF (0x00000800U) 00056d: line 187 define TIM_TIM2_USBHS_SOF (0x00000C00U) 000591: line 188 define TIM_TIM5_GPIO (0x00000000U) 0005b0: line 189 define TIM_TIM5_LSI (0x00000040U) 0005ce: line 190 define TIM_TIM5_LSE (0x00000080U) 0005ec: line 191 define TIM_TIM5_RTC (0x000000C0U) 00060a: line 192 define TIM_TIM11_GPIO (0x00000000U) 00062a: line 193 define TIM_TIM11_SPDIFRX (0x00000001U) 00064d: line 194 define TIM_TIM11_HSE (0x00000002U) 00066c: line 195 define TIM_TIM11_MCO1 (0x00000003U) 00068c: line 203 define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001U) 0006bc: line 204 define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002U) 0006f1: line 205 define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000U) 000722: line 213 define TIM_BREAK2_DISABLE ((uint32_t)0x00000000U) 000750: line 214 define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E) 00077f: line 222 define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000U) 0007b1: line 223 define TIM_BREAK2POLARITY_HIGH (TIM_BDTR_BK2P) 0007dc: line 231 define TIM_GROUPCH5_NONE ((uint32_t)0x00000000U) 000809: line 232 define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) 000832: line 233 define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) 00085b: line 234 define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) 000884: line 242 define TIM_TRGO2_RESET ((uint32_t)0x00000000U) 0008af: line 243 define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0)) 0008e0: line 244 define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1)) 000911: line 245 define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) 000950: line 246 define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2)) 000981: line 247 define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)) 0009c3: line 248 define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)) 000a05: line 249 define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) 000a58: line 250 define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3)) 000a89: line 251 define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)) 000acb: line 252 define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)) 000b1b: line 253 define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) 000b7c: line 254 define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)) 000bd3: line 255 define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)) 000c3c: line 256 define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)) 000ca3: line 257 define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) 000d1d: line 265 define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000U) 000d4a: line 266 define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2)) 000d7e: line 267 define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)) 000dc3: line 268 define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)) 000e0a: line 269 define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)) 000e64: line 270 define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3)) 000ea8: line 278 define TIM_BREAKINPUT_BRK ((uint32_t)0x00000001U) 000ed6: line 279 define TIM_BREAKINPUT_BRK2 ((uint32_t)0x00000002U) 000f05: line 287 define TIM_BREAKINPUTSOURCE_BKIN ((uint32_t)0x00000001U) 000f3a: line 288 define TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)0x00000008U) 000f71: line 296 define TIM_BREAKINPUTSOURCE_DISABLE ((uint32_t)0x00000000U) 000fa9: line 297 define TIM_BREAKINPUTSOURCE_ENABLE ((uint32_t)0x00000001U) 000fe0: line 330 define __HAL_TIM_SET_COMPARE(__HANDLE__,__CHANNEL__,__COMPARE__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) : ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) : ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) : ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) 0011f2: line 351 define __HAL_TIM_GET_COMPARE(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) : ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) : ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) : ((__HANDLE__)->Instance->CCR6)) 001398: line 492 define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4) || ((CHANNEL) == TIM_CHANNEL_5) || ((CHANNEL) == TIM_CHANNEL_6) || ((CHANNEL) == TIM_CHANNEL_ALL)) 001495: line 500 define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2)) 0014f5: line 503 define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2)) 001554: line 506 define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3)) 0015dd: line 509 define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || ((MODE) == TIM_OCMODE_PWM2) || ((MODE) == TIM_OCMODE_COMBINED_PWM1) || ((MODE) == TIM_OCMODE_COMBINED_PWM2) || ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM1) || ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM2)) 0016d7: line 516 define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || ((MODE) == TIM_OCMODE_ACTIVE) || ((MODE) == TIM_OCMODE_INACTIVE) || ((MODE) == TIM_OCMODE_TOGGLE) || ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || ((MODE) == TIM_OCMODE_FORCED_INACTIVE) || ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM1) || ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM2)) 001820: line 524 define IS_TIM_REMAP(__TIM_REMAP__) (((__TIM_REMAP__) == TIM_TIM2_TIM8_TRGO)|| ((__TIM_REMAP__) == TIM_TIM2_ETH_PTP)|| ((__TIM_REMAP__) == TIM_TIM2_USBFS_SOF)|| ((__TIM_REMAP__) == TIM_TIM2_USBHS_SOF)|| ((__TIM_REMAP__) == TIM_TIM5_GPIO)|| ((__TIM_REMAP__) == TIM_TIM5_LSI)|| ((__TIM_REMAP__) == TIM_TIM5_LSE)|| ((__TIM_REMAP__) == TIM_TIM5_RTC)|| ((__TIM_REMAP__) == TIM_TIM11_GPIO)|| ((__TIM_REMAP__) == TIM_TIM11_SPDIFRX)|| ((__TIM_REMAP__) == TIM_TIM11_HSE)|| ((__TIM_REMAP__) == TIM_TIM11_MCO1)) 001a10: line 536 define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFF) 001a4a: line 537 define IS_TIM_BREAK_FILTER(__FILTER__) ((__FILTER__) <= 0xF) 001a83: line 538 define IS_TIM_CLEARINPUT_SOURCE(MODE) (((MODE) == TIM_CLEARINPUTSOURCE_ETR) || ((MODE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || ((MODE) == TIM_CLEARINPUTSOURCE_NONE)) 001b22: line 541 define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_BREAK2_ENABLE) || ((STATE) == TIM_BREAK2_DISABLE)) 001b84: line 543 define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) 001c08: line 545 define IS_TIM_GROUPCH5(OCREF) ((((OCREF) & 0x1FFFFFFF) == 0x00000000)) 001c4b: line 546 define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2_RESET) || ((SOURCE) == TIM_TRGO2_ENABLE) || ((SOURCE) == TIM_TRGO2_UPDATE) || ((SOURCE) == TIM_TRGO2_OC1) || ((SOURCE) == TIM_TRGO2_OC1REF) || ((SOURCE) == TIM_TRGO2_OC2REF) || ((SOURCE) == TIM_TRGO2_OC3REF) || ((SOURCE) == TIM_TRGO2_OC3REF) || ((SOURCE) == TIM_TRGO2_OC4REF) || ((SOURCE) == TIM_TRGO2_OC5REF) || ((SOURCE) == TIM_TRGO2_OC6REF) || ((SOURCE) == TIM_TRGO2_OC4REF_RISINGFALLING) || ((SOURCE) == TIM_TRGO2_OC6REF_RISINGFALLING) || ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) 001f19: line 563 define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || ((MODE) == TIM_SLAVEMODE_RESET) || ((MODE) == TIM_SLAVEMODE_GATED) || ((MODE) == TIM_SLAVEMODE_TRIGGER) || ((MODE) == TIM_SLAVEMODE_EXTERNAL1) || ((MODE) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) 00201d: line 571 define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) 00209a: line 574 define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM)) 00211f: line 577 define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) 0021ab: end include 0021ac: end of translation unit ** Section #253 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 124 bytes 000000: Header: length 120 (not including this field) version 3 prologue length 110 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_tim_ex.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 74 69 6d 5f 65 78 2e 68 00 01 00 00 000060: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000077: file "" : 00 000078: DW_LNS_negate_stmt : 06 000079: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_tim_ex.h:1.0 [ ** Section #254 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 888 bytes 000000: Header: size 0x374 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_tim_ex.h 00004c: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000093: DW_AT_language DW_LANG_C89 000095: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010c: DW_AT_macro_info 0x0 000110: DW_AT_stmt_list 0x0 000114: 42 = 0x13 (DW_TAG_structure_type) 000115: DW_AT_sibling 0x172 000117: DW_AT_byte_size 0x10 000118: 30 = 0xd (DW_TAG_member) 000119: DW_AT_name IC1Polarity 000125: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00012a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00012d: 30 = 0xd (DW_TAG_member) 00012e: DW_AT_name IC1Prescaler 00013b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000140: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000143: 30 = 0xd (DW_TAG_member) 000144: DW_AT_name IC1Filter 00014e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000153: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000156: 30 = 0xd (DW_TAG_member) 000157: DW_AT_name Commutation_Delay 000169: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00016e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000171: 0 null 000172: 80 = 0x16 (DW_TAG_typedef) 000173: DW_AT_name TIM_HallSensor_InitTypeDef 00018e: DW_AT_type indirect DW_FORM_ref2 0x114 000191: DW_AT_decl_file 0x1 000192: DW_AT_decl_line 0x4f 000193: DW_AT_decl_column 0x3 000194: 42 = 0x13 (DW_TAG_structure_type) 000195: DW_AT_sibling 0x1ed 000197: DW_AT_byte_size 0xc 000198: 30 = 0xd (DW_TAG_member) 000199: DW_AT_name MasterOutputTrigger 0001ad: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001b2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0001b5: 30 = 0xd (DW_TAG_member) 0001b6: DW_AT_name MasterOutputTrigger2 0001cb: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001d0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0001d3: 30 = 0xd (DW_TAG_member) 0001d4: DW_AT_name MasterSlaveMode 0001e4: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001e9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0001ec: 0 null 0001ed: 80 = 0x16 (DW_TAG_typedef) 0001ee: DW_AT_name TIM_MasterConfigTypeDef 000206: DW_AT_type indirect DW_FORM_ref2 0x194 000209: DW_AT_decl_file 0x1 00020a: DW_AT_decl_line 0x5b 00020b: DW_AT_decl_column 0x2 00020c: 42 = 0x13 (DW_TAG_structure_type) 00020d: DW_AT_sibling 0x305 00020f: DW_AT_byte_size 0x2c 000210: 30 = 0xd (DW_TAG_member) 000211: DW_AT_name OffStateRunMode 000221: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000226: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000229: 30 = 0xd (DW_TAG_member) 00022a: DW_AT_name OffStateIDLEMode 00023b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000240: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000243: 30 = 0xd (DW_TAG_member) 000244: DW_AT_name LockLevel 00024e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000253: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000256: 30 = 0xd (DW_TAG_member) 000257: DW_AT_name DeadTime 000260: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000265: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000268: 30 = 0xd (DW_TAG_member) 000269: DW_AT_name BreakState 000274: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000279: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 00027c: 30 = 0xd (DW_TAG_member) 00027d: DW_AT_name BreakPolarity 00028b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000290: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 000293: 30 = 0xd (DW_TAG_member) 000294: DW_AT_name BreakFilter 0002a0: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002a5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 0002a8: 30 = 0xd (DW_TAG_member) 0002a9: DW_AT_name Break2State 0002b5: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002ba: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 0002bd: 30 = 0xd (DW_TAG_member) 0002be: DW_AT_name Break2Polarity 0002cd: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002d2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 0002d5: 30 = 0xd (DW_TAG_member) 0002d6: DW_AT_name Break2Filter 0002e3: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002e8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 0002eb: 30 = 0xd (DW_TAG_member) 0002ec: DW_AT_name AutomaticOutput 0002fc: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000301: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 000304: 0 null 000305: 80 = 0x16 (DW_TAG_typedef) 000306: DW_AT_name TIM_BreakDeadTimeConfigTypeDef 000325: DW_AT_type indirect DW_FORM_ref2 0x20c 000328: DW_AT_decl_file 0x1 000329: DW_AT_decl_line 0x7a 00032a: DW_AT_decl_column 0x3 00032b: 42 = 0x13 (DW_TAG_structure_type) 00032c: DW_AT_sibling 0x350 00032e: DW_AT_byte_size 0x8 00032f: 30 = 0xd (DW_TAG_member) 000330: DW_AT_name Source 000337: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00033c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00033f: 30 = 0xd (DW_TAG_member) 000340: DW_AT_name Enable 000347: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00034c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00034f: 0 null 000350: 80 = 0x16 (DW_TAG_typedef) 000351: DW_AT_name TIMEx_BreakInputConfigTypeDef 00036f: DW_AT_type indirect DW_FORM_ref2 0x32b 000372: DW_AT_decl_file 0x1 000373: DW_AT_decl_line 0x85 000375: DW_AT_decl_column 0x3 000376: 0 null 000377: 0 padding ** Section #418 '.rel.debug_info' (SHT_REL) Size : 184 bytes (alignment 4) Symbol table #343 '.symtab' 23 relocations applied to section #254 '.debug_info' ** Section #255 '__ARM_grp.stm32f7xx_hal_tim.h.2_Ypa100_hpScuYWpugf_i20000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #256 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 22892 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_TIM_H 00001c: include at line 47 - file 2 00001f: end include 000020: line 311 define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000U) 00005b: line 312 define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) 00008f: line 313 define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) 0000d5: line 321 define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) 000100: line 322 define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000U) 000133: line 330 define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000U) 000160: line 331 define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) 00018b: line 332 define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) 0001b6: line 333 define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) 0001df: line 341 define TIM_COUNTERMODE_UP ((uint32_t)0x0000U) 000209: line 342 define TIM_COUNTERMODE_DOWN TIM_CR1_DIR 00022d: line 343 define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 00025d: line 344 define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 00028d: line 345 define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS 0002bb: line 353 define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000U) 0002e9: line 354 define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) 000313: line 355 define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) 00033d: line 363 define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000U) 00036c: line 364 define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) 000396: line 373 define TIM_OCFAST_DISABLE ((uint32_t)0x0000U) 0003c0: line 374 define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) 0003e7: line 382 define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000U) 000417: line 383 define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE) 000443: line 391 define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000U) 00046e: line 392 define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) 000494: line 400 define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000U) 0004c0: line 401 define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP) 0004e8: line 409 define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) 00050e: line 410 define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000U) 00053b: line 418 define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N) 000563: line 419 define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000U) 000591: line 427 define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING 0005ca: line 428 define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING 000605: line 429 define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE 000642: line 437 define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) 000671: line 439 define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) 0006a2: line 441 define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) 0006ca: line 450 define TIM_ICPSC_DIV1 ((uint32_t)0x0000U) 0006f0: line 451 define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) 000717: line 452 define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) 00073e: line 453 define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) 000763: line 461 define TIM_OPMODE_SINGLE (TIM_CR1_OPM) 000786: line 462 define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000U) 0007b3: line 470 define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) 0007db: line 471 define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) 000803: line 472 define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) 00083d: line 481 define TIM_IT_UPDATE (TIM_DIER_UIE) 00085d: line 482 define TIM_IT_CC1 (TIM_DIER_CC1IE) 00087c: line 483 define TIM_IT_CC2 (TIM_DIER_CC2IE) 00089b: line 484 define TIM_IT_CC3 (TIM_DIER_CC3IE) 0008ba: line 485 define TIM_IT_CC4 (TIM_DIER_CC4IE) 0008d9: line 486 define TIM_IT_COM (TIM_DIER_COMIE) 0008f8: line 487 define TIM_IT_TRIGGER (TIM_DIER_TIE) 000919: line 488 define TIM_IT_BREAK (TIM_DIER_BIE) 000938: line 496 define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS) 00095f: line 497 define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000U) 00098f: line 505 define TIM_DMA_UPDATE (TIM_DIER_UDE) 0009b0: line 506 define TIM_DMA_CC1 (TIM_DIER_CC1DE) 0009d0: line 507 define TIM_DMA_CC2 (TIM_DIER_CC2DE) 0009f0: line 508 define TIM_DMA_CC3 (TIM_DIER_CC3DE) 000a10: line 509 define TIM_DMA_CC4 (TIM_DIER_CC4DE) 000a30: line 510 define TIM_DMA_COM (TIM_DIER_COMDE) 000a50: line 511 define TIM_DMA_TRIGGER (TIM_DIER_TDE) 000a72: line 519 define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG 000a97: line 520 define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G 000abb: line 521 define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G 000adf: line 522 define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G 000b03: line 523 define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G 000b27: line 524 define TIM_EVENTSOURCE_COM TIM_EGR_COMG 000b4b: line 525 define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG 000b71: line 526 define TIM_EVENTSOURCE_BREAK TIM_EGR_BG 000b95: line 527 define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G 000bbb: line 535 define TIM_FLAG_UPDATE (TIM_SR_UIF) 000bdb: line 536 define TIM_FLAG_CC1 (TIM_SR_CC1IF) 000bfa: line 537 define TIM_FLAG_CC2 (TIM_SR_CC2IF) 000c19: line 538 define TIM_FLAG_CC3 (TIM_SR_CC3IF) 000c38: line 539 define TIM_FLAG_CC4 (TIM_SR_CC4IF) 000c57: line 540 define TIM_FLAG_COM (TIM_SR_COMIF) 000c76: line 541 define TIM_FLAG_TRIGGER (TIM_SR_TIF) 000c97: line 542 define TIM_FLAG_BREAK (TIM_SR_BIF) 000cb6: line 543 define TIM_FLAG_BREAK2 (TIM_SR_B2IF) 000cd7: line 544 define TIM_FLAG_CC1OF (TIM_SR_CC1OF) 000cf8: line 545 define TIM_FLAG_CC2OF (TIM_SR_CC2OF) 000d19: line 546 define TIM_FLAG_CC3OF (TIM_SR_CC3OF) 000d3a: line 547 define TIM_FLAG_CC4OF (TIM_SR_CC4OF) 000d5b: line 555 define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) 000d89: line 556 define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) 000db7: line 557 define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000U) 000de3: line 558 define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) 000e0b: line 559 define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) 000e33: line 560 define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) 000e6b: line 561 define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) 000e94: line 562 define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) 000ecb: line 563 define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) 000f02: line 564 define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) 000f2c: line 572 define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED 000f63: line 573 define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED 000fa0: line 574 define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING 000fdc: line 575 define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING 00101a: line 576 define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE 00105a: line 584 define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 00108b: line 585 define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 0010bc: line 586 define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 0010ed: line 587 define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 00111e: line 595 define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED 00115a: line 596 define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED 00119c: line 604 define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 0011d2: line 605 define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 001208: line 606 define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 00123e: line 607 define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 001274: line 615 define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) 001297: line 616 define TIM_OSSR_DISABLE ((uint32_t)0x0000U) 0012bf: line 624 define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) 0012e2: line 625 define TIM_OSSI_DISABLE ((uint32_t)0x0000U) 00130a: line 633 define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000U) 001333: line 634 define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) 001358: line 635 define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) 00137d: line 636 define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) 0013a0: line 643 define TIM_BREAK_ENABLE (TIM_BDTR_BKE) 0013c3: line 644 define TIM_BREAK_DISABLE ((uint32_t)0x0000U) 0013ec: line 652 define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000U) 001419: line 653 define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP) 001442: line 661 define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) 00146f: line 662 define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000U) 0014a2: line 670 define TIM_TRGO_RESET ((uint32_t)0x0000U) 0014c8: line 671 define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) 0014eb: line 672 define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) 00150e: line 673 define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) 001540: line 674 define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) 001563: line 675 define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) 001598: line 676 define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) 0015cd: line 677 define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) 001612: line 685 define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080) 001643: line 686 define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000U) 001676: line 694 define TIM_TS_ITR0 ((uint32_t)0x0000U) 001699: line 695 define TIM_TS_ITR1 ((uint32_t)0x0010U) 0016bc: line 696 define TIM_TS_ITR2 ((uint32_t)0x0020U) 0016df: line 697 define TIM_TS_ITR3 ((uint32_t)0x0030U) 001702: line 698 define TIM_TS_TI1F_ED ((uint32_t)0x0040U) 001728: line 699 define TIM_TS_TI1FP1 ((uint32_t)0x0050U) 00174d: line 700 define TIM_TS_TI2FP2 ((uint32_t)0x0060U) 001772: line 701 define TIM_TS_ETRF ((uint32_t)0x0070U) 001795: line 702 define TIM_TS_NONE ((uint32_t)0xFFFFU) 0017b8: line 710 define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED 0017f1: line 711 define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED 001830: line 712 define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING 00186e: line 713 define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING 0018ae: line 714 define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE 0018f0: line 722 define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 001923: line 723 define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 001956: line 724 define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 001989: line 725 define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 0019bc: line 734 define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000U) 0019e8: line 735 define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) 001a1a: line 743 define TIM_DMABASE_CR1 (0x00000000U) 001a3b: line 744 define TIM_DMABASE_CR2 (0x00000001U) 001a5c: line 745 define TIM_DMABASE_SMCR (0x00000002U) 001a7e: line 746 define TIM_DMABASE_DIER (0x00000003U) 001aa0: line 747 define TIM_DMABASE_SR (0x00000004U) 001ac0: line 748 define TIM_DMABASE_EGR (0x00000005U) 001ae1: line 749 define TIM_DMABASE_CCMR1 (0x00000006U) 001b04: line 750 define TIM_DMABASE_CCMR2 (0x00000007U) 001b27: line 751 define TIM_DMABASE_CCER (0x00000008U) 001b49: line 752 define TIM_DMABASE_CNT (0x00000009U) 001b6a: line 753 define TIM_DMABASE_PSC (0x0000000AU) 001b8b: line 754 define TIM_DMABASE_ARR (0x0000000BU) 001bac: line 755 define TIM_DMABASE_RCR (0x0000000CU) 001bcd: line 756 define TIM_DMABASE_CCR1 (0x0000000DU) 001bef: line 757 define TIM_DMABASE_CCR2 (0x0000000EU) 001c11: line 758 define TIM_DMABASE_CCR3 (0x0000000FU) 001c33: line 759 define TIM_DMABASE_CCR4 (0x00000010U) 001c55: line 760 define TIM_DMABASE_BDTR (0x00000011U) 001c77: line 761 define TIM_DMABASE_DCR (0x00000012U) 001c98: line 762 define TIM_DMABASE_OR (0x00000013U) 001cb8: line 770 define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U) 001ce6: line 771 define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U) 001d15: line 772 define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U) 001d44: line 773 define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U) 001d73: line 774 define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U) 001da2: line 775 define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U) 001dd1: line 776 define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U) 001e00: line 777 define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U) 001e2f: line 778 define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U) 001e5e: line 779 define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U) 001e8e: line 780 define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U) 001ebe: line 781 define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U) 001eee: line 782 define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U) 001f1e: line 783 define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U) 001f4e: line 784 define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U) 001f7e: line 785 define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U) 001fae: line 786 define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U) 001fde: line 787 define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U) 00200e: line 795 define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U) 002035: line 796 define TIM_DMA_ID_CC1 ((uint16_t) 0x1U) 002059: line 797 define TIM_DMA_ID_CC2 ((uint16_t) 0x2U) 00207d: line 798 define TIM_DMA_ID_CC3 ((uint16_t) 0x3U) 0020a1: line 799 define TIM_DMA_ID_CC4 ((uint16_t) 0x4U) 0020c5: line 800 define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5U) 0020f1: line 801 define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6U) 002119: line 809 define TIM_CCx_ENABLE ((uint32_t)0x0001U) 00213f: line 810 define TIM_CCx_DISABLE ((uint32_t)0x0000U) 002166: line 811 define TIM_CCxN_ENABLE ((uint32_t)0x0004U) 00218d: line 812 define TIM_CCxN_DISABLE ((uint32_t)0x0000U) 0021b5: line 829 define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) 00220d: line 836 define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) 00225a: line 843 define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_URS)) 0022ab: line 850 define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) 0022fe: line 855 define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) 002360: line 856 define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) 0023b6: line 863 define __HAL_TIM_DISABLE(__HANDLE__) do { if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) { if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) { (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); } } } while(0) 00249a: line 879 define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS)) 0024ed: line 889 define __HAL_TIM_MOE_DISABLE(__HANDLE__) do { if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) { if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) { (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); } } } while(0) 0025d7: line 900 define __HAL_TIM_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) 00263a: line 901 define __HAL_TIM_ENABLE_DMA(__HANDLE__,__DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) 002692: line 902 define __HAL_TIM_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) 0026f7: line 903 define __HAL_TIM_DISABLE_DMA(__HANDLE__,__DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) 002751: line 904 define __HAL_TIM_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) 0027b5: line 905 define __HAL_TIM_CLEAR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) 00280d: line 907 define __HAL_TIM_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 002898: line 908 define __HAL_TIM_CLEAR_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) 0028f8: line 910 define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) 002966: line 911 define __HAL_TIM_SET_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) 0029c5: line 913 define TIM_SET_ICPRESCALERVALUE(__HANDLE__,__CHANNEL__,__ICPSC__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) : ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8))) 002b3e: line 919 define TIM_RESET_ICPRESCALERVALUE(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) : ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) 002ce1: line 925 define TIM_SET_CAPTUREPOLARITY(__HANDLE__,__CHANNEL__,__POLARITY__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) : ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P))) 002e7e: line 931 define TIM_RESET_CAPTUREPOLARITY(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) : ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P)) 003049: line 943 define __HAL_TIM_SET_COUNTER(__HANDLE__,__COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) 0030a8: line 950 define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) 0030eb: line 959 define __HAL_TIM_SET_AUTORELOAD(__HANDLE__,__AUTORELOAD__) do{ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); (__HANDLE__)->Init.Period = (__AUTORELOAD__); } while(0) 00318f: line 969 define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) 0031d5: line 982 define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__,__CKD__) do{ (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); (__HANDLE__)->Instance->CR1 |= (__CKD__); (__HANDLE__)->Init.ClockDivision = (__CKD__); } while(0) 0032a8: line 993 define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) 0032ff: line 1013 define __HAL_TIM_SET_ICPRESCALER(__HANDLE__,__CHANNEL__,__ICPSC__) do{ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); } while(0) 0033ca: line 1030 define __HAL_TIM_GET_ICPRESCALER(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) : ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) : (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8) 00354a: line 1052 define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__,__CHANNEL__,__POLARITY__) do{ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); }while(0) 00361c: include at line 1063 - file 3 003620: end include 003621: line 1278 define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || ((__MODE__) == TIM_COUNTERMODE_DOWN) || ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) 003725: line 1284 define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) 0037c4: line 1288 define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || ((__STATE__) == TIM_OCFAST_ENABLE)) 003830: line 1291 define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || ((STATE) == TIM_OUTPUTSTATE_ENABLE)) 00389c: line 1294 define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || ((STATE) == TIM_OUTPUTNSTATE_ENABLE)) 00390b: line 1297 define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || ((__POLARITY__) == TIM_OCPOLARITY_LOW)) 003983: line 1300 define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) 0039fe: line 1303 define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || ((__STATE__) == TIM_OCIDLESTATE_RESET)) 003a71: line 1306 define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || ((__STATE__) == TIM_OCNIDLESTATE_RESET)) 003ae7: line 1309 define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) 003b94: line 1313 define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || ((__SELECTION__) == TIM_ICSELECTION_TRC)) 003c49: line 1317 define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || ((__PRESCALER__) == TIM_ICPSC_DIV2) || ((__PRESCALER__) == TIM_ICPSC_DIV4) || ((__PRESCALER__) == TIM_ICPSC_DIV8)) 003d0a: line 1322 define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || ((__MODE__) == TIM_OPMODE_REPETITIVE)) 003d74: line 1325 define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || ((__MODE__) == TIM_ENCODERMODE_TI2) || ((__MODE__) == TIM_ENCODERMODE_TI12)) 003e0a: line 1329 define IS_TIM_IT(__IT__) ((((__IT__) & 0xFFFFFF00U) == 0x00000000U) && ((__IT__) != 0x00000000U)) 003e68: line 1332 define IS_TIM_GET_IT(__IT__) (((__IT__) == TIM_IT_UPDATE) || ((__IT__) == TIM_IT_CC1) || ((__IT__) == TIM_IT_CC2) || ((__IT__) == TIM_IT_CC3) || ((__IT__) == TIM_IT_CC4) || ((__IT__) == TIM_IT_COM) || ((__IT__) == TIM_IT_TRIGGER) || ((__IT__) == TIM_IT_BREAK)) 003f69: line 1341 define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 003fdb: line 1343 define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 00404f: line 1345 define IS_TIM_FLAG(__FLAG__) (((__FLAG__) == TIM_FLAG_UPDATE) || ((__FLAG__) == TIM_FLAG_CC1) || ((__FLAG__) == TIM_FLAG_CC2) || ((__FLAG__) == TIM_FLAG_CC3) || ((__FLAG__) == TIM_FLAG_CC4) || ((__FLAG__) == TIM_FLAG_COM) || ((__FLAG__) == TIM_FLAG_TRIGGER) || ((__FLAG__) == TIM_FLAG_BREAK) || ((__FLAG__) == TIM_FLAG_BREAK2) || ((__FLAG__) == TIM_FLAG_CC1OF) || ((__FLAG__) == TIM_FLAG_CC2OF) || ((__FLAG__) == TIM_FLAG_CC3OF) || ((__FLAG__) == TIM_FLAG_CC4OF)) 00421b: line 1359 define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) 0043e0: line 1370 define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) 0044ff: line 1376 define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) 0045e6: line 1381 define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) 004622: line 1383 define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) 0046be: line 1386 define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) 0047bf: line 1391 define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) 004801: line 1393 define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || ((__STATE__) == TIM_OSSR_DISABLE)) 004869: line 1396 define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || ((__STATE__) == TIM_OSSI_DISABLE)) 0048d1: line 1399 define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || ((__LEVEL__) == TIM_LOCKLEVEL_1) || ((__LEVEL__) == TIM_LOCKLEVEL_2) || ((__LEVEL__) == TIM_LOCKLEVEL_3)) 004982: line 1404 define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || ((__STATE__) == TIM_BREAK_DISABLE)) 0049ed: line 1407 define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) 004a6e: line 1410 define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) 004af8: line 1413 define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || ((__SOURCE__) == TIM_TRGO_ENABLE) || ((__SOURCE__) == TIM_TRGO_UPDATE) || ((__SOURCE__) == TIM_TRGO_OC1) || ((__SOURCE__) == TIM_TRGO_OC1REF) || ((__SOURCE__) == TIM_TRGO_OC2REF) || ((__SOURCE__) == TIM_TRGO_OC3REF) || ((__SOURCE__) == TIM_TRGO_OC4REF)) 004c3d: line 1422 define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) 004cba: line 1425 define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_TI1F_ED) || ((__SELECTION__) == TIM_TS_TI1FP1) || ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF)) 004e0b: line 1434 define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || ((SELECTION) == TIM_TS_ITR1) || ((SELECTION) == TIM_TS_ITR2) || ((SELECTION) == TIM_TS_ITR3)) 004eba: line 1439 define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_NONE)) 004fa6: line 1445 define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) 0050d5: line 1451 define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) 0051c6: line 1456 define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) 005204: line 1458 define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) 005297: line 1461 define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || ((__BASE__) == TIM_DMABASE_CR2) || ((__BASE__) == TIM_DMABASE_SMCR) || ((__BASE__) == TIM_DMABASE_DIER) || ((__BASE__) == TIM_DMABASE_SR) || ((__BASE__) == TIM_DMABASE_EGR) || ((__BASE__) == TIM_DMABASE_CCMR1) || ((__BASE__) == TIM_DMABASE_CCMR2) || ((__BASE__) == TIM_DMABASE_CCER) || ((__BASE__) == TIM_DMABASE_CNT) || ((__BASE__) == TIM_DMABASE_PSC) || ((__BASE__) == TIM_DMABASE_ARR) || ((__BASE__) == TIM_DMABASE_RCR) || ((__BASE__) == TIM_DMABASE_CCR1) || ((__BASE__) == TIM_DMABASE_CCR2) || ((__BASE__) == TIM_DMABASE_CCR3) || ((__BASE__) == TIM_DMABASE_CCR4) || ((__BASE__) == TIM_DMABASE_BDTR) || ((__BASE__) == TIM_DMABASE_DCR) || ((__BASE__) == TIM_DMABASE_OR)) 005579: line 1482 define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) 005937: line 1501 define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) 005969: end include 00596a: end of translation unit ** Section #257 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 148 bytes 000000: Header: length 144 (not including this field) version 3 prologue length 133 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_tim.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 74 69 6d 2e 68 00 01 00 00 00005d: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000074: file "stm32f7xx_hal_tim_ex.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 74 69 6d 5f 65 78 2e 68 00 01 00 00 00008e: file "" : 00 00008f: DW_LNS_negate_stmt : 06 000090: DW_LNS_negate_stmt : 06 000091: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_tim.h:1.0 ** Section #258 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 2052 bytes 000000: Header: size 0x800 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_tim.h 000049: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000090: DW_AT_language DW_LANG_C89 000092: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 000109: DW_AT_macro_info 0x0 00010d: DW_AT_stmt_list 0x0 000111: 42 = 0x13 (DW_TAG_structure_type) 000112: DW_AT_sibling 0x180 000114: DW_AT_byte_size 0x14 000115: 30 = 0xd (DW_TAG_member) 000116: DW_AT_name Prescaler 000120: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000125: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000128: 30 = 0xd (DW_TAG_member) 000129: DW_AT_name CounterMode 000135: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00013a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00013d: 30 = 0xd (DW_TAG_member) 00013e: DW_AT_name Period 000145: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00014a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 00014d: 30 = 0xd (DW_TAG_member) 00014e: DW_AT_name ClockDivision 00015c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000161: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000164: 30 = 0xd (DW_TAG_member) 000165: DW_AT_name RepetitionCounter 000177: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00017c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 00017f: 0 null 000180: 80 = 0x16 (DW_TAG_typedef) 000181: DW_AT_name TIM_Base_InitTypeDef 000196: DW_AT_type indirect DW_FORM_ref2 0x111 000199: DW_AT_decl_file 0x1 00019a: DW_AT_decl_line 0x58 00019b: DW_AT_decl_column 0x3 00019c: 42 = 0x13 (DW_TAG_structure_type) 00019d: DW_AT_sibling 0x228 00019f: DW_AT_byte_size 0x1c 0001a0: 30 = 0xd (DW_TAG_member) 0001a1: DW_AT_name OCMode 0001a8: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001ad: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0001b0: 30 = 0xd (DW_TAG_member) 0001b1: DW_AT_name Pulse 0001b7: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001bc: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0001bf: 30 = 0xd (DW_TAG_member) 0001c0: DW_AT_name OCPolarity 0001cb: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001d0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0001d3: 30 = 0xd (DW_TAG_member) 0001d4: DW_AT_name OCNPolarity 0001e0: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001e5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0001e8: 30 = 0xd (DW_TAG_member) 0001e9: DW_AT_name OCFastMode 0001f4: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001f9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 0001fc: 30 = 0xd (DW_TAG_member) 0001fd: DW_AT_name OCIdleState 000209: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00020e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 000211: 30 = 0xd (DW_TAG_member) 000212: DW_AT_name OCNIdleState 00021f: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000224: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 000227: 0 null 000228: 80 = 0x16 (DW_TAG_typedef) 000229: DW_AT_name TIM_OC_InitTypeDef 00023c: DW_AT_type indirect DW_FORM_ref2 0x19c 00023f: DW_AT_decl_file 0x1 000240: DW_AT_decl_line 0x79 000241: DW_AT_decl_column 0x3 000242: 42 = 0x13 (DW_TAG_structure_type) 000243: DW_AT_sibling 0x2f5 000245: DW_AT_byte_size 0x24 000246: 30 = 0xd (DW_TAG_member) 000247: DW_AT_name OCMode 00024e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000253: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000256: 30 = 0xd (DW_TAG_member) 000257: DW_AT_name Pulse 00025d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000262: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000265: 30 = 0xd (DW_TAG_member) 000266: DW_AT_name OCPolarity 000271: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000276: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000279: 30 = 0xd (DW_TAG_member) 00027a: DW_AT_name OCNPolarity 000286: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00028b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00028e: 30 = 0xd (DW_TAG_member) 00028f: DW_AT_name OCIdleState 00029b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002a0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 0002a3: 30 = 0xd (DW_TAG_member) 0002a4: DW_AT_name OCNIdleState 0002b1: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002b6: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 0002b9: 30 = 0xd (DW_TAG_member) 0002ba: DW_AT_name ICPolarity 0002c5: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002ca: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 0002cd: 30 = 0xd (DW_TAG_member) 0002ce: DW_AT_name ICSelection 0002da: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002df: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 0002e2: 30 = 0xd (DW_TAG_member) 0002e3: DW_AT_name ICFilter 0002ec: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002f1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 0002f4: 0 null 0002f5: 80 = 0x16 (DW_TAG_typedef) 0002f6: DW_AT_name TIM_OnePulse_InitTypeDef 00030f: DW_AT_type indirect DW_FORM_ref2 0x242 000312: DW_AT_decl_file 0x1 000313: DW_AT_decl_line 0x9d 000315: DW_AT_decl_column 0x3 000316: 42 = 0x13 (DW_TAG_structure_type) 000317: DW_AT_sibling 0x36b 000319: DW_AT_byte_size 0x10 00031a: 30 = 0xd (DW_TAG_member) 00031b: DW_AT_name ICPolarity 000326: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00032b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00032e: 30 = 0xd (DW_TAG_member) 00032f: DW_AT_name ICSelection 00033b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000340: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000343: 30 = 0xd (DW_TAG_member) 000344: DW_AT_name ICPrescaler 000350: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000355: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000358: 30 = 0xd (DW_TAG_member) 000359: DW_AT_name ICFilter 000362: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000367: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00036a: 0 null 00036b: 80 = 0x16 (DW_TAG_typedef) 00036c: DW_AT_name TIM_IC_InitTypeDef 00037f: DW_AT_type indirect DW_FORM_ref2 0x316 000382: DW_AT_decl_file 0x1 000383: DW_AT_decl_line 0xb1 000385: DW_AT_decl_column 0x3 000386: 42 = 0x13 (DW_TAG_structure_type) 000387: DW_AT_sibling 0x448 000389: DW_AT_byte_size 0x24 00038a: 30 = 0xd (DW_TAG_member) 00038b: DW_AT_name EncoderMode 000397: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00039c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00039f: 30 = 0xd (DW_TAG_member) 0003a0: DW_AT_name IC1Polarity 0003ac: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003b1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0003b4: 30 = 0xd (DW_TAG_member) 0003b5: DW_AT_name IC1Selection 0003c2: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003c7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0003ca: 30 = 0xd (DW_TAG_member) 0003cb: DW_AT_name IC1Prescaler 0003d8: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003dd: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0003e0: 30 = 0xd (DW_TAG_member) 0003e1: DW_AT_name IC1Filter 0003eb: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003f0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 0003f3: 30 = 0xd (DW_TAG_member) 0003f4: DW_AT_name IC2Polarity 000400: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000405: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 000408: 30 = 0xd (DW_TAG_member) 000409: DW_AT_name IC2Selection 000416: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00041b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 00041e: 30 = 0xd (DW_TAG_member) 00041f: DW_AT_name IC2Prescaler 00042c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000431: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 000434: 30 = 0xd (DW_TAG_member) 000435: DW_AT_name IC2Filter 00043f: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000444: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 000447: 0 null 000448: 80 = 0x16 (DW_TAG_typedef) 000449: DW_AT_name TIM_Encoder_InitTypeDef 000461: DW_AT_type indirect DW_FORM_ref2 0x386 000464: DW_AT_decl_file 0x1 000465: DW_AT_decl_line 0xd3 000467: DW_AT_decl_column 0x3 000468: 42 = 0x13 (DW_TAG_structure_type) 000469: DW_AT_sibling 0x4c6 00046b: DW_AT_byte_size 0x10 00046c: 30 = 0xd (DW_TAG_member) 00046d: DW_AT_name ClockSource 000479: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00047e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000481: 30 = 0xd (DW_TAG_member) 000482: DW_AT_name ClockPolarity 000490: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000495: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000498: 30 = 0xd (DW_TAG_member) 000499: DW_AT_name ClockPrescaler 0004a8: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004ad: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0004b0: 30 = 0xd (DW_TAG_member) 0004b1: DW_AT_name ClockFilter 0004bd: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004c2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0004c5: 0 null 0004c6: 80 = 0x16 (DW_TAG_typedef) 0004c7: DW_AT_name TIM_ClockConfigTypeDef 0004de: DW_AT_type indirect DW_FORM_ref2 0x468 0004e1: DW_AT_decl_file 0x1 0004e2: DW_AT_decl_line 0xe2 0004e4: DW_AT_decl_column 0x2 0004e5: 42 = 0x13 (DW_TAG_structure_type) 0004e6: DW_AT_sibling 0x570 0004e8: DW_AT_byte_size 0x14 0004e9: 30 = 0xd (DW_TAG_member) 0004ea: DW_AT_name ClearInputState 0004fa: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004ff: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000502: 30 = 0xd (DW_TAG_member) 000503: DW_AT_name ClearInputSource 000514: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000519: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00051c: 30 = 0xd (DW_TAG_member) 00051d: DW_AT_name ClearInputPolarity 000530: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000535: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000538: 30 = 0xd (DW_TAG_member) 000539: DW_AT_name ClearInputPrescaler 00054d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000552: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000555: 30 = 0xd (DW_TAG_member) 000556: DW_AT_name ClearInputFilter 000567: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00056c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 00056f: 0 null 000570: 80 = 0x16 (DW_TAG_typedef) 000571: DW_AT_name TIM_ClearInputConfigTypeDef 00058d: DW_AT_type indirect DW_FORM_ref2 0x4e5 000590: DW_AT_decl_file 0x1 000591: DW_AT_decl_line 0xf3 000593: DW_AT_decl_column 0x2 000594: 42 = 0x13 (DW_TAG_structure_type) 000595: DW_AT_sibling 0x60c 000597: DW_AT_byte_size 0x14 000598: 30 = 0xd (DW_TAG_member) 000599: DW_AT_name SlaveMode 0005a3: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0005a8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0005ab: 30 = 0xd (DW_TAG_member) 0005ac: DW_AT_name InputTrigger 0005b9: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0005be: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0005c1: 30 = 0xd (DW_TAG_member) 0005c2: DW_AT_name TriggerPolarity 0005d2: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0005d7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0005da: 30 = 0xd (DW_TAG_member) 0005db: DW_AT_name TriggerPrescaler 0005ec: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0005f1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0005f4: 30 = 0xd (DW_TAG_member) 0005f5: DW_AT_name TriggerFilter 000603: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000608: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 00060b: 0 null 00060c: 80 = 0x16 (DW_TAG_typedef) 00060d: DW_AT_name TIM_SlaveConfigTypeDef 000624: DW_AT_type indirect DW_FORM_ref2 0x594 000627: DW_AT_decl_file 0x1 000628: DW_AT_decl_line 0x104 00062a: DW_AT_decl_column 0x2 00062b: 19 = 0x4 (DW_TAG_enumeration_type) 00062c: DW_AT_sibling 0x6a4 00062e: DW_AT_byte_size 0x1 00062f: 20 = 0x28 (DW_TAG_enumerator) 000630: DW_AT_name HAL_TIM_STATE_RESET 000644: DW_AT_const_value indirect DW_FORM_data1 0x0 000646: 20 = 0x28 (DW_TAG_enumerator) 000647: DW_AT_name HAL_TIM_STATE_READY 00065b: DW_AT_const_value indirect DW_FORM_data1 0x1 00065d: 20 = 0x28 (DW_TAG_enumerator) 00065e: DW_AT_name HAL_TIM_STATE_BUSY 000671: DW_AT_const_value indirect DW_FORM_data1 0x2 000673: 20 = 0x28 (DW_TAG_enumerator) 000674: DW_AT_name HAL_TIM_STATE_TIMEOUT 00068a: DW_AT_const_value indirect DW_FORM_data1 0x3 00068c: 20 = 0x28 (DW_TAG_enumerator) 00068d: DW_AT_name HAL_TIM_STATE_ERROR 0006a1: DW_AT_const_value indirect DW_FORM_data1 0x4 0006a3: 0 null 0006a4: 80 = 0x16 (DW_TAG_typedef) 0006a5: DW_AT_name HAL_TIM_StateTypeDef 0006ba: DW_AT_type indirect DW_FORM_ref2 0x62b 0006bd: DW_AT_decl_file 0x1 0006be: DW_AT_decl_line 0x110 0006c0: DW_AT_decl_column 0x2 0006c1: 19 = 0x4 (DW_TAG_enumeration_type) 0006c2: DW_AT_sibling 0x758 0006c4: DW_AT_byte_size 0x1 0006c5: 20 = 0x28 (DW_TAG_enumerator) 0006c6: DW_AT_name HAL_TIM_ACTIVE_CHANNEL_1 0006df: DW_AT_const_value indirect DW_FORM_data1 0x1 0006e1: 20 = 0x28 (DW_TAG_enumerator) 0006e2: DW_AT_name HAL_TIM_ACTIVE_CHANNEL_2 0006fb: DW_AT_const_value indirect DW_FORM_data1 0x2 0006fd: 20 = 0x28 (DW_TAG_enumerator) 0006fe: DW_AT_name HAL_TIM_ACTIVE_CHANNEL_3 000717: DW_AT_const_value indirect DW_FORM_data1 0x4 000719: 20 = 0x28 (DW_TAG_enumerator) 00071a: DW_AT_name HAL_TIM_ACTIVE_CHANNEL_4 000733: DW_AT_const_value indirect DW_FORM_data1 0x8 000735: 20 = 0x28 (DW_TAG_enumerator) 000736: DW_AT_name HAL_TIM_ACTIVE_CHANNEL_CLEARED 000755: DW_AT_const_value indirect DW_FORM_data1 0x0 000757: 0 null 000758: 80 = 0x16 (DW_TAG_typedef) 000759: DW_AT_name HAL_TIM_ActiveChannel 00076f: DW_AT_type indirect DW_FORM_ref2 0x6c1 000772: DW_AT_decl_file 0x1 000773: DW_AT_decl_line 0x11c 000775: DW_AT_decl_column 0x2 000776: 42 = 0x13 (DW_TAG_structure_type) 000777: DW_AT_sibling 0x7d6 000779: DW_AT_byte_size 0x3c 00077a: 30 = 0xd (DW_TAG_member) 00077b: DW_AT_name Instance 000784: DW_AT_type indirect DW_FORM_ref2 0x7d6 000787: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00078a: 30 = 0xd (DW_TAG_member) 00078b: DW_AT_name Init 000790: DW_AT_type indirect DW_FORM_ref2 0x180 000793: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000796: 30 = 0xd (DW_TAG_member) 000797: DW_AT_name Channel 00079f: DW_AT_type indirect DW_FORM_ref2 0x758 0007a2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 0007a5: 3 = 0x1 (DW_TAG_array_type) 0007a6: DW_AT_sibling 0x7ae 0007a8: DW_AT_type indirect DW_FORM_ref2 0x7dc 0007ab: 1 = 0x21 (DW_TAG_subrange_type) 0007ac: DW_AT_upper_bound 0x6 0007ad: 0 null 0007ae: 30 = 0xd (DW_TAG_member) 0007af: DW_AT_name hdma 0007b4: DW_AT_type indirect DW_FORM_ref2 0x7a5 0007b7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 0007ba: 30 = 0xd (DW_TAG_member) 0007bb: DW_AT_name Lock 0007c0: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 0007c5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 0007c8: 30 = 0xd (DW_TAG_member) 0007c9: DW_AT_name State 0007cf: DW_AT_type indirect DW_FORM_ref2 0x7e2 0007d2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 57 } 0007d5: 0 null 0007d6: 34 = 0xf (DW_TAG_pointer_type) 0007d7: DW_AT_type indirect DW_FORM_ref_addr 0x2796+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 0007dc: 34 = 0xf (DW_TAG_pointer_type) 0007dd: DW_AT_type indirect DW_FORM_ref_addr 0x1a0+__ARM_grp..debug_info$stm32f7xx_hal_dma.h$.2_wD1100_gh0hnOcebnc_s10000 0007e2: 116 = 0x35 (DW_TAG_volatile_type) 0007e3: DW_AT_type indirect DW_FORM_ref2 0x6a4 0007e6: 80 = 0x16 (DW_TAG_typedef) 0007e7: DW_AT_name TIM_HandleTypeDef 0007f9: DW_AT_type indirect DW_FORM_ref2 0x776 0007fc: DW_AT_decl_file 0x1 0007fd: DW_AT_decl_line 0x12a 0007ff: DW_AT_decl_column 0x2 000800: 0 null 000801: 0 padding 000802: 0 padding 000803: 0 padding ** Section #419 '.rel.debug_info' (SHT_REL) Size : 432 bytes (alignment 4) Symbol table #343 '.symtab' 54 relocations applied to section #258 '.debug_info' ** Section #259 '__ARM_grp.stm32f7xx_hal_uart_ex.h.2_sO2000_knT90mZZOj2_300000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #260 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 4724 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_UART_EX_H 000020: include at line 47 - file 2 000023: end include 000024: line 66 define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1) 000053: line 67 define UART_WORDLENGTH_8B ((uint32_t)0x0000U) 00007c: line 68 define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0) 0000ab: line 69 define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || ((__LENGTH__) == UART_WORDLENGTH_8B) || ((__LENGTH__) == UART_WORDLENGTH_9B)) 000144: line 72 define IS_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B)) 000184: line 81 define UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000U) 0001b5: line 82 define UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7) 0001ea: line 83 define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || ((__ADDRESS__) == UART_ADDRESS_DETECT_7B)) 00026f: line 105 define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) do { if((__HANDLE__)->Instance == USART1) { switch(__HAL_RCC_GET_USART1_SOURCE()) { case RCC_USART1CLKSOURCE_PCLK2: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; break; case RCC_USART1CLKSOURCE_HSI: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; break; case RCC_USART1CLKSOURCE_SYSCLK: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; break; case RCC_USART1CLKSOURCE_LSE: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; break; default: break; } } else if((__HANDLE__)->Instance == USART2) { switch(__HAL_RCC_GET_USART2_SOURCE()) { case RCC_USART2CLKSOURCE_PCLK1: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; break; case RCC_USART2CLKSOURCE_HSI: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; break; case RCC_USART2CLKSOURCE_SYSCLK: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; break; case RCC_USART2CLKSOURCE_LSE: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; break; default: break; } } else if((__HANDLE__)->Instance == USART3) { switch(__HAL_RCC_GET_USART3_SOURCE()) { case RCC_USART3CLKSOURCE_PCLK1: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; break; case RCC_USART3CLKSOURCE_HSI: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; break; case RCC_USART3CLKSOURCE_SYSCLK: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; break; case RCC_USART3CLKSOURCE_LSE: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; break; default: break; } } else if((__HANDLE__)->Instance == UART4) { switch(__HAL_RCC_GET_UART4_SOURCE()) { case RCC_UART4CLKSOURCE_PCLK1: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; break; case RCC_UART4CLKSOURCE_HSI: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; break; case RCC_UART4CLKSOURCE_SYSCLK: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; break; case RCC_UART4CLKSOURCE_LSE: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; break; default: break; } } else if ((__HANDLE__)->Instance == UART5) { switch(__HAL_RCC_GET_UART5_SOURCE()) { case RCC_UART5CLKSOURCE_PCLK1: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; break; case RCC_UART5CLKSOURCE_HSI: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; break; case RCC_UART5CLKSOURCE_SYSCLK: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; break; case RCC_UART5CLKSOURCE_LSE: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; break; default: break; } } else if((__HANDLE__)->Instance == USART6) { switch(__HAL_RCC_GET_USART6_SOURCE()) { case RCC_USART6CLKSOURCE_PCLK2: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; break; case RCC_USART6CLKSOURCE_HSI: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; break; case RCC_USART6CLKSOURCE_SYSCLK: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; break; case RCC_USART6CLKSOURCE_LSE: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; break; default: break; } } else if ((__HANDLE__)->Instance == UART7) { switch(__HAL_RCC_GET_UART7_SOURCE()) { case RCC_UART7CLKSOURCE_PCLK1: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; break; case RCC_UART7CLKSOURCE_HSI: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; break; case RCC_UART7CLKSOURCE_SYSCLK: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; break; case RCC_UART7CLKSOURCE_LSE: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; break; default: break; } } else if ((__HANDLE__)->Instance == UART8) { switch(__HAL_RCC_GET_UART8_SOURCE()) { case RCC_UART8CLKSOURCE_PCLK1: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; break; case RCC_UART8CLKSOURCE_HSI: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; break; case RCC_UART8CLKSOURCE_SYSCLK: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; break; case RCC_UART8CLKSOURCE_LSE: (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; break; default: break; } } } while(0) 001007: line 278 define UART_MASK_COMPUTATION(__HANDLE__) do { if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) { if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) { (__HANDLE__)->Mask = 0x01FF ; } else { (__HANDLE__)->Mask = 0x00FF ; } } else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) { if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) { (__HANDLE__)->Mask = 0x00FF ; } else { (__HANDLE__)->Mask = 0x007F ; } } else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) { if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) { (__HANDLE__)->Mask = 0x007F ; } else { (__HANDLE__)->Mask = 0x003F ; } } } while(0) 001271: end include 001272: end of translation unit ** Section #261 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 124 bytes 000000: Header: length 120 (not including this field) version 3 prologue length 111 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_uart_ex.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 75 61 72 74 5f 65 78 2e 68 00 01 00 00 000061: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000078: file "" : 00 000079: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart_ex.h:1.0 ** Section #262 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 280 bytes 000000: Header: size 0x114 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart_ex.h 00004d: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000094: DW_AT_language DW_LANG_C89 000096: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010d: DW_AT_macro_info 0x0 000111: DW_AT_stmt_list 0x0 000115: 0 null 000116: 0 padding 000117: 0 padding ** Section #420 '.rel.debug_info' (SHT_REL) Size : 24 bytes (alignment 4) Symbol table #343 '.symtab' 3 relocations applied to section #262 '.debug_info' ** Section #263 '__ARM_grp.stm32f7xx_hal_uart.h.2_kG5100_p3XYNYXQ64c_W10000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #264 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 13456 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_UART_H 00001d: include at line 47 - file 2 000020: end include 000021: line 271 define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U) 000050: line 272 define HAL_UART_ERROR_PE ((uint32_t)0x00000001U) 00007d: line 273 define HAL_UART_ERROR_NE ((uint32_t)0x00000002U) 0000aa: line 274 define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) 0000d7: line 275 define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) 000105: line 276 define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) 000133: line 283 define UART_STOPBITS_1 ((uint32_t)0x00000000U) 00015e: line 284 define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) 00018e: line 292 define UART_PARITY_NONE ((uint32_t)0x00000000U) 0001ba: line 293 define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) 0001e8: line 294 define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) 000226: line 302 define UART_HWCONTROL_NONE ((uint32_t)0x00000000U) 000255: line 303 define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) 000286: line 304 define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) 0002b7: line 305 define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) 0002ff: line 313 define UART_MODE_RX ((uint32_t)USART_CR1_RE) 000328: line 314 define UART_MODE_TX ((uint32_t)USART_CR1_TE) 000351: line 315 define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) 00038d: line 323 define UART_STATE_DISABLE ((uint32_t)0x00000000U) 0003bb: line 324 define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) 0003e9: line 332 define UART_OVERSAMPLING_16 ((uint32_t)0x00000000U) 000419: line 333 define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) 00044c: line 341 define UART_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000U) 000483: line 342 define UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) 0004be: line 350 define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x0000U) 0004fd: line 351 define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0) 00054b: line 352 define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1) 000597: line 353 define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE) 0005e1: line 361 define UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000U) 00061a: line 362 define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) 000656: line 370 define UART_LIN_DISABLE ((uint32_t)0x00000000U) 000682: line 371 define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN) 0006b1: line 379 define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000U) 0006ea: line 380 define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) 000726: line 388 define UART_DMA_TX_DISABLE ((uint32_t)0x00000000U) 000755: line 389 define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) 000786: line 397 define UART_DMA_RX_DISABLE ((uint32_t)0x0000U) 0007b1: line 398 define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) 0007e2: line 406 define UART_HALF_DUPLEX_DISABLE ((uint32_t)0x0000U) 000812: line 407 define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL) 000849: line 415 define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000U) 00087f: line 416 define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) 0008bb: line 424 define UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) 0008f0: line 425 define UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ) 000926: line 426 define UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ) 00095b: line 427 define UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) 000994: line 428 define UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) 0009cd: line 436 define UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000U) 000a00: line 437 define UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001U) 000a39: line 438 define UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002U) 000a72: line 439 define UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004U) 000aad: line 440 define UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008U) 000ae2: line 441 define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010U) 000b23: line 442 define UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020U) 000b65: line 443 define UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040U) 000ba2: line 444 define UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080U) 000bdb: line 452 define UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000U) 000c14: line 453 define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) 000c50: line 461 define UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000U) 000c89: line 462 define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) 000cc5: line 470 define UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000U) 000d00: line 471 define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) 000d40: line 479 define UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000U) 000d78: line 480 define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) 000db2: line 488 define UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000U) 000dec: line 489 define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) 000e2c: line 497 define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000U) 000e6c: line 498 define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN) 000eaf: line 506 define UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000U) 000eee: line 507 define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) 000f31: line 515 define UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000U) 000f6d: line 516 define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) 000faf: line 524 define UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000U) 000feb: line 525 define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME) 001028: line 533 define UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24U) 001055: line 541 define UART_DE_POLARITY_HIGH ((uint32_t)0x00000000U) 001086: line 542 define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP) 0010b8: line 550 define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21U) 0010ea: line 558 define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16U) 00111c: line 566 define UART_IT_MASK ((uint32_t)0x001FU) 001140: line 574 define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU 001165: line 584 define UART_FLAG_TEACK ((uint32_t)0x00200000U) 001190: line 585 define UART_FLAG_SBKF ((uint32_t)0x00040000U) 0011ba: line 586 define UART_FLAG_CMF ((uint32_t)0x00020000U) 0011e3: line 587 define UART_FLAG_BUSY ((uint32_t)0x00010000U) 00120d: line 588 define UART_FLAG_ABRF ((uint32_t)0x00008000U) 001237: line 589 define UART_FLAG_ABRE ((uint32_t)0x00004000U) 001261: line 590 define UART_FLAG_EOBF ((uint32_t)0x00001000U) 00128b: line 591 define UART_FLAG_RTOF ((uint32_t)0x00000800U) 0012b5: line 592 define UART_FLAG_CTS ((uint32_t)0x00000400U) 0012de: line 593 define UART_FLAG_CTSIF ((uint32_t)0x00000200U) 001309: line 594 define UART_FLAG_LBDF ((uint32_t)0x00000100U) 001333: line 595 define UART_FLAG_TXE ((uint32_t)0x00000080U) 00135c: line 596 define UART_FLAG_TC ((uint32_t)0x00000040U) 001384: line 597 define UART_FLAG_RXNE ((uint32_t)0x00000020U) 0013ae: line 598 define UART_FLAG_IDLE ((uint32_t)0x00000010U) 0013d8: line 599 define UART_FLAG_ORE ((uint32_t)0x00000008U) 001401: line 600 define UART_FLAG_NE ((uint32_t)0x00000004U) 001429: line 601 define UART_FLAG_FE ((uint32_t)0x00000002U) 001451: line 602 define UART_FLAG_PE ((uint32_t)0x00000001U) 001479: line 617 define UART_IT_PE ((uint32_t)0x0028U) 00149b: line 618 define UART_IT_TXE ((uint32_t)0x0727U) 0014be: line 619 define UART_IT_TC ((uint32_t)0x0626U) 0014e0: line 620 define UART_IT_RXNE ((uint32_t)0x0525U) 001504: line 621 define UART_IT_IDLE ((uint32_t)0x0424U) 001528: line 622 define UART_IT_LBD ((uint32_t)0x0846U) 00154b: line 623 define UART_IT_CTS ((uint32_t)0x096AU) 00156e: line 624 define UART_IT_CM ((uint32_t)0x112EU) 001590: line 633 define UART_IT_ERR ((uint32_t)0x0060U) 0015b3: line 638 define UART_IT_ORE ((uint32_t)0x0300U) 0015d6: line 639 define UART_IT_NE ((uint32_t)0x0200U) 0015f8: line 640 define UART_IT_FE ((uint32_t)0x0100U) 00161a: line 648 define UART_CLEAR_PEF USART_ICR_PECF 00163b: line 649 define UART_CLEAR_FEF USART_ICR_FECF 00165c: line 650 define UART_CLEAR_NEF USART_ICR_NCF 00167c: line 651 define UART_CLEAR_OREF USART_ICR_ORECF 00169f: line 652 define UART_CLEAR_IDLEF USART_ICR_IDLECF 0016c4: line 653 define UART_CLEAR_TCF USART_ICR_TCCF 0016e5: line 654 define UART_CLEAR_LBDF USART_ICR_LBDCF 001708: line 655 define UART_CLEAR_CTSF USART_ICR_CTSCF 00172b: line 656 define UART_CLEAR_RTOF USART_ICR_RTOCF 00174e: line 657 define UART_CLEAR_EOBF USART_ICR_EOBCF 001771: line 658 define UART_CLEAR_CMF USART_ICR_CMCF 001792: line 677 define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ (__HANDLE__)->gState = HAL_UART_STATE_RESET; (__HANDLE__)->RxState = HAL_UART_STATE_RESET; } while(0) 001829: line 685 define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) do{ SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); } while(0) 0018e5: line 709 define __HAL_UART_CLEAR_IT(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__FLAG__)) 001946: line 715 define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_PEF) 00199e: line 721 define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_FEF) 0019f6: line 727 define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_NEF) 001a4e: line 733 define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_OREF) 001aa8: line 739 define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_IDLEF) 001b04: line 768 define __HAL_UART_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) 001b6b: line 786 define __HAL_UART_ENABLE_IT(__HANDLE__,__INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK)))) 001cd5: line 806 define __HAL_UART_DISABLE_IT(__HANDLE__,__INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK)))) 001e46: line 827 define __HAL_UART_GET_IT(__HANDLE__,__IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) 001eb1: line 845 define __HAL_UART_GET_IT_SOURCE(__HANDLE__,__IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK))) 001fbd: line 859 define __HAL_UART_SEND_REQ(__HANDLE__,__REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__)) 00201d: line 865 define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) 00207e: line 871 define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) 0020f8: line 877 define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) 002147: line 883 define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) 002198: line 898 define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) do{ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; } while(0) 00223c: line 917 define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) do{ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); } while(0) 0022e6: line 936 define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) do{ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; } while(0) 00238a: line 955 define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) do{ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); } while(0) 002434: line 974 define UART_DIV_LPUART(_PCLK_,_BAUD_) ((((_PCLK_)*256)+((_BAUD_)/2))/((_BAUD_))) 002481: line 981 define UART_DIV_SAMPLING8(_PCLK_,_BAUD_) ((((_PCLK_)*2)+((_BAUD_)/2))/((_BAUD_))) 0024cf: line 988 define UART_DIV_SAMPLING16(_PCLK_,_BAUD_) ((((_PCLK_))+((_BAUD_)/2))/((_BAUD_))) 00251c: line 996 define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 9000001) 002551: line 1002 define IS_UART_ASSERTIONTIME(TIME) ((TIME) <= 0x1F) 002581: line 1008 define IS_UART_DEASSERTIONTIME(TIME) ((TIME) <= 0x1F) 0025b3: line 1010 define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || ((STOPBITS) == UART_STOPBITS_2)) 002616: line 1013 define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || ((PARITY) == UART_PARITY_EVEN) || ((PARITY) == UART_PARITY_ODD)) 002694: line 1017 define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == UART_HWCONTROL_NONE) || ((CONTROL) == UART_HWCONTROL_RTS) || ((CONTROL) == UART_HWCONTROL_CTS) || ((CONTROL) == UART_HWCONTROL_RTS_CTS)) 002756: line 1023 define IS_UART_MODE(MODE) ((((MODE) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((MODE) != (uint32_t)0x00)) 0027cc: line 1025 define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || ((STATE) == UART_STATE_ENABLE)) 002828: line 1028 define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || ((SAMPLING) == UART_OVERSAMPLING_8)) 002898: line 1031 define IS_UART_ONE_BIT_SAMPLE(ONEBIT) (((ONEBIT) == UART_ONE_BIT_SAMPLE_DISABLE) || ((ONEBIT) == UART_ONE_BIT_SAMPLE_ENABLE)) 002912: line 1034 define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(MODE) (((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME)) 002a1f: line 1039 define IS_UART_RECEIVER_TIMEOUT(TIMEOUT) (((TIMEOUT) == UART_RECEIVER_TIMEOUT_DISABLE) || ((TIMEOUT) == UART_RECEIVER_TIMEOUT_ENABLE)) 002aa2: line 1042 define IS_UART_LIN(LIN) (((LIN) == UART_LIN_DISABLE) || ((LIN) == UART_LIN_ENABLE)) 002af2: line 1045 define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK)) 002b6c: line 1048 define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B)) 002bf4: line 1051 define IS_UART_DMA_TX(DMATX) (((DMATX) == UART_DMA_TX_DISABLE) || ((DMATX) == UART_DMA_TX_ENABLE)) 002c53: line 1054 define IS_UART_DMA_RX(DMARX) (((DMARX) == UART_DMA_RX_DISABLE) || ((DMARX) == UART_DMA_RX_ENABLE)) 002cb2: line 1057 define IS_UART_HALF_DUPLEX(HDSEL) (((HDSEL) == UART_HALF_DUPLEX_DISABLE) || ((HDSEL) == UART_HALF_DUPLEX_ENABLE)) 002d20: line 1060 define IS_UART_REQUEST_PARAMETER(PARAM) (((PARAM) == UART_AUTOBAUD_REQUEST) || ((PARAM) == UART_SENDBREAK_REQUEST) || ((PARAM) == UART_MUTE_MODE_REQUEST) || ((PARAM) == UART_RXDATA_FLUSH_REQUEST) || ((PARAM) == UART_TXDATA_FLUSH_REQUEST)) 002e0b: line 1066 define IS_UART_ADVFEATURE_INIT(INIT) ((INIT) <= (UART_ADVFEATURE_NO_INIT | UART_ADVFEATURE_TXINVERT_INIT | UART_ADVFEATURE_RXINVERT_INIT | UART_ADVFEATURE_DATAINVERT_INIT | UART_ADVFEATURE_SWAP_INIT | UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | UART_ADVFEATURE_DMADISABLEONERROR_INIT | UART_ADVFEATURE_AUTOBAUDRATE_INIT | UART_ADVFEATURE_MSBFIRST_INIT)) 002f65: line 1076 define IS_UART_ADVFEATURE_TXINV(TXINV) (((TXINV) == UART_ADVFEATURE_TXINV_DISABLE) || ((TXINV) == UART_ADVFEATURE_TXINV_ENABLE)) 002fe2: line 1079 define IS_UART_ADVFEATURE_RXINV(RXINV) (((RXINV) == UART_ADVFEATURE_RXINV_DISABLE) || ((RXINV) == UART_ADVFEATURE_RXINV_ENABLE)) 00305f: line 1082 define IS_UART_ADVFEATURE_DATAINV(DATAINV) (((DATAINV) == UART_ADVFEATURE_DATAINV_DISABLE) || ((DATAINV) == UART_ADVFEATURE_DATAINV_ENABLE)) 0030e8: line 1085 define IS_UART_ADVFEATURE_SWAP(SWAP) (((SWAP) == UART_ADVFEATURE_SWAP_DISABLE) || ((SWAP) == UART_ADVFEATURE_SWAP_ENABLE)) 00315f: line 1088 define IS_UART_OVERRUN(OVERRUN) (((OVERRUN) == UART_ADVFEATURE_OVERRUN_ENABLE) || ((OVERRUN) == UART_ADVFEATURE_OVERRUN_DISABLE)) 0031dd: line 1091 define IS_UART_ADVFEATURE_AUTOBAUDRATE(AUTOBAUDRATE) (((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || ((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) 003284: line 1094 define IS_UART_ADVFEATURE_DMAONRXERROR(DMA) (((DMA) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || ((DMA) == UART_ADVFEATURE_DMA_DISABLEONRXERROR)) 003310: line 1097 define IS_UART_ADVFEATURE_MSBFIRST(MSBFIRST) (((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_DISABLE) || ((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_ENABLE)) 00339f: line 1100 define IS_UART_MUTE_MODE(MUTE) (((MUTE) == UART_ADVFEATURE_MUTEMODE_DISABLE) || ((MUTE) == UART_ADVFEATURE_MUTEMODE_ENABLE)) 003418: line 1103 define IS_UART_DE_POLARITY(POLARITY) (((POLARITY) == UART_DE_POLARITY_HIGH) || ((POLARITY) == UART_DE_POLARITY_LOW)) 003489: include at line 1110 - file 3 00348d: end include 00348e: end include 00348f: end of translation unit ** Section #265 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 148 bytes 000000: Header: length 144 (not including this field) version 3 prologue length 135 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_uart.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 75 61 72 74 2e 68 00 01 00 00 00005e: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000075: file "stm32f7xx_hal_uart_ex.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 75 61 72 74 5f 65 78 2e 68 00 01 00 00 000090: file "" : 00 000091: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart.h:1.0 ** Section #266 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 1492 bytes 000000: Header: size 0x5d0 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart.h 00004a: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000091: DW_AT_language DW_LANG_C89 000093: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010a: DW_AT_macro_info 0x0 00010e: DW_AT_stmt_list 0x0 000112: 42 = 0x13 (DW_TAG_structure_type) 000113: DW_AT_sibling 0x1ae 000115: DW_AT_byte_size 0x20 000116: 30 = 0xd (DW_TAG_member) 000117: DW_AT_name BaudRate 000120: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000125: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000128: 30 = 0xd (DW_TAG_member) 000129: DW_AT_name WordLength 000134: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000139: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00013c: 30 = 0xd (DW_TAG_member) 00013d: DW_AT_name StopBits 000146: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00014b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 00014e: 30 = 0xd (DW_TAG_member) 00014f: DW_AT_name Parity 000156: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00015b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00015e: 30 = 0xd (DW_TAG_member) 00015f: DW_AT_name Mode 000164: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000169: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 00016c: 30 = 0xd (DW_TAG_member) 00016d: DW_AT_name HwFlowCtl 000177: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00017c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 00017f: 30 = 0xd (DW_TAG_member) 000180: DW_AT_name OverSampling 00018d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000192: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 000195: 30 = 0xd (DW_TAG_member) 000196: DW_AT_name OneBitSampling 0001a5: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001aa: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 0001ad: 0 null 0001ae: 80 = 0x16 (DW_TAG_typedef) 0001af: DW_AT_name UART_InitTypeDef 0001c0: DW_AT_type indirect DW_FORM_ref2 0x112 0001c3: DW_AT_decl_file 0x1 0001c4: DW_AT_decl_line 0x66 0001c5: DW_AT_decl_column 0x2 0001c6: 42 = 0x13 (DW_TAG_structure_type) 0001c7: DW_AT_sibling 0x2b6 0001c9: DW_AT_byte_size 0x28 0001ca: 30 = 0xd (DW_TAG_member) 0001cb: DW_AT_name AdvFeatureInit 0001da: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001df: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0001e2: 30 = 0xd (DW_TAG_member) 0001e3: DW_AT_name TxPinLevelInvert 0001f4: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001f9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0001fc: 30 = 0xd (DW_TAG_member) 0001fd: DW_AT_name RxPinLevelInvert 00020e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000213: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000216: 30 = 0xd (DW_TAG_member) 000217: DW_AT_name DataInvert 000222: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000227: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00022a: 30 = 0xd (DW_TAG_member) 00022b: DW_AT_name Swap 000230: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000235: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000238: 30 = 0xd (DW_TAG_member) 000239: DW_AT_name OverrunDisable 000248: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00024d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 000250: 30 = 0xd (DW_TAG_member) 000251: DW_AT_name DMADisableonRxError 000265: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00026a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 00026d: 30 = 0xd (DW_TAG_member) 00026e: DW_AT_name AutoBaudRateEnable 000281: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000286: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 000289: 30 = 0xd (DW_TAG_member) 00028a: DW_AT_name AutoBaudRateMode 00029b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002a0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 0002a3: 30 = 0xd (DW_TAG_member) 0002a4: DW_AT_name MSBFirst 0002ad: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002b2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 0002b5: 0 null 0002b6: 80 = 0x16 (DW_TAG_typedef) 0002b7: DW_AT_name UART_AdvFeatureInitTypeDef 0002d2: DW_AT_type indirect DW_FORM_ref2 0x1c6 0002d5: DW_AT_decl_file 0x1 0002d6: DW_AT_decl_line 0x8d 0002d8: DW_AT_decl_column 0x3 0002d9: 19 = 0x4 (DW_TAG_enumeration_type) 0002da: DW_AT_sibling 0x3a8 0002dc: DW_AT_byte_size 0x1 0002dd: 20 = 0x28 (DW_TAG_enumerator) 0002de: DW_AT_name HAL_UART_STATE_RESET 0002f3: DW_AT_const_value indirect DW_FORM_data1 0x0 0002f5: 20 = 0x28 (DW_TAG_enumerator) 0002f6: DW_AT_name HAL_UART_STATE_READY 00030b: DW_AT_const_value indirect DW_FORM_data1 0x20 00030d: 20 = 0x28 (DW_TAG_enumerator) 00030e: DW_AT_name HAL_UART_STATE_BUSY 000322: DW_AT_const_value indirect DW_FORM_data1 0x24 000324: 20 = 0x28 (DW_TAG_enumerator) 000325: DW_AT_name HAL_UART_STATE_BUSY_TX 00033c: DW_AT_const_value indirect DW_FORM_data1 0x21 00033e: 20 = 0x28 (DW_TAG_enumerator) 00033f: DW_AT_name HAL_UART_STATE_BUSY_RX 000356: DW_AT_const_value indirect DW_FORM_data1 0x22 000358: 20 = 0x28 (DW_TAG_enumerator) 000359: DW_AT_name HAL_UART_STATE_BUSY_TX_RX 000373: DW_AT_const_value indirect DW_FORM_data1 0x23 000375: 20 = 0x28 (DW_TAG_enumerator) 000376: DW_AT_name HAL_UART_STATE_TIMEOUT 00038d: DW_AT_const_value indirect DW_FORM_data1 0xa0 00038f: 20 = 0x28 (DW_TAG_enumerator) 000390: DW_AT_name HAL_UART_STATE_ERROR 0003a5: DW_AT_const_value indirect DW_FORM_data1 0xe0 0003a7: 0 null 0003a8: 80 = 0x16 (DW_TAG_typedef) 0003a9: DW_AT_name HAL_UART_StateTypeDef 0003bf: DW_AT_type indirect DW_FORM_ref2 0x2d9 0003c2: DW_AT_decl_file 0x1 0003c3: DW_AT_decl_line 0xcb 0003c5: DW_AT_decl_column 0x2 0003c6: 19 = 0x4 (DW_TAG_enumeration_type) 0003c7: DW_AT_sibling 0x468 0003c9: DW_AT_byte_size 0x1 0003ca: 20 = 0x28 (DW_TAG_enumerator) 0003cb: DW_AT_name UART_CLOCKSOURCE_PCLK1 0003e2: DW_AT_const_value indirect DW_FORM_data1 0x0 0003e4: 20 = 0x28 (DW_TAG_enumerator) 0003e5: DW_AT_name UART_CLOCKSOURCE_PCLK2 0003fc: DW_AT_const_value indirect DW_FORM_data1 0x1 0003fe: 20 = 0x28 (DW_TAG_enumerator) 0003ff: DW_AT_name UART_CLOCKSOURCE_HSI 000414: DW_AT_const_value indirect DW_FORM_data1 0x2 000416: 20 = 0x28 (DW_TAG_enumerator) 000417: DW_AT_name UART_CLOCKSOURCE_SYSCLK 00042f: DW_AT_const_value indirect DW_FORM_data1 0x4 000431: 20 = 0x28 (DW_TAG_enumerator) 000432: DW_AT_name UART_CLOCKSOURCE_LSE 000447: DW_AT_const_value indirect DW_FORM_data1 0x8 000449: 20 = 0x28 (DW_TAG_enumerator) 00044a: DW_AT_name UART_CLOCKSOURCE_UNDEFINED 000465: DW_AT_const_value indirect DW_FORM_data1 0x10 000467: 0 null 000468: 80 = 0x16 (DW_TAG_typedef) 000469: DW_AT_name UART_ClockSourceTypeDef 000481: DW_AT_type indirect DW_FORM_ref2 0x3c6 000484: DW_AT_decl_file 0x1 000485: DW_AT_decl_line 0xd8 000487: DW_AT_decl_column 0x2 000488: 42 = 0x13 (DW_TAG_structure_type) 000489: DW_AT_sibling 0x595 00048b: DW_AT_byte_size 0x70 00048c: 30 = 0xd (DW_TAG_member) 00048d: DW_AT_name Instance 000496: DW_AT_type indirect DW_FORM_ref2 0x595 000499: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00049c: 30 = 0xd (DW_TAG_member) 00049d: DW_AT_name Init 0004a2: DW_AT_type indirect DW_FORM_ref2 0x1ae 0004a5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0004a8: 30 = 0xd (DW_TAG_member) 0004a9: DW_AT_name AdvancedInit 0004b6: DW_AT_type indirect DW_FORM_ref2 0x2b6 0004b9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 0004bc: 30 = 0xd (DW_TAG_member) 0004bd: DW_AT_name pTxBuffPtr 0004c8: DW_AT_type indirect DW_FORM_ref2 0x59b 0004cb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 76 } 0004ce: 30 = 0xd (DW_TAG_member) 0004cf: DW_AT_name TxXferSize 0004da: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004df: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 80 } 0004e2: 30 = 0xd (DW_TAG_member) 0004e3: DW_AT_name TxXferCount 0004ef: DW_AT_type indirect DW_FORM_ref2 0x5a1 0004f2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 82 } 0004f5: 30 = 0xd (DW_TAG_member) 0004f6: DW_AT_name pRxBuffPtr 000501: DW_AT_type indirect DW_FORM_ref2 0x59b 000504: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 84 } 000507: 30 = 0xd (DW_TAG_member) 000508: DW_AT_name RxXferSize 000513: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000518: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 88 } 00051b: 30 = 0xd (DW_TAG_member) 00051c: DW_AT_name RxXferCount 000528: DW_AT_type indirect DW_FORM_ref2 0x5a1 00052b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 90 } 00052e: 30 = 0xd (DW_TAG_member) 00052f: DW_AT_name Mask 000534: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000539: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 92 } 00053c: 30 = 0xd (DW_TAG_member) 00053d: DW_AT_name hdmatx 000544: DW_AT_type indirect DW_FORM_ref2 0x5a7 000547: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 96 } 00054a: 30 = 0xd (DW_TAG_member) 00054b: DW_AT_name hdmarx 000552: DW_AT_type indirect DW_FORM_ref2 0x5a7 000555: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 100 } 000558: 30 = 0xd (DW_TAG_member) 000559: DW_AT_name Lock 00055e: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 000563: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 104 } 000566: 30 = 0xd (DW_TAG_member) 000567: DW_AT_name gState 00056e: DW_AT_type indirect DW_FORM_ref2 0x5ad 000571: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 105 } 000574: 30 = 0xd (DW_TAG_member) 000575: DW_AT_name RxState 00057d: DW_AT_type indirect DW_FORM_ref2 0x5ad 000580: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 106 } 000583: 30 = 0xd (DW_TAG_member) 000584: DW_AT_name ErrorCode 00058e: DW_AT_type indirect DW_FORM_ref2 0x5b1 000591: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 108 } 000594: 0 null 000595: 34 = 0xf (DW_TAG_pointer_type) 000596: DW_AT_type indirect DW_FORM_ref_addr 0x289d+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 00059b: 34 = 0xf (DW_TAG_pointer_type) 00059c: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0005a1: 116 = 0x35 (DW_TAG_volatile_type) 0005a2: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0005a7: 34 = 0xf (DW_TAG_pointer_type) 0005a8: DW_AT_type indirect DW_FORM_ref_addr 0x1a0+__ARM_grp..debug_info$stm32f7xx_hal_dma.h$.2_wD1100_gh0hnOcebnc_s10000 0005ad: 116 = 0x35 (DW_TAG_volatile_type) 0005ae: DW_AT_type indirect DW_FORM_ref2 0x3a8 0005b1: 116 = 0x35 (DW_TAG_volatile_type) 0005b2: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0005b7: 80 = 0x16 (DW_TAG_typedef) 0005b8: DW_AT_name UART_HandleTypeDef 0005cb: DW_AT_type indirect DW_FORM_ref2 0x488 0005ce: DW_AT_decl_file 0x1 0005cf: DW_AT_decl_line 0x102 0005d1: DW_AT_decl_column 0x2 0005d2: 0 null 0005d3: 0 padding ** Section #421 '.rel.debug_info' (SHT_REL) Size : 240 bytes (alignment 4) Symbol table #343 '.symtab' 30 relocations applied to section #266 '.debug_info' ** Section #267 '__ARM_grp.stm32f7xx_hal_usart_ex.h.2_kZ0000_lk38sJZEeBc_300000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #268 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 972 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_USART_EX_H 000021: include at line 47 - file 2 000024: end include 000025: line 66 define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1) 000055: line 67 define USART_WORDLENGTH_8B ((uint32_t)0x00000000U) 000083: line 68 define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0) 0000b3: line 93 define __HAL_USART_MASK_COMPUTATION(__HANDLE__) do { if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) { if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) { (__HANDLE__)->Mask = 0x01FF ; } else { (__HANDLE__)->Mask = 0x00FF ; } } else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) { if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) { (__HANDLE__)->Mask = 0x00FF ; } else { (__HANDLE__)->Mask = 0x007F ; } } else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) { if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) { (__HANDLE__)->Mask = 0x007F ; } else { (__HANDLE__)->Mask = 0x003F ; } } } while(0) 000329: line 130 define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || ((__LENGTH__) == USART_WORDLENGTH_8B) || ((__LENGTH__) == USART_WORDLENGTH_9B)) 0003c7: end include 0003c8: end of translation unit ** Section #269 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 128 bytes 000000: Header: length 124 (not including this field) version 3 prologue length 112 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_usart_ex.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 75 73 61 72 74 5f 65 78 2e 68 00 01 00 00 000062: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000079: file "" : 00 00007a: DW_LNS_negate_stmt : 06 00007b: DW_LNS_negate_stmt : 06 00007c: DW_LNS_negate_stmt : 06 00007d: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_usart_ex.h:1.0 [ ** Section #270 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 280 bytes 000000: Header: size 0x114 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_usart_ex.h 00004e: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000095: DW_AT_language DW_LANG_C89 000097: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010e: DW_AT_macro_info 0x0 000112: DW_AT_stmt_list 0x0 000116: 0 null 000117: 0 padding ** Section #422 '.rel.debug_info' (SHT_REL) Size : 24 bytes (alignment 4) Symbol table #343 '.symtab' 3 relocations applied to section #270 '.debug_info' ** Section #271 '__ARM_grp.stm32f7xx_hal_usart.h.2_Iy2100_EAWdV68fLsd_N10000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #272 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 7204 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_USART_H 00001e: include at line 47 - file 2 000021: end include 000022: line 178 define HAL_USART_ERROR_NONE ((uint32_t)0x00000000U) 000052: line 179 define HAL_USART_ERROR_PE ((uint32_t)0x00000001U) 000080: line 180 define HAL_USART_ERROR_NE ((uint32_t)0x00000002U) 0000ae: line 181 define HAL_USART_ERROR_FE ((uint32_t)0x00000004U) 0000dc: line 182 define HAL_USART_ERROR_ORE ((uint32_t)0x00000008U) 00010b: line 183 define HAL_USART_ERROR_DMA ((uint32_t)0x00000010U) 00013a: line 191 define USART_STOPBITS_1 ((uint32_t)0x0000U) 000162: line 192 define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) 000193: line 193 define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) 0001db: line 201 define USART_PARITY_NONE ((uint32_t)0x0000U) 000204: line 202 define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) 000233: line 203 define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) 000272: line 211 define USART_MODE_RX ((uint32_t)USART_CR1_RE) 00029c: line 212 define USART_MODE_TX ((uint32_t)USART_CR1_TE) 0002c6: line 213 define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) 000303: line 221 define USART_OVERSAMPLING_16 ((uint32_t)0x0000U) 000330: line 222 define USART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) 000364: line 229 define USART_CLOCK_DISABLE ((uint32_t)0x0000U) 00038f: line 230 define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN) 0003c1: line 238 define USART_POLARITY_LOW ((uint32_t)0x0000U) 0003eb: line 239 define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) 00041d: line 247 define USART_PHASE_1EDGE ((uint32_t)0x0000U) 000446: line 248 define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) 000476: line 256 define USART_LASTBIT_DISABLE ((uint32_t)0x0000U) 0004a3: line 257 define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) 0004d6: line 265 define USART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) 000510: line 266 define USART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) 00054a: line 276 define USART_FLAG_REACK ((uint32_t)0x00400000U) 000576: line 277 define USART_FLAG_TEACK ((uint32_t)0x00200000U) 0005a2: line 278 define USART_FLAG_BUSY ((uint32_t)0x00010000U) 0005cd: line 279 define USART_FLAG_CTS ((uint32_t)0x00000400U) 0005f7: line 280 define USART_FLAG_CTSIF ((uint32_t)0x00000200U) 000623: line 281 define USART_FLAG_LBDF ((uint32_t)0x00000100U) 00064e: line 282 define USART_FLAG_TXE ((uint32_t)0x00000080U) 000678: line 283 define USART_FLAG_TC ((uint32_t)0x00000040U) 0006a1: line 284 define USART_FLAG_RXNE ((uint32_t)0x00000020U) 0006cc: line 285 define USART_FLAG_IDLE ((uint32_t)0x00000010U) 0006f7: line 286 define USART_FLAG_ORE ((uint32_t)0x00000008U) 000721: line 287 define USART_FLAG_NE ((uint32_t)0x00000004U) 00074a: line 288 define USART_FLAG_FE ((uint32_t)0x00000002U) 000773: line 289 define USART_FLAG_PE ((uint32_t)0x00000001U) 00079c: line 305 define USART_IT_PE ((uint16_t)0x0028U) 0007bf: line 306 define USART_IT_TXE ((uint16_t)0x0727U) 0007e3: line 307 define USART_IT_TC ((uint16_t)0x0626U) 000806: line 308 define USART_IT_RXNE ((uint16_t)0x0525U) 00082b: line 309 define USART_IT_IDLE ((uint16_t)0x0424U) 000850: line 310 define USART_IT_ERR ((uint16_t)0x0060U) 000874: line 312 define USART_IT_ORE ((uint16_t)0x0300U) 000898: line 313 define USART_IT_NE ((uint16_t)0x0200U) 0008bb: line 314 define USART_IT_FE ((uint16_t)0x0100U) 0008de: line 322 define USART_CLEAR_PEF USART_ICR_PECF 000900: line 323 define USART_CLEAR_FEF USART_ICR_FECF 000922: line 324 define USART_CLEAR_NEF USART_ICR_NCF 000943: line 325 define USART_CLEAR_OREF USART_ICR_ORECF 000967: line 326 define USART_CLEAR_IDLEF USART_ICR_IDLECF 00098d: line 327 define USART_CLEAR_TCF USART_ICR_TCCF 0009af: line 328 define USART_CLEAR_CTSF USART_ICR_CTSCF 0009d3: line 346 define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET) 000a2f: line 366 define __HAL_USART_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) 000a97: line 381 define __HAL_USART_ENABLE_IT(__HANDLE__,__INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK)))) 000c05: line 397 define __HAL_USART_DISABLE_IT(__HANDLE__,__INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK)))) 000d7a: line 416 define __HAL_USART_GET_IT(__HANDLE__,__IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) 000de6: line 432 define __HAL_USART_GET_IT_SOURCE(__HANDLE__,__IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & USART_IT_MASK))) 000ef2: line 451 define __HAL_USART_CLEAR_IT(__HANDLE__,__IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) 000f5c: line 462 define __HAL_USART_SEND_REQ(__HANDLE__,__REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) 000fbd: line 468 define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) 00100d: line 474 define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) 00105f: include at line 480 - file 3 001063: end include 001064: line 551 define USART_IT_MASK ((uint16_t)0x001FU) 001089: line 565 define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) do { if((__HANDLE__)->Instance == USART1) { switch(__HAL_RCC_GET_USART1_SOURCE()) { case RCC_USART1CLKSOURCE_PCLK2: (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; break; case RCC_USART1CLKSOURCE_HSI: (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; break; case RCC_USART1CLKSOURCE_SYSCLK: (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; break; case RCC_USART1CLKSOURCE_LSE: (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; break; default: break; } } else if((__HANDLE__)->Instance == USART2) { switch(__HAL_RCC_GET_USART2_SOURCE()) { case RCC_USART2CLKSOURCE_PCLK1: (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; break; case RCC_USART2CLKSOURCE_HSI: (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; break; case RCC_USART2CLKSOURCE_SYSCLK: (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; break; case RCC_USART2CLKSOURCE_LSE: (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; break; default: break; } } else if((__HANDLE__)->Instance == USART3) { switch(__HAL_RCC_GET_USART3_SOURCE()) { case RCC_USART3CLKSOURCE_PCLK1: (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; break; case RCC_USART3CLKSOURCE_HSI: (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; break; case RCC_USART3CLKSOURCE_SYSCLK: (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; break; case RCC_USART3CLKSOURCE_LSE: (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; break; default: break; } } else if((__HANDLE__)->Instance == USART6) { switch(__HAL_RCC_GET_USART6_SOURCE()) { case RCC_USART6CLKSOURCE_PCLK2: (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; break; case RCC_USART6CLKSOURCE_HSI: (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; break; case RCC_USART6CLKSOURCE_SYSCLK: (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; break; case RCC_USART6CLKSOURCE_LSE: (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; break; default: break; } } } while(0) 001790: line 650 define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_1) || ((__STOPBITS__) == USART_STOPBITS_1_5) || ((__STOPBITS__) == USART_STOPBITS_2)) 00182c: line 653 define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || ((__PARITY__) == USART_PARITY_EVEN) || ((__PARITY__) == USART_PARITY_ODD)) 0018be: line 656 define IS_USART_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFFFFFF3U) == 0x00U) && ((__MODE__) != (uint32_t)0x00U)) 00192e: line 657 define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || ((__SAMPLING__) == USART_OVERSAMPLING_8)) 0019ad: line 659 define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__)== USART_CLOCK_DISABLE) || ((__CLOCK__)== USART_CLOCK_ENABLE)) 001a16: line 661 define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH)) 001a81: line 662 define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE)) 001ae6: line 663 define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || ((__LASTBIT__) == USART_LASTBIT_ENABLE)) 001b5d: line 665 define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST)) 001be3: line 667 define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001) 001c21: end include 001c22: end of translation unit ** Section #273 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 152 bytes 000000: Header: length 148 (not including this field) version 3 prologue length 137 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_usart.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 75 73 61 72 74 2e 68 00 01 00 00 00005f: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000076: file "stm32f7xx_hal_usart_ex.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 75 73 61 72 74 5f 65 78 2e 68 00 01 00 00 000092: file "" : 00 000093: DW_LNS_negate_stmt : 06 000094: DW_LNS_negate_stmt : 06 000095: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_usart.h:1.0 ** Section #274 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 1212 bytes 000000: Header: size 0x4b8 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_usart.h 00004b: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000092: DW_AT_language DW_LANG_C89 000094: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010b: DW_AT_macro_info 0x0 00010f: DW_AT_stmt_list 0x0 000113: 42 = 0x13 (DW_TAG_structure_type) 000114: DW_AT_sibling 0x1bf 000116: DW_AT_byte_size 0x24 000117: 30 = 0xd (DW_TAG_member) 000118: DW_AT_name BaudRate 000121: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000126: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000129: 30 = 0xd (DW_TAG_member) 00012a: DW_AT_name WordLength 000135: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00013a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00013d: 30 = 0xd (DW_TAG_member) 00013e: DW_AT_name StopBits 000147: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00014c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 00014f: 30 = 0xd (DW_TAG_member) 000150: DW_AT_name Parity 000157: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00015c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00015f: 30 = 0xd (DW_TAG_member) 000160: DW_AT_name Mode 000165: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00016a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 00016d: 30 = 0xd (DW_TAG_member) 00016e: DW_AT_name OverSampling 00017b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000180: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 000183: 30 = 0xd (DW_TAG_member) 000184: DW_AT_name CLKPolarity 000190: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000195: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 000198: 30 = 0xd (DW_TAG_member) 000199: DW_AT_name CLKPhase 0001a2: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001a7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 0001aa: 30 = 0xd (DW_TAG_member) 0001ab: DW_AT_name CLKLastBit 0001b6: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001bb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 0001be: 0 null 0001bf: 80 = 0x16 (DW_TAG_typedef) 0001c0: DW_AT_name USART_InitTypeDef 0001d2: DW_AT_type indirect DW_FORM_ref2 0x113 0001d5: DW_AT_decl_file 0x1 0001d6: DW_AT_decl_line 0x63 0001d7: DW_AT_decl_column 0x2 0001d8: 19 = 0x4 (DW_TAG_enumeration_type) 0001d9: DW_AT_sibling 0x2af 0001db: DW_AT_byte_size 0x1 0001dc: 20 = 0x28 (DW_TAG_enumerator) 0001dd: DW_AT_name HAL_USART_STATE_RESET 0001f3: DW_AT_const_value indirect DW_FORM_data1 0x0 0001f5: 20 = 0x28 (DW_TAG_enumerator) 0001f6: DW_AT_name HAL_USART_STATE_READY 00020c: DW_AT_const_value indirect DW_FORM_data1 0x1 00020e: 20 = 0x28 (DW_TAG_enumerator) 00020f: DW_AT_name HAL_USART_STATE_BUSY 000224: DW_AT_const_value indirect DW_FORM_data1 0x2 000226: 20 = 0x28 (DW_TAG_enumerator) 000227: DW_AT_name HAL_USART_STATE_BUSY_TX 00023f: DW_AT_const_value indirect DW_FORM_data1 0x12 000241: 20 = 0x28 (DW_TAG_enumerator) 000242: DW_AT_name HAL_USART_STATE_BUSY_RX 00025a: DW_AT_const_value indirect DW_FORM_data1 0x22 00025c: 20 = 0x28 (DW_TAG_enumerator) 00025d: DW_AT_name HAL_USART_STATE_BUSY_TX_RX 000278: DW_AT_const_value indirect DW_FORM_data1 0x32 00027a: 20 = 0x28 (DW_TAG_enumerator) 00027b: DW_AT_name HAL_USART_STATE_TIMEOUT 000293: DW_AT_const_value indirect DW_FORM_data1 0x3 000295: 20 = 0x28 (DW_TAG_enumerator) 000296: DW_AT_name HAL_USART_STATE_ERROR 0002ac: DW_AT_const_value indirect DW_FORM_data1 0x4 0002ae: 0 null 0002af: 80 = 0x16 (DW_TAG_typedef) 0002b0: DW_AT_name HAL_USART_StateTypeDef 0002c7: DW_AT_type indirect DW_FORM_ref2 0x1d8 0002ca: DW_AT_decl_file 0x1 0002cb: DW_AT_decl_line 0x72 0002cc: DW_AT_decl_column 0x2 0002cd: 19 = 0x4 (DW_TAG_enumeration_type) 0002ce: DW_AT_sibling 0x375 0002d0: DW_AT_byte_size 0x1 0002d1: 20 = 0x28 (DW_TAG_enumerator) 0002d2: DW_AT_name USART_CLOCKSOURCE_PCLK1 0002ea: DW_AT_const_value indirect DW_FORM_data1 0x0 0002ec: 20 = 0x28 (DW_TAG_enumerator) 0002ed: DW_AT_name USART_CLOCKSOURCE_PCLK2 000305: DW_AT_const_value indirect DW_FORM_data1 0x1 000307: 20 = 0x28 (DW_TAG_enumerator) 000308: DW_AT_name USART_CLOCKSOURCE_HSI 00031e: DW_AT_const_value indirect DW_FORM_data1 0x2 000320: 20 = 0x28 (DW_TAG_enumerator) 000321: DW_AT_name USART_CLOCKSOURCE_SYSCLK 00033a: DW_AT_const_value indirect DW_FORM_data1 0x4 00033c: 20 = 0x28 (DW_TAG_enumerator) 00033d: DW_AT_name USART_CLOCKSOURCE_LSE 000353: DW_AT_const_value indirect DW_FORM_data1 0x8 000355: 20 = 0x28 (DW_TAG_enumerator) 000356: DW_AT_name USART_CLOCKSOURCE_UNDEFINED 000372: DW_AT_const_value indirect DW_FORM_data1 0x10 000374: 0 null 000375: 80 = 0x16 (DW_TAG_typedef) 000376: DW_AT_name USART_ClockSourceTypeDef 00038f: DW_AT_type indirect DW_FORM_ref2 0x2cd 000392: DW_AT_decl_file 0x1 000393: DW_AT_decl_line 0x80 000395: DW_AT_decl_column 0x2 000396: 42 = 0x13 (DW_TAG_structure_type) 000397: DW_AT_sibling 0x47f 000399: DW_AT_byte_size 0x4c 00039a: 30 = 0xd (DW_TAG_member) 00039b: DW_AT_name Instance 0003a4: DW_AT_type indirect DW_FORM_ref2 0x47f 0003a7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0003aa: 30 = 0xd (DW_TAG_member) 0003ab: DW_AT_name Init 0003b0: DW_AT_type indirect DW_FORM_ref2 0x1bf 0003b3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0003b6: 30 = 0xd (DW_TAG_member) 0003b7: DW_AT_name pTxBuffPtr 0003c2: DW_AT_type indirect DW_FORM_ref2 0x485 0003c5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 0003c8: 30 = 0xd (DW_TAG_member) 0003c9: DW_AT_name TxXferSize 0003d4: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003d9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 0003dc: 30 = 0xd (DW_TAG_member) 0003dd: DW_AT_name TxXferCount 0003e9: DW_AT_type indirect DW_FORM_ref2 0x48b 0003ec: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 46 } 0003ef: 30 = 0xd (DW_TAG_member) 0003f0: DW_AT_name pRxBuffPtr 0003fb: DW_AT_type indirect DW_FORM_ref2 0x485 0003fe: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 000401: 30 = 0xd (DW_TAG_member) 000402: DW_AT_name RxXferSize 00040d: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000412: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 000415: 30 = 0xd (DW_TAG_member) 000416: DW_AT_name RxXferCount 000422: DW_AT_type indirect DW_FORM_ref2 0x48b 000425: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 54 } 000428: 30 = 0xd (DW_TAG_member) 000429: DW_AT_name Mask 00042e: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000433: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 000436: 30 = 0xd (DW_TAG_member) 000437: DW_AT_name hdmatx 00043e: DW_AT_type indirect DW_FORM_ref2 0x491 000441: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 60 } 000444: 30 = 0xd (DW_TAG_member) 000445: DW_AT_name hdmarx 00044c: DW_AT_type indirect DW_FORM_ref2 0x491 00044f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 64 } 000452: 30 = 0xd (DW_TAG_member) 000453: DW_AT_name Lock 000458: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 00045d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 68 } 000460: 30 = 0xd (DW_TAG_member) 000461: DW_AT_name State 000467: DW_AT_type indirect DW_FORM_ref2 0x2af 00046a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 69 } 00046d: 30 = 0xd (DW_TAG_member) 00046e: DW_AT_name ErrorCode 000478: DW_AT_type indirect DW_FORM_ref2 0x497 00047b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 72 } 00047e: 0 null 00047f: 34 = 0xf (DW_TAG_pointer_type) 000480: DW_AT_type indirect DW_FORM_ref_addr 0x289d+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 000485: 34 = 0xf (DW_TAG_pointer_type) 000486: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00048b: 116 = 0x35 (DW_TAG_volatile_type) 00048c: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000491: 34 = 0xf (DW_TAG_pointer_type) 000492: DW_AT_type indirect DW_FORM_ref_addr 0x1a0+__ARM_grp..debug_info$stm32f7xx_hal_dma.h$.2_wD1100_gh0hnOcebnc_s10000 000497: 116 = 0x35 (DW_TAG_volatile_type) 000498: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00049d: 80 = 0x16 (DW_TAG_typedef) 00049e: DW_AT_name USART_HandleTypeDef 0004b2: DW_AT_type indirect DW_FORM_ref2 0x396 0004b5: DW_AT_decl_file 0x1 0004b6: DW_AT_decl_line 0xa4 0004b8: DW_AT_decl_column 0x2 0004b9: 0 null 0004ba: 0 padding 0004bb: 0 padding ** Section #423 '.rel.debug_info' (SHT_REL) Size : 168 bytes (alignment 4) Symbol table #343 '.symtab' 21 relocations applied to section #274 '.debug_info' ** Section #275 '__ARM_grp.stm32f7xx_hal_irda_ex.h.2_IP1000_GwwolZ8zYn7_300000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #276 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 2716 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_IRDA_EX_H 000020: include at line 47 - file 2 000023: end include 000024: line 66 define IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1) 000053: line 67 define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000U) 000080: line 68 define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0) 0000af: line 90 define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) do { if((__HANDLE__)->Instance == USART1) { switch(__HAL_RCC_GET_USART1_SOURCE()) { case RCC_USART1CLKSOURCE_PCLK2: (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; break; case RCC_USART1CLKSOURCE_HSI: (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; break; case RCC_USART1CLKSOURCE_SYSCLK: (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; break; case RCC_USART1CLKSOURCE_LSE: (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; break; default: break; } } else if((__HANDLE__)->Instance == USART2) { switch(__HAL_RCC_GET_USART2_SOURCE()) { case RCC_USART2CLKSOURCE_PCLK1: (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; break; case RCC_USART2CLKSOURCE_HSI: (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; break; case RCC_USART2CLKSOURCE_SYSCLK: (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; break; case RCC_USART2CLKSOURCE_LSE: (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; break; default: break; } } else if((__HANDLE__)->Instance == USART3) { switch(__HAL_RCC_GET_USART3_SOURCE()) { case RCC_USART3CLKSOURCE_PCLK1: (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; break; case RCC_USART3CLKSOURCE_HSI: (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; break; case RCC_USART3CLKSOURCE_SYSCLK: (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; break; case RCC_USART3CLKSOURCE_LSE: (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; break; default: break; } } else if((__HANDLE__)->Instance == USART6) { switch(__HAL_RCC_GET_USART6_SOURCE()) { case RCC_USART6CLKSOURCE_PCLK2: (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; break; case RCC_USART6CLKSOURCE_HSI: (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; break; case RCC_USART6CLKSOURCE_SYSCLK: (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; break; case RCC_USART6CLKSOURCE_LSE: (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; break; default: break; } } } while(0) 0007a4: line 179 define IRDA_MASK_COMPUTATION(__HANDLE__) do { if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) { if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) { (__HANDLE__)->Mask = 0x01FF ; } else { (__HANDLE__)->Mask = 0x00FF ; } } else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) { if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) { (__HANDLE__)->Mask = 0x00FF ; } else { (__HANDLE__)->Mask = 0x007F ; } } else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) { if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) { (__HANDLE__)->Mask = 0x007F ; } else { (__HANDLE__)->Mask = 0x003F ; } } } while(0) 000a0e: line 216 define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_7B) || ((LENGTH) == IRDA_WORDLENGTH_8B) || ((LENGTH) == IRDA_WORDLENGTH_9B)) 000a98: end include 000a99: end of translation unit ** Section #277 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 124 bytes 000000: Header: length 120 (not including this field) version 3 prologue length 111 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_irda_ex.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 69 72 64 61 5f 65 78 2e 68 00 01 00 00 000061: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000078: file "" : 00 000079: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_irda_ex.h:1.0 ** Section #278 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 280 bytes 000000: Header: size 0x114 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_irda_ex.h 00004d: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000094: DW_AT_language DW_LANG_C89 000096: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010d: DW_AT_macro_info 0x0 000111: DW_AT_stmt_list 0x0 000115: 0 null 000116: 0 padding 000117: 0 padding ** Section #424 '.rel.debug_info' (SHT_REL) Size : 24 bytes (alignment 4) Symbol table #343 '.symtab' 3 relocations applied to section #278 '.debug_info' ** Section #279 '__ARM_grp.stm32f7xx_hal_irda.h.2_o_1100_XOhO04P9_J9_K10000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #280 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 6076 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_IRDA_H 00001d: include at line 47 - file 2 000020: end include 000021: line 221 define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U) 000050: line 222 define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U) 00007d: line 223 define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U) 0000aa: line 224 define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U) 0000d7: line 225 define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U) 000105: line 226 define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U) 000133: line 234 define IRDA_PARITY_NONE ((uint32_t)0x0000U) 00015b: line 235 define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE) 000189: line 236 define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) 0001c7: line 245 define IRDA_MODE_RX ((uint32_t)USART_CR1_RE) 0001f0: line 246 define IRDA_MODE_TX ((uint32_t)USART_CR1_TE) 000219: line 247 define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) 000255: line 255 define IRDA_POWERMODE_NORMAL ((uint32_t)0x0000U) 000282: line 256 define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP) 0002b8: line 264 define IRDA_STATE_DISABLE ((uint32_t)0x0000U) 0002e2: line 265 define IRDA_STATE_ENABLE ((uint32_t)USART_CR1_UE) 000310: line 273 define IRDA_MODE_DISABLE ((uint32_t)0x0000U) 000339: line 274 define IRDA_MODE_ENABLE ((uint32_t)USART_CR3_IREN) 000368: line 282 define IRDA_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000U) 00039f: line 283 define IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) 0003da: line 291 define IRDA_DMA_TX_DISABLE ((uint32_t)0x00000000U) 000409: line 292 define IRDA_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) 00043a: line 300 define IRDA_DMA_RX_DISABLE ((uint32_t)0x0000U) 000465: line 301 define IRDA_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) 000496: line 311 define IRDA_FLAG_REACK ((uint32_t)0x00400000U) 0004c1: line 312 define IRDA_FLAG_TEACK ((uint32_t)0x00200000U) 0004ec: line 313 define IRDA_FLAG_BUSY ((uint32_t)0x00010000U) 000516: line 314 define IRDA_FLAG_ABRF ((uint32_t)0x00008000U) 000540: line 315 define IRDA_FLAG_ABRE ((uint32_t)0x00004000U) 00056a: line 316 define IRDA_FLAG_TXE ((uint32_t)0x00000080U) 000593: line 317 define IRDA_FLAG_TC ((uint32_t)0x00000040U) 0005bb: line 318 define IRDA_FLAG_RXNE ((uint32_t)0x00000020U) 0005e5: line 319 define IRDA_FLAG_ORE ((uint32_t)0x00000008U) 00060e: line 320 define IRDA_FLAG_NE ((uint32_t)0x00000004U) 000636: line 321 define IRDA_FLAG_FE ((uint32_t)0x00000002U) 00065e: line 322 define IRDA_FLAG_PE ((uint32_t)0x00000001U) 000686: line 337 define IRDA_IT_PE ((uint16_t)0x0028U) 0006a8: line 338 define IRDA_IT_TXE ((uint16_t)0x0727U) 0006cb: line 339 define IRDA_IT_TC ((uint16_t)0x0626U) 0006ed: line 340 define IRDA_IT_RXNE ((uint16_t)0x0525U) 000711: line 341 define IRDA_IT_IDLE ((uint16_t)0x0424U) 000735: line 352 define IRDA_IT_ERR ((uint16_t)0x0060U) 000758: line 357 define IRDA_IT_ORE ((uint16_t)0x0300U) 00077b: line 358 define IRDA_IT_NE ((uint16_t)0x0200U) 00079d: line 359 define IRDA_IT_FE ((uint16_t)0x0100U) 0007bf: line 367 define IRDA_CLEAR_PEF USART_ICR_PECF 0007e0: line 368 define IRDA_CLEAR_FEF USART_ICR_FECF 000801: line 369 define IRDA_CLEAR_NEF USART_ICR_NCF 000821: line 370 define IRDA_CLEAR_OREF USART_ICR_ORECF 000844: line 371 define IRDA_CLEAR_TCF USART_ICR_TCCF 000865: line 381 define IRDA_AUTOBAUD_REQUEST ((uint16_t)USART_RQR_ABRRQ) 00089a: line 382 define IRDA_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ) 0008d3: line 383 define IRDA_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ) 00090c: line 403 define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET) 000966: line 409 define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) do{ SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); } while(0) 000a22: line 426 define __HAL_IRDA_CLEAR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) 000a7b: line 432 define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF) 000ad6: line 439 define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF) 000b31: line 445 define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF) 000b8c: line 451 define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF) 000be9: line 457 define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF) 000c48: line 480 define __HAL_IRDA_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) 000caf: line 496 define __HAL_IRDA_ENABLE_IT(__HANDLE__,__INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK))): ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK))): ((__HANDLE__)->Instance->CR3 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK)))) 000e14: line 513 define __HAL_IRDA_DISABLE_IT(__HANDLE__,__INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK))): ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK))): ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK)))) 000f9e: line 532 define __HAL_IRDA_GET_IT(__HANDLE__,__IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) 001009: line 549 define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__,__IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & IRDA_IT_MASK))) 001113: line 565 define __HAL_IRDA_CLEAR_IT(__HANDLE__,__IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__)) 00117d: line 578 define __HAL_IRDA_SEND_REQ(__HANDLE__,__REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) 0011dd: line 585 define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) 00122c: line 592 define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) 00127d: include at line 599 - file 3 001281: end include 001282: line 679 define IRDA_IT_MASK ((uint16_t)0x001FU) 0012a6: line 696 define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201) 0012e2: line 702 define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0) 00131c: line 704 define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || ((__PARITY__) == IRDA_PARITY_EVEN) || ((__PARITY__) == IRDA_PARITY_ODD)) 0013aa: line 708 define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00U)) 001433: line 710 define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || ((__MODE__) == IRDA_POWERMODE_NORMAL)) 0014a5: line 713 define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || ((__STATE__) == IRDA_STATE_ENABLE)) 00150d: line 716 define IS_IRDA_MODE(__STATE__) (((__STATE__) == IRDA_MODE_DISABLE) || ((__STATE__) == IRDA_MODE_ENABLE)) 001572: line 719 define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE)) 0015f8: line 722 define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || ((__DMATX__) == IRDA_DMA_TX_ENABLE)) 001663: line 725 define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || ((__DMARX__) == IRDA_DMA_RX_ENABLE)) 0016ce: line 728 define IS_IRDA_REQUEST_PARAMETER(PARAM) (((PARAM) == IRDA_AUTOBAUD_REQUEST) || ((PARAM) == IRDA_SENDBREAK_REQUEST) || ((PARAM) == IRDA_MUTE_MODE_REQUEST) || ((PARAM) == IRDA_RXDATA_FLUSH_REQUEST) || ((PARAM) == IRDA_TXDATA_FLUSH_REQUEST)) 0017b9: end include 0017ba: end of translation unit ** Section #281 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 148 bytes 000000: Header: length 144 (not including this field) version 3 prologue length 135 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_irda.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 69 72 64 61 2e 68 00 01 00 00 00005e: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000075: file "stm32f7xx_hal_irda_ex.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 69 72 64 61 5f 65 78 2e 68 00 01 00 00 000090: file "" : 00 000091: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_irda.h:1.0 ** Section #282 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 1152 bytes 000000: Header: size 0x47c bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_irda.h 00004a: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000091: DW_AT_language DW_LANG_C89 000093: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010a: DW_AT_macro_info 0x0 00010e: DW_AT_stmt_list 0x0 000112: 42 = 0x13 (DW_TAG_structure_type) 000113: DW_AT_sibling 0x181 000115: DW_AT_byte_size 0x14 000116: 30 = 0xd (DW_TAG_member) 000117: DW_AT_name BaudRate 000120: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000125: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000128: 30 = 0xd (DW_TAG_member) 000129: DW_AT_name WordLength 000134: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000139: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00013c: 30 = 0xd (DW_TAG_member) 00013d: DW_AT_name Parity 000144: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000149: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 00014c: 30 = 0xd (DW_TAG_member) 00014d: DW_AT_name Mode 000152: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000157: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00015a: 30 = 0xd (DW_TAG_member) 00015b: DW_AT_name Prescaler 000165: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00016a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 14 } 00016d: 30 = 0xd (DW_TAG_member) 00016e: DW_AT_name PowerMode 000178: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00017d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000180: 0 null 000181: 80 = 0x16 (DW_TAG_typedef) 000182: DW_AT_name IRDA_InitTypeDef 000193: DW_AT_type indirect DW_FORM_ref2 0x112 000196: DW_AT_decl_file 0x1 000197: DW_AT_decl_line 0x59 000198: DW_AT_decl_column 0x2 000199: 19 = 0x4 (DW_TAG_enumeration_type) 00019a: DW_AT_sibling 0x268 00019c: DW_AT_byte_size 0x1 00019d: 20 = 0x28 (DW_TAG_enumerator) 00019e: DW_AT_name HAL_IRDA_STATE_RESET 0001b3: DW_AT_const_value indirect DW_FORM_data1 0x0 0001b5: 20 = 0x28 (DW_TAG_enumerator) 0001b6: DW_AT_name HAL_IRDA_STATE_READY 0001cb: DW_AT_const_value indirect DW_FORM_data1 0x20 0001cd: 20 = 0x28 (DW_TAG_enumerator) 0001ce: DW_AT_name HAL_IRDA_STATE_BUSY 0001e2: DW_AT_const_value indirect DW_FORM_data1 0x24 0001e4: 20 = 0x28 (DW_TAG_enumerator) 0001e5: DW_AT_name HAL_IRDA_STATE_BUSY_TX 0001fc: DW_AT_const_value indirect DW_FORM_data1 0x21 0001fe: 20 = 0x28 (DW_TAG_enumerator) 0001ff: DW_AT_name HAL_IRDA_STATE_BUSY_RX 000216: DW_AT_const_value indirect DW_FORM_data1 0x22 000218: 20 = 0x28 (DW_TAG_enumerator) 000219: DW_AT_name HAL_IRDA_STATE_BUSY_TX_RX 000233: DW_AT_const_value indirect DW_FORM_data1 0x23 000235: 20 = 0x28 (DW_TAG_enumerator) 000236: DW_AT_name HAL_IRDA_STATE_TIMEOUT 00024d: DW_AT_const_value indirect DW_FORM_data1 0xa0 00024f: 20 = 0x28 (DW_TAG_enumerator) 000250: DW_AT_name HAL_IRDA_STATE_ERROR 000265: DW_AT_const_value indirect DW_FORM_data1 0xe0 000267: 0 null 000268: 80 = 0x16 (DW_TAG_typedef) 000269: DW_AT_name HAL_IRDA_StateTypeDef 00027f: DW_AT_type indirect DW_FORM_ref2 0x199 000282: DW_AT_decl_file 0x1 000283: DW_AT_decl_line 0x95 000285: DW_AT_decl_column 0x2 000286: 19 = 0x4 (DW_TAG_enumeration_type) 000287: DW_AT_sibling 0x328 000289: DW_AT_byte_size 0x1 00028a: 20 = 0x28 (DW_TAG_enumerator) 00028b: DW_AT_name IRDA_CLOCKSOURCE_PCLK1 0002a2: DW_AT_const_value indirect DW_FORM_data1 0x0 0002a4: 20 = 0x28 (DW_TAG_enumerator) 0002a5: DW_AT_name IRDA_CLOCKSOURCE_PCLK2 0002bc: DW_AT_const_value indirect DW_FORM_data1 0x1 0002be: 20 = 0x28 (DW_TAG_enumerator) 0002bf: DW_AT_name IRDA_CLOCKSOURCE_HSI 0002d4: DW_AT_const_value indirect DW_FORM_data1 0x2 0002d6: 20 = 0x28 (DW_TAG_enumerator) 0002d7: DW_AT_name IRDA_CLOCKSOURCE_SYSCLK 0002ef: DW_AT_const_value indirect DW_FORM_data1 0x4 0002f1: 20 = 0x28 (DW_TAG_enumerator) 0002f2: DW_AT_name IRDA_CLOCKSOURCE_LSE 000307: DW_AT_const_value indirect DW_FORM_data1 0x8 000309: 20 = 0x28 (DW_TAG_enumerator) 00030a: DW_AT_name IRDA_CLOCKSOURCE_UNDEFINED 000325: DW_AT_const_value indirect DW_FORM_data1 0x10 000327: 0 null 000328: 80 = 0x16 (DW_TAG_typedef) 000329: DW_AT_name IRDA_ClockSourceTypeDef 000341: DW_AT_type indirect DW_FORM_ref2 0x286 000344: DW_AT_decl_file 0x1 000345: DW_AT_decl_line 0xa2 000347: DW_AT_decl_column 0x2 000348: 42 = 0x13 (DW_TAG_structure_type) 000349: DW_AT_sibling 0x441 00034b: DW_AT_byte_size 0x3c 00034c: 30 = 0xd (DW_TAG_member) 00034d: DW_AT_name Instance 000356: DW_AT_type indirect DW_FORM_ref2 0x441 000359: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00035c: 30 = 0xd (DW_TAG_member) 00035d: DW_AT_name Init 000362: DW_AT_type indirect DW_FORM_ref2 0x181 000365: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000368: 30 = 0xd (DW_TAG_member) 000369: DW_AT_name pTxBuffPtr 000374: DW_AT_type indirect DW_FORM_ref2 0x447 000377: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 00037a: 30 = 0xd (DW_TAG_member) 00037b: DW_AT_name TxXferSize 000386: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00038b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 00038e: 30 = 0xd (DW_TAG_member) 00038f: DW_AT_name TxXferCount 00039b: DW_AT_type indirect DW_FORM_ref2 0x44d 00039e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 30 } 0003a1: 30 = 0xd (DW_TAG_member) 0003a2: DW_AT_name pRxBuffPtr 0003ad: DW_AT_type indirect DW_FORM_ref2 0x447 0003b0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 0003b3: 30 = 0xd (DW_TAG_member) 0003b4: DW_AT_name RxXferSize 0003bf: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003c4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 0003c7: 30 = 0xd (DW_TAG_member) 0003c8: DW_AT_name RxXferCount 0003d4: DW_AT_type indirect DW_FORM_ref2 0x44d 0003d7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 38 } 0003da: 30 = 0xd (DW_TAG_member) 0003db: DW_AT_name Mask 0003e0: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003e5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 0003e8: 30 = 0xd (DW_TAG_member) 0003e9: DW_AT_name hdmatx 0003f0: DW_AT_type indirect DW_FORM_ref2 0x453 0003f3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 0003f6: 30 = 0xd (DW_TAG_member) 0003f7: DW_AT_name hdmarx 0003fe: DW_AT_type indirect DW_FORM_ref2 0x453 000401: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 000404: 30 = 0xd (DW_TAG_member) 000405: DW_AT_name Lock 00040a: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 00040f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 000412: 30 = 0xd (DW_TAG_member) 000413: DW_AT_name gState 00041a: DW_AT_type indirect DW_FORM_ref2 0x459 00041d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 53 } 000420: 30 = 0xd (DW_TAG_member) 000421: DW_AT_name RxState 000429: DW_AT_type indirect DW_FORM_ref2 0x459 00042c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 54 } 00042f: 30 = 0xd (DW_TAG_member) 000430: DW_AT_name ErrorCode 00043a: DW_AT_type indirect DW_FORM_ref2 0x45d 00043d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 000440: 0 null 000441: 34 = 0xf (DW_TAG_pointer_type) 000442: DW_AT_type indirect DW_FORM_ref_addr 0x289d+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 000447: 34 = 0xf (DW_TAG_pointer_type) 000448: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00044d: 116 = 0x35 (DW_TAG_volatile_type) 00044e: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000453: 34 = 0xf (DW_TAG_pointer_type) 000454: DW_AT_type indirect DW_FORM_ref_addr 0x1a0+__ARM_grp..debug_info$stm32f7xx_hal_dma.h$.2_wD1100_gh0hnOcebnc_s10000 000459: 116 = 0x35 (DW_TAG_volatile_type) 00045a: DW_AT_type indirect DW_FORM_ref2 0x268 00045d: 116 = 0x35 (DW_TAG_volatile_type) 00045e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000463: 80 = 0x16 (DW_TAG_typedef) 000464: DW_AT_name IRDA_HandleTypeDef 000477: DW_AT_type indirect DW_FORM_ref2 0x348 00047a: DW_AT_decl_file 0x1 00047b: DW_AT_decl_line 0xca 00047d: DW_AT_decl_column 0x2 00047e: 0 null 00047f: 0 padding ** Section #425 '.rel.debug_info' (SHT_REL) Size : 144 bytes (alignment 4) Symbol table #343 '.symtab' 18 relocations applied to section #282 '.debug_info' ** Section #283 '__ARM_grp.stm32f7xx_hal_smartcard_ex.h.2_UK1000_UkUwiv9UvW2_300000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #284 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 2552 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_SMARTCARD_EX_H 000025: include at line 47 - file 2 000028: end include 000029: line 70 define SMARTCARD_TC SMARTCARD_IT_TC 000048: line 121 define SMARTCARD_CLEAR_PEF USART_ICR_PECF 00006d: line 122 define SMARTCARD_CLEAR_FEF USART_ICR_FECF 000092: line 123 define SMARTCARD_CLEAR_NEF USART_ICR_NCF 0000b6: line 124 define SMARTCARD_CLEAR_OREF USART_ICR_ORECF 0000dd: line 125 define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF 000106: line 126 define SMARTCARD_CLEAR_TCF USART_ICR_TCCF 00012b: line 130 define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF 000153: line 131 define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF 00017b: line 143 define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) do { if((__HANDLE__)->Instance == USART1) { switch(__HAL_RCC_GET_USART1_SOURCE()) { case RCC_USART1CLKSOURCE_PCLK2: (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; break; case RCC_USART1CLKSOURCE_HSI: (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; break; case RCC_USART1CLKSOURCE_SYSCLK: (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; break; case RCC_USART1CLKSOURCE_LSE: (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; break; default: break; } } else if((__HANDLE__)->Instance == USART2) { switch(__HAL_RCC_GET_USART2_SOURCE()) { case RCC_USART2CLKSOURCE_PCLK1: (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; break; case RCC_USART2CLKSOURCE_HSI: (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; break; case RCC_USART2CLKSOURCE_SYSCLK: (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; break; case RCC_USART2CLKSOURCE_LSE: (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; break; default: break; } } else if((__HANDLE__)->Instance == USART3) { switch(__HAL_RCC_GET_USART3_SOURCE()) { case RCC_USART3CLKSOURCE_PCLK1: (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; break; case RCC_USART3CLKSOURCE_HSI: (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; break; case RCC_USART3CLKSOURCE_SYSCLK: (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; break; case RCC_USART3CLKSOURCE_LSE: (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; break; default: break; } } else if((__HANDLE__)->Instance == USART6) { switch(__HAL_RCC_GET_USART6_SOURCE()) { case RCC_USART6CLKSOURCE_PCLK2: (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; break; case RCC_USART6CLKSOURCE_HSI: (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; break; case RCC_USART6CLKSOURCE_SYSCLK: (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; break; case RCC_USART6CLKSOURCE_LSE: (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; break; default: break; } } } while(0) 0008c6: line 247 define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) do { (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; } while(0) 000951: line 264 define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) (SMARTCARD_FLAG_TC) 00099b: line 276 define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) ((__TXCOMPLETE__) == SMARTCARD_TC) 0009f6: end include 0009f7: end of translation unit ** Section #285 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 132 bytes 000000: Header: length 128 (not including this field) version 3 prologue length 116 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_smartcard_ex.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 73 6d 61 72 74 63 61 72 64 5f 65 78 2e 68 00 01 00 00 000066: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 00007d: file "" : 00 00007e: DW_LNS_negate_stmt : 06 00007f: DW_LNS_negate_stmt : 06 000080: DW_LNS_negate_stmt : 06 000081: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_smartcard_ex.h:1.0 [ ** Section #286 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 284 bytes 000000: Header: size 0x118 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_smartcard_ex.h 000052: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000099: DW_AT_language DW_LANG_C89 00009b: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 000112: DW_AT_macro_info 0x0 000116: DW_AT_stmt_list 0x0 00011a: 0 null 00011b: 0 padding ** Section #426 '.rel.debug_info' (SHT_REL) Size : 24 bytes (alignment 4) Symbol table #343 '.symtab' 3 relocations applied to section #286 '.debug_info' ** Section #287 '__ARM_grp.stm32f7xx_hal_smartcard.h.2_w94100_O9faRddsNf8_020000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #288 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 10228 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_SMARTCARD_H 000022: include at line 47 - file 2 000025: end include 000026: line 285 define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00U) 000054: line 286 define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x01U) 000080: line 287 define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x02U) 0000ac: line 288 define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x04U) 0000d8: line 289 define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x08U) 000105: line 290 define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x10U) 000132: line 291 define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x20U) 00015f: line 299 define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0) 000194: line 307 define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP)) 0001cb: line 315 define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE) 0001fe: line 316 define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) 000241: line 324 define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE) 00026f: line 325 define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE) 00029d: line 326 define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) 0002de: line 334 define SMARTCARD_POLARITY_LOW ((uint32_t)0x0000U) 00030c: line 335 define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) 000342: line 343 define SMARTCARD_PHASE_1EDGE ((uint32_t)0x0000U) 00036f: line 344 define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) 0003a3: line 352 define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x0000U) 0003d4: line 353 define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) 00040b: line 361 define SMARTCARD_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x0000U) 000443: line 362 define SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) 000483: line 371 define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK) 0004b7: line 372 define SMARTCARD_NACK_DISABLE ((uint32_t)0x0000U) 0004e5: line 380 define SMARTCARD_TIMEOUT_DISABLE ((uint32_t)0x00000000U) 00051a: line 381 define SMARTCARD_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) 000552: line 390 define SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT) 000584: line 391 define SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR) 0005b6: line 400 define SMARTCARD_ADVFEATURE_NO_INIT ((uint32_t)0x00000000U) 0005ee: line 401 define SMARTCARD_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001U) 00062c: line 402 define SMARTCARD_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002U) 00066a: line 403 define SMARTCARD_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004U) 0006aa: line 404 define SMARTCARD_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008U) 0006e4: line 405 define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010U) 00072a: line 406 define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020U) 000771: line 407 define SMARTCARD_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080U) 0007af: line 415 define SMARTCARD_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000U) 0007ed: line 416 define SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) 00082e: line 424 define SMARTCARD_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000U) 00086c: line 425 define SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) 0008ad: line 433 define SMARTCARD_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000U) 0008ed: line 434 define SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) 000932: line 442 define SMARTCARD_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000U) 00096f: line 443 define SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) 0009ae: line 451 define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000U) 0009ed: line 452 define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) 000a32: line 460 define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000U) 000a76: line 461 define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) 000abe: line 469 define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000U) 000aff: line 470 define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) 000b46: line 480 define SMARTCARD_FLAG_REACK ((uint32_t)0x00400000U) 000b76: line 481 define SMARTCARD_FLAG_TEACK ((uint32_t)0x00200000U) 000ba6: line 482 define SMARTCARD_FLAG_BUSY ((uint32_t)0x00010000U) 000bd5: line 483 define SMARTCARD_FLAG_EOBF ((uint32_t)0x00001000U) 000c04: line 484 define SMARTCARD_FLAG_RTOF ((uint32_t)0x00000800U) 000c33: line 485 define SMARTCARD_FLAG_TXE ((uint32_t)0x00000080U) 000c61: line 486 define SMARTCARD_FLAG_TC ((uint32_t)0x00000040U) 000c8e: line 487 define SMARTCARD_FLAG_RXNE ((uint32_t)0x00000020U) 000cbd: line 488 define SMARTCARD_FLAG_IDLE ((uint32_t)0x00000010U) 000cec: line 489 define SMARTCARD_FLAG_ORE ((uint32_t)0x00000008U) 000d1a: line 490 define SMARTCARD_FLAG_NE ((uint32_t)0x00000004U) 000d47: line 491 define SMARTCARD_FLAG_FE ((uint32_t)0x00000002U) 000d74: line 492 define SMARTCARD_FLAG_PE ((uint32_t)0x00000001U) 000da1: line 508 define SMARTCARD_IT_PE ((uint16_t)0x0028U) 000dc8: line 509 define SMARTCARD_IT_TXE ((uint16_t)0x0727U) 000df0: line 510 define SMARTCARD_IT_TC ((uint16_t)0x0626U) 000e17: line 511 define SMARTCARD_IT_RXNE ((uint16_t)0x0525U) 000e40: line 512 define SMARTCARD_IT_IDLE ((uint16_t)0x0424U) 000e69: line 513 define SMARTCARD_IT_ERR ((uint16_t)0x0060U) 000e91: line 514 define SMARTCARD_IT_ORE ((uint16_t)0x0300U) 000eb9: line 515 define SMARTCARD_IT_NE ((uint16_t)0x0200U) 000ee0: line 516 define SMARTCARD_IT_FE ((uint16_t)0x0100U) 000f07: line 518 define SMARTCARD_IT_EOB ((uint16_t)0x0C3BU) 000f2f: line 519 define SMARTCARD_IT_RTO ((uint16_t)0x0B3AU) 000f57: line 528 define SMARTCARD_CLEAR_PEF USART_ICR_PECF 000f7d: line 529 define SMARTCARD_CLEAR_FEF USART_ICR_FECF 000fa3: line 530 define SMARTCARD_CLEAR_NEF USART_ICR_NCF 000fc8: line 531 define SMARTCARD_CLEAR_OREF USART_ICR_ORECF 000ff0: line 532 define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF 00101a: line 533 define SMARTCARD_CLEAR_TCF USART_ICR_TCCF 001040: line 534 define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF 001068: line 535 define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF 001090: line 543 define SMARTCARD_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) 0010ce: line 544 define SMARTCARD_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) 00110c: line 553 define SMARTCARD_CR3_SCARCNT_LSB_POS ((uint32_t) 17U) 00113e: line 561 define SMARTCARD_GTPR_GT_LSB_POS ((uint32_t) 8U) 00116b: line 569 define SMARTCARD_RTOR_BLEN_LSB_POS ((uint32_t) 24U) 00119b: line 577 define SMARTCARD_IT_MASK ((uint16_t)0x001FU) 0011c4: line 596 define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET) 001228: line 603 define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) (__HAL_SMARTCARD_SEND_REQ((__HANDLE__), SMARTCARD_RXDATA_FLUSH_REQUEST)) 0012a1: line 624 define __HAL_SMARTCARD_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) 00130d: line 643 define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) 00136b: line 649 define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF) 0013d5: line 656 define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF) 00143f: line 662 define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF) 0014a9: line 668 define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF) 001515: line 674 define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF) 001583: line 690 define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__,__INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 |= (1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 |= (1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): ((__HANDLE__)->Instance->CR3 |= (1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) 0016fc: line 707 define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__,__INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) 00189a: line 727 define __HAL_SMARTCARD_GET_IT(__HANDLE__,__IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) 00190a: line 745 define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__,__IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK))) 001a1e: line 765 define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__,__IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) 001a8c: line 777 define __HAL_SMARTCARD_SEND_REQ(__HANDLE__,__REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__)) 001af1: line 784 define __HAL_SMARTCARD_ENABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 |= USART_CR1_UE) 001b46: line 791 define __HAL_SMARTCARD_DISABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) 001b9d: line 801 define __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__,__REQUEST__) ((__HANDLE__)->Instance->CR3 |= (__REQUEST__)) 001c0a: line 802 define __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__,__REQUEST__) ((__HANDLE__)->Instance->CR3 &= ~(__REQUEST__)) 001c79: include at line 808 - file 3 001c7d: end include 001c7e: line 877 define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B) 001cd0: line 878 define IS_SMARTCARD_STOPBITS(__STOPBITS__) ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5) 001d22: line 879 define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || ((__PARITY__) == SMARTCARD_PARITY_ODD)) 001d99: line 881 define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFF3) == 0x00) && ((__MODE__) != (uint32_t)0x00)) 001e06: line 882 define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH)) 001e7d: line 883 define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE)) 001eee: line 884 define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE)) 001f71: line 886 define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE)) 002006: line 888 define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || ((__NACK__) == SMARTCARD_NACK_DISABLE)) 002077: line 890 define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE)) 0020fa: line 892 define IS_SMARTCARD_ADVFEATURE_INIT(INIT) ((INIT) <= (SMARTCARD_ADVFEATURE_NO_INIT | SMARTCARD_ADVFEATURE_TXINVERT_INIT | SMARTCARD_ADVFEATURE_RXINVERT_INIT | SMARTCARD_ADVFEATURE_DATAINVERT_INIT | SMARTCARD_ADVFEATURE_SWAP_INIT | SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT | SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | SMARTCARD_ADVFEATURE_MSBFIRST_INIT)) 00225d: line 900 define IS_SMARTCARD_ADVFEATURE_TXINV(TXINV) (((TXINV) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || ((TXINV) == SMARTCARD_ADVFEATURE_TXINV_ENABLE)) 0022e9: line 902 define IS_SMARTCARD_ADVFEATURE_RXINV(RXINV) (((RXINV) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || ((RXINV) == SMARTCARD_ADVFEATURE_RXINV_ENABLE)) 002375: line 904 define IS_SMARTCARD_ADVFEATURE_DATAINV(DATAINV) (((DATAINV) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || ((DATAINV) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE)) 00240d: line 906 define IS_SMARTCARD_ADVFEATURE_SWAP(SWAP) (((SWAP) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || ((SWAP) == SMARTCARD_ADVFEATURE_SWAP_ENABLE)) 002493: line 908 define IS_SMARTCARD_OVERRUN(OVERRUN) (((OVERRUN) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || ((OVERRUN) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE)) 002520: line 910 define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(DMA) (((DMA) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || ((DMA) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR)) 0025bb: line 912 define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001) 0025fd: line 913 define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFF) 00263c: line 914 define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFF) 00268d: line 915 define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7) 0026cd: line 916 define IS_SMARTCARD_ADVFEATURE_MSBFIRST(MSBFIRST) (((MSBFIRST) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || ((MSBFIRST) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE)) 00276b: line 918 define IS_SMARTCARD_REQUEST_PARAMETER(PARAM) (((PARAM) == SMARTCARD_RXDATA_FLUSH_REQUEST) || ((PARAM) == SMARTCARD_TXDATA_FLUSH_REQUEST)) 0027f1: end include 0027f2: end of translation unit ** Section #289 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 160 bytes 000000: Header: length 156 (not including this field) version 3 prologue length 145 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_smartcard.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 73 6d 61 72 74 63 61 72 64 2e 68 00 01 00 00 000063: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 00007a: file "stm32f7xx_hal_smartcard_ex.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 73 6d 61 72 74 63 61 72 64 5f 65 78 2e 68 00 01 00 00 00009a: file "" : 00 00009b: DW_LNS_negate_stmt : 06 00009c: DW_LNS_negate_stmt : 06 00009d: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_smartcard.h:1.0 ** Section #290 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 1728 bytes 000000: Header: size 0x6bc bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_smartcard.h 00004f: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000096: DW_AT_language DW_LANG_C89 000098: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010f: DW_AT_macro_info 0x0 000113: DW_AT_stmt_list 0x0 000117: 42 = 0x13 (DW_TAG_structure_type) 000118: DW_AT_sibling 0x259 00011a: DW_AT_byte_size 0x40 00011b: 30 = 0xd (DW_TAG_member) 00011c: DW_AT_name BaudRate 000125: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00012a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00012d: 30 = 0xd (DW_TAG_member) 00012e: DW_AT_name WordLength 000139: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00013e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000141: 30 = 0xd (DW_TAG_member) 000142: DW_AT_name StopBits 00014b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000150: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000153: 30 = 0xd (DW_TAG_member) 000154: DW_AT_name Parity 00015b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000160: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000163: 30 = 0xd (DW_TAG_member) 000164: DW_AT_name Mode 000169: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00016e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000171: 30 = 0xd (DW_TAG_member) 000172: DW_AT_name CLKPolarity 00017e: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000183: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 000186: 30 = 0xd (DW_TAG_member) 000187: DW_AT_name CLKPhase 000190: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000195: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 000198: 30 = 0xd (DW_TAG_member) 000199: DW_AT_name CLKLastBit 0001a4: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001a9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 0001ac: 30 = 0xd (DW_TAG_member) 0001ad: DW_AT_name OneBitSampling 0001bc: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001c1: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 0001c4: 30 = 0xd (DW_TAG_member) 0001c5: DW_AT_name Prescaler 0001cf: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001d4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 0001d7: 30 = 0xd (DW_TAG_member) 0001d8: DW_AT_name GuardTime 0001e2: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001e7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 0001ea: 30 = 0xd (DW_TAG_member) 0001eb: DW_AT_name NACKEnable 0001f6: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001fb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 0001fe: 30 = 0xd (DW_TAG_member) 0001ff: DW_AT_name TimeOutEnable 00020d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000212: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 000215: 30 = 0xd (DW_TAG_member) 000216: DW_AT_name TimeOutValue 000223: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000228: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 00022b: 30 = 0xd (DW_TAG_member) 00022c: DW_AT_name BlockLength 000238: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00023d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 000240: 30 = 0xd (DW_TAG_member) 000241: DW_AT_name AutoRetryCount 000250: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000255: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 60 } 000258: 0 null 000259: 80 = 0x16 (DW_TAG_typedef) 00025a: DW_AT_name SMARTCARD_InitTypeDef 000270: DW_AT_type indirect DW_FORM_ref2 0x117 000273: DW_AT_decl_file 0x1 000274: DW_AT_decl_line 0x7b 000275: DW_AT_decl_column 0x2 000276: 42 = 0x13 (DW_TAG_structure_type) 000277: DW_AT_sibling 0x350 000279: DW_AT_byte_size 0x24 00027a: 30 = 0xd (DW_TAG_member) 00027b: DW_AT_name AdvFeatureInit 00028a: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00028f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000292: 30 = 0xd (DW_TAG_member) 000293: DW_AT_name TxPinLevelInvert 0002a4: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002a9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0002ac: 30 = 0xd (DW_TAG_member) 0002ad: DW_AT_name RxPinLevelInvert 0002be: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002c3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0002c6: 30 = 0xd (DW_TAG_member) 0002c7: DW_AT_name DataInvert 0002d2: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002d7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0002da: 30 = 0xd (DW_TAG_member) 0002db: DW_AT_name Swap 0002e0: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002e5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 0002e8: 30 = 0xd (DW_TAG_member) 0002e9: DW_AT_name OverrunDisable 0002f8: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002fd: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 000300: 30 = 0xd (DW_TAG_member) 000301: DW_AT_name DMADisableonRxError 000315: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00031a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 00031d: 30 = 0xd (DW_TAG_member) 00031e: DW_AT_name MSBFirst 000327: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00032c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 00032f: 30 = 0xd (DW_TAG_member) 000330: DW_AT_name TxCompletionIndication 000347: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00034c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 00034f: 0 null 000350: 80 = 0x16 (DW_TAG_typedef) 000351: DW_AT_name SMARTCARD_AdvFeatureInitTypeDef 000371: DW_AT_type indirect DW_FORM_ref2 0x276 000374: DW_AT_decl_file 0x1 000375: DW_AT_decl_line 0x9f 000377: DW_AT_decl_column 0x2 000378: 19 = 0x4 (DW_TAG_enumeration_type) 000379: DW_AT_sibling 0x46f 00037b: DW_AT_byte_size 0x1 00037c: 20 = 0x28 (DW_TAG_enumerator) 00037d: DW_AT_name HAL_SMARTCARD_STATE_RESET 000397: DW_AT_const_value indirect DW_FORM_data1 0x0 000399: 20 = 0x28 (DW_TAG_enumerator) 00039a: DW_AT_name HAL_SMARTCARD_STATE_READY 0003b4: DW_AT_const_value indirect DW_FORM_data1 0x20 0003b6: 20 = 0x28 (DW_TAG_enumerator) 0003b7: DW_AT_name HAL_SMARTCARD_STATE_BUSY 0003d0: DW_AT_const_value indirect DW_FORM_data1 0x24 0003d2: 20 = 0x28 (DW_TAG_enumerator) 0003d3: DW_AT_name HAL_SMARTCARD_STATE_BUSY_TX 0003ef: DW_AT_const_value indirect DW_FORM_data1 0x21 0003f1: 20 = 0x28 (DW_TAG_enumerator) 0003f2: DW_AT_name HAL_SMARTCARD_STATE_BUSY_RX 00040e: DW_AT_const_value indirect DW_FORM_data1 0x22 000410: 20 = 0x28 (DW_TAG_enumerator) 000411: DW_AT_name HAL_SMARTCARD_STATE_BUSY_TX_RX 000430: DW_AT_const_value indirect DW_FORM_data1 0x23 000432: 20 = 0x28 (DW_TAG_enumerator) 000433: DW_AT_name HAL_SMARTCARD_STATE_TIMEOUT 00044f: DW_AT_const_value indirect DW_FORM_data1 0xa0 000451: 20 = 0x28 (DW_TAG_enumerator) 000452: DW_AT_name HAL_SMARTCARD_STATE_ERROR 00046c: DW_AT_const_value indirect DW_FORM_data1 0xe0 00046e: 0 null 00046f: 80 = 0x16 (DW_TAG_typedef) 000470: DW_AT_name HAL_SMARTCARD_StateTypeDef 00048b: DW_AT_type indirect DW_FORM_ref2 0x378 00048e: DW_AT_decl_file 0x1 00048f: DW_AT_decl_line 0xdb 000491: DW_AT_decl_column 0x2 000492: 19 = 0x4 (DW_TAG_enumeration_type) 000493: DW_AT_sibling 0x552 000495: DW_AT_byte_size 0x1 000496: 20 = 0x28 (DW_TAG_enumerator) 000497: DW_AT_name SMARTCARD_CLOCKSOURCE_PCLK1 0004b3: DW_AT_const_value indirect DW_FORM_data1 0x0 0004b5: 20 = 0x28 (DW_TAG_enumerator) 0004b6: DW_AT_name SMARTCARD_CLOCKSOURCE_PCLK2 0004d2: DW_AT_const_value indirect DW_FORM_data1 0x1 0004d4: 20 = 0x28 (DW_TAG_enumerator) 0004d5: DW_AT_name SMARTCARD_CLOCKSOURCE_HSI 0004ef: DW_AT_const_value indirect DW_FORM_data1 0x2 0004f1: 20 = 0x28 (DW_TAG_enumerator) 0004f2: DW_AT_name SMARTCARD_CLOCKSOURCE_SYSCLK 00050f: DW_AT_const_value indirect DW_FORM_data1 0x4 000511: 20 = 0x28 (DW_TAG_enumerator) 000512: DW_AT_name SMARTCARD_CLOCKSOURCE_LSE 00052c: DW_AT_const_value indirect DW_FORM_data1 0x8 00052e: 20 = 0x28 (DW_TAG_enumerator) 00052f: DW_AT_name SMARTCARD_CLOCKSOURCE_UNDEFINED 00054f: DW_AT_const_value indirect DW_FORM_data1 0x10 000551: 0 null 000552: 80 = 0x16 (DW_TAG_typedef) 000553: DW_AT_name SMARTCARD_ClockSourceTypeDef 000570: DW_AT_type indirect DW_FORM_ref2 0x492 000573: DW_AT_decl_file 0x1 000574: DW_AT_decl_line 0xe8 000576: DW_AT_decl_column 0x2 000577: 42 = 0x13 (DW_TAG_structure_type) 000578: DW_AT_sibling 0x67b 00057a: DW_AT_byte_size 0x88 00057c: 30 = 0xd (DW_TAG_member) 00057d: DW_AT_name Instance 000586: DW_AT_type indirect DW_FORM_ref2 0x67b 000589: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00058c: 30 = 0xd (DW_TAG_member) 00058d: DW_AT_name Init 000592: DW_AT_type indirect DW_FORM_ref2 0x259 000595: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000598: 30 = 0xd (DW_TAG_member) 000599: DW_AT_name AdvancedInit 0005a6: DW_AT_type indirect DW_FORM_ref2 0x350 0005a9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 68 } 0005ac: 30 = 0xd (DW_TAG_member) 0005ad: DW_AT_name pTxBuffPtr 0005b8: DW_AT_type indirect DW_FORM_ref2 0x681 0005bb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 104 } 0005be: 30 = 0xd (DW_TAG_member) 0005bf: DW_AT_name TxXferSize 0005ca: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0005cf: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 108 } 0005d2: 30 = 0xd (DW_TAG_member) 0005d3: DW_AT_name TxXferCount 0005df: DW_AT_type indirect DW_FORM_ref2 0x687 0005e2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 110 } 0005e5: 30 = 0xd (DW_TAG_member) 0005e6: DW_AT_name pRxBuffPtr 0005f1: DW_AT_type indirect DW_FORM_ref2 0x681 0005f4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 112 } 0005f7: 30 = 0xd (DW_TAG_member) 0005f8: DW_AT_name RxXferSize 000603: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000608: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 116 } 00060b: 30 = 0xd (DW_TAG_member) 00060c: DW_AT_name RxXferCount 000618: DW_AT_type indirect DW_FORM_ref2 0x687 00061b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 118 } 00061e: 30 = 0xd (DW_TAG_member) 00061f: DW_AT_name hdmatx 000626: DW_AT_type indirect DW_FORM_ref2 0x68d 000629: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 120 } 00062c: 30 = 0xd (DW_TAG_member) 00062d: DW_AT_name hdmarx 000634: DW_AT_type indirect DW_FORM_ref2 0x68d 000637: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 124 } 00063a: 30 = 0xd (DW_TAG_member) 00063b: DW_AT_name Lock 000640: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 000645: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 128 } 000649: 30 = 0xd (DW_TAG_member) 00064a: DW_AT_name gState 000651: DW_AT_type indirect DW_FORM_ref2 0x693 000654: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 129 } 000658: 30 = 0xd (DW_TAG_member) 000659: DW_AT_name RxState 000661: DW_AT_type indirect DW_FORM_ref2 0x693 000664: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 130 } 000668: 30 = 0xd (DW_TAG_member) 000669: DW_AT_name ErrorCode 000673: DW_AT_type indirect DW_FORM_ref2 0x697 000676: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 132 } 00067a: 0 null 00067b: 34 = 0xf (DW_TAG_pointer_type) 00067c: DW_AT_type indirect DW_FORM_ref_addr 0x289d+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 000681: 34 = 0xf (DW_TAG_pointer_type) 000682: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000687: 116 = 0x35 (DW_TAG_volatile_type) 000688: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00068d: 34 = 0xf (DW_TAG_pointer_type) 00068e: DW_AT_type indirect DW_FORM_ref_addr 0x1a0+__ARM_grp..debug_info$stm32f7xx_hal_dma.h$.2_wD1100_gh0hnOcebnc_s10000 000693: 116 = 0x35 (DW_TAG_volatile_type) 000694: DW_AT_type indirect DW_FORM_ref2 0x46f 000697: 116 = 0x35 (DW_TAG_volatile_type) 000698: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00069d: 80 = 0x16 (DW_TAG_typedef) 00069e: DW_AT_name SMARTCARD_HandleTypeDef 0006b6: DW_AT_type indirect DW_FORM_ref2 0x577 0006b9: DW_AT_decl_file 0x1 0006ba: DW_AT_decl_line 0x110 0006bc: DW_AT_decl_column 0x2 0006bd: 0 null 0006be: 0 padding 0006bf: 0 padding ** Section #427 '.rel.debug_info' (SHT_REL) Size : 288 bytes (alignment 4) Symbol table #343 '.symtab' 36 relocations applied to section #290 '.debug_info' ** Section #291 '__ARM_grp.stm32f7xx_hal_wwdg.h.2_sTX000_57gUOrj4sNe_d10000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #292 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 1484 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_WWDG_H 00001d: include at line 47 - file 2 000020: end include 000021: line 105 define WWDG_IT_EWI WWDG_CFR_EWI 00003c: line 114 define WWDG_FLAG_EWIF WWDG_SR_EWIF 00005a: line 122 define WWDG_PRESCALER_1 0x00000000U 000079: line 123 define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 00009d: line 124 define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 0000c1: line 125 define WWDG_PRESCALER_8 WWDG_CFR_WDGTB 0000e3: line 133 define WWDG_EWI_DISABLE 0x00000000u 000103: line 134 define WWDG_EWI_ENABLE WWDG_CFR_EWI 000123: line 148 define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || ((__PRESCALER__) == WWDG_PRESCALER_2) || ((__PRESCALER__) == WWDG_PRESCALER_4) || ((__PRESCALER__) == WWDG_PRESCALER_8)) 0001ea: line 153 define IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W)) 000249: line 155 define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T)) 0002aa: line 157 define IS_WWDG_EWI_MODE(__MODE__) (((__MODE__) == WWDG_EWI_ENABLE) || ((__MODE__) == WWDG_EWI_DISABLE)) 00030e: line 175 define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA) 000361: line 186 define __HAL_WWDG_ENABLE_IT(__HANDLE__,__INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__)) 0003c9: line 196 define __HAL_WWDG_GET_IT(__HANDLE__,__INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__)) 00042a: line 205 define __HAL_WWDG_CLEAR_IT(__HANDLE__,__INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__)) 000490: line 215 define __HAL_WWDG_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) 0004f6: line 225 define __HAL_WWDG_CLEAR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) 00054f: line 234 define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__)) 0005ca: end include 0005cb: end of translation unit ** Section #293 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 124 bytes 000000: Header: length 120 (not including this field) version 3 prologue length 108 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_wwdg.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 77 77 64 67 2e 68 00 01 00 00 00005e: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000075: file "" : 00 000076: DW_LNS_negate_stmt : 06 000077: DW_LNS_negate_stmt : 06 000078: DW_LNS_negate_stmt : 06 000079: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_wwdg.h:1.0 [ ** Section #294 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 440 bytes 000000: Header: size 0x1b4 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_wwdg.h 00004a: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000091: DW_AT_language DW_LANG_C89 000093: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010a: DW_AT_macro_info 0x0 00010e: DW_AT_stmt_list 0x0 000112: 42 = 0x13 (DW_TAG_structure_type) 000113: DW_AT_sibling 0x15c 000115: DW_AT_byte_size 0x10 000116: 30 = 0xd (DW_TAG_member) 000117: DW_AT_name Prescaler 000121: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000126: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000129: 30 = 0xd (DW_TAG_member) 00012a: DW_AT_name Window 000131: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000136: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000139: 30 = 0xd (DW_TAG_member) 00013a: DW_AT_name Counter 000142: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000147: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 00014a: 30 = 0xd (DW_TAG_member) 00014b: DW_AT_name EWIMode 000153: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000158: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00015b: 0 null 00015c: 80 = 0x16 (DW_TAG_typedef) 00015d: DW_AT_name WWDG_InitTypeDef 00016e: DW_AT_type indirect DW_FORM_ref2 0x112 000171: DW_AT_decl_file 0x1 000172: DW_AT_decl_line 0x50 000173: DW_AT_decl_column 0x2 000174: 42 = 0x13 (DW_TAG_structure_type) 000175: DW_AT_sibling 0x195 000177: DW_AT_byte_size 0x14 000178: 30 = 0xd (DW_TAG_member) 000179: DW_AT_name Instance 000182: DW_AT_type indirect DW_FORM_ref2 0x195 000185: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000188: 30 = 0xd (DW_TAG_member) 000189: DW_AT_name Init 00018e: DW_AT_type indirect DW_FORM_ref2 0x15c 000191: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000194: 0 null 000195: 34 = 0xf (DW_TAG_pointer_type) 000196: DW_AT_type indirect DW_FORM_ref_addr 0x28d7+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 00019b: 80 = 0x16 (DW_TAG_typedef) 00019c: DW_AT_name WWDG_HandleTypeDef 0001af: DW_AT_type indirect DW_FORM_ref2 0x174 0001b2: DW_AT_decl_file 0x1 0001b3: DW_AT_decl_line 0x5b 0001b4: DW_AT_decl_column 0x2 0001b5: 0 null 0001b6: 0 padding 0001b7: 0 padding ** Section #428 '.rel.debug_info' (SHT_REL) Size : 64 bytes (alignment 4) Symbol table #343 '.symtab' 8 relocations applied to section #294 '.debug_info' ** Section #295 '__ARM_grp.stm32f7xx_ll_usb.h.2_MO2000_K_sR9CwNEYd_K00000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #296 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 2548 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_LL_USB_H 00001b: include at line 47 - file 2 00001e: end include 00001f: line 236 define USB_OTG_MODE_DEVICE 0U 000039: line 237 define USB_OTG_MODE_HOST 1U 000051: line 238 define USB_OTG_MODE_DRD 2U 000068: line 246 define USB_OTG_SPEED_HIGH 0U 000081: line 247 define USB_OTG_SPEED_HIGH_IN_FULL 1U 0000a2: line 248 define USB_OTG_SPEED_LOW 2U 0000ba: line 249 define USB_OTG_SPEED_FULL 3U 0000d3: line 257 define USB_OTG_ULPI_PHY 1U 0000ea: line 258 define USB_OTG_EMBEDDED_PHY 2U 000105: line 266 define USB_OTG_HS_MAX_PACKET_SIZE 512U 000128: line 267 define USB_OTG_FS_MAX_PACKET_SIZE 64U 00014a: line 268 define USB_OTG_MAX_EP0_SIZE 64U 000166: line 276 define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0 << 1) 000195: line 277 define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1 << 1) 0001c4: line 278 define DSTS_ENUMSPD_LS_PHY_6MHZ (2 << 1) 0001e9: line 279 define DSTS_ENUMSPD_FS_PHY_48MHZ (3 << 1) 00020f: line 287 define DCFG_FRAME_INTERVAL_80 0U 00022c: line 288 define DCFG_FRAME_INTERVAL_85 1U 000249: line 289 define DCFG_FRAME_INTERVAL_90 2U 000266: line 290 define DCFG_FRAME_INTERVAL_95 3U 000283: line 298 define DEP0CTL_MPS_64 0U 000298: line 299 define DEP0CTL_MPS_32 1U 0002ad: line 300 define DEP0CTL_MPS_16 2U 0002c2: line 301 define DEP0CTL_MPS_8 3U 0002d6: line 309 define EP_SPEED_LOW 0U 0002e9: line 310 define EP_SPEED_FULL 1U 0002fd: line 311 define EP_SPEED_HIGH 2U 000311: line 319 define EP_TYPE_CTRL 0U 000324: line 320 define EP_TYPE_ISOC 1U 000337: line 321 define EP_TYPE_BULK 2U 00034a: line 322 define EP_TYPE_INTR 3U 00035d: line 323 define EP_TYPE_MSK 3U 00036f: line 331 define STS_GOUT_NAK 1U 000382: line 332 define STS_DATA_UPDT 2U 000396: line 333 define STS_XFER_COMP 3U 0003aa: line 334 define STS_SETUP_COMP 4U 0003bf: line 335 define STS_SETUP_UPDT 6U 0003d4: line 343 define HCFG_30_60_MHZ 0U 0003e9: line 344 define HCFG_48_MHZ 1U 0003fb: line 345 define HCFG_6_MHZ 2U 00040c: line 353 define HPRT0_PRTSPD_HIGH_SPEED 0U 00042a: line 354 define HPRT0_PRTSPD_FULL_SPEED 1U 000448: line 355 define HPRT0_PRTSPD_LOW_SPEED 2U 000465: line 360 define HCCHAR_CTRL 0U 000477: line 361 define HCCHAR_ISOC 1U 000489: line 362 define HCCHAR_BULK 2U 00049b: line 363 define HCCHAR_INTR 3U 0004ad: line 365 define HC_PID_DATA0 0U 0004c0: line 366 define HC_PID_DATA2 1U 0004d3: line 367 define HC_PID_DATA1 2U 0004e6: line 368 define HC_PID_SETUP 3U 0004f9: line 370 define GRXSTS_PKTSTS_IN 2U 000510: line 371 define GRXSTS_PKTSTS_IN_XFER_COMP 3U 000531: line 372 define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U 000555: line 373 define GRXSTS_PKTSTS_CH_HALTED 7U 000573: line 375 define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE) 0005bd: line 376 define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE) 000607: line 378 define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)((uint32_t )USBx + USB_OTG_DEVICE_BASE)) 000659: line 379 define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)((uint32_t)USBx + USB_OTG_IN_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE)) 0006ce: line 380 define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)((uint32_t)USBx + USB_OTG_OUT_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE)) 000746: line 381 define USBx_DFIFO(i) *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + (i) * USB_OTG_FIFO_SIZE) 0007a8: line 383 define USBx_HOST ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE)) 0007f4: line 384 define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE)) 00086f: line 389 define USB_MASK_INTERRUPT(__INSTANCE__,__INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__)) 0008cf: line 390 define USB_UNMASK_INTERRUPT(__INSTANCE__,__INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__)) 000930: line 392 define CLEAR_IN_EP_INTR(__EPNUM__,__INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__)) 00098f: line 393 define CLEAR_OUT_EP_INTR(__EPNUM__,__INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__)) 0009f0: end include 0009f1: end of translation unit ** Section #297 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 120 bytes 000000: Header: length 116 (not including this field) version 3 prologue length 106 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_ll_usb.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 6c 6c 5f 75 73 62 2e 68 00 01 00 00 00005c: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000073: file "" : 00 000074: DW_LNS_negate_stmt : 06 000075: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_usb.h:1.0 [ ** Section #298 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 1556 bytes 000000: Header: size 0x610 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_usb.h 000048: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 00008f: DW_AT_language DW_LANG_C89 000091: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 000108: DW_AT_macro_info 0x0 00010c: DW_AT_stmt_list 0x0 000110: 19 = 0x4 (DW_TAG_enumeration_type) 000111: DW_AT_sibling 0x155 000113: DW_AT_byte_size 0x1 000114: 20 = 0x28 (DW_TAG_enumerator) 000115: DW_AT_name USB_OTG_DEVICE_MODE 000129: DW_AT_const_value indirect DW_FORM_data1 0x0 00012b: 20 = 0x28 (DW_TAG_enumerator) 00012c: DW_AT_name USB_OTG_HOST_MODE 00013e: DW_AT_const_value indirect DW_FORM_data1 0x1 000140: 20 = 0x28 (DW_TAG_enumerator) 000141: DW_AT_name USB_OTG_DRD_MODE 000152: DW_AT_const_value indirect DW_FORM_data1 0x2 000154: 0 null 000155: 80 = 0x16 (DW_TAG_typedef) 000156: DW_AT_name USB_OTG_ModeTypeDef 00016a: DW_AT_type indirect DW_FORM_ref2 0x110 00016d: DW_AT_decl_file 0x1 00016e: DW_AT_decl_line 0x44 00016f: DW_AT_decl_column 0x2 000170: 19 = 0x4 (DW_TAG_enumeration_type) 000171: DW_AT_sibling 0x1c3 000173: DW_AT_byte_size 0x1 000174: 20 = 0x28 (DW_TAG_enumerator) 000175: DW_AT_name URB_IDLE 00017e: DW_AT_const_value indirect DW_FORM_data1 0x0 000180: 20 = 0x28 (DW_TAG_enumerator) 000181: DW_AT_name URB_DONE 00018a: DW_AT_const_value indirect DW_FORM_data1 0x1 00018c: 20 = 0x28 (DW_TAG_enumerator) 00018d: DW_AT_name URB_NOTREADY 00019a: DW_AT_const_value indirect DW_FORM_data1 0x2 00019c: 20 = 0x28 (DW_TAG_enumerator) 00019d: DW_AT_name URB_NYET 0001a6: DW_AT_const_value indirect DW_FORM_data1 0x3 0001a8: 20 = 0x28 (DW_TAG_enumerator) 0001a9: DW_AT_name URB_ERROR 0001b3: DW_AT_const_value indirect DW_FORM_data1 0x4 0001b5: 20 = 0x28 (DW_TAG_enumerator) 0001b6: DW_AT_name URB_STALL 0001c0: DW_AT_const_value indirect DW_FORM_data1 0x5 0001c2: 0 null 0001c3: 80 = 0x16 (DW_TAG_typedef) 0001c4: DW_AT_name USB_OTG_URBStateTypeDef 0001dc: DW_AT_type indirect DW_FORM_ref2 0x170 0001df: DW_AT_decl_file 0x1 0001e0: DW_AT_decl_line 0x51 0001e1: DW_AT_decl_column 0x2 0001e2: 19 = 0x4 (DW_TAG_enumeration_type) 0001e3: DW_AT_sibling 0x257 0001e5: DW_AT_byte_size 0x1 0001e6: 20 = 0x28 (DW_TAG_enumerator) 0001e7: DW_AT_name HC_IDLE 0001ef: DW_AT_const_value indirect DW_FORM_data1 0x0 0001f1: 20 = 0x28 (DW_TAG_enumerator) 0001f2: DW_AT_name HC_XFRC 0001fa: DW_AT_const_value indirect DW_FORM_data1 0x1 0001fc: 20 = 0x28 (DW_TAG_enumerator) 0001fd: DW_AT_name HC_HALTED 000207: DW_AT_const_value indirect DW_FORM_data1 0x2 000209: 20 = 0x28 (DW_TAG_enumerator) 00020a: DW_AT_name HC_NAK 000211: DW_AT_const_value indirect DW_FORM_data1 0x3 000213: 20 = 0x28 (DW_TAG_enumerator) 000214: DW_AT_name HC_NYET 00021c: DW_AT_const_value indirect DW_FORM_data1 0x4 00021e: 20 = 0x28 (DW_TAG_enumerator) 00021f: DW_AT_name HC_STALL 000228: DW_AT_const_value indirect DW_FORM_data1 0x5 00022a: 20 = 0x28 (DW_TAG_enumerator) 00022b: DW_AT_name HC_XACTERR 000236: DW_AT_const_value indirect DW_FORM_data1 0x6 000238: 20 = 0x28 (DW_TAG_enumerator) 000239: DW_AT_name HC_BBLERR 000243: DW_AT_const_value indirect DW_FORM_data1 0x7 000245: 20 = 0x28 (DW_TAG_enumerator) 000246: DW_AT_name HC_DATATGLERR 000254: DW_AT_const_value indirect DW_FORM_data1 0x8 000256: 0 null 000257: 80 = 0x16 (DW_TAG_typedef) 000258: DW_AT_name USB_OTG_HCStateTypeDef 00026f: DW_AT_type indirect DW_FORM_ref2 0x1e2 000272: DW_AT_decl_file 0x1 000273: DW_AT_decl_line 0x61 000274: DW_AT_decl_column 0x2 000275: 42 = 0x13 (DW_TAG_structure_type) 000276: DW_AT_sibling 0x385 000278: DW_AT_byte_size 0x30 000279: 30 = 0xd (DW_TAG_member) 00027a: DW_AT_name dev_endpoints 000288: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00028d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000290: 30 = 0xd (DW_TAG_member) 000291: DW_AT_name Host_channels 00029f: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002a4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0002a7: 30 = 0xd (DW_TAG_member) 0002a8: DW_AT_name speed 0002ae: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002b3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0002b6: 30 = 0xd (DW_TAG_member) 0002b7: DW_AT_name dma_enable 0002c2: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002c7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 0002ca: 30 = 0xd (DW_TAG_member) 0002cb: DW_AT_name ep0_mps 0002d3: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002d8: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 0002db: 30 = 0xd (DW_TAG_member) 0002dc: DW_AT_name phy_itface 0002e7: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002ec: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 0002ef: 30 = 0xd (DW_TAG_member) 0002f0: DW_AT_name Sof_enable 0002fb: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000300: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 000303: 30 = 0xd (DW_TAG_member) 000304: DW_AT_name low_power_enable 000315: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00031a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 00031d: 30 = 0xd (DW_TAG_member) 00031e: DW_AT_name lpm_enable 000329: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00032e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 000331: 30 = 0xd (DW_TAG_member) 000332: DW_AT_name vbus_sensing_enable 000346: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00034b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 00034e: 30 = 0xd (DW_TAG_member) 00034f: DW_AT_name use_dedicated_ep1 000361: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000366: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 000369: 30 = 0xd (DW_TAG_member) 00036a: DW_AT_name use_external_vbus 00037c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000381: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 000384: 0 null 000385: 80 = 0x16 (DW_TAG_typedef) 000386: DW_AT_name USB_OTG_CfgTypeDef 000399: DW_AT_type indirect DW_FORM_ref2 0x275 00039c: DW_AT_decl_file 0x1 00039d: DW_AT_decl_line 0x87 00039f: DW_AT_decl_column 0x2 0003a0: 42 = 0x13 (DW_TAG_structure_type) 0003a1: DW_AT_sibling 0x482 0003a3: DW_AT_byte_size 0x1c 0003a4: 30 = 0xd (DW_TAG_member) 0003a5: DW_AT_name num 0003a9: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003ae: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0003b1: 30 = 0xd (DW_TAG_member) 0003b2: DW_AT_name is_in 0003b8: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003bd: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 1 } 0003c0: 30 = 0xd (DW_TAG_member) 0003c1: DW_AT_name is_stall 0003ca: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003cf: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 2 } 0003d2: 30 = 0xd (DW_TAG_member) 0003d3: DW_AT_name type 0003d8: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003dd: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 3 } 0003e0: 30 = 0xd (DW_TAG_member) 0003e1: DW_AT_name data_pid_start 0003f0: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003f5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0003f8: 30 = 0xd (DW_TAG_member) 0003f9: DW_AT_name even_odd_frame 000408: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00040d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 5 } 000410: 30 = 0xd (DW_TAG_member) 000411: DW_AT_name tx_fifo_num 00041d: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000422: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 6 } 000425: 30 = 0xd (DW_TAG_member) 000426: DW_AT_name maxpacket 000430: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000435: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000438: 30 = 0xd (DW_TAG_member) 000439: DW_AT_name xfer_buff 000443: DW_AT_type indirect DW_FORM_ref2 0x482 000446: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000449: 30 = 0xd (DW_TAG_member) 00044a: DW_AT_name dma_addr 000453: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000458: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 00045b: 30 = 0xd (DW_TAG_member) 00045c: DW_AT_name xfer_len 000465: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00046a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 00046d: 30 = 0xd (DW_TAG_member) 00046e: DW_AT_name xfer_count 000479: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00047e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 000481: 0 null 000482: 34 = 0xf (DW_TAG_pointer_type) 000483: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000488: 80 = 0x16 (DW_TAG_typedef) 000489: DW_AT_name USB_OTG_EPTypeDef 00049b: DW_AT_type indirect DW_FORM_ref2 0x3a0 00049e: DW_AT_decl_file 0x1 00049f: DW_AT_decl_line 0xab 0004a1: DW_AT_decl_column 0x2 0004a2: 42 = 0x13 (DW_TAG_structure_type) 0004a3: DW_AT_sibling 0x5f6 0004a5: DW_AT_byte_size 0x28 0004a6: 30 = 0xd (DW_TAG_member) 0004a7: DW_AT_name dev_addr 0004b0: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004b5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0004b8: 30 = 0xd (DW_TAG_member) 0004b9: DW_AT_name ch_num 0004c0: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004c5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 1 } 0004c8: 30 = 0xd (DW_TAG_member) 0004c9: DW_AT_name ep_num 0004d0: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004d5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 2 } 0004d8: 30 = 0xd (DW_TAG_member) 0004d9: DW_AT_name ep_is_in 0004e2: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004e7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 3 } 0004ea: 30 = 0xd (DW_TAG_member) 0004eb: DW_AT_name speed 0004f1: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004f6: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0004f9: 30 = 0xd (DW_TAG_member) 0004fa: DW_AT_name do_ping 000502: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000507: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 5 } 00050a: 30 = 0xd (DW_TAG_member) 00050b: DW_AT_name process_ping 000518: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00051d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 6 } 000520: 30 = 0xd (DW_TAG_member) 000521: DW_AT_name ep_type 000529: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00052e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 7 } 000531: 30 = 0xd (DW_TAG_member) 000532: DW_AT_name max_packet 00053d: DW_AT_type indirect DW_FORM_ref_addr 0x15d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000542: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000545: 30 = 0xd (DW_TAG_member) 000546: DW_AT_name data_pid 00054f: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000554: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 10 } 000557: 30 = 0xd (DW_TAG_member) 000558: DW_AT_name xfer_buff 000562: DW_AT_type indirect DW_FORM_ref2 0x482 000565: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000568: 30 = 0xd (DW_TAG_member) 000569: DW_AT_name xfer_len 000572: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000577: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 00057a: 30 = 0xd (DW_TAG_member) 00057b: DW_AT_name xfer_count 000586: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00058b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 00058e: 30 = 0xd (DW_TAG_member) 00058f: DW_AT_name toggle_in 000599: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00059e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 0005a1: 30 = 0xd (DW_TAG_member) 0005a2: DW_AT_name toggle_out 0005ad: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0005b2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 25 } 0005b5: 30 = 0xd (DW_TAG_member) 0005b6: DW_AT_name dma_addr 0005bf: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0005c4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 0005c7: 30 = 0xd (DW_TAG_member) 0005c8: DW_AT_name ErrCnt 0005cf: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0005d4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 0005d7: 30 = 0xd (DW_TAG_member) 0005d8: DW_AT_name urb_state 0005e2: DW_AT_type indirect DW_FORM_ref2 0x1c3 0005e5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 0005e8: 30 = 0xd (DW_TAG_member) 0005e9: DW_AT_name state 0005ef: DW_AT_type indirect DW_FORM_ref2 0x257 0005f2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 37 } 0005f5: 0 null 0005f6: 80 = 0x16 (DW_TAG_typedef) 0005f7: DW_AT_name USB_OTG_HCTypeDef 000609: DW_AT_type indirect DW_FORM_ref2 0x4a2 00060c: DW_AT_decl_file 0x1 00060d: DW_AT_decl_line 0xe1 00060f: DW_AT_decl_column 0x2 000610: 0 null 000611: 0 padding 000612: 0 padding 000613: 0 padding ** Section #429 '.rel.debug_info' (SHT_REL) Size : 344 bytes (alignment 4) Symbol table #343 '.symtab' 43 relocations applied to section #298 '.debug_info' ** Section #299 '__ARM_grp.stm32f7xx_hal_pcd_ex.h.2_cx0000_exuvwxHCX03_300000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #300 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 40 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_PCD_EX_H 00001f: include at line 47 - file 2 000022: end include 000023: end include 000024: end of translation unit ** Section #301 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 124 bytes 000000: Header: length 120 (not including this field) version 3 prologue length 110 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_pcd_ex.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 70 63 64 5f 65 78 2e 68 00 01 00 00 000060: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000077: file "" : 00 000078: DW_LNS_negate_stmt : 06 000079: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pcd_ex.h:1.0 [ ** Section #302 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 352 bytes 000000: Header: size 0x15c bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pcd_ex.h 00004c: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000093: DW_AT_language DW_LANG_C89 000095: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010c: DW_AT_macro_info 0x0 000110: DW_AT_stmt_list 0x0 000114: 19 = 0x4 (DW_TAG_enumeration_type) 000115: DW_AT_sibling 0x143 000117: DW_AT_byte_size 0x1 000118: 20 = 0x28 (DW_TAG_enumerator) 000119: DW_AT_name PCD_LPM_L0_ACTIVE 00012b: DW_AT_const_value indirect DW_FORM_data1 0x0 00012d: 20 = 0x28 (DW_TAG_enumerator) 00012e: DW_AT_name PCD_LPM_L1_ACTIVE 000140: DW_AT_const_value indirect DW_FORM_data1 0x1 000142: 0 null 000143: 80 = 0x16 (DW_TAG_typedef) 000144: DW_AT_name PCD_LPM_MsgTypeDef 000157: DW_AT_type indirect DW_FORM_ref2 0x114 00015a: DW_AT_decl_file 0x1 00015b: DW_AT_decl_line 0x3d 00015c: DW_AT_decl_column 0x2 00015d: 0 null 00015e: 0 padding 00015f: 0 padding ** Section #430 '.rel.debug_info' (SHT_REL) Size : 24 bytes (alignment 4) Symbol table #343 '.symtab' 3 relocations applied to section #302 '.debug_info' ** Section #303 '__ARM_grp.stm32f7xx_hal_pcd.h.2_co_000_WDNCADEqjz5_Z10000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #304 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 3584 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_PCD_H 00001c: include at line 47 - file 2 00001f: end include 000020: include at line 111 - file 3 000023: end include 000024: line 121 define PCD_SPEED_HIGH 0U 000038: line 122 define PCD_SPEED_HIGH_IN_FULL 1U 000054: line 123 define PCD_SPEED_FULL 2U 000068: line 131 define PCD_PHY_ULPI 1U 00007b: line 132 define PCD_PHY_EMBEDDED 2U 000092: line 141 define USBD_HS_TRDT_VALUE 9U 0000ab: line 144 define USBD_FS_TRDT_VALUE 5U 0000c4: line 160 define __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance) 000111: line 161 define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance) 000160: line 163 define __HAL_PCD_GET_FLAG(__HANDLE__,__INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) 0001e4: line 164 define __HAL_PCD_CLEAR_FLAG(__HANDLE__,__INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) 00024c: line 165 define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0) 0002ac: line 168 define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK) 000341: line 171 define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK 0003d1: line 173 define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10) 000452: line 175 define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08U) 00048a: line 176 define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0CU) 0004c3: line 177 define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10U) 000503: line 179 define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08U) 00053b: line 180 define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0CU) 000574: line 181 define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10U) 0005b4: line 183 define USB_OTG_HS_WAKEUP_EXTI_LINE ((uint32_t)0x00100000U) 0005eb: line 184 define USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)0x00040000U) 000622: line 186 define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE) 000679: line 187 define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE) 0006d2: line 188 define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE) 000726: line 189 define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE) 00077c: line 191 define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE 000809: line 194 define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (USB_OTG_HS_WAKEUP_EXTI_LINE); EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE) 000899: line 197 define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE;) EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; EXTI->FTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE 000987: line 202 define __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE) 0009e4: line 204 define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE 000a39: line 205 define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE) 000a92: line 206 define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE) 000ae6: line 207 define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE 000b3a: line 209 define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE 000bc7: line 213 define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE); EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE) 000c57: line 216 define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE 000d45: line 221 define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE) 000da2: line 308 define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || ((INSTANCE) == USB_OTG_HS)) 000dfe: end include 000dff: end of translation unit ** Section #305 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 148 bytes 000000: Header: length 144 (not including this field) version 3 prologue length 132 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_pcd.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 70 63 64 2e 68 00 01 00 00 00005d: file "stm32f7xx_ll_usb.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 6c 6c 5f 75 73 62 2e 68 00 01 00 00 000073: file "stm32f7xx_hal_pcd_ex.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 70 63 64 5f 65 78 2e 68 00 01 00 00 00008d: file "" : 00 00008e: DW_LNS_negate_stmt : 06 00008f: DW_LNS_negate_stmt : 06 000090: DW_LNS_negate_stmt : 06 000091: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pcd.h:1.0 [ ** Section #306 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 808 bytes 000000: Header: size 0x324 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pcd.h 000049: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000090: DW_AT_language DW_LANG_C89 000092: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 000109: DW_AT_macro_info 0x0 00010d: DW_AT_stmt_list 0x0 000111: 117 = 0x3b (DW_TAG_unspecified_type) 000112: DW_AT_name void 000117: 34 = 0xf (DW_TAG_pointer_type) 000118: DW_AT_type indirect DW_FORM_ref2 0x111 00011b: 80 = 0x16 (DW_TAG_typedef) 00011c: DW_AT_name PCD_StateTypeDef 00012d: DW_AT_type indirect DW_FORM_ref2 0x1ad 000130: DW_AT_decl_file 0x1 000131: DW_AT_decl_line 0x48 000132: DW_AT_decl_column 0x3 000133: 80 = 0x16 (DW_TAG_typedef) 000134: DW_AT_name PCD_LPM_StateTypeDef 000149: DW_AT_type indirect DW_FORM_ref2 0x226 00014c: DW_AT_decl_file 0x1 00014d: DW_AT_decl_line 0x51 00014e: DW_AT_decl_column 0x2 00014f: 80 = 0x16 (DW_TAG_typedef) 000150: DW_AT_name PCD_TypeDef 00015c: DW_AT_type indirect DW_FORM_ref_addr 0x2ae0+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 000161: DW_AT_decl_file 0x1 000162: DW_AT_decl_line 0x53 000163: DW_AT_decl_column 0x20 000164: 80 = 0x16 (DW_TAG_typedef) 000165: DW_AT_name PCD_InitTypeDef 000175: DW_AT_type indirect DW_FORM_ref_addr 0x385+__ARM_grp..debug_info$stm32f7xx_ll_usb.h$.2_MO2000_K_sR9CwNEYd_K00000 00017a: DW_AT_decl_file 0x1 00017b: DW_AT_decl_line 0x54 00017c: DW_AT_decl_column 0x20 00017d: 80 = 0x16 (DW_TAG_typedef) 00017e: DW_AT_name PCD_EPTypeDef 00018c: DW_AT_type indirect DW_FORM_ref_addr 0x488+__ARM_grp..debug_info$stm32f7xx_ll_usb.h$.2_MO2000_K_sR9CwNEYd_K00000 000191: DW_AT_decl_file 0x1 000192: DW_AT_decl_line 0x55 000193: DW_AT_decl_column 0x20 000194: 80 = 0x16 (DW_TAG_typedef) 000195: DW_AT_name PCD_HandleTypeDef 0001a7: DW_AT_type indirect DW_FORM_ref2 0x253 0001aa: DW_AT_decl_file 0x1 0001ab: DW_AT_decl_line 0x68 0001ac: DW_AT_decl_column 0x3 0001ad: 19 = 0x4 (DW_TAG_enumeration_type) 0001ae: DW_AT_sibling 0x226 0001b0: DW_AT_byte_size 0x1 0001b1: 20 = 0x28 (DW_TAG_enumerator) 0001b2: DW_AT_name HAL_PCD_STATE_RESET 0001c6: DW_AT_const_value indirect DW_FORM_data1 0x0 0001c8: 20 = 0x28 (DW_TAG_enumerator) 0001c9: DW_AT_name HAL_PCD_STATE_READY 0001dd: DW_AT_const_value indirect DW_FORM_data1 0x1 0001df: 20 = 0x28 (DW_TAG_enumerator) 0001e0: DW_AT_name HAL_PCD_STATE_ERROR 0001f4: DW_AT_const_value indirect DW_FORM_data1 0x2 0001f6: 20 = 0x28 (DW_TAG_enumerator) 0001f7: DW_AT_name HAL_PCD_STATE_BUSY 00020a: DW_AT_const_value indirect DW_FORM_data1 0x3 00020c: 20 = 0x28 (DW_TAG_enumerator) 00020d: DW_AT_name HAL_PCD_STATE_TIMEOUT 000223: DW_AT_const_value indirect DW_FORM_data1 0x4 000225: 0 null 000226: 19 = 0x4 (DW_TAG_enumeration_type) 000227: DW_AT_sibling 0x253 000229: DW_AT_byte_size 0x1 00022a: 20 = 0x28 (DW_TAG_enumerator) 00022b: DW_AT_name LPM_L0 000232: DW_AT_const_value indirect DW_FORM_data1 0x0 000234: 20 = 0x28 (DW_TAG_enumerator) 000235: DW_AT_name LPM_L1 00023c: DW_AT_const_value indirect DW_FORM_data1 0x1 00023e: 20 = 0x28 (DW_TAG_enumerator) 00023f: DW_AT_name LPM_L2 000246: DW_AT_const_value indirect DW_FORM_data1 0x2 000248: 20 = 0x28 (DW_TAG_enumerator) 000249: DW_AT_name LPM_L3 000250: DW_AT_const_value indirect DW_FORM_data1 0x3 000252: 0 null 000253: 42 = 0x13 (DW_TAG_structure_type) 000254: DW_AT_sibling 0x31d 000256: DW_AT_byte_size 0x3c0 000258: 30 = 0xd (DW_TAG_member) 000259: DW_AT_name Instance 000262: DW_AT_type indirect DW_FORM_ref2 0x31d 000265: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000268: 30 = 0xd (DW_TAG_member) 000269: DW_AT_name Init 00026e: DW_AT_type indirect DW_FORM_ref2 0x164 000271: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000274: 3 = 0x1 (DW_TAG_array_type) 000275: DW_AT_sibling 0x27d 000277: DW_AT_type indirect DW_FORM_ref2 0x17d 00027a: 1 = 0x21 (DW_TAG_subrange_type) 00027b: DW_AT_upper_bound 0xe 00027c: 0 null 00027d: 30 = 0xd (DW_TAG_member) 00027e: DW_AT_name IN_ep 000284: DW_AT_type indirect DW_FORM_ref2 0x274 000287: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 00028a: 3 = 0x1 (DW_TAG_array_type) 00028b: DW_AT_sibling 0x293 00028d: DW_AT_type indirect DW_FORM_ref2 0x17d 000290: 1 = 0x21 (DW_TAG_subrange_type) 000291: DW_AT_upper_bound 0xe 000292: 0 null 000293: 30 = 0xd (DW_TAG_member) 000294: DW_AT_name OUT_ep 00029b: DW_AT_type indirect DW_FORM_ref2 0x28a 00029e: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 472 } 0002a2: 30 = 0xd (DW_TAG_member) 0002a3: DW_AT_name Lock 0002a8: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 0002ad: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 892 } 0002b1: 30 = 0xd (DW_TAG_member) 0002b2: DW_AT_name State 0002b8: DW_AT_type indirect DW_FORM_ref2 0x321 0002bb: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 893 } 0002bf: 3 = 0x1 (DW_TAG_array_type) 0002c0: DW_AT_sibling 0x2ca 0002c2: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002c7: 1 = 0x21 (DW_TAG_subrange_type) 0002c8: DW_AT_upper_bound 0xb 0002c9: 0 null 0002ca: 30 = 0xd (DW_TAG_member) 0002cb: DW_AT_name Setup 0002d1: DW_AT_type indirect DW_FORM_ref2 0x2bf 0002d4: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 896 } 0002d8: 30 = 0xd (DW_TAG_member) 0002d9: DW_AT_name LPM_State 0002e3: DW_AT_type indirect DW_FORM_ref2 0x133 0002e6: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 944 } 0002ea: 30 = 0xd (DW_TAG_member) 0002eb: DW_AT_name BESL 0002f0: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002f5: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 948 } 0002f9: 30 = 0xd (DW_TAG_member) 0002fa: DW_AT_name lpm_active 000305: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00030a: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 952 } 00030e: 30 = 0xd (DW_TAG_member) 00030f: DW_AT_name pData 000315: DW_AT_type indirect DW_FORM_ref2 0x117 000318: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 956 } 00031c: 0 null 00031d: 34 = 0xf (DW_TAG_pointer_type) 00031e: DW_AT_type indirect DW_FORM_ref2 0x14f 000321: 116 = 0x35 (DW_TAG_volatile_type) 000322: DW_AT_type indirect DW_FORM_ref2 0x11b 000325: 0 null 000326: 0 padding 000327: 0 padding ** Section #431 '.rel.debug_info' (SHT_REL) Size : 80 bytes (alignment 4) Symbol table #343 '.symtab' 10 relocations applied to section #306 '.debug_info' ** Section #307 '__ARM_grp.stm32f7xx_hal_hcd.h.2_Q9Z000_BjPo$GAT_P1_Y10000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #308 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 1164 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_HCD_H 00001c: include at line 47 - file 2 00001f: end include 000020: line 112 define HCD_SPEED_HIGH 0U 000034: line 113 define HCD_SPEED_LOW 2U 000047: line 114 define HCD_SPEED_FULL 3U 00005b: line 122 define HCD_PHY_ULPI 1U 00006d: line 123 define HCD_PHY_EMBEDDED 2U 000083: line 137 define __HAL_HCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance) 0000d0: line 138 define __HAL_HCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance) 00011f: line 140 define __HAL_HCD_GET_FLAG(__HANDLE__,__INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) 0001a3: line 141 define __HAL_HCD_CLEAR_FLAG(__HANDLE__,__INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) 00020b: line 142 define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) 00026c: line 144 define __HAL_HCD_CLEAR_HC_INT(chnum,__INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__)) 0002c5: line 145 define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM) 00031f: line 146 define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM) 00037a: line 147 define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM) 0003d3: line 148 define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM) 00042d: line 239 define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || ((INSTANCE) == USB_OTG_HS)) 000489: end include 00048a: end of translation unit ** Section #309 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 120 bytes 000000: Header: length 116 (not including this field) version 3 prologue length 106 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_hcd.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 68 63 64 2e 68 00 01 00 00 00005d: file "stm32f7xx_ll_usb.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 6c 6c 5f 75 73 62 2e 68 00 01 00 00 000073: file "" : 00 000074: DW_LNS_negate_stmt : 06 000075: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_hcd.h:1.0 [ ** Section #310 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 688 bytes 000000: Header: size 0x2ac bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_hcd.h 000049: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000090: DW_AT_language DW_LANG_C89 000092: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 000109: DW_AT_macro_info 0x0 00010d: DW_AT_stmt_list 0x0 000111: 117 = 0x3b (DW_TAG_unspecified_type) 000112: DW_AT_name void 000117: 34 = 0xf (DW_TAG_pointer_type) 000118: DW_AT_type indirect DW_FORM_ref2 0x111 00011b: 80 = 0x16 (DW_TAG_typedef) 00011c: DW_AT_name HCD_StateTypeDef 00012d: DW_AT_type indirect DW_FORM_ref2 0x1ca 000130: DW_AT_decl_file 0x1 000131: DW_AT_decl_line 0x49 000132: DW_AT_decl_column 0x3 000133: 80 = 0x16 (DW_TAG_typedef) 000134: DW_AT_name HCD_TypeDef 000140: DW_AT_type indirect DW_FORM_ref_addr 0x2ae0+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 000145: DW_AT_decl_file 0x1 000146: DW_AT_decl_line 0x4b 000147: DW_AT_decl_column 0x21 000148: 80 = 0x16 (DW_TAG_typedef) 000149: DW_AT_name HCD_InitTypeDef 000159: DW_AT_type indirect DW_FORM_ref_addr 0x385+__ARM_grp..debug_info$stm32f7xx_ll_usb.h$.2_MO2000_K_sR9CwNEYd_K00000 00015e: DW_AT_decl_file 0x1 00015f: DW_AT_decl_line 0x4c 000160: DW_AT_decl_column 0x21 000161: 80 = 0x16 (DW_TAG_typedef) 000162: DW_AT_name HCD_HCTypeDef 000170: DW_AT_type indirect DW_FORM_ref_addr 0x5f6+__ARM_grp..debug_info$stm32f7xx_ll_usb.h$.2_MO2000_K_sR9CwNEYd_K00000 000175: DW_AT_decl_file 0x1 000176: DW_AT_decl_line 0x4d 000177: DW_AT_decl_column 0x21 000178: 80 = 0x16 (DW_TAG_typedef) 000179: DW_AT_name HCD_URBStateTypeDef 00018d: DW_AT_type indirect DW_FORM_ref_addr 0x1c3+__ARM_grp..debug_info$stm32f7xx_ll_usb.h$.2_MO2000_K_sR9CwNEYd_K00000 000192: DW_AT_decl_file 0x1 000193: DW_AT_decl_line 0x4e 000194: DW_AT_decl_column 0x21 000195: 80 = 0x16 (DW_TAG_typedef) 000196: DW_AT_name HCD_HCStateTypeDef 0001a9: DW_AT_type indirect DW_FORM_ref_addr 0x257+__ARM_grp..debug_info$stm32f7xx_ll_usb.h$.2_MO2000_K_sR9CwNEYd_K00000 0001ae: DW_AT_decl_file 0x1 0001af: DW_AT_decl_line 0x4f 0001b0: DW_AT_decl_column 0x21 0001b1: 80 = 0x16 (DW_TAG_typedef) 0001b2: DW_AT_name HCD_HandleTypeDef 0001c4: DW_AT_type indirect DW_FORM_ref2 0x243 0001c7: DW_AT_decl_file 0x1 0001c8: DW_AT_decl_line 0x5f 0001c9: DW_AT_decl_column 0x3 0001ca: 19 = 0x4 (DW_TAG_enumeration_type) 0001cb: DW_AT_sibling 0x243 0001cd: DW_AT_byte_size 0x1 0001ce: 20 = 0x28 (DW_TAG_enumerator) 0001cf: DW_AT_name HAL_HCD_STATE_RESET 0001e3: DW_AT_const_value indirect DW_FORM_data1 0x0 0001e5: 20 = 0x28 (DW_TAG_enumerator) 0001e6: DW_AT_name HAL_HCD_STATE_READY 0001fa: DW_AT_const_value indirect DW_FORM_data1 0x1 0001fc: 20 = 0x28 (DW_TAG_enumerator) 0001fd: DW_AT_name HAL_HCD_STATE_ERROR 000211: DW_AT_const_value indirect DW_FORM_data1 0x2 000213: 20 = 0x28 (DW_TAG_enumerator) 000214: DW_AT_name HAL_HCD_STATE_BUSY 000227: DW_AT_const_value indirect DW_FORM_data1 0x3 000229: 20 = 0x28 (DW_TAG_enumerator) 00022a: DW_AT_name HAL_HCD_STATE_TIMEOUT 000240: DW_AT_const_value indirect DW_FORM_data1 0x4 000242: 0 null 000243: 42 = 0x13 (DW_TAG_structure_type) 000244: DW_AT_sibling 0x2a3 000246: DW_AT_byte_size 0x294 000248: 30 = 0xd (DW_TAG_member) 000249: DW_AT_name Instance 000252: DW_AT_type indirect DW_FORM_ref2 0x2a3 000255: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000258: 30 = 0xd (DW_TAG_member) 000259: DW_AT_name Init 00025e: DW_AT_type indirect DW_FORM_ref2 0x148 000261: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000264: 3 = 0x1 (DW_TAG_array_type) 000265: DW_AT_sibling 0x26d 000267: DW_AT_type indirect DW_FORM_ref2 0x161 00026a: 1 = 0x21 (DW_TAG_subrange_type) 00026b: DW_AT_upper_bound 0xe 00026c: 0 null 00026d: 30 = 0xd (DW_TAG_member) 00026e: DW_AT_name hc 000271: DW_AT_type indirect DW_FORM_ref2 0x264 000274: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 000277: 30 = 0xd (DW_TAG_member) 000278: DW_AT_name Lock 00027d: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 000282: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 652 } 000286: 30 = 0xd (DW_TAG_member) 000287: DW_AT_name State 00028d: DW_AT_type indirect DW_FORM_ref2 0x2a7 000290: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 653 } 000294: 30 = 0xd (DW_TAG_member) 000295: DW_AT_name pData 00029b: DW_AT_type indirect DW_FORM_ref2 0x117 00029e: DW_AT_data_member_location block size 0x3 = { DW_OP_plus_uconst 656 } 0002a2: 0 null 0002a3: 34 = 0xf (DW_TAG_pointer_type) 0002a4: DW_AT_type indirect DW_FORM_ref2 0x133 0002a7: 116 = 0x35 (DW_TAG_volatile_type) 0002a8: DW_AT_type indirect DW_FORM_ref2 0x11b 0002ab: 0 null 0002ac: 0 padding 0002ad: 0 padding 0002ae: 0 padding 0002af: 0 padding ** Section #432 '.rel.debug_info' (SHT_REL) Size : 72 bytes (alignment 4) Symbol table #343 '.symtab' 9 relocations applied to section #310 '.debug_info' ** Section #311 '__ARM_grp.stm32f7xx_hal_dfsdm.h.2_4z3100_OAhVPkgGP1a_a20000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #312 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 8116 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_DFSDM_H 00001e: include at line 48 - file 2 000021: end include 000022: line 259 define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000U) 00005f: line 260 define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC 00009a: line 268 define DFSDM_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000U) 0000d3: line 269 define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 00010d: line 277 define DFSDM_CHANNEL_STANDARD_MODE ((uint32_t)0x00000000U) 000144: line 278 define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 00017e: line 279 define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 0001b1: line 287 define DFSDM_CHANNEL_SAME_CHANNEL_PINS ((uint32_t)0x00000000U) 0001ec: line 288 define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL 00022a: line 296 define DFSDM_CHANNEL_SPI_RISING ((uint32_t)0x00000000U) 00025e: line 297 define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 000290: line 298 define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 0002c8: line 299 define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP 0002ff: line 307 define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL ((uint32_t)0x00000000U) 00033b: line 308 define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 000378: line 309 define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 0003c2: line 310 define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL 000409: line 318 define DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000U) 000441: line 319 define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 000476: line 320 define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 0004ab: line 321 define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD 0004de: line 329 define DFSDM_FILTER_SW_TRIGGER ((uint32_t)0x00000000U) 000511: line 330 define DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001U) 000546: line 331 define DFSDM_FILTER_EXT_TRIGGER ((uint32_t)0x00000002U) 00057a: line 339 define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) 0005b5: line 340 define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 0005f0: line 341 define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 00062a: line 342 define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) 000680: line 343 define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2 0006ba: line 344 define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) 00070f: line 345 define DFSDM_FILTER_EXT_TRIG_TIM10_OC1 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) 000764: line 346 define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) 0007d2: line 348 define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3 00080c: line 349 define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_4) 00085e: line 350 define DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_4) 0008c9: line 352 define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_4) 000938: line 361 define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0 000973: line 362 define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 0009af: line 363 define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN 0009e7: line 371 define DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000U) 000a1e: line 372 define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 000a4e: line 373 define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 000a7e: line 374 define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) 000ac6: line 375 define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2 000af6: line 376 define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) 000b3e: line 384 define DFSDM_FILTER_AWD_FILTER_DATA ((uint32_t)0x00000000U) 000b76: line 385 define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL 000bab: line 393 define DFSDM_FILTER_ERROR_NONE ((uint32_t)0x00000000U) 000bde: line 394 define DFSDM_FILTER_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001U) 000c1c: line 395 define DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002U) 000c5b: line 396 define DFSDM_FILTER_ERROR_DMA ((uint32_t)0x00000003U) 000c8d: line 404 define DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000U) 000cbe: line 405 define DFSDM_BREAK_SIGNAL_0 ((uint32_t)0x00000001U) 000cee: line 406 define DFSDM_BREAK_SIGNAL_1 ((uint32_t)0x00000002U) 000d1e: line 407 define DFSDM_BREAK_SIGNAL_2 ((uint32_t)0x00000004U) 000d4e: line 408 define DFSDM_BREAK_SIGNAL_3 ((uint32_t)0x00000008U) 000d7e: line 424 define DFSDM_CHANNEL_0 ((uint32_t)0x00000001U) 000da9: line 425 define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U) 000dd4: line 426 define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U) 000dff: line 427 define DFSDM_CHANNEL_3 ((uint32_t)0x00030008U) 000e2a: line 428 define DFSDM_CHANNEL_4 ((uint32_t)0x00040010U) 000e55: line 429 define DFSDM_CHANNEL_5 ((uint32_t)0x00050020U) 000e80: line 430 define DFSDM_CHANNEL_6 ((uint32_t)0x00060040U) 000eab: line 431 define DFSDM_CHANNEL_7 ((uint32_t)0x00070080U) 000ed6: line 439 define DFSDM_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000U) 000f0b: line 440 define DFSDM_CONTINUOUS_CONV_ON ((uint32_t)0x00000001U) 000f3f: line 448 define DFSDM_AWD_HIGH_THRESHOLD ((uint32_t)0x00000000U) 000f73: line 449 define DFSDM_AWD_LOW_THRESHOLD ((uint32_t)0x00000001U) 000fa6: line 468 define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET) 001012: line 474 define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET) 00107c: line 622 define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO)) 001106: line 624 define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256)) 001161: line 625 define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER)) 0011df: line 627 define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || ((MODE) == DFSDM_CHANNEL_DUAL_MODE)) 001285: line 630 define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS)) 00130c: line 632 define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING)) 0013eb: line 636 define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING)) 0014e7: line 640 define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER)) 0015b9: line 644 define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 32)) 001609: line 645 define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) 00165b: line 646 define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1F) 001698: line 647 define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFF) 0016d3: line 648 define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER)) 001747: line 650 define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || ((TRIG) == DFSDM_FILTER_EXT_TRIGGER)) 0017e3: line 653 define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2)|| ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2)|| ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) || ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT)) 001a33: line 665 define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES)) 001aec: line 668 define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || ((ORDER) == DFSDM_FILTER_SINC5_ORDER)) 001c09: line 674 define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 1024)) 001c53: line 675 define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 256)) 001ca7: line 676 define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA)) 001d28: line 678 define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) 001d80: line 679 define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xFU) 001db3: line 680 define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || ((CHANNEL) == DFSDM_CHANNEL_1) || ((CHANNEL) == DFSDM_CHANNEL_2) || ((CHANNEL) == DFSDM_CHANNEL_3) || ((CHANNEL) == DFSDM_CHANNEL_4) || ((CHANNEL) == DFSDM_CHANNEL_5) || ((CHANNEL) == DFSDM_CHANNEL_6) || ((CHANNEL) == DFSDM_CHANNEL_7)) 001ee7: line 688 define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FFU)) 001f3e: line 689 define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || ((MODE) == DFSDM_CONTINUOUS_CONV_ON)) 001fb0: end include 001fb1: end of translation unit ** Section #313 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 124 bytes 000000: Header: length 120 (not including this field) version 3 prologue length 109 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_dfsdm.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 66 73 64 6d 2e 68 00 01 00 00 00005f: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000076: file "" : 00 000077: DW_LNS_negate_stmt : 06 000078: DW_LNS_negate_stmt : 06 000079: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dfsdm.h:1.0 ** Section #314 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 2188 bytes 000000: Header: size 0x888 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dfsdm.h 00004b: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000092: DW_AT_language DW_LANG_C89 000094: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010b: DW_AT_macro_info 0x0 00010f: DW_AT_stmt_list 0x0 000113: 19 = 0x4 (DW_TAG_enumeration_type) 000114: DW_AT_sibling 0x17b 000116: DW_AT_byte_size 0x1 000117: 20 = 0x28 (DW_TAG_enumerator) 000118: DW_AT_name HAL_DFSDM_CHANNEL_STATE_RESET 000136: DW_AT_const_value indirect DW_FORM_data1 0x0 000138: 20 = 0x28 (DW_TAG_enumerator) 000139: DW_AT_name HAL_DFSDM_CHANNEL_STATE_READY 000157: DW_AT_const_value indirect DW_FORM_data1 0x1 000159: 20 = 0x28 (DW_TAG_enumerator) 00015a: DW_AT_name HAL_DFSDM_CHANNEL_STATE_ERROR 000178: DW_AT_const_value indirect DW_FORM_data1 0xff 00017a: 0 null 00017b: 80 = 0x16 (DW_TAG_typedef) 00017c: DW_AT_name HAL_DFSDM_Channel_StateTypeDef 00019b: DW_AT_type indirect DW_FORM_ref2 0x113 00019e: DW_AT_decl_file 0x1 00019f: DW_AT_decl_line 0x47 0001a0: DW_AT_decl_column 0x2 0001a1: 42 = 0x13 (DW_TAG_structure_type) 0001a2: DW_AT_sibling 0x1de 0001a4: DW_AT_byte_size 0xc 0001a5: 30 = 0xd (DW_TAG_member) 0001a6: DW_AT_name Activation 0001b1: DW_AT_type indirect DW_FORM_ref_addr 0x165+__ARM_grp..debug_info$stm32f7xx.h$.2_UW0000_aRwJTR5xRm2_300000 0001b6: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0001b9: 30 = 0xd (DW_TAG_member) 0001ba: DW_AT_name Selection 0001c4: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001c9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0001cc: 30 = 0xd (DW_TAG_member) 0001cd: DW_AT_name Divider 0001d5: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001da: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 0001dd: 0 null 0001de: 80 = 0x16 (DW_TAG_typedef) 0001df: DW_AT_name DFSDM_Channel_OutputClockTypeDef 000200: DW_AT_type indirect DW_FORM_ref2 0x1a1 000203: DW_AT_decl_file 0x1 000204: DW_AT_decl_line 0x53 000205: DW_AT_decl_column 0x2 000206: 42 = 0x13 (DW_TAG_structure_type) 000207: DW_AT_sibling 0x243 000209: DW_AT_byte_size 0xc 00020a: 30 = 0xd (DW_TAG_member) 00020b: DW_AT_name Multiplexer 000217: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00021c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00021f: 30 = 0xd (DW_TAG_member) 000220: DW_AT_name DataPacking 00022c: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000231: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000234: 30 = 0xd (DW_TAG_member) 000235: DW_AT_name Pins 00023a: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00023f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000242: 0 null 000243: 80 = 0x16 (DW_TAG_typedef) 000244: DW_AT_name DFSDM_Channel_InputTypeDef 00025f: DW_AT_type indirect DW_FORM_ref2 0x206 000262: DW_AT_decl_file 0x1 000263: DW_AT_decl_line 0x60 000264: DW_AT_decl_column 0x2 000265: 42 = 0x13 (DW_TAG_structure_type) 000266: DW_AT_sibling 0x28a 000268: DW_AT_byte_size 0x8 000269: 30 = 0xd (DW_TAG_member) 00026a: DW_AT_name Type 00026f: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000274: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 000277: 30 = 0xd (DW_TAG_member) 000278: DW_AT_name SpiClock 000281: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000286: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000289: 0 null 00028a: 80 = 0x16 (DW_TAG_typedef) 00028b: DW_AT_name DFSDM_Channel_SerialInterfaceTypeDef 0002b0: DW_AT_type indirect DW_FORM_ref2 0x265 0002b3: DW_AT_decl_file 0x1 0002b4: DW_AT_decl_line 0x6b 0002b5: DW_AT_decl_column 0x2 0002b6: 42 = 0x13 (DW_TAG_structure_type) 0002b7: DW_AT_sibling 0x2e6 0002b9: DW_AT_byte_size 0x8 0002ba: 30 = 0xd (DW_TAG_member) 0002bb: DW_AT_name FilterOrder 0002c7: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002cc: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0002cf: 30 = 0xd (DW_TAG_member) 0002d0: DW_AT_name Oversampling 0002dd: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002e2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0002e5: 0 null 0002e6: 80 = 0x16 (DW_TAG_typedef) 0002e7: DW_AT_name DFSDM_Channel_AwdTypeDef 000300: DW_AT_type indirect DW_FORM_ref2 0x2b6 000303: DW_AT_decl_file 0x1 000304: DW_AT_decl_line 0x76 000305: DW_AT_decl_column 0x2 000306: 42 = 0x13 (DW_TAG_structure_type) 000307: DW_AT_sibling 0x374 000309: DW_AT_byte_size 0x30 00030a: 30 = 0xd (DW_TAG_member) 00030b: DW_AT_name OutputClock 000317: DW_AT_type indirect DW_FORM_ref2 0x1de 00031a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00031d: 30 = 0xd (DW_TAG_member) 00031e: DW_AT_name Input 000324: DW_AT_type indirect DW_FORM_ref2 0x243 000327: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00032a: 30 = 0xd (DW_TAG_member) 00032b: DW_AT_name SerialInterface 00033b: DW_AT_type indirect DW_FORM_ref2 0x28a 00033e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 000341: 30 = 0xd (DW_TAG_member) 000342: DW_AT_name Awd 000346: DW_AT_type indirect DW_FORM_ref2 0x2e6 000349: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 00034c: 30 = 0xd (DW_TAG_member) 00034d: DW_AT_name Offset 000354: DW_AT_type indirect DW_FORM_ref_addr 0x130+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000359: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 00035c: 30 = 0xd (DW_TAG_member) 00035d: DW_AT_name RightBitShift 00036b: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000370: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 000373: 0 null 000374: 80 = 0x16 (DW_TAG_typedef) 000375: DW_AT_name DFSDM_Channel_InitTypeDef 00038f: DW_AT_type indirect DW_FORM_ref2 0x306 000392: DW_AT_decl_file 0x1 000393: DW_AT_decl_line 0x85 000395: DW_AT_decl_column 0x2 000396: 42 = 0x13 (DW_TAG_structure_type) 000397: DW_AT_sibling 0x3c4 000399: DW_AT_byte_size 0x38 00039a: 30 = 0xd (DW_TAG_member) 00039b: DW_AT_name Instance 0003a4: DW_AT_type indirect DW_FORM_ref2 0x3c4 0003a7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0003aa: 30 = 0xd (DW_TAG_member) 0003ab: DW_AT_name Init 0003b0: DW_AT_type indirect DW_FORM_ref2 0x374 0003b3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0003b6: 30 = 0xd (DW_TAG_member) 0003b7: DW_AT_name State 0003bd: DW_AT_type indirect DW_FORM_ref2 0x17b 0003c0: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 0003c3: 0 null 0003c4: 34 = 0xf (DW_TAG_pointer_type) 0003c5: DW_AT_type indirect DW_FORM_ref_addr 0xf73+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 0003ca: 80 = 0x16 (DW_TAG_typedef) 0003cb: DW_AT_name DFSDM_Channel_HandleTypeDef 0003e7: DW_AT_type indirect DW_FORM_ref2 0x396 0003ea: DW_AT_decl_file 0x1 0003eb: DW_AT_decl_line 0x8f 0003ed: DW_AT_decl_column 0x2 0003ee: 19 = 0x4 (DW_TAG_enumeration_type) 0003ef: DW_AT_sibling 0x4b1 0003f1: DW_AT_byte_size 0x1 0003f2: 20 = 0x28 (DW_TAG_enumerator) 0003f3: DW_AT_name HAL_DFSDM_FILTER_STATE_RESET 000410: DW_AT_const_value indirect DW_FORM_data1 0x0 000412: 20 = 0x28 (DW_TAG_enumerator) 000413: DW_AT_name HAL_DFSDM_FILTER_STATE_READY 000430: DW_AT_const_value indirect DW_FORM_data1 0x1 000432: 20 = 0x28 (DW_TAG_enumerator) 000433: DW_AT_name HAL_DFSDM_FILTER_STATE_REG 00044e: DW_AT_const_value indirect DW_FORM_data1 0x2 000450: 20 = 0x28 (DW_TAG_enumerator) 000451: DW_AT_name HAL_DFSDM_FILTER_STATE_INJ 00046c: DW_AT_const_value indirect DW_FORM_data1 0x3 00046e: 20 = 0x28 (DW_TAG_enumerator) 00046f: DW_AT_name HAL_DFSDM_FILTER_STATE_REG_INJ 00048e: DW_AT_const_value indirect DW_FORM_data1 0x4 000490: 20 = 0x28 (DW_TAG_enumerator) 000491: DW_AT_name HAL_DFSDM_FILTER_STATE_ERROR 0004ae: DW_AT_const_value indirect DW_FORM_data1 0xff 0004b0: 0 null 0004b1: 80 = 0x16 (DW_TAG_typedef) 0004b2: DW_AT_name HAL_DFSDM_Filter_StateTypeDef 0004d0: DW_AT_type indirect DW_FORM_ref2 0x3ee 0004d3: DW_AT_decl_file 0x1 0004d4: DW_AT_decl_line 0x9c 0004d6: DW_AT_decl_column 0x2 0004d7: 42 = 0x13 (DW_TAG_structure_type) 0004d8: DW_AT_sibling 0x510 0004da: DW_AT_byte_size 0x8 0004db: 30 = 0xd (DW_TAG_member) 0004dc: DW_AT_name Trigger 0004e4: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0004e9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0004ec: 30 = 0xd (DW_TAG_member) 0004ed: DW_AT_name FastMode 0004f6: DW_AT_type indirect DW_FORM_ref_addr 0x165+__ARM_grp..debug_info$stm32f7xx.h$.2_UW0000_aRwJTR5xRm2_300000 0004fb: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0004fe: 30 = 0xd (DW_TAG_member) 0004ff: DW_AT_name DmaMode 000507: DW_AT_type indirect DW_FORM_ref_addr 0x165+__ARM_grp..debug_info$stm32f7xx.h$.2_UW0000_aRwJTR5xRm2_300000 00050c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 5 } 00050f: 0 null 000510: 80 = 0x16 (DW_TAG_typedef) 000511: DW_AT_name DFSDM_Filter_RegularParamTypeDef 000532: DW_AT_type indirect DW_FORM_ref2 0x4d7 000535: DW_AT_decl_file 0x1 000536: DW_AT_decl_line 0xa7 000538: DW_AT_decl_column 0x2 000539: 42 = 0x13 (DW_TAG_structure_type) 00053a: DW_AT_sibling 0x59e 00053c: DW_AT_byte_size 0x10 00053d: 30 = 0xd (DW_TAG_member) 00053e: DW_AT_name Trigger 000546: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00054b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00054e: 30 = 0xd (DW_TAG_member) 00054f: DW_AT_name ScanMode 000558: DW_AT_type indirect DW_FORM_ref_addr 0x165+__ARM_grp..debug_info$stm32f7xx.h$.2_UW0000_aRwJTR5xRm2_300000 00055d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000560: 30 = 0xd (DW_TAG_member) 000561: DW_AT_name DmaMode 000569: DW_AT_type indirect DW_FORM_ref_addr 0x165+__ARM_grp..debug_info$stm32f7xx.h$.2_UW0000_aRwJTR5xRm2_300000 00056e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 5 } 000571: 30 = 0xd (DW_TAG_member) 000572: DW_AT_name ExtTrigger 00057d: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000582: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000585: 30 = 0xd (DW_TAG_member) 000586: DW_AT_name ExtTriggerEdge 000595: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00059a: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 00059d: 0 null 00059e: 80 = 0x16 (DW_TAG_typedef) 00059f: DW_AT_name DFSDM_Filter_InjectedParamTypeDef 0005c1: DW_AT_type indirect DW_FORM_ref2 0x539 0005c4: DW_AT_decl_file 0x1 0005c5: DW_AT_decl_line 0xb6 0005c7: DW_AT_decl_column 0x2 0005c8: 42 = 0x13 (DW_TAG_structure_type) 0005c9: DW_AT_sibling 0x60f 0005cb: DW_AT_byte_size 0xc 0005cc: 30 = 0xd (DW_TAG_member) 0005cd: DW_AT_name SincOrder 0005d7: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0005dc: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0005df: 30 = 0xd (DW_TAG_member) 0005e0: DW_AT_name Oversampling 0005ed: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0005f2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0005f5: 30 = 0xd (DW_TAG_member) 0005f6: DW_AT_name IntOversampling 000606: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00060b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 00060e: 0 null 00060f: 80 = 0x16 (DW_TAG_typedef) 000610: DW_AT_name DFSDM_Filter_FilterParamTypeDef 000630: DW_AT_type indirect DW_FORM_ref2 0x5c8 000633: DW_AT_decl_file 0x1 000634: DW_AT_decl_line 0xc3 000636: DW_AT_decl_column 0x2 000637: 42 = 0x13 (DW_TAG_structure_type) 000638: DW_AT_sibling 0x678 00063a: DW_AT_byte_size 0x24 00063b: 30 = 0xd (DW_TAG_member) 00063c: DW_AT_name RegularParam 000649: DW_AT_type indirect DW_FORM_ref2 0x510 00064c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00064f: 30 = 0xd (DW_TAG_member) 000650: DW_AT_name InjectedParam 00065e: DW_AT_type indirect DW_FORM_ref2 0x59e 000661: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 000664: 30 = 0xd (DW_TAG_member) 000665: DW_AT_name FilterParam 000671: DW_AT_type indirect DW_FORM_ref2 0x60f 000674: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 000677: 0 null 000678: 80 = 0x16 (DW_TAG_typedef) 000679: DW_AT_name DFSDM_Filter_InitTypeDef 000692: DW_AT_type indirect DW_FORM_ref2 0x637 000695: DW_AT_decl_file 0x1 000696: DW_AT_decl_line 0xcd 000698: DW_AT_decl_column 0x2 000699: 42 = 0x13 (DW_TAG_structure_type) 00069a: DW_AT_sibling 0x7ab 00069c: DW_AT_byte_size 0x54 00069d: 30 = 0xd (DW_TAG_member) 00069e: DW_AT_name Instance 0006a7: DW_AT_type indirect DW_FORM_ref2 0x7ab 0006aa: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0006ad: 30 = 0xd (DW_TAG_member) 0006ae: DW_AT_name Init 0006b3: DW_AT_type indirect DW_FORM_ref2 0x678 0006b6: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0006b9: 30 = 0xd (DW_TAG_member) 0006ba: DW_AT_name hdmaReg 0006c2: DW_AT_type indirect DW_FORM_ref2 0x7b1 0006c5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 0006c8: 30 = 0xd (DW_TAG_member) 0006c9: DW_AT_name hdmaInj 0006d1: DW_AT_type indirect DW_FORM_ref2 0x7b1 0006d4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 0006d7: 30 = 0xd (DW_TAG_member) 0006d8: DW_AT_name RegularContMode 0006e8: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0006ed: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 0006f0: 30 = 0xd (DW_TAG_member) 0006f1: DW_AT_name RegularTrigger 000700: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000705: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 000708: 30 = 0xd (DW_TAG_member) 000709: DW_AT_name InjectedTrigger 000719: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00071e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 000721: 30 = 0xd (DW_TAG_member) 000722: DW_AT_name ExtTriggerEdge 000731: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000736: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 60 } 000739: 30 = 0xd (DW_TAG_member) 00073a: DW_AT_name InjectedScanMode 00074b: DW_AT_type indirect DW_FORM_ref_addr 0x165+__ARM_grp..debug_info$stm32f7xx.h$.2_UW0000_aRwJTR5xRm2_300000 000750: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 64 } 000753: 30 = 0xd (DW_TAG_member) 000754: DW_AT_name InjectedChannelsNbr 000768: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00076d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 68 } 000770: 30 = 0xd (DW_TAG_member) 000771: DW_AT_name InjConvRemaining 000782: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000787: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 72 } 00078a: 30 = 0xd (DW_TAG_member) 00078b: DW_AT_name State 000791: DW_AT_type indirect DW_FORM_ref2 0x4b1 000794: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 76 } 000797: 30 = 0xd (DW_TAG_member) 000798: DW_AT_name ErrorCode 0007a2: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0007a7: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 80 } 0007aa: 0 null 0007ab: 34 = 0xf (DW_TAG_pointer_type) 0007ac: DW_AT_type indirect DW_FORM_ref_addr 0xf03+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 0007b1: 34 = 0xf (DW_TAG_pointer_type) 0007b2: DW_AT_type indirect DW_FORM_ref_addr 0x1a0+__ARM_grp..debug_info$stm32f7xx_hal_dma.h$.2_wD1100_gh0hnOcebnc_s10000 0007b7: 80 = 0x16 (DW_TAG_typedef) 0007b8: DW_AT_name DFSDM_Filter_HandleTypeDef 0007d3: DW_AT_type indirect DW_FORM_ref2 0x699 0007d6: DW_AT_decl_file 0x1 0007d7: DW_AT_decl_line 0xe1 0007d9: DW_AT_decl_column 0x2 0007da: 42 = 0x13 (DW_TAG_structure_type) 0007db: DW_AT_sibling 0x862 0007dd: DW_AT_byte_size 0x18 0007de: 30 = 0xd (DW_TAG_member) 0007df: DW_AT_name DataSource 0007ea: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0007ef: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0007f2: 30 = 0xd (DW_TAG_member) 0007f3: DW_AT_name Channel 0007fb: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000800: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000803: 30 = 0xd (DW_TAG_member) 000804: DW_AT_name HighThreshold 000812: DW_AT_type indirect DW_FORM_ref_addr 0x130+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000817: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 00081a: 30 = 0xd (DW_TAG_member) 00081b: DW_AT_name LowThreshold 000828: DW_AT_type indirect DW_FORM_ref_addr 0x130+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00082d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000830: 30 = 0xd (DW_TAG_member) 000831: DW_AT_name HighBreakSignal 000841: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000846: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 16 } 000849: 30 = 0xd (DW_TAG_member) 00084a: DW_AT_name LowBreakSignal 000859: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00085e: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 000861: 0 null 000862: 80 = 0x16 (DW_TAG_typedef) 000863: DW_AT_name DFSDM_Filter_AwdParamTypeDef 000880: DW_AT_type indirect DW_FORM_ref2 0x7da 000883: DW_AT_decl_file 0x1 000884: DW_AT_decl_line 0xf4 000886: DW_AT_decl_column 0x2 000887: 0 null 000888: 0 padding 000889: 0 padding 00088a: 0 padding 00088b: 0 padding ** Section #433 '.rel.debug_info' (SHT_REL) Size : 344 bytes (alignment 4) Symbol table #343 '.symtab' 43 relocations applied to section #314 '.debug_info' ** Section #315 '__ARM_grp.stm32f7xx_hal_dsi.h.2_0v0000_NaicQu0zaRe_300000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #316 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 32 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_DSI_H 00001c: end include 00001d: end of translation unit ** Section #317 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 100 bytes 000000: Header: length 96 (not including this field) version 3 prologue length 84 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_dsi.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 73 69 2e 68 00 01 00 00 00005d: file "" : 00 00005e: DW_LNS_negate_stmt : 06 00005f: DW_LNS_negate_stmt : 06 000060: DW_LNS_negate_stmt : 06 000061: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dsi.h:1.0 [ ** Section #318 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 276 bytes 000000: Header: size 0x110 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dsi.h 000049: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000090: DW_AT_language DW_LANG_C89 000092: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 000109: DW_AT_macro_info 0x0 00010d: DW_AT_stmt_list 0x0 000111: 0 null 000112: 0 padding 000113: 0 padding ** Section #434 '.rel.debug_info' (SHT_REL) Size : 24 bytes (alignment 4) Symbol table #343 '.symtab' 3 relocations applied to section #318 '.debug_info' ** Section #319 '__ARM_grp.stm32f7xx_hal_jpeg.h.2_0n0100_zsL$j8Jxlfd_I10000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #320 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 2848 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_JPEG_H 00001d: include at line 47 - file 2 000020: end include 000021: line 170 define HAL_JPEG_ERROR_NONE ((uint32_t)0x00000000U) 000050: line 171 define HAL_JPEG_ERROR_HUFF_TABLE ((uint32_t)0x00000001U) 000085: line 172 define HAL_JPEG_ERROR_QUANT_TABLE ((uint32_t)0x00000002U) 0000bb: line 173 define HAL_JPEG_ERROR_DMA ((uint32_t)0x00000004U) 0000e9: line 174 define HAL_JPEG_ERROR_TIMEOUT ((uint32_t)0x00000008U) 00011b: line 184 define JPEG_QUANT_TABLE_SIZE ((uint32_t)64U) 000144: line 194 define JPEG_GRAYSCALE_COLORSPACE ((uint32_t)0x00000000U) 000179: line 195 define JPEG_YCBCR_COLORSPACE JPEG_CONFR1_COLORSPACE_0 0001ab: line 196 define JPEG_CMYK_COLORSPACE JPEG_CONFR1_COLORSPACE 0001da: line 208 define JPEG_444_SUBSAMPLING ((uint32_t)0x00000000U) 00020a: line 209 define JPEG_420_SUBSAMPLING ((uint32_t)0x00000001U) 00023a: line 210 define JPEG_422_SUBSAMPLING ((uint32_t)0x00000002U) 00026a: line 220 define JPEG_IMAGE_QUALITY_MIN ((uint32_t)1U) 000293: line 221 define JPEG_IMAGE_QUALITY_MAX ((uint32_t)100U) 0002be: line 231 define JPEG_IT_IFT ((uint32_t)JPEG_CR_IFTIE) 0002e7: line 232 define JPEG_IT_IFNF ((uint32_t)JPEG_CR_IFNFIE) 000312: line 233 define JPEG_IT_OFT ((uint32_t)JPEG_CR_OFTIE) 00033b: line 234 define JPEG_IT_OFNE ((uint32_t)JPEG_CR_OFTIE) 000365: line 235 define JPEG_IT_EOC ((uint32_t)JPEG_CR_EOCIE) 00038e: line 236 define JPEG_IT_HPD ((uint32_t)JPEG_CR_HPDIE) 0003b7: line 245 define JPEG_FLAG_IFTF ((uint32_t)JPEG_SR_IFTF) 0003e2: line 246 define JPEG_FLAG_IFNFF ((uint32_t)JPEG_SR_IFNFF) 00040f: line 247 define JPEG_FLAG_OFTF ((uint32_t)JPEG_SR_OFTF) 00043a: line 248 define JPEG_FLAG_OFNEF ((uint32_t)JPEG_SR_OFNEF) 000467: line 249 define JPEG_FLAG_EOCF ((uint32_t)JPEG_SR_EOCF) 000492: line 250 define JPEG_FLAG_HPDF ((uint32_t)JPEG_SR_HPDF) 0004bd: line 251 define JPEG_FLAG_COF ((uint32_t)JPEG_SR_COF) 0004e6: line 253 define JPEG_FLAG_ALL ((uint32_t)0x000000FEU) 00050f: line 262 define JPEG_PAUSE_RESUME_INPUT ((uint32_t)0x00000001U) 000542: line 263 define JPEG_PAUSE_RESUME_OUTPUT ((uint32_t)0x00000002U) 000576: line 264 define JPEG_PAUSE_RESUME_INPUT_OUTPUT ((uint32_t)0x00000003U) 0005b0: line 282 define __HAL_JPEG_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_JPEG_STATE_RESET) 00060b: line 290 define __HAL_JPEG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= JPEG_CR_JCEN) 000659: line 297 define __HAL_JPEG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~JPEG_CR_JCEN) 0006a9: line 318 define __HAL_JPEG_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__))) 000701: line 331 define __HAL_JPEG_CLEAR_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->CFR |= ((__FLAG__) & (JPEG_FLAG_EOCF | JPEG_FLAG_HPDF)))) 000783: line 348 define __HAL_JPEG_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__) ) 0007e6: line 366 define __HAL_JPEG_DISABLE_IT(__HANDLE__,__INTERRUPT__) MODIFY_REG((__HANDLE__)->Instance->CR, (__INTERRUPT__), 0) 000854: line 383 define __HAL_JPEG_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) 0008b9: line 526 define IS_JPEG_CHROMASUBSAMPLING(SUBSAMPLING) (((SUBSAMPLING) == JPEG_444_SUBSAMPLING) || ((SUBSAMPLING) == JPEG_420_SUBSAMPLING) || ((SUBSAMPLING) == JPEG_422_SUBSAMPLING)) 000963: line 530 define IS_JPEG_IMAGE_QUALITY(NUMBER) (((NUMBER) >= JPEG_IMAGE_QUALITY_MIN) && ((NUMBER) <= JPEG_IMAGE_QUALITY_MAX)) 0009d3: line 532 define IS_JPEG_COLORSPACE(COLORSPACE) (((COLORSPACE) == JPEG_GRAYSCALE_COLORSPACE) || ((COLORSPACE) == JPEG_YCBCR_COLORSPACE) || ((COLORSPACE) == JPEG_CMYK_COLORSPACE)) 000a78: line 536 define IS_JPEG_PAUSE_RESUME_STATE(VALUE) (((VALUE) == JPEG_PAUSE_RESUME_INPUT) || ((VALUE) == JPEG_PAUSE_RESUME_OUTPUT)|| ((VALUE) == JPEG_PAUSE_RESUME_INPUT_OUTPUT)) 000b1b: end include 000b1c: end of translation unit ** Section #321 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 124 bytes 000000: Header: length 120 (not including this field) version 3 prologue length 108 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_jpeg.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 6a 70 65 67 2e 68 00 01 00 00 00005e: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000075: file "" : 00 000076: DW_LNS_negate_stmt : 06 000077: DW_LNS_negate_stmt : 06 000078: DW_LNS_negate_stmt : 06 000079: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_jpeg.h:1.0 [ ** Section #322 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 1040 bytes 000000: Header: size 0x40c bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_jpeg.h 00004a: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000091: DW_AT_language DW_LANG_C89 000093: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010a: DW_AT_macro_info 0x0 00010e: DW_AT_stmt_list 0x0 000112: 42 = 0x13 (DW_TAG_structure_type) 000113: DW_AT_sibling 0x185 000115: DW_AT_byte_size 0x10 000116: 30 = 0xd (DW_TAG_member) 000117: DW_AT_name ColorSpace 000122: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000127: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00012a: 30 = 0xd (DW_TAG_member) 00012b: DW_AT_name ChromaSubsampling 00013d: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000142: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 1 } 000145: 30 = 0xd (DW_TAG_member) 000146: DW_AT_name ImageHeight 000152: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000157: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 00015a: 30 = 0xd (DW_TAG_member) 00015b: DW_AT_name ImageWidth 000166: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00016b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 8 } 00016e: 30 = 0xd (DW_TAG_member) 00016f: DW_AT_name ImageQuality 00017c: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000181: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000184: 0 null 000185: 80 = 0x16 (DW_TAG_typedef) 000186: DW_AT_name JPEG_ConfTypeDef 000197: DW_AT_type indirect DW_FORM_ref2 0x112 00019a: DW_AT_decl_file 0x1 00019b: DW_AT_decl_line 0x50 00019c: DW_AT_decl_column 0x2 00019d: 19 = 0x4 (DW_TAG_enumeration_type) 00019e: DW_AT_sibling 0x25b 0001a0: DW_AT_byte_size 0x1 0001a1: 20 = 0x28 (DW_TAG_enumerator) 0001a2: DW_AT_name HAL_JPEG_STATE_RESET 0001b7: DW_AT_const_value indirect DW_FORM_data1 0x0 0001b9: 20 = 0x28 (DW_TAG_enumerator) 0001ba: DW_AT_name HAL_JPEG_STATE_READY 0001cf: DW_AT_const_value indirect DW_FORM_data1 0x1 0001d1: 20 = 0x28 (DW_TAG_enumerator) 0001d2: DW_AT_name HAL_JPEG_STATE_BUSY 0001e6: DW_AT_const_value indirect DW_FORM_data1 0x2 0001e8: 20 = 0x28 (DW_TAG_enumerator) 0001e9: DW_AT_name HAL_JPEG_STATE_BUSY_ENCODING 000206: DW_AT_const_value indirect DW_FORM_data1 0x3 000208: 20 = 0x28 (DW_TAG_enumerator) 000209: DW_AT_name HAL_JPEG_STATE_BUSY_DECODING 000226: DW_AT_const_value indirect DW_FORM_data1 0x4 000228: 20 = 0x28 (DW_TAG_enumerator) 000229: DW_AT_name HAL_JPEG_STATE_TIMEOUT 000240: DW_AT_const_value indirect DW_FORM_data1 0x5 000242: 20 = 0x28 (DW_TAG_enumerator) 000243: DW_AT_name HAL_JPEG_STATE_ERROR 000258: DW_AT_const_value indirect DW_FORM_data1 0x6 00025a: 0 null 00025b: 80 = 0x16 (DW_TAG_typedef) 00025c: DW_AT_name HAL_JPEG_STATETypeDef 000272: DW_AT_type indirect DW_FORM_ref2 0x19d 000275: DW_AT_decl_file 0x1 000276: DW_AT_decl_line 0x62 000277: DW_AT_decl_column 0x2 000278: 42 = 0x13 (DW_TAG_structure_type) 000279: DW_AT_sibling 0x3d7 00027b: DW_AT_byte_size 0x54 00027c: 30 = 0xd (DW_TAG_member) 00027d: DW_AT_name Instance 000286: DW_AT_type indirect DW_FORM_ref2 0x3d7 000289: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 00028c: 30 = 0xd (DW_TAG_member) 00028d: DW_AT_name Conf 000292: DW_AT_type indirect DW_FORM_ref2 0x185 000295: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000298: 30 = 0xd (DW_TAG_member) 000299: DW_AT_name pJpegInBuffPtr 0002a8: DW_AT_type indirect DW_FORM_ref2 0x3dd 0002ab: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 20 } 0002ae: 30 = 0xd (DW_TAG_member) 0002af: DW_AT_name pJpegOutBuffPtr 0002bf: DW_AT_type indirect DW_FORM_ref2 0x3dd 0002c2: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 24 } 0002c5: 30 = 0xd (DW_TAG_member) 0002c6: DW_AT_name JpegInCount 0002d2: DW_AT_type indirect DW_FORM_ref2 0x3e3 0002d5: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 28 } 0002d8: 30 = 0xd (DW_TAG_member) 0002d9: DW_AT_name JpegOutCount 0002e6: DW_AT_type indirect DW_FORM_ref2 0x3e3 0002e9: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 32 } 0002ec: 30 = 0xd (DW_TAG_member) 0002ed: DW_AT_name InDataLength 0002fa: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0002ff: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 36 } 000302: 30 = 0xd (DW_TAG_member) 000303: DW_AT_name OutDataLength 000311: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 000316: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 40 } 000319: 30 = 0xd (DW_TAG_member) 00031a: DW_AT_name hdmain 000321: DW_AT_type indirect DW_FORM_ref2 0x3e9 000324: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 44 } 000327: 30 = 0xd (DW_TAG_member) 000328: DW_AT_name hdmaout 000330: DW_AT_type indirect DW_FORM_ref2 0x3e9 000333: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 48 } 000336: 30 = 0xd (DW_TAG_member) 000337: DW_AT_name CustomQuanTable 000347: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 00034c: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 52 } 00034f: 30 = 0xd (DW_TAG_member) 000350: DW_AT_name QuantTable0 00035c: DW_AT_type indirect DW_FORM_ref2 0x3dd 00035f: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 56 } 000362: 30 = 0xd (DW_TAG_member) 000363: DW_AT_name QuantTable1 00036f: DW_AT_type indirect DW_FORM_ref2 0x3dd 000372: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 60 } 000375: 30 = 0xd (DW_TAG_member) 000376: DW_AT_name QuantTable2 000382: DW_AT_type indirect DW_FORM_ref2 0x3dd 000385: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 64 } 000388: 30 = 0xd (DW_TAG_member) 000389: DW_AT_name QuantTable3 000395: DW_AT_type indirect DW_FORM_ref2 0x3dd 000398: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 68 } 00039b: 30 = 0xd (DW_TAG_member) 00039c: DW_AT_name Lock 0003a1: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 0003a6: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 72 } 0003a9: 30 = 0xd (DW_TAG_member) 0003aa: DW_AT_name State 0003b0: DW_AT_type indirect DW_FORM_ref2 0x3ef 0003b3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 73 } 0003b6: 30 = 0xd (DW_TAG_member) 0003b7: DW_AT_name ErrorCode 0003c1: DW_AT_type indirect DW_FORM_ref2 0x3e3 0003c4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 76 } 0003c7: 30 = 0xd (DW_TAG_member) 0003c8: DW_AT_name Context 0003d0: DW_AT_type indirect DW_FORM_ref2 0x3e3 0003d3: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 80 } 0003d6: 0 null 0003d7: 34 = 0xf (DW_TAG_pointer_type) 0003d8: DW_AT_type indirect DW_FORM_ref_addr 0x312e+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 0003dd: 34 = 0xf (DW_TAG_pointer_type) 0003de: DW_AT_type indirect DW_FORM_ref_addr 0x14e+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003e3: 116 = 0x35 (DW_TAG_volatile_type) 0003e4: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0003e9: 34 = 0xf (DW_TAG_pointer_type) 0003ea: DW_AT_type indirect DW_FORM_ref_addr 0x1a0+__ARM_grp..debug_info$stm32f7xx_hal_dma.h$.2_wD1100_gh0hnOcebnc_s10000 0003ef: 116 = 0x35 (DW_TAG_volatile_type) 0003f0: DW_AT_type indirect DW_FORM_ref2 0x25b 0003f3: 80 = 0x16 (DW_TAG_typedef) 0003f4: DW_AT_name JPEG_HandleTypeDef 000407: DW_AT_type indirect DW_FORM_ref2 0x278 00040a: DW_AT_decl_file 0x1 00040b: DW_AT_decl_line 0x95 00040d: DW_AT_decl_column 0x2 00040e: 0 null 00040f: 0 padding ** Section #435 '.rel.debug_info' (SHT_REL) Size : 128 bytes (alignment 4) Symbol table #343 '.symtab' 16 relocations applied to section #322 '.debug_info' ** Section #323 '__ARM_grp.stm32f7xx_hal_mdios.h.2_4e_000_04RvB$CKy66_f10000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #324 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 5508 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_MDIOS_H 00001e: include at line 49 - file 2 000021: end include 000022: line 127 define MDIOS_PREAMBLE_CHECK_ENABLE ((uint32_t)0x00000000U) 000058: line 128 define MDIOS_PREAMBLE_CHECK_DISABLE MDIOS_CR_DPC 000085: line 136 define MDIOS_REG0 ((uint32_t)0x00000000U) 0000ab: line 137 define MDIOS_REG1 ((uint32_t)0x00000001U) 0000d1: line 138 define MDIOS_REG2 ((uint32_t)0x00000002U) 0000f7: line 139 define MDIOS_REG3 ((uint32_t)0x00000003U) 00011d: line 140 define MDIOS_REG4 ((uint32_t)0x00000004U) 000143: line 141 define MDIOS_REG5 ((uint32_t)0x00000005U) 000169: line 142 define MDIOS_REG6 ((uint32_t)0x00000006U) 00018f: line 143 define MDIOS_REG7 ((uint32_t)0x00000007U) 0001b5: line 144 define MDIOS_REG8 ((uint32_t)0x00000008U) 0001db: line 145 define MDIOS_REG9 ((uint32_t)0x00000009U) 000201: line 146 define MDIOS_REG10 ((uint32_t)0x0000000AU) 000228: line 147 define MDIOS_REG11 ((uint32_t)0x0000000BU) 00024f: line 148 define MDIOS_REG12 ((uint32_t)0x0000000CU) 000276: line 149 define MDIOS_REG13 ((uint32_t)0x0000000DU) 00029d: line 150 define MDIOS_REG14 ((uint32_t)0x0000000EU) 0002c4: line 151 define MDIOS_REG15 ((uint32_t)0x0000000FU) 0002eb: line 152 define MDIOS_REG16 ((uint32_t)0x00000010U) 000312: line 153 define MDIOS_REG17 ((uint32_t)0x00000011U) 000339: line 154 define MDIOS_REG18 ((uint32_t)0x00000012U) 000360: line 155 define MDIOS_REG19 ((uint32_t)0x00000013U) 000387: line 156 define MDIOS_REG20 ((uint32_t)0x00000014U) 0003ae: line 157 define MDIOS_REG21 ((uint32_t)0x00000015U) 0003d5: line 158 define MDIOS_REG22 ((uint32_t)0x00000016U) 0003fc: line 159 define MDIOS_REG23 ((uint32_t)0x00000017U) 000423: line 160 define MDIOS_REG24 ((uint32_t)0x00000018U) 00044a: line 161 define MDIOS_REG25 ((uint32_t)0x00000019U) 000471: line 162 define MDIOS_REG26 ((uint32_t)0x0000001AU) 000498: line 163 define MDIOS_REG27 ((uint32_t)0x0000001BU) 0004bf: line 164 define MDIOS_REG28 ((uint32_t)0x0000001CU) 0004e6: line 165 define MDIOS_REG29 ((uint32_t)0x0000001DU) 00050d: line 166 define MDIOS_REG30 ((uint32_t)0x0000001EU) 000534: line 167 define MDIOS_REG31 ((uint32_t)0x0000001FU) 00055b: line 175 define MDIOS_REG0_FLAG ((uint32_t)0x00000001U) 000586: line 176 define MDIOS_REG1_FLAG ((uint32_t)0x00000002U) 0005b1: line 177 define MDIOS_REG2_FLAG ((uint32_t)0x00000004U) 0005dc: line 178 define MDIOS_REG3_FLAG ((uint32_t)0x00000008U) 000607: line 179 define MDIOS_REG4_FLAG ((uint32_t)0x00000010U) 000632: line 180 define MDIOS_REG5_FLAG ((uint32_t)0x00000020U) 00065d: line 181 define MDIOS_REG6_FLAG ((uint32_t)0x00000040U) 000688: line 182 define MDIOS_REG7_FLAG ((uint32_t)0x00000080U) 0006b3: line 183 define MDIOS_REG8_FLAG ((uint32_t)0x00000100U) 0006de: line 184 define MDIOS_REG9_FLAG ((uint32_t)0x00000200U) 000709: line 185 define MDIOS_REG10_FLAG ((uint32_t)0x00000400U) 000735: line 186 define MDIOS_REG11_FLAG ((uint32_t)0x00000800U) 000761: line 187 define MDIOS_REG12_FLAG ((uint32_t)0x00001000U) 00078d: line 188 define MDIOS_REG13_FLAG ((uint32_t)0x00002000U) 0007b9: line 189 define MDIOS_REG14_FLAG ((uint32_t)0x00004000U) 0007e5: line 190 define MDIOS_REG15_FLAG ((uint32_t)0x00008000U) 000811: line 191 define MDIOS_REG16_FLAG ((uint32_t)0x00010000U) 00083d: line 192 define MDIOS_REG17_FLAG ((uint32_t)0x00020000U) 000869: line 193 define MDIOS_REG18_FLAG ((uint32_t)0x00040000U) 000895: line 194 define MDIOS_REG19_FLAG ((uint32_t)0x00080000U) 0008c1: line 195 define MDIOS_REG20_FLAG ((uint32_t)0x00100000U) 0008ed: line 196 define MDIOS_REG21_FLAG ((uint32_t)0x00200000U) 000919: line 197 define MDIOS_REG22_FLAG ((uint32_t)0x00400000U) 000945: line 198 define MDIOS_REG23_FLAG ((uint32_t)0x00800000U) 000971: line 199 define MDIOS_REG24_FLAG ((uint32_t)0x01000000U) 00099d: line 200 define MDIOS_REG25_FLAG ((uint32_t)0x02000000U) 0009c9: line 201 define MDIOS_REG26_FLAG ((uint32_t)0x04000000U) 0009f5: line 202 define MDIOS_REG27_FLAG ((uint32_t)0x08000000U) 000a21: line 203 define MDIOS_REG28_FLAG ((uint32_t)0x10000000U) 000a4d: line 204 define MDIOS_REG29_FLAG ((uint32_t)0x20000000U) 000a79: line 205 define MDIOS_REG30_FLAG ((uint32_t)0x40000000U) 000aa5: line 206 define MDIOS_REG31_FLAG ((uint32_t)0x80000000U) 000ad1: line 207 define MDIOS_ALLREG_FLAG ((uint32_t)0xFFFFFFFFU) 000afe: line 215 define MDIOS_IT_WRITE MDIOS_CR_WRIE 000b1e: line 216 define MDIOS_IT_READ MDIOS_CR_RDIE 000b3d: line 217 define MDIOS_IT_ERROR MDIOS_CR_EIE 000b5c: line 225 define MDIOS_TURNAROUND_ERROR_FLAG MDIOS_SR_TERF 000b89: line 226 define MDIOS_START_ERROR_FLAG MDIOS_SR_SERF 000bb1: line 227 define MDIOS_PREAMBLE_ERROR_FLAG MDIOS_SR_PERF 000bdc: line 235 define MDIOS_WAKEUP_EXTI_LINE ((uint32_t)0x01000000) 000c0d: line 252 define __HAL_MDIOS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MDIOS_STATE_RESET) 000c69: line 259 define __HAL_MDIOS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= MDIOS_CR_EN) 000cb7: line 260 define __HAL_MDIOS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~MDIOS_CR_EN) 000d07: line 273 define __HAL_MDIOS_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) 000d6a: line 285 define __HAL_MDIOS_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) 000dcf: line 292 define __HAL_MDIOS_GET_WRITE_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->WRFR & (__FLAG__)) 000e2e: line 299 define __HAL_MDIOS_GET_READ_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->RDFR & (__FLAG__)) 000e8c: line 310 define __HAL_MDIOS_GET_ERROR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->SR & (__FLAG__)) 000ee9: line 321 define __HAL_MDIOS_CLEAR_ERROR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->CLRFR) |= (__FLAG__) 000f4c: line 333 define __HAL_MDIOS_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) 000fb2: line 339 define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_IT() (EXTI->IMR |= (MDIOS_WAKEUP_EXTI_LINE)) 001001: line 345 define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_IT() (EXTI->IMR &= ~(MDIOS_WAKEUP_EXTI_LINE)) 001052: line 351 define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_EVENT() (EXTI->EMR |= (MDIOS_WAKEUP_EXTI_LINE)) 0010a4: line 357 define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(MDIOS_WAKEUP_EXTI_LINE)) 0010f8: line 363 define __HAL_MDIOS_WAKEUP_EXTI_GET_FLAG() (EXTI->PR & (MDIOS_WAKEUP_EXTI_LINE)) 001144: line 369 define __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG() (EXTI->PR = (MDIOS_WAKEUP_EXTI_LINE)) 001192: line 375 define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= MDIOS_WAKEUP_EXTI_LINE 0011ef: line 381 define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(MDIOS_WAKEUP_EXTI_LINE) 001250: line 387 define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (MDIOS_WAKEUP_EXTI_LINE) 0012b0: line 393 define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(MDIOS_WAKEUP_EXTI_LINE) 001312: line 399 define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR |= MDIOS_WAKEUP_EXTI_LINE; EXTI->FTSR |= MDIOS_WAKEUP_EXTI_LINE 001397: line 406 define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(MDIOS_WAKEUP_EXTI_LINE); EXTI->FTSR &= ~(MDIOS_WAKEUP_EXTI_LINE) 001423: line 412 define __HAL_MDIOS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (MDIOS_WAKEUP_EXTI_LINE)) 001478: line 500 define IS_MDIOS_PORTADDRESS(__ADDR__) ((__ADDR__) < 32) 0014ac: line 502 define IS_MDIOS_REGISTER(__REGISTER__) ((__REGISTER__) < 32) 0014e5: line 504 define IS_MDIOS_PREAMBLECHECK(__PREAMBLECHECK__) (((__PREAMBLECHECK__) == MDIOS_PREAMBLE_CHECK_ENABLE) || ((__PREAMBLECHECK__) == MDIOS_PREAMBLE_CHECK_DISABLE)) 001582: end include 001583: end of translation unit ** Section #325 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 124 bytes 000000: Header: length 120 (not including this field) version 3 prologue length 109 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000045: directory "" : 00 000046: file "stm32f7xx_hal_mdios.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 6d 64 69 6f 73 2e 68 00 01 00 00 00005f: file "stm32f7xx_hal_def.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 65 66 2e 68 00 01 00 00 000076: file "" : 00 000077: DW_LNS_negate_stmt : 06 000078: DW_LNS_negate_stmt : 06 000079: DW_LNE_end sequence : 00 01 01 00000000: ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_mdios.h:1.0 ** Section #326 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 584 bytes 000000: Header: size 0x244 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\Libraries\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_mdios.h 00004b: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000092: DW_AT_language DW_LANG_C89 000094: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 00010b: DW_AT_macro_info 0x0 00010f: DW_AT_stmt_list 0x0 000113: 19 = 0x4 (DW_TAG_enumeration_type) 000114: DW_AT_sibling 0x17b 000116: DW_AT_byte_size 0x1 000117: 20 = 0x28 (DW_TAG_enumerator) 000118: DW_AT_name HAL_MDIOS_STATE_RESET 00012e: DW_AT_const_value indirect DW_FORM_data1 0x0 000130: 20 = 0x28 (DW_TAG_enumerator) 000131: DW_AT_name HAL_MDIOS_STATE_READY 000147: DW_AT_const_value indirect DW_FORM_data1 0x1 000149: 20 = 0x28 (DW_TAG_enumerator) 00014a: DW_AT_name HAL_MDIOS_STATE_BUSY 00015f: DW_AT_const_value indirect DW_FORM_data1 0x2 000161: 20 = 0x28 (DW_TAG_enumerator) 000162: DW_AT_name HAL_MDIOS_STATE_ERROR 000178: DW_AT_const_value indirect DW_FORM_data1 0x4 00017a: 0 null 00017b: 80 = 0x16 (DW_TAG_typedef) 00017c: DW_AT_name HAL_MDIOS_StateTypeDef 000193: DW_AT_type indirect DW_FORM_ref2 0x113 000196: DW_AT_decl_file 0x1 000197: DW_AT_decl_line 0x4a 000198: DW_AT_decl_column 0x2 000199: 42 = 0x13 (DW_TAG_structure_type) 00019a: DW_AT_sibling 0x1ca 00019c: DW_AT_byte_size 0x8 00019d: 30 = 0xd (DW_TAG_member) 00019e: DW_AT_name PortAddress 0001aa: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001af: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0001b2: 30 = 0xd (DW_TAG_member) 0001b3: DW_AT_name PreambleCheck 0001c1: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0001c6: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 0001c9: 0 null 0001ca: 80 = 0x16 (DW_TAG_typedef) 0001cb: DW_AT_name MDIOS_InitTypeDef 0001dd: DW_AT_type indirect DW_FORM_ref2 0x199 0001e0: DW_AT_decl_file 0x1 0001e1: DW_AT_decl_line 0x5a 0001e2: DW_AT_decl_column 0x2 0001e3: 42 = 0x13 (DW_TAG_structure_type) 0001e4: DW_AT_sibling 0x21f 0001e6: DW_AT_byte_size 0x10 0001e7: 30 = 0xd (DW_TAG_member) 0001e8: DW_AT_name Instance 0001f1: DW_AT_type indirect DW_FORM_ref2 0x21f 0001f4: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 0 } 0001f7: 30 = 0xd (DW_TAG_member) 0001f8: DW_AT_name Init 0001fd: DW_AT_type indirect DW_FORM_ref2 0x1ca 000200: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 4 } 000203: 30 = 0xd (DW_TAG_member) 000204: DW_AT_name State 00020a: DW_AT_type indirect DW_FORM_ref2 0x225 00020d: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 12 } 000210: 30 = 0xd (DW_TAG_member) 000211: DW_AT_name Lock 000216: DW_AT_type indirect DW_FORM_ref_addr 0x184+__ARM_grp..debug_info$stm32f7xx_hal_def.h$.2_kZ0000_qdUHTrAfbN8_300000 00021b: DW_AT_data_member_location block size 0x2 = { DW_OP_plus_uconst 13 } 00021e: 0 null 00021f: 34 = 0xf (DW_TAG_pointer_type) 000220: DW_AT_type indirect DW_FORM_ref_addr 0x3584+__ARM_grp..debug_info$stm32f767xx.h$.2_8vN100_X1EE77Qf3Q1_510000 000225: 116 = 0x35 (DW_TAG_volatile_type) 000226: DW_AT_type indirect DW_FORM_ref2 0x17b 000229: 80 = 0x16 (DW_TAG_typedef) 00022a: DW_AT_name MDIOS_HandleTypeDef 00023e: DW_AT_type indirect DW_FORM_ref2 0x1e3 000241: DW_AT_decl_file 0x1 000242: DW_AT_decl_line 0x6d 000243: DW_AT_decl_column 0x2 000244: 0 null 000245: 0 padding 000246: 0 padding 000247: 0 padding ** Section #436 '.rel.debug_info' (SHT_REL) Size : 56 bytes (alignment 4) Symbol table #343 '.symtab' 7 relocations applied to section #326 '.debug_info' ** Section #327 '__ARM_grp.stm32f7xx_hal_conf.h.2_Qu2000_ovbBubWaf1e_300000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #328 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 3072 bytes 000000: include at line 0 - file 1 000003: line 40 define __STM32F7xx_HAL_CONF_H 00001d: line 53 define HAL_MODULE_ENABLED 000033: line 54 define HAL_ADC_MODULE_ENABLED 00004d: line 55 define HAL_CAN_MODULE_ENABLED 000067: line 56 define HAL_CEC_MODULE_ENABLED 000081: line 57 define HAL_CRC_MODULE_ENABLED 00009b: line 58 define HAL_CRYP_MODULE_ENABLED 0000b6: line 59 define HAL_DAC_MODULE_ENABLED 0000d0: line 60 define HAL_DCMI_MODULE_ENABLED 0000eb: line 61 define HAL_DMA_MODULE_ENABLED 000105: line 62 define HAL_DMA2D_MODULE_ENABLED 000121: line 63 define HAL_ETH_MODULE_ENABLED 00013b: line 64 define HAL_FLASH_MODULE_ENABLED 000157: line 65 define HAL_NAND_MODULE_ENABLED 000172: line 66 define HAL_NOR_MODULE_ENABLED 00018c: line 67 define HAL_SRAM_MODULE_ENABLED 0001a7: line 68 define HAL_SDRAM_MODULE_ENABLED 0001c3: line 69 define HAL_HASH_MODULE_ENABLED 0001de: line 70 define HAL_GPIO_MODULE_ENABLED 0001f9: line 71 define HAL_I2C_MODULE_ENABLED 000213: line 72 define HAL_I2S_MODULE_ENABLED 00022d: line 73 define HAL_IWDG_MODULE_ENABLED 000248: line 74 define HAL_LPTIM_MODULE_ENABLED 000264: line 75 define HAL_LTDC_MODULE_ENABLED 00027f: line 76 define HAL_PWR_MODULE_ENABLED 000299: line 77 define HAL_QSPI_MODULE_ENABLED 0002b4: line 78 define HAL_RCC_MODULE_ENABLED 0002ce: line 79 define HAL_RNG_MODULE_ENABLED 0002e8: line 80 define HAL_RTC_MODULE_ENABLED 000302: line 81 define HAL_SAI_MODULE_ENABLED 00031c: line 82 define HAL_SD_MODULE_ENABLED 000335: line 83 define HAL_SPDIFRX_MODULE_ENABLED 000353: line 84 define HAL_SPI_MODULE_ENABLED 00036d: line 85 define HAL_TIM_MODULE_ENABLED 000387: line 86 define HAL_UART_MODULE_ENABLED 0003a2: line 87 define HAL_USART_MODULE_ENABLED 0003be: line 88 define HAL_IRDA_MODULE_ENABLED 0003d9: line 89 define HAL_SMARTCARD_MODULE_ENABLED 0003f9: line 90 define HAL_WWDG_MODULE_ENABLED 000414: line 91 define HAL_CORTEX_MODULE_ENABLED 000431: line 92 define HAL_PCD_MODULE_ENABLED 00044b: line 93 define HAL_HCD_MODULE_ENABLED 000465: line 94 define HAL_DFSDM_MODULE_ENABLED 000481: line 95 define HAL_DSI_MODULE_ENABLED 00049b: line 96 define HAL_JPEG_MODULE_ENABLED 0004b6: line 97 define HAL_MDIOS_MODULE_ENABLED 0004d2: line 107 define HSE_VALUE ((uint32_t)25000000U) 0004f4: line 111 define HSE_STARTUP_TIMEOUT ((uint32_t)100U) 00051b: line 120 define HSI_VALUE ((uint32_t)16000000U) 00053d: line 127 define LSI_VALUE ((uint32_t)32000U) 00055c: line 135 define LSE_VALUE ((uint32_t)32768U) 00057c: line 139 define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) 0005a5: line 148 define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) 0005d3: line 158 define VDD_VALUE ((uint32_t)3300U) 0005f2: line 159 define TICK_INT_PRIORITY ((uint32_t)0x0FU) 000619: line 160 define USE_RTOS 0U 000628: line 161 define PREFETCH_ENABLE 1U 00063e: line 162 define ART_ACCLERATOR_ENABLE 1U 00065a: line 176 define MAC_ADDR0 2U 00066a: line 177 define MAC_ADDR1 0U 00067a: line 178 define MAC_ADDR2 0U 00068a: line 179 define MAC_ADDR3 0U 00069a: line 180 define MAC_ADDR4 0U 0006aa: line 181 define MAC_ADDR5 0U 0006ba: line 184 define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE 0006e1: line 185 define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE 000708: line 186 define ETH_RXBUFNB ((uint32_t)5) 000725: line 187 define ETH_TXBUFNB ((uint32_t)5) 000742: line 191 define LAN8742A_PHY_ADDRESS 0x00 00075f: line 193 define PHY_RESET_DELAY ((uint32_t)0x00000FFF) 000789: line 195 define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF) 0007b4: line 197 define PHY_READ_TO ((uint32_t)0x0000FFFF) 0007da: line 198 define PHY_WRITE_TO ((uint32_t)0x0000FFFF) 000801: line 202 define PHY_BCR ((uint16_t)0x00) 00081d: line 203 define PHY_BSR ((uint16_t)0x01) 000839: line 205 define PHY_RESET ((uint16_t)0x8000) 000859: line 206 define PHY_LOOPBACK ((uint16_t)0x4000) 00087c: line 207 define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) 0008a6: line 208 define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) 0008d0: line 209 define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) 0008f9: line 210 define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) 000922: line 211 define PHY_AUTONEGOTIATION ((uint16_t)0x1000) 00094c: line 212 define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) 00097e: line 213 define PHY_POWERDOWN ((uint16_t)0x0800) 0009a2: line 214 define PHY_ISOLATE ((uint16_t)0x0400) 0009c4: line 216 define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) 0009f0: line 217 define PHY_LINKED_STATUS ((uint16_t)0x0004) 000a18: line 218 define PHY_JABBER_DETECTION ((uint16_t)0x0002) 000a43: line 222 define PHY_SR ((uint16_t)0x1F) 000a5e: line 224 define PHY_SPEED_STATUS ((uint16_t)0x0004) 000a85: line 225 define PHY_DUPLEX_STATUS ((uint16_t)0x0010) 000aad: line 228 define PHY_ISFR ((uint16_t)0x1D) 000aca: line 229 define PHY_ISFR_INT4 ((uint16_t)0x0010) 000aee: line 238 define USE_SPI_CRC 1U 000b00: include at line 246 - file 2 000b04: end include 000b05: include at line 250 - file 3 000b09: end include 000b0a: include at line 254 - file 4 000b0e: end include 000b0f: include at line 258 - file 5 000b13: end include 000b14: include at line 262 - file 6 000b18: end include 000b19: include at line 266 - file 7 000b1d: end include 000b1e: include at line 270 - file 8 000b22: end include 000b23: include at line 274 - file 9 000b27: end include 000b28: include at line 278 - file 10 000b2c: end include 000b2d: include at line 282 - file 11 000b31: end include 000b32: include at line 286 - file 12 000b36: end include 000b37: include at line 290 - file 13 000b3b: end include 000b3c: include at line 294 - file 14 000b40: end include 000b41: include at line 298 - file 15 000b45: end include 000b46: include at line 302 - file 16 000b4a: end include 000b4b: include at line 306 - file 17 000b4f: end include 000b50: include at line 310 - file 18 000b54: end include 000b55: include at line 314 - file 19 000b59: end include 000b5a: include at line 318 - file 20 000b5e: end include 000b5f: include at line 322 - file 21 000b63: end include 000b64: include at line 326 - file 22 000b68: end include 000b69: include at line 330 - file 23 000b6d: end include 000b6e: include at line 334 - file 24 000b72: end include 000b73: include at line 338 - file 25 000b77: end include 000b78: include at line 342 - file 26 000b7c: end include 000b7d: include at line 346 - file 27 000b81: end include 000b82: include at line 350 - file 28 000b86: end include 000b87: include at line 354 - file 29 000b8b: end include 000b8c: include at line 358 - file 30 000b90: end include 000b91: include at line 362 - file 31 000b95: end include 000b96: include at line 366 - file 32 000b9a: end include 000b9b: include at line 370 - file 33 000b9f: end include 000ba0: include at line 374 - file 34 000ba4: end include 000ba5: include at line 378 - file 35 000ba9: end include 000baa: include at line 382 - file 36 000bae: end include 000baf: include at line 386 - file 37 000bb3: end include 000bb4: include at line 390 - file 38 000bb8: end include 000bb9: include at line 394 - file 39 000bbd: end include 000bbe: include at line 398 - file 40 000bc2: end include 000bc3: include at line 402 - file 41 000bc7: end include 000bc8: include at line 406 - file 42 000bcc: end include 000bcd: include at line 410 - file 43 000bd1: end include 000bd2: include at line 414 - file 44 000bd6: end include 000bd7: include at line 418 - file 45 000bdb: end include 000bdc: line 435 define assert_param(expr) ((void)0) 000bfc: end include 000bfd: end of translation unit ** Section #329 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 1164 bytes 000000: Header: length 1160 (not including this field) version 3 prologue length 1148 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\User\" : 2e 2e 5c 2e 2e 5c 55 73 65 72 5c 00 000027: directory "..\..\Libraries\STM32F7xx_HAL_Driver\Inc\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 53 54 4d 33 32 46 37 78 78 5f 48 41 4c 5f 44 72 69 76 65 72 5c 49 6e 63 5c 00 000051: directory "" : 00 000052: file "stm32f7xx_hal_conf.h": dir 1 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 63 6f 6e 66 2e 68 00 01 00 00 00006a: file "stm32f7xx_hal_rcc.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 72 63 63 2e 68 00 02 00 00 000081: file "stm32f7xx_hal_gpio.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 67 70 69 6f 2e 68 00 02 00 00 000099: file "stm32f7xx_hal_dma.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 6d 61 2e 68 00 02 00 00 0000b0: file "stm32f7xx_hal_cortex.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 63 6f 72 74 65 78 2e 68 00 02 00 00 0000ca: file "stm32f7xx_hal_adc.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 61 64 63 2e 68 00 02 00 00 0000e1: file "stm32f7xx_hal_can.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 63 61 6e 2e 68 00 02 00 00 0000f8: file "stm32f7xx_hal_cec.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 63 65 63 2e 68 00 02 00 00 00010f: file "stm32f7xx_hal_crc.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 63 72 63 2e 68 00 02 00 00 000126: file "stm32f7xx_hal_cryp.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 63 72 79 70 2e 68 00 02 00 00 00013e: file "stm32f7xx_hal_dma2d.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 6d 61 32 64 2e 68 00 02 00 00 000157: file "stm32f7xx_hal_dac.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 61 63 2e 68 00 02 00 00 00016e: file "stm32f7xx_hal_dcmi.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 63 6d 69 2e 68 00 02 00 00 000186: file "stm32f7xx_hal_eth.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 65 74 68 2e 68 00 02 00 00 00019d: file "stm32f7xx_hal_flash.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 66 6c 61 73 68 2e 68 00 02 00 00 0001b6: file "stm32f7xx_hal_sram.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 73 72 61 6d 2e 68 00 02 00 00 0001ce: file "stm32f7xx_hal_nor.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 6e 6f 72 2e 68 00 02 00 00 0001e5: file "stm32f7xx_hal_nand.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 6e 61 6e 64 2e 68 00 02 00 00 0001fd: file "stm32f7xx_hal_sdram.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 73 64 72 61 6d 2e 68 00 02 00 00 000216: file "stm32f7xx_hal_hash.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 68 61 73 68 2e 68 00 02 00 00 00022e: file "stm32f7xx_hal_i2c.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 69 32 63 2e 68 00 02 00 00 000245: file "stm32f7xx_hal_i2s.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 69 32 73 2e 68 00 02 00 00 00025c: file "stm32f7xx_hal_iwdg.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 69 77 64 67 2e 68 00 02 00 00 000274: file "stm32f7xx_hal_lptim.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 6c 70 74 69 6d 2e 68 00 02 00 00 00028d: file "stm32f7xx_hal_ltdc.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 6c 74 64 63 2e 68 00 02 00 00 0002a5: file "stm32f7xx_hal_pwr.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 70 77 72 2e 68 00 02 00 00 0002bc: file "stm32f7xx_hal_qspi.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 71 73 70 69 2e 68 00 02 00 00 0002d4: file "stm32f7xx_hal_rng.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 72 6e 67 2e 68 00 02 00 00 0002eb: file "stm32f7xx_hal_rtc.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 72 74 63 2e 68 00 02 00 00 000302: file "stm32f7xx_hal_sai.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 73 61 69 2e 68 00 02 00 00 000319: file "stm32f7xx_hal_sd.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 73 64 2e 68 00 02 00 00 00032f: file "stm32f7xx_hal_spdifrx.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 73 70 64 69 66 72 78 2e 68 00 02 00 00 00034a: file "stm32f7xx_hal_spi.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 73 70 69 2e 68 00 02 00 00 000361: file "stm32f7xx_hal_tim.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 74 69 6d 2e 68 00 02 00 00 000378: file "stm32f7xx_hal_uart.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 75 61 72 74 2e 68 00 02 00 00 000390: file "stm32f7xx_hal_usart.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 75 73 61 72 74 2e 68 00 02 00 00 0003a9: file "stm32f7xx_hal_irda.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 69 72 64 61 2e 68 00 02 00 00 0003c1: file "stm32f7xx_hal_smartcard.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 73 6d 61 72 74 63 61 72 64 2e 68 00 02 00 00 0003de: file "stm32f7xx_hal_wwdg.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 77 77 64 67 2e 68 00 02 00 00 0003f6: file "stm32f7xx_hal_pcd.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 70 63 64 2e 68 00 02 00 00 00040d: file "stm32f7xx_hal_hcd.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 68 63 64 2e 68 00 02 00 00 000424: file "stm32f7xx_hal_dfsdm.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 66 73 64 6d 2e 68 00 02 00 00 00043d: file "stm32f7xx_hal_dsi.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 64 73 69 2e 68 00 02 00 00 000454: file "stm32f7xx_hal_jpeg.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 6a 70 65 67 2e 68 00 02 00 00 00046c: file "stm32f7xx_hal_mdios.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 5f 68 61 6c 5f 6d 64 69 6f 73 2e 68 00 02 00 00 000485: file "" : 00 000486: DW_LNS_negate_stmt : 06 000487: DW_LNS_negate_stmt : 06 000488: DW_LNS_negate_stmt : 06 000489: DW_LNE_end sequence : 00 01 01 00000000: ..\..\User\stm32f7xx_hal_conf.h:1.0 [ ** Section #330 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 248 bytes 000000: Header: size 0xf4 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\User\stm32f7xx_hal_conf.h 00002c: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 000073: DW_AT_language DW_LANG_C89 000075: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 0000ec: DW_AT_macro_info 0x0 0000f0: DW_AT_stmt_list 0x0 0000f4: 0 null 0000f5: 0 padding 0000f6: 0 padding 0000f7: 0 padding ** Section #437 '.rel.debug_info' (SHT_REL) Size : 24 bytes (alignment 4) Symbol table #343 '.symtab' 3 relocations applied to section #330 '.debug_info' ** Section #331 '__ARM_grp.bsp_led.h.2_Uh1000_2f8gAcSFco7_300000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #332 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 1644 bytes 000000: include at line 0 - file 1 000003: line 2 define __LED_H 00000e: include at line 4 - file 2 000011: end include 000012: line 9 define LED1_PIN GPIO_PIN_10 000029: line 10 define LED1_GPIO_PORT GPIOH 000040: line 11 define LED1_GPIO_CLK_ENABLE() __GPIOH_CLK_ENABLE() 00006e: line 14 define LED2_PIN GPIO_PIN_11 000085: line 15 define LED2_GPIO_PORT GPIOH 00009c: line 16 define LED2_GPIO_CLK_ENABLE() __GPIOH_CLK_ENABLE() 0000ca: line 19 define LED3_PIN GPIO_PIN_12 0000e1: line 20 define LED3_GPIO_PORT GPIOH 0000f8: line 21 define LED3_GPIO_CLK_ENABLE() __GPIOH_CLK_ENABLE() 000126: line 24 define LED4_PIN GPIO_PIN_11 00013d: line 25 define LED4_GPIO_PORT GPIOD 000154: line 26 define LED4_GPIO_CLK_ENABLE() __GPIOD_CLK_ENABLE() 000182: line 34 define ON GPIO_PIN_RESET 000196: line 35 define OFF GPIO_PIN_SET 0001a9: line 38 define LED1(a) HAL_GPIO_WritePin(LED1_GPIO_PORT,LED1_PIN,a) 0001e0: line 41 define LED2(a) HAL_GPIO_WritePin(LED2_GPIO_PORT,LED2_PIN,a) 000217: line 44 define LED3(a) HAL_GPIO_WritePin(LED2_GPIO_PORT,LED3_PIN,a) 00024e: line 47 define LED4(a) HAL_GPIO_WritePin(LED4_GPIO_PORT,LED4_PIN,a) 000285: line 51 define digitalHi(p,i) {p->BSRR=i;} 0002a3: line 52 define digitalLo(p,i) {p->BSRR=(uint32_t)i << 16;} 0002d1: line 53 define digitalToggle(p,i) {p->ODR ^=i;} 0002f4: line 57 define LED1_TOGGLE digitalToggle(LED1_GPIO_PORT,LED1_PIN) 000329: line 58 define LED1_OFF digitalHi(LED1_GPIO_PORT,LED1_PIN) 000357: line 59 define LED1_ON digitalLo(LED1_GPIO_PORT,LED1_PIN) 000384: line 61 define LED2_TOGGLE digitalToggle(LED2_GPIO_PORT,LED2_PIN) 0003b9: line 62 define LED2_OFF digitalHi(LED2_GPIO_PORT,LED2_PIN) 0003e7: line 63 define LED2_ON digitalLo(LED2_GPIO_PORT,LED2_PIN) 000414: line 65 define LED3_TOGGLE digitalToggle(LED3_GPIO_PORT,LED3_PIN) 000449: line 66 define LED3_OFF digitalHi(LED3_GPIO_PORT,LED3_PIN) 000477: line 67 define LED3_ON digitalLo(LED3_GPIO_PORT,LED3_PIN) 0004a4: line 69 define LED4_TOGGLE digitalToggle(LED4_GPIO_PORT,LED4_PIN) 0004d9: line 70 define LED4_OFF digitalHi(LED4_GPIO_PORT,LED4_PIN) 000507: line 71 define LED4_ON digitalLo(LED4_GPIO_PORT,LED4_PIN) 000534: line 77 define LED_RED LED1_ON; LED2_OFF LED3_OFF 000559: line 83 define LED_GREEN LED1_OFF; LED2_ON LED3_OFF 000580: line 89 define LED_BLUE LED1_OFF; LED2_OFF LED3_ON 0005a6: line 96 define LED_YELLOW LED1_ON; LED2_ON LED3_OFF 0005cd: line 101 define LED_PURPLE LED1_ON; LED2_OFF LED3_ON 0005f4: line 107 define LED_CYAN LED1_OFF; LED2_ON LED3_ON 000619: line 113 define LED_WHITE LED1_ON; LED2_ON LED3_ON 00063e: line 119 define LED_RGBOFF LED1_OFF; LED2_OFF LED3_OFF 000667: end include 000668: end of translation unit ** Section #333 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 132 bytes 000000: Header: length 128 (not including this field) version 3 prologue length 116 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\User\" : 2e 2e 5c 2e 2e 5c 55 73 65 72 5c 00 000027: directory "..\..\Libraries\CMSIS\Device\ST\STM32F7xx\Include\": 2e 2e 5c 2e 2e 5c 4c 69 62 72 61 72 69 65 73 5c 43 4d 53 49 53 5c 44 65 76 69 63 65 5c 53 54 5c 53 54 4d 33 32 46 37 78 78 5c 49 6e 63 6c 75 64 65 5c 00 00005a: directory "" : 00 00005b: file "./led/bsp_led.h": dir 1 time 0x0 length 0: 2e 2f 6c 65 64 2f 62 73 70 5f 6c 65 64 2e 68 00 01 00 00 00006e: file "stm32f7xx.h": dir 2 time 0x0 length 0: 73 74 6d 33 32 66 37 78 78 2e 68 00 02 00 00 00007d: file "" : 00 00007e: DW_LNS_negate_stmt : 06 00007f: DW_LNS_negate_stmt : 06 000080: DW_LNS_negate_stmt : 06 000081: DW_LNE_end sequence : 00 01 01 00000000: ..\..\User\./led/bsp_led.h:1.0 [ ** Section #334 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 244 bytes 000000: Header: size 0xf0 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\User\./led/bsp_led.h 000027: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 00006e: DW_AT_language DW_LANG_C89 000070: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 0000e7: DW_AT_macro_info 0x0 0000eb: DW_AT_stmt_list 0x0 0000ef: 0 null 0000f0: 0 padding 0000f1: 0 padding 0000f2: 0 padding 0000f3: 0 padding ** Section #438 '.rel.debug_info' (SHT_REL) Size : 24 bytes (alignment 4) Symbol table #343 '.symtab' 3 relocations applied to section #334 '.debug_info' ** Section #335 '__ARM_grp.bsp_led.c.2_ce1000_8TrENnCvU$7_700000' (SHT_GROUP) Size : 16 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #336 '.debug_macinfo' (SHT_PROGBITS) [SHF_GROUP] Size : 12 bytes 000000: include at line 0 - file 1 000003: include at line 18 - file 2 000006: end include 000007: end include 000008: end of translation unit ** Section #337 '.debug_line' (SHT_PROGBITS) [SHF_GROUP] Size : 92 bytes 000000: Header: length 88 (not including this field) version 3 prologue length 78 minimum instruction length 1 default is_stmt 0 line base 0 line range 6 opcode base 13 opcode args 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1 00001b: directory "..\..\User\" : 2e 2e 5c 2e 2e 5c 55 73 65 72 5c 00 000027: directory "" : 00 000028: file "..\..\User\led\bsp_led.c": dir 0 time 0x0 length 0: 2e 2e 5c 2e 2e 5c 55 73 65 72 5c 6c 65 64 5c 62 73 70 5f 6c 65 64 2e 63 00 00 00 00 000044: file "./led/bsp_led.h": dir 1 time 0x0 length 0: 2e 2f 6c 65 64 2f 62 73 70 5f 6c 65 64 2e 68 00 01 00 00 000057: file "" : 00 000058: DW_LNS_negate_stmt : 06 000059: DW_LNE_end sequence : 00 01 01 00000000: ..\..\User\led\bsp_led.c:1.0 [ ** Section #338 '.debug_info' (SHT_PROGBITS) [SHF_GROUP] Size : 248 bytes 000000: Header: size 0xf4 bytes, dwarf version 3, abbrevp __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000, address size 4 00000b: 10 = 0x11 (DW_TAG_compile_unit) 00000c: DW_AT_name ..\..\User\led\bsp_led.c 000025: DW_AT_producer Component: ARM Compiler 5.06 update 3 (build 300) Tool: ArmCC [4d35f0] 00006c: DW_AT_language DW_LANG_C89 00006e: DW_AT_comp_dir H:\Git_Project\f767_code\1-HAL搴撲緥绋 - 鍓湰\5-GPIO杈撳嚭鈥斾娇鐢ㄥ浐浠跺簱鐐逛寒LED鐏-MDK\Project\RVMDK锛坲v5锛 0000e5: DW_AT_macro_info 0x0 0000e9: DW_AT_stmt_list 0x0 0000ed: 116 = 0x35 (DW_TAG_volatile_type) 0000ee: DW_AT_type indirect DW_FORM_ref_addr 0x16d+__ARM_grp..debug_info$stdint.h$.2_4H1000_rQLou6Y$5Wb_300000 0000f3: 0 null 0000f4: 0 padding 0000f5: 0 padding 0000f6: 0 padding 0000f7: 0 padding ** Section #439 '.rel.debug_info' (SHT_REL) Size : 32 bytes (alignment 4) Symbol table #343 '.symtab' 4 relocations applied to section #338 '.debug_info' ** Section #339 '__ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000' (SHT_GROUP) Size : 8 bytes (alignment 4) Symbol table #343 '.symtab' ** Section #340 '.debug_abbrev' (SHT_PROGBITS) [SHF_GROUP] Size : 1444 bytes 00000000 1: no children: DW_TAG_subrange_type 000003 DW_AT_upper_bound DW_FORM_udata 00000007 2: no children: DW_TAG_subrange_type 0000000c 3: children: DW_TAG_array_type 00000f DW_AT_sibling DW_FORM_ref_udata 000011 DW_AT_type DW_FORM_indirect 00000015 4: no children: DW_TAG_base_type 000018 DW_AT_byte_size DW_FORM_data1 00001a DW_AT_encoding DW_FORM_data1 00001c DW_AT_name DW_FORM_string 00000020 5: children: DW_TAG_compile_unit 000023 DW_AT_name DW_FORM_string 000025 DW_AT_producer DW_FORM_string 000027 DW_AT_language DW_FORM_data2 000029 DW_AT_comp_dir DW_FORM_string 00002b DW_AT_low_pc DW_FORM_addr 00002d DW_AT_high_pc DW_FORM_addr 00002f DW_AT_stmt_list DW_FORM_data4 00000033 6: children: DW_TAG_compile_unit 000036 DW_AT_name DW_FORM_string 000038 DW_AT_producer DW_FORM_string 00003a DW_AT_language DW_FORM_data2 00003c DW_AT_comp_dir DW_FORM_string 00003e DW_AT_low_pc DW_FORM_addr 000040 DW_AT_high_pc DW_FORM_addr 00000044 7: children: DW_TAG_compile_unit 000047 DW_AT_name DW_FORM_string 000049 DW_AT_producer DW_FORM_string 00004b DW_AT_language DW_FORM_data2 00004d DW_AT_comp_dir DW_FORM_string 00004f DW_AT_stmt_list DW_FORM_data4 00000053 8: children: DW_TAG_compile_unit 000056 DW_AT_name DW_FORM_string 000058 DW_AT_producer DW_FORM_string 00005a DW_AT_language DW_FORM_data2 00005c DW_AT_comp_dir DW_FORM_string 00000060 9: children: DW_TAG_compile_unit 000063 DW_AT_name DW_FORM_string 000065 DW_AT_producer DW_FORM_string 000067 DW_AT_language DW_FORM_data2 000069 DW_AT_comp_dir DW_FORM_string 00006b DW_AT_macro_info DW_FORM_data4 00006d DW_AT_low_pc DW_FORM_addr 00006f DW_AT_high_pc DW_FORM_addr 000071 DW_AT_stmt_list DW_FORM_data4 00000075 10: children: DW_TAG_compile_unit 000078 DW_AT_name DW_FORM_string 00007a DW_AT_producer DW_FORM_string 00007c DW_AT_language DW_FORM_data2 00007e DW_AT_comp_dir DW_FORM_string 000080 DW_AT_macro_info DW_FORM_data4 000082 DW_AT_stmt_list DW_FORM_data4 00000086 11: children: DW_TAG_compile_unit 000089 DW_AT_name DW_FORM_string 00008b DW_AT_producer DW_FORM_string 00008d DW_AT_language DW_FORM_data2 00008f DW_AT_low_pc DW_FORM_addr 000091 DW_AT_high_pc DW_FORM_addr 000093 DW_AT_stmt_list DW_FORM_data4 00000097 12: children: DW_TAG_compile_unit 00009a DW_AT_name DW_FORM_string 00009c DW_AT_producer DW_FORM_string 00009e DW_AT_language DW_FORM_data2 0000a0 DW_AT_low_pc DW_FORM_addr 0000a2 DW_AT_high_pc DW_FORM_addr 000000a6 13: children: DW_TAG_compile_unit 0000a9 DW_AT_name DW_FORM_string 0000ab DW_AT_producer DW_FORM_string 0000ad DW_AT_language DW_FORM_data2 0000af DW_AT_stmt_list DW_FORM_data4 000000b3 14: children: DW_TAG_compile_unit 0000b6 DW_AT_name DW_FORM_string 0000b8 DW_AT_producer DW_FORM_string 0000ba DW_AT_language DW_FORM_data2 000000be 15: children: DW_TAG_compile_unit 0000c1 DW_AT_name DW_FORM_string 0000c3 DW_AT_producer DW_FORM_string 0000c5 DW_AT_language DW_FORM_data2 0000c7 DW_AT_macro_info DW_FORM_data4 0000c9 DW_AT_low_pc DW_FORM_addr 0000cb DW_AT_high_pc DW_FORM_addr 0000cd DW_AT_stmt_list DW_FORM_data4 000000d1 16: children: DW_TAG_compile_unit 0000d4 DW_AT_name DW_FORM_string 0000d6 DW_AT_producer DW_FORM_string 0000d8 DW_AT_language DW_FORM_data2 0000da DW_AT_macro_info DW_FORM_data4 0000dc DW_AT_stmt_list DW_FORM_data4 000000e0 17: no children: DW_TAG_const_type 0000e3 DW_AT_type DW_FORM_indirect 000000e7 18: children: DW_TAG_enumeration_type 0000ea DW_AT_sibling DW_FORM_ref_udata 0000ec DW_AT_name DW_FORM_string 0000ee DW_AT_byte_size DW_FORM_data1 000000f2 19: children: DW_TAG_enumeration_type 0000f5 DW_AT_sibling DW_FORM_ref_udata 0000f7 DW_AT_byte_size DW_FORM_data1 000000fb 20: no children: DW_TAG_enumerator 0000fe DW_AT_name DW_FORM_string 000100 DW_AT_const_value DW_FORM_indirect 00000104 21: no children: DW_TAG_enumerator 000107 DW_AT_name DW_FORM_string 000109 DW_AT_const_value DW_FORM_sdata 0000010d 22: children: DW_TAG_lexical_block 000110 DW_AT_sibling DW_FORM_ref_udata 000112 DW_AT_low_pc DW_FORM_addr 000114 DW_AT_high_pc DW_FORM_addr 00000118 23: no children: DW_TAG_lexical_block 00011b DW_AT_low_pc DW_FORM_addr 00011d DW_AT_high_pc DW_FORM_addr 00000121 24: children: DW_TAG_lexical_block 000124 DW_AT_sibling DW_FORM_ref_udata 00000128 25: no children: DW_TAG_lexical_block 0000012d 26: children: DW_TAG_lexical_block 000130 DW_AT_sibling DW_FORM_ref_udata 000132 DW_AT_low_pc DW_FORM_addr 000134 DW_AT_high_pc DW_FORM_addr 000136 DW_AT_abstract_origin DW_FORM_ref_addr 0000013a 27: no children: DW_TAG_lexical_block 00013d DW_AT_low_pc DW_FORM_addr 00013f DW_AT_high_pc DW_FORM_addr 000141 DW_AT_abstract_origin DW_FORM_ref_addr 00000145 28: children: DW_TAG_lexical_block 000148 DW_AT_sibling DW_FORM_ref_udata 00014a DW_AT_abstract_origin DW_FORM_ref_addr 0000014e 29: no children: DW_TAG_lexical_block 000151 DW_AT_abstract_origin DW_FORM_ref_addr 00000155 30: no children: DW_TAG_member 000158 DW_AT_name DW_FORM_string 00015a DW_AT_type DW_FORM_indirect 00015c DW_AT_data_member_location DW_FORM_block 00000160 31: no children: DW_TAG_member 000163 DW_AT_name DW_FORM_string 000165 DW_AT_type DW_FORM_indirect 00000169 32: no children: DW_TAG_member 00016c DW_AT_name DW_FORM_string 00016e DW_AT_type DW_FORM_indirect 000170 DW_AT_data_member_location DW_FORM_block 000172 DW_AT_artificial DW_FORM_flag 00000176 33: no children: DW_TAG_member 000179 DW_AT_name DW_FORM_string 00017b DW_AT_type DW_FORM_indirect 00017d DW_AT_data_member_location DW_FORM_block 00017f DW_AT_byte_size DW_FORM_data1 000181 DW_AT_bit_size DW_FORM_data1 000183 DW_AT_bit_offset DW_FORM_data1 00000187 34: no children: DW_TAG_pointer_type 00018a DW_AT_type DW_FORM_indirect 0000018e 35: no children: DW_TAG_restrict_type 000191 DW_AT_type DW_FORM_indirect 00000195 36: no children: DW_TAG_formal_parameter 000198 DW_AT_type DW_FORM_indirect 00019a DW_AT_name DW_FORM_string 0000019e 37: no children: DW_TAG_formal_parameter 0001a1 DW_AT_type DW_FORM_indirect 000001a5 38: no children: DW_TAG_formal_parameter 0001a8 DW_AT_type DW_FORM_indirect 0001aa DW_AT_location DW_FORM_block 000001ae 39: no children: DW_TAG_formal_parameter 0001b1 DW_AT_type DW_FORM_indirect 0001b3 DW_AT_location DW_FORM_data4 000001b7 40: no children: DW_TAG_reference_type 0001ba DW_AT_type DW_FORM_indirect 000001be 41: children: DW_TAG_structure_type 0001c1 DW_AT_sibling DW_FORM_ref_udata 0001c3 DW_AT_name DW_FORM_string 0001c5 DW_AT_byte_size DW_FORM_udata 000001c9 42: children: DW_TAG_structure_type 0001cc DW_AT_sibling DW_FORM_ref_udata 0001ce DW_AT_byte_size DW_FORM_udata 000001d2 43: children: DW_TAG_structure_type 0001d5 DW_AT_sibling DW_FORM_ref_udata 0001d7 DW_AT_name DW_FORM_string 000001db 44: children: DW_TAG_structure_type 000001e0 45: no children: DW_TAG_structure_type 0001e3 DW_AT_name DW_FORM_string 000001e7 46: no children: DW_TAG_structure_type 000001ec 47: children: DW_TAG_structure_type 0001ef DW_AT_sibling DW_FORM_ref_udata 0001f1 DW_AT_artificial DW_FORM_flag 0001f3 DW_AT_name DW_FORM_string 0001f5 DW_AT_byte_size DW_FORM_udata 000001f9 48: children: DW_TAG_structure_type 0001fc DW_AT_sibling DW_FORM_ref_udata 0001fe DW_AT_artificial DW_FORM_flag 000200 DW_AT_byte_size DW_FORM_udata 00000204 49: children: DW_TAG_structure_type 000207 DW_AT_sibling DW_FORM_ref_udata 000209 DW_AT_artificial DW_FORM_flag 00020b DW_AT_name DW_FORM_string 0000020f 50: children: DW_TAG_structure_type 000212 DW_AT_artificial DW_FORM_flag 00000216 51: no children: DW_TAG_structure_type 000219 DW_AT_artificial DW_FORM_flag 00021b DW_AT_name DW_FORM_string 0000021f 52: no children: DW_TAG_structure_type 000222 DW_AT_artificial DW_FORM_flag 00000226 53: children: DW_TAG_subprogram 000229 DW_AT_sibling DW_FORM_ref_udata 00022b DW_AT_decl_file DW_FORM_udata 00022d DW_AT_decl_line DW_FORM_udata 00022f DW_AT_decl_column DW_FORM_udata 000231 DW_AT_name DW_FORM_string 000233 DW_AT_external DW_FORM_flag 000235 DW_AT_type DW_FORM_indirect 000237 DW_AT_low_pc DW_FORM_addr 000239 DW_AT_high_pc DW_FORM_addr 0000023d 54: children: DW_TAG_subprogram 000240 DW_AT_sibling DW_FORM_ref_udata 000242 DW_AT_decl_file DW_FORM_udata 000244 DW_AT_decl_line DW_FORM_udata 000246 DW_AT_decl_column DW_FORM_udata 000248 DW_AT_name DW_FORM_string 00024a DW_AT_external DW_FORM_flag 00024c DW_AT_low_pc DW_FORM_addr 00024e DW_AT_high_pc DW_FORM_addr 00000252 55: children: DW_TAG_subprogram 000255 DW_AT_sibling DW_FORM_ref_udata 000257 DW_AT_decl_file DW_FORM_udata 000259 DW_AT_decl_line DW_FORM_udata 00025b DW_AT_decl_column DW_FORM_udata 00025d DW_AT_specification DW_FORM_indirect 00025f DW_AT_low_pc DW_FORM_addr 000261 DW_AT_high_pc DW_FORM_addr 00000265 56: children: DW_TAG_subprogram 000268 DW_AT_sibling DW_FORM_ref_udata 00026a DW_AT_decl_file DW_FORM_udata 00026c DW_AT_decl_line DW_FORM_udata 00026e DW_AT_decl_column DW_FORM_udata 000270 DW_AT_name DW_FORM_string 000272 DW_AT_external DW_FORM_flag 000274 DW_AT_type DW_FORM_indirect 000276 DW_AT_inline DW_FORM_udata 0000027a 57: children: DW_TAG_subprogram 00027d DW_AT_sibling DW_FORM_ref_udata 00027f DW_AT_decl_file DW_FORM_udata 000281 DW_AT_decl_line DW_FORM_udata 000283 DW_AT_decl_column DW_FORM_udata 000285 DW_AT_name DW_FORM_string 000287 DW_AT_external DW_FORM_flag 000289 DW_AT_inline DW_FORM_udata 0000028d 58: children: DW_TAG_subprogram 000290 DW_AT_sibling DW_FORM_ref_udata 000292 DW_AT_decl_file DW_FORM_udata 000294 DW_AT_decl_line DW_FORM_udata 000296 DW_AT_decl_column DW_FORM_udata 000298 DW_AT_specification DW_FORM_indirect 00029a DW_AT_inline DW_FORM_udata 0000029e 59: children: DW_TAG_subprogram 0002a1 DW_AT_sibling DW_FORM_ref_udata 0002a3 DW_AT_decl_file DW_FORM_udata 0002a5 DW_AT_decl_line DW_FORM_udata 0002a7 DW_AT_decl_column DW_FORM_udata 0002a9 DW_AT_name DW_FORM_string 0002ab DW_AT_external DW_FORM_flag 0002ad DW_AT_type DW_FORM_indirect 000002b1 60: children: DW_TAG_subprogram 0002b4 DW_AT_sibling DW_FORM_ref_udata 0002b6 DW_AT_decl_file DW_FORM_udata 0002b8 DW_AT_decl_line DW_FORM_udata 0002ba DW_AT_decl_column DW_FORM_udata 0002bc DW_AT_name DW_FORM_string 0002be DW_AT_external DW_FORM_flag 000002c2 61: children: DW_TAG_subprogram 0002c5 DW_AT_sibling DW_FORM_ref_udata 0002c7 DW_AT_decl_file DW_FORM_udata 0002c9 DW_AT_decl_line DW_FORM_udata 0002cb DW_AT_decl_column DW_FORM_udata 0002cd DW_AT_specification DW_FORM_indirect 000002d1 62: children: DW_TAG_subprogram 0002d4 DW_AT_sibling DW_FORM_ref_udata 0002d6 DW_AT_decl_file DW_FORM_udata 0002d8 DW_AT_decl_line DW_FORM_udata 0002da DW_AT_decl_column DW_FORM_udata 0002dc DW_AT_name DW_FORM_string 0002de DW_AT_external DW_FORM_flag 0002e0 DW_AT_type DW_FORM_indirect 0002e2 DW_AT_low_pc DW_FORM_addr 0002e4 DW_AT_high_pc DW_FORM_addr 0002e6 DW_AT_frame_base DW_FORM_data4 000002ea 63: children: DW_TAG_subprogram 0002ed DW_AT_sibling DW_FORM_ref_udata 0002ef DW_AT_decl_file DW_FORM_udata 0002f1 DW_AT_decl_line DW_FORM_udata 0002f3 DW_AT_decl_column DW_FORM_udata 0002f5 DW_AT_name DW_FORM_string 0002f7 DW_AT_external DW_FORM_flag 0002f9 DW_AT_low_pc DW_FORM_addr 0002fb DW_AT_high_pc DW_FORM_addr 0002fd DW_AT_frame_base DW_FORM_data4 00000301 64: children: DW_TAG_subprogram 000304 DW_AT_sibling DW_FORM_ref_udata 000306 DW_AT_decl_file DW_FORM_udata 000308 DW_AT_decl_line DW_FORM_udata 00030a DW_AT_decl_column DW_FORM_udata 00030c DW_AT_specification DW_FORM_indirect 00030e DW_AT_low_pc DW_FORM_addr 000310 DW_AT_high_pc DW_FORM_addr 000312 DW_AT_frame_base DW_FORM_data4 00000316 65: children: DW_TAG_subprogram 000319 DW_AT_sibling DW_FORM_ref_udata 00031b DW_AT_decl_file DW_FORM_udata 00031d DW_AT_decl_line DW_FORM_udata 00031f DW_AT_decl_column DW_FORM_udata 000321 DW_AT_name DW_FORM_string 000323 DW_AT_external DW_FORM_flag 000325 DW_AT_type DW_FORM_indirect 000327 DW_AT_low_pc DW_FORM_addr 000329 DW_AT_high_pc DW_FORM_addr 00032b DW_AT_frame_base DW_FORM_block1 0000032f 66: children: DW_TAG_subprogram 000332 DW_AT_sibling DW_FORM_ref_udata 000334 DW_AT_decl_file DW_FORM_udata 000336 DW_AT_decl_line DW_FORM_udata 000338 DW_AT_decl_column DW_FORM_udata 00033a DW_AT_name DW_FORM_string 00033c DW_AT_external DW_FORM_flag 00033e DW_AT_low_pc DW_FORM_addr 000340 DW_AT_high_pc DW_FORM_addr 000342 DW_AT_frame_base DW_FORM_block1 00000346 67: children: DW_TAG_subprogram 000349 DW_AT_sibling DW_FORM_ref_udata 00034b DW_AT_decl_file DW_FORM_udata 00034d DW_AT_decl_line DW_FORM_udata 00034f DW_AT_decl_column DW_FORM_udata 000351 DW_AT_specification DW_FORM_indirect 000353 DW_AT_low_pc DW_FORM_addr 000355 DW_AT_high_pc DW_FORM_addr 000357 DW_AT_frame_base DW_FORM_block1 0000035b 68: children: DW_TAG_inlined_subroutine 00035e DW_AT_sibling DW_FORM_ref_udata 000360 DW_AT_abstract_origin DW_FORM_ref_addr 000362 DW_AT_low_pc DW_FORM_addr 000364 DW_AT_high_pc DW_FORM_addr 00000368 69: children: DW_TAG_inlined_subroutine 00036b DW_AT_sibling DW_FORM_ref_udata 00036d DW_AT_abstract_origin DW_FORM_ref_addr 00000371 70: children: DW_TAG_inlined_subroutine 000374 DW_AT_sibling DW_FORM_ref_udata 000376 DW_AT_abstract_origin DW_FORM_ref_addr 000378 DW_AT_low_pc DW_FORM_addr 00037a DW_AT_high_pc DW_FORM_addr 00037c DW_AT_call_file DW_FORM_udata 00037e DW_AT_call_line DW_FORM_udata 000380 DW_AT_call_column DW_FORM_udata 00000384 71: children: DW_TAG_inlined_subroutine 000387 DW_AT_sibling DW_FORM_ref_udata 000389 DW_AT_abstract_origin DW_FORM_ref_addr 00038b DW_AT_call_file DW_FORM_udata 00038d DW_AT_call_line DW_FORM_udata 00038f DW_AT_call_column DW_FORM_udata 00000393 72: children: DW_TAG_subprogram 000396 DW_AT_sibling DW_FORM_ref_udata 000398 DW_AT_abstract_origin DW_FORM_ref_addr 00039a DW_AT_low_pc DW_FORM_addr 00039c DW_AT_high_pc DW_FORM_addr 000003a0 73: children: DW_TAG_subprogram 0003a3 DW_AT_sibling DW_FORM_ref_udata 0003a5 DW_AT_abstract_origin DW_FORM_ref_addr 0003a7 DW_AT_low_pc DW_FORM_addr 0003a9 DW_AT_high_pc DW_FORM_addr 0003ab DW_AT_frame_base DW_FORM_data4 000003af 74: children: DW_TAG_subprogram 0003b2 DW_AT_sibling DW_FORM_ref_udata 0003b4 DW_AT_abstract_origin DW_FORM_ref_addr 0003b6 DW_AT_low_pc DW_FORM_addr 0003b8 DW_AT_high_pc DW_FORM_addr 0003ba DW_AT_frame_base DW_FORM_block1 000003be 75: children: DW_TAG_subprogram 0003c1 DW_AT_sibling DW_FORM_ref_udata 0003c3 DW_AT_abstract_origin DW_FORM_ref_addr 000003c7 76: children: DW_TAG_subprogram 0003ca DW_AT_sibling DW_FORM_ref_udata 0003cc DW_AT_name DW_FORM_string 0003ce DW_AT_declaration DW_FORM_flag 0003d0 DW_AT_artificial DW_FORM_flag 0003d2 DW_AT_type DW_FORM_indirect 0003d4 DW_AT_external DW_FORM_flag 000003d8 77: children: DW_TAG_subprogram 0003db DW_AT_sibling DW_FORM_ref_udata 0003dd DW_AT_name DW_FORM_string 0003df DW_AT_declaration DW_FORM_flag 0003e1 DW_AT_artificial DW_FORM_flag 0003e3 DW_AT_external DW_FORM_flag 000003e7 78: children: DW_TAG_subroutine_type 0003ea DW_AT_sibling DW_FORM_ref_udata 0003ec DW_AT_type DW_FORM_indirect 000003f0 79: children: DW_TAG_subroutine_type 0003f3 DW_AT_sibling DW_FORM_ref_udata 000003f7 80: no children: DW_TAG_typedef 0003fa DW_AT_name DW_FORM_string 0003fc DW_AT_type DW_FORM_indirect 0003fe DW_AT_decl_file DW_FORM_udata 000400 DW_AT_decl_line DW_FORM_udata 000402 DW_AT_decl_column DW_FORM_udata 00000406 81: no children: DW_TAG_typedef 000409 DW_AT_name DW_FORM_string 00040b DW_AT_type DW_FORM_indirect 00040d DW_AT_artificial DW_FORM_flag 00000411 82: children: DW_TAG_union_type 000414 DW_AT_sibling DW_FORM_ref_udata 000416 DW_AT_name DW_FORM_string 000418 DW_AT_byte_size DW_FORM_udata 0000041c 83: children: DW_TAG_union_type 00041f DW_AT_sibling DW_FORM_ref_udata 000421 DW_AT_byte_size DW_FORM_udata 00000425 84: children: DW_TAG_union_type 000428 DW_AT_sibling DW_FORM_ref_udata 00042a DW_AT_name DW_FORM_string 0000042e 85: no children: DW_TAG_union_type 000431 DW_AT_name DW_FORM_string 00000435 86: no children: DW_TAG_unspecified_parameters 0000043a 87: no children: DW_TAG_unspecified_parameters 00043d DW_AT_abstract_origin DW_FORM_ref_addr 00000441 88: no children: DW_TAG_variable 000444 DW_AT_name DW_FORM_string 000446 DW_AT_type DW_FORM_indirect 000448 DW_AT_location DW_FORM_block 00044a DW_AT_start_scope DW_FORM_udata 0000044e 89: no children: DW_TAG_variable 000451 DW_AT_name DW_FORM_string 000453 DW_AT_type DW_FORM_indirect 000455 DW_AT_location DW_FORM_block 00000459 90: no children: DW_TAG_variable 00045c DW_AT_name DW_FORM_string 00045e DW_AT_type DW_FORM_indirect 000460 DW_AT_location DW_FORM_data4 00000464 91: no children: DW_TAG_variable 000467 DW_AT_name DW_FORM_string 000469 DW_AT_type DW_FORM_indirect 00046b DW_AT_start_scope DW_FORM_udata 0000046f 92: no children: DW_TAG_variable 000472 DW_AT_name DW_FORM_string 000474 DW_AT_type DW_FORM_indirect 00000478 93: no children: DW_TAG_variable 00047b DW_AT_name DW_FORM_string 00047d DW_AT_type DW_FORM_indirect 00047f DW_AT_location DW_FORM_block 000481 DW_AT_artificial DW_FORM_flag 00000485 94: no children: DW_TAG_variable 000488 DW_AT_name DW_FORM_string 00048a DW_AT_type DW_FORM_indirect 00048c DW_AT_location DW_FORM_block 00048e DW_AT_start_scope DW_FORM_udata 000490 DW_AT_artificial DW_FORM_flag 00000494 95: no children: DW_TAG_variable 000497 DW_AT_name DW_FORM_string 000499 DW_AT_type DW_FORM_indirect 00049b DW_AT_location DW_FORM_data4 00049d DW_AT_artificial DW_FORM_flag 000004a1 96: no children: DW_TAG_variable 0004a4 DW_AT_name DW_FORM_string 0004a6 DW_AT_type DW_FORM_indirect 0004a8 DW_AT_start_scope DW_FORM_udata 0004aa DW_AT_artificial DW_FORM_flag 000004ae 97: no children: DW_TAG_variable 0004b1 DW_AT_name DW_FORM_string 0004b3 DW_AT_type DW_FORM_indirect 0004b5 DW_AT_artificial DW_FORM_flag 000004b9 98: no children: DW_TAG_variable 0004bc DW_AT_abstract_origin DW_FORM_ref_addr 0004be DW_AT_location DW_FORM_block 0004c0 DW_AT_start_scope DW_FORM_udata 000004c4 99: no children: DW_TAG_variable 0004c7 DW_AT_abstract_origin DW_FORM_ref_addr 0004c9 DW_AT_location DW_FORM_data4 000004cd 100: no children: DW_TAG_variable 0004d0 DW_AT_abstract_origin DW_FORM_ref_addr 0004d2 DW_AT_start_scope DW_FORM_udata 000004d6 101: no children: DW_TAG_variable 0004d9 DW_AT_abstract_origin DW_FORM_ref_addr 000004dd 102: no children: DW_TAG_formal_parameter 0004e0 DW_AT_abstract_origin DW_FORM_ref_addr 000004e4 103: no children: DW_TAG_formal_parameter 0004e7 DW_AT_abstract_origin DW_FORM_ref_addr 0004e9 DW_AT_const_value DW_FORM_indirect 000004ed 104: no children: DW_TAG_formal_parameter 0004f0 DW_AT_name DW_FORM_string 0004f2 DW_AT_type DW_FORM_indirect 0004f4 DW_AT_location DW_FORM_block 000004f8 105: no children: DW_TAG_formal_parameter 0004fb DW_AT_name DW_FORM_string 0004fd DW_AT_type DW_FORM_indirect 0004ff DW_AT_location DW_FORM_data4 00000503 106: no children: DW_TAG_formal_parameter 000506 DW_AT_name DW_FORM_string 000508 DW_AT_type DW_FORM_indirect 0000050c 107: no children: DW_TAG_formal_parameter 00050f DW_AT_name DW_FORM_string 000511 DW_AT_type DW_FORM_indirect 000513 DW_AT_location DW_FORM_block 000515 DW_AT_artificial DW_FORM_flag 00000519 108: no children: DW_TAG_formal_parameter 00051c DW_AT_name DW_FORM_string 00051e DW_AT_type DW_FORM_indirect 000520 DW_AT_location DW_FORM_block 000522 DW_AT_start_scope DW_FORM_udata 000524 DW_AT_artificial DW_FORM_flag 00000528 109: no children: DW_TAG_formal_parameter 00052b DW_AT_name DW_FORM_string 00052d DW_AT_type DW_FORM_indirect 00052f DW_AT_location DW_FORM_data4 000531 DW_AT_artificial DW_FORM_flag 00000535 110: no children: DW_TAG_formal_parameter 000538 DW_AT_abstract_origin DW_FORM_ref_addr 00053a DW_AT_location DW_FORM_block 0000053e 111: no children: DW_TAG_formal_parameter 000541 DW_AT_abstract_origin DW_FORM_ref_addr 000543 DW_AT_location DW_FORM_data4 00000547 112: no children: DW_TAG_variable 00054a DW_AT_name DW_FORM_string 00054c DW_AT_type DW_FORM_indirect 00054e DW_AT_location DW_FORM_block 000550 DW_AT_external DW_FORM_flag 00000554 113: no children: DW_TAG_variable 000557 DW_AT_name DW_FORM_string 000559 DW_AT_type DW_FORM_indirect 00055b DW_AT_external DW_FORM_flag 00055d DW_AT_declaration DW_FORM_flag 00000561 114: no children: DW_TAG_variable 000564 DW_AT_name DW_FORM_string 000566 DW_AT_type DW_FORM_indirect 000568 DW_AT_const_value DW_FORM_indirect 00056a DW_AT_start_scope DW_FORM_udata 0000056e 115: no children: DW_TAG_variable 000571 DW_AT_name DW_FORM_string 000573 DW_AT_type DW_FORM_indirect 000575 DW_AT_const_value DW_FORM_indirect 00000579 116: no children: DW_TAG_volatile_type 00057c DW_AT_type DW_FORM_indirect 00000580 117: no children: DW_TAG_unspecified_type 000583 DW_AT_name DW_FORM_string 00000587 118: no children: DW_TAG_imported_unit 00058a DW_AT_import DW_FORM_ref_addr 0000058e 119: children: DW_TAG_compile_unit 000591 DW_AT_producer DW_FORM_string 000593 DW_AT_language DW_FORM_data2 00000597 120: children: DW_TAG_partial_unit 00059a DW_AT_producer DW_FORM_string 00059c DW_AT_language DW_FORM_data2 ** Section #341 '.arm_vfe_header' (SHT_PROGBITS) Size : 4 bytes (alignment 4) ** Section #342 '.comment' (SHT_PROGBITS) Size : 1284 bytes ** Section #343 '.symtab' (SHT_SYMTAB) Size : 5808 bytes (alignment 4) String table #441 '.strtab' Last local symbol no. 37 ** Section #440 '.shstrtab' (SHT_STRTAB) Size : 4849 bytes ** Section #441 '.strtab' (SHT_STRTAB) Size : 22503 bytes ** Section #442 '.ARM.attributes' (SHT_ARM_ATTRIBUTES) Size : 128 bytes