// File: STM32H7x3.dbgconf // Version: 1.0.0 // Note: refer to STM32H7x3 reference manual (RM0433) // refer to STM32H753xI STM32H743xI datasheets // <<< Use Configuration Wizard in Context Menu >>> // DBGMCU configuration register (DBGMCU_CR) // TRGOEN External trigger output enable // DBGSTBY_D3 Allow debug in D3 Standby mode // DBGSTOP_D3 Allow debug in D3 Stop mode // DBGSTBY_D1 Allow D1 domain debug in Standby mode // DBGSTOP_D1 Allow D1 domain debug in Stop mode // DBGSLEEP_D1 Allow D1 domain debug in Sleep mode // DbgMCU_CR = 0x00000000; // DBGMCU D1APB1 peripheral freeze register (DBGMCU_D1APB1FZ1) // Reserved bits must be kept at reset value // WWDG1 WWDG1 stop in debug // DbgMCU_D1APB1_Fz = 0x00000000; // DBGMCU D2APB1L peripheral freeze register (DBGMCU_D2APB1LFZ1) // Reserved bits must be kept at reset value // I2C3 I2C3 SMBUS timeout stop in debug // I2C2 I2C2 SMBUS timeout stop in debug // I2C1 I2C1 SMBUS timeout stop in debug // LPTIM1 LPTIM1 stop in debug // TIM14 TIM14 stop in debug // TIM13 TIM13 stop in debug // TIM12 TIM12 stop in debug // TIM7 TIM7 stop in debug // TIM6 TIM6 stop in debug // TIM5 TIM5 stop in debug // TIM4 TIM4 stop in debug // TIM3 TIM3 stop in debug // TIM2 TIM2 stop in debug // DbgMCU_D2APB1L_Fz = 0x00000000; // DBGMCU D2APB1H peripheral freeze register (DBGMCU_D2APB1HFZ1) // Reserved bits must be kept at reset value // FDCAN FDCAN stop in debug // DbgMCU_D2APB1H_Fz = 0x00000000; // DBGMCU D2APB2 peripheral freeze register (DBGMCU_D2APB2FZ1) // Reserved bits must be kept at reset value // HRTIM HRTIM stop in debug // TIM17 TIM17 stop in debug // TIM16 TIM16 stop in debug // TIM15 TIM15 stop in debug // TIM8 TIM8 stop in debug // TIM1 TIM1 stop in debug // DbgMCU_D2APB2_Fz = 0x00000000; // DBGMCU D3APB4 peripheral freeze register (DBGMCU_D3APB4FZ1) // Reserved bits must be kept at reset value // WDGLSD2 LS watchdog for D2 stop in debug // WDGLSD1 LS watchdog for D1 stop in debug // RTC RTC stop in debug // LPTIM5 LPTIM5 stop in debug // LPTIM4 LPTIM4 stop in debug // LPTIM3 LPTIM2 stop in debug // LPTIM2 LPTIM2 stop in debug // I2C4 I2C4 SMBUS timeout stop in debug // DbgMCU_D3APB4_Fz = 0x00000000; // TPIU Pin Routing (TRACECLK fixed on Pin PE2) // TRACECLK: Pin PE2 // TRACED0 // ETM Trace Data 0 // <0x00040003=> Pin PE3 // <0x00020001=> Pin PC1 // <0x0006000D=> Pin PG13 // TRACED1 // ETM Trace Data 1 // <0x00040004=> Pin PE4 // <0x00020008=> Pin PC8 // <0x0006000E=> Pin PG14 // TRACED2 // ETM Trace Data 2 // <0x00040005=> Pin PE5 // <0x00030002=> Pin PD2 // TRACED3 // ETM Trace Data 3 // <0x00040006=> Pin PE6 // <0x0002000C=> Pin PC12 // TraceClk_Pin = 0x00040002; TraceD0_Pin = 0x00040003; TraceD1_Pin = 0x00040004; TraceD2_Pin = 0x00040005; TraceD3_Pin = 0x00040006; // <<< end of configuration section >>>