STM32H750XB_RT-THREAD/48-MDK编译过程及文件全解/SCT文件应用/1.自动分配变量到SDRAM/User/sdram/bsp_sdram.c

/**
  ******************************************************************************
  * @file    bsp_sdram.c
  * @author  fire
  * @version V1.0
  * @date    2015-xx-xx
  * @brief   sdramӦ<EFBFBD>ú<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӿ<EFBFBD>
  ******************************************************************************
  * @attention
  *
  * ʵ<EFBFBD><EFBFBD>ƽ̨:Ұ<EFBFBD><EFBFBD>  STM32 H750 <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>  
  * <EFBFBD><EFBFBD>̳    :http://www.chuxue123.com
  * <EFBFBD>Ա<EFBFBD>    :http://firestm32.taobao.com
  *
  ******************************************************************************
  */
  
#include "./sdram/bsp_sdram.h"  
//static FMC_SDRAM_CommandTypeDef Command;
SDRAM_HandleTypeDef hsdram1;
#define sdramHandle hsdram1
/**
  * @brief  <EFBFBD>ӳ<EFBFBD>һ<EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>
  * @param  <EFBFBD>ӳٵ<EFBFBD>ʱ<EFBFBD>䳤<EFBFBD><EFBFBD>
  * @retval None
  */
static void SDRAM_delay(__IO uint32_t nCount)
{
  __IO uint32_t index = 0; 
  for(index = (100000 * nCount); index != 0; index--)
  {
  }
}

/**
  * @brief  <EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SDRAM<EFBFBD><EFBFBD>IO
  * @param  <EFBFBD><EFBFBD>
  * @retval <EFBFBD><EFBFBD>
  */
static void SDRAM_GPIO_Config(void)
{		
  //ʹ<><CAB9>GPIO<49><4F>ʱ<EFBFBD><CAB1>
  RCC->AHB4ENR |= 0x1FC; 

  //<2F><><EFBFBD>ö˿<C3B6>C<EFBFBD><43>D<EFBFBD><44>E<EFBFBD><45>F<EFBFBD><46>G<EFBFBD><47>H<EFBFBD><48>I<EFBFBD><49>Ӧ<EFBFBD><D3A6><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
  GPIOC->MODER = 0xFFFFFFFE;
  GPIOC->OTYPER = 0;
  GPIOC->OSPEEDR = 0x00000003;
  GPIOC->PUPDR = 0x00000001;
  GPIOC->AFR[0] = 0x0000000C;
  
  GPIOD->MODER = 0xAFEAFFFA;
  GPIOD->OTYPER = 0;
  GPIOD->OSPEEDR = 0xF03F000F;
  GPIOD->PUPDR = 0x50150005;
  GPIOD->AFR[0] = 0x000000CC;  
  GPIOD->AFR[1] = 0xCC000CCC;

  GPIOE->MODER = 0xAAAABFFA;
  GPIOE->OTYPER = 0;
  GPIOE->OSPEEDR = 0xFFFFC00F;
  GPIOE->PUPDR = 0x55554005;
  GPIOE->AFR[0] = 0xC00000CC;  
  GPIOE->AFR[1] = 0xCCCCCCCC;
  
  GPIOF->MODER = 0xAABFFAAA;
  GPIOF->OTYPER = 0;
  GPIOF->OSPEEDR = 0xFFC00FFF;
  GPIOF->PUPDR = 0x55400555;
  GPIOF->AFR[0] = 0x00CCCCCC;
  GPIOF->AFR[1] = 0xCCCCC000;
  
  GPIOG->MODER = 0xBFFEFAEA;
  GPIOG->OTYPER = 0;
  GPIOG->OSPEEDR = 0xC0030F3F;
  GPIOG->PUPDR = 0x40010515;
  GPIOG->AFR[0] = 0x00CC0CCC;  
  GPIOG->AFR[1] = 0xC000000C;

  GPIOH->MODER = 0xAAAAAFFF;
  GPIOH->OTYPER = 0;
  GPIOH->OSPEEDR = 0xFFFFF000;
  GPIOH->PUPDR = 0x55555000;
  GPIOH->AFR[0] = 0xCC000000;  
  GPIOH->AFR[1] = 0xCCCCCCCC;  

  GPIOI->MODER = 0xFFEBAAAA;
  GPIOI->OTYPER = 0;
  GPIOI->OSPEEDR = 0x003CFFFF;
  GPIOI->PUPDR = 0x00145555;
  GPIOI->AFR[0] = 0xCCCCCCCC;  
  GPIOI->AFR[1] = 0x00000CC0;

}

/**
  * @brief  <EFBFBD><EFBFBD>SDRAMоƬ<EFBFBD><EFBFBD><EFBFBD>г<EFBFBD>ʼ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
  * @param  None. 
  * @retval None.
  */
static void SDRAM_InitSequence(void)
{


	/* Step 1 ----------------------------------------------------------------*/
	/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EEA3BA><EFBFBD><EFBFBD><EFBFBD>ṩ<EFBFBD><E1B9A9>SDRAM<41><4D>ʱ<EFBFBD><CAB1> */
  FMC_Bank5_6->SDCMR = 0x00000009;
	/* Step 2: <20><>ʱ100us */ 
	SDRAM_delay(1);
	/* Step 3 ----------------------------------------------------------------*/
	/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EEA3BA><EFBFBD><EFBFBD><EFBFBD>е<EFBFBD>bankԤ<6B><D4A4><EFBFBD><EFBFBD> */  
  FMC_Bank5_6->SDCMR = 0x0000000A;
	/* Step 4 ----------------------------------------------------------------*/
	/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Զ<EFBFBD>ˢ<EFBFBD><CBA2> */   
  FMC_Bank5_6->SDCMR = 0x000000EB;
	/* Step 5 ----------------------------------------------------------------*/
	/* <20><><EFBFBD><EFBFBD>sdram<61>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
  FMC_Bank5_6->SDCMR = 0x0004600C;
	/* Step 6 ----------------------------------------------------------------*/
  /* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ˢ<EFBFBD><CBA2><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
  FMC_Bank5_6->SDRTR |= (1855<<1);
}


/**
  * @brief  <EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><EFBFBD>SDRAM<EFBFBD><EFBFBD>FMC<EFBFBD><EFBFBD>GPIO<EFBFBD>ӿڣ<EFBFBD>
  *         <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SDRAM<EFBFBD><EFBFBD>д<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ǰ<EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
  * @param  None
  * @retval None
  */
void SDRAM_Init(void)
{

  /* <20><><EFBFBD><EFBFBD>FMC<4D>ӿ<EFBFBD><D3BF><EFBFBD><EFBFBD>ص<EFBFBD> GPIO*/
  SDRAM_GPIO_Config();
  
  //ʹ<><CAB9>HSE
  RCC->CR |= RCC_CR_HSEON;
  while(!(RCC->CR&(1<<17)));
  //ѡ<><D1A1>HSE<53><45>ΪPLLʱ<4C><CAB1>Դ
  RCC->PLLCKSELR |= (1 << 1);
  //ʹ<><CAB9>PLL2R
  RCC->PLLCKSELR |= (25 << 12);//PLL2M
  RCC->PLLCFGR |= (1 << 21); 
  RCC->PLLCFGR &= ~(3 << 6);
  RCC->PLLCFGR &= ~(1 << 5);
  RCC->PLLCFGR &= ~(1 << 4);
  RCC->PLL2DIVR |= (265 << 0);//PLL2N
  RCC->PLL2DIVR |= (2 << 9);//PLL2P
  RCC->PLL2DIVR |= (2 << 16);//PLL2Q
  RCC->PLL2DIVR |= (2 << 24);//PLL2R

  //ʹ<><CAB9>PLL2
  RCC->CR |= (1 << 26);
  while(!(RCC->CR&(1<<27)));
  RCC->D1CCIPR |= (2<<0); 
  
  (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN));
  
  FMC_Bank5_6->SDCR[FMC_SDRAM_BANK1] = 0x00003AD0;
  FMC_Bank5_6->SDCR[FMC_SDRAM_BANK2] = 0x000001E9;
  
  FMC_Bank5_6->SDTR[FMC_SDRAM_BANK1] = 0x0F1F7FFF;
  FMC_Bank5_6->SDTR[FMC_SDRAM_BANK2] = 0x01010471;
  
  __FMC_ENABLE();                      
  /* FMC SDRAM <20>豸ʱ<E8B1B8><CAB1><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC> */
  SDRAM_InitSequence(); 
  
}



/**
  * @brief  <EFBFBD>ԡ<EFBFBD><EFBFBD>֡<EFBFBD>Ϊ<EFBFBD><EFBFBD>λ<EFBFBD><EFBFBD>sdramд<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 
  * @param  pBuffer: ָ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݵ<EFBFBD>ָ<EFBFBD><EFBFBD> 
  * @param  uwWriteAddress: Ҫд<EFBFBD><EFBFBD><EFBFBD><EFBFBD>SDRAM<EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>ַ
  * @param  uwBufferSize: Ҫд<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݴ<EFBFBD>С
  * @retval None.
  */
void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBufferSize)
{
  __IO uint32_t write_pointer = (uint32_t)uwWriteAddress;

  /* <20><>ֹд<D6B9><D0B4><EFBFBD><EFBFBD> */
  //HAL_SDRAM_WriteProtection_Disable(&hsdram1);
  FMC_Bank5_6->SDCR[1] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE;
  /* <20><><EFBFBD><EFBFBD>SDRAM<41><4D>־<EFBFBD><D6BE><EFBFBD>ȴ<EFBFBD><C8B4><EFBFBD>SDRAM<41><4D><EFBFBD><EFBFBD> */ 
//  while(HAL_SDRAM_GetState(&hsdram1) != RESET)
//  {
//  }

  /* ѭ<><D1AD>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
  for (; uwBufferSize != 0; uwBufferSize--) 
  {
    /* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݵ<EFBFBD>SDRAM */
    *(uint32_t *) (SDRAM_BANK_ADDR + write_pointer) = *pBuffer++;

    /* <20><>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>*/
    write_pointer += 4;
  }
    
}

/**
  * @brief  <EFBFBD><EFBFBD>SDRAM<EFBFBD>ж<EFBFBD>ȡ<EFBFBD><EFBFBD><EFBFBD><EFBFBD> 
  * @param  pBuffer: ָ<EFBFBD><EFBFBD><EFBFBD>洢<EFBFBD><EFBFBD><EFBFBD>ݵ<EFBFBD>buffer
  * @param  ReadAddress: Ҫ<EFBFBD><EFBFBD>ȡ<EFBFBD><EFBFBD><EFBFBD>ݵĵ<EFBFBD>ʮ
  * @param  uwBufferSize: Ҫ<EFBFBD><EFBFBD>ȡ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݴ<EFBFBD>С
  * @retval None.
  */
void SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBufferSize)
{
  __IO uint32_t write_pointer = (uint32_t)uwReadAddress;
  
   
  /* <20><><EFBFBD><EFBFBD>SDRAM<41><4D>־<EFBFBD><D6BE><EFBFBD>ȴ<EFBFBD><C8B4><EFBFBD>SDRAM<41><4D><EFBFBD><EFBFBD> */  
//  while ( HAL_SDRAM_GetState(&hsdram1) != RESET)
//  {
//  }
  
  /*<2A><>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD> */
  for(; uwBufferSize != 0x00; uwBufferSize--)
  {
   *pBuffer++ = *(__IO uint32_t *)(SDRAM_BANK_ADDR + write_pointer );
    
   /* <20><>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>*/
    write_pointer += 4;
  } 
}


/**
  * @brief  <EFBFBD><EFBFBD><EFBFBD><EFBFBD>SDRAM<EFBFBD>Ƿ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 
  * @param  None
  * @retval <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1<EFBFBD><EFBFBD><EFBFBD>쳣<EFBFBD><EFBFBD><EFBFBD><EFBFBD>0
  */
uint8_t SDRAM_Test(void)
{
  /*д<><D0B4><EFBFBD><EFBFBD><EFBFBD>ݼ<EFBFBD><DDBC><EFBFBD><EFBFBD><EFBFBD>*/
  uint32_t counter=0;
  
  /* 8λ<38><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
  uint8_t ubWritedata_8b = 0, ubReaddata_8b = 0;  
  
  /* 16λ<36><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
  uint16_t uhWritedata_16b = 0, uhReaddata_16b = 0; 
  
  SDRAM_INFO("<EFBFBD><EFBFBD><EFBFBD>ڼ<EFBFBD><EFBFBD><EFBFBD>SDRAM<EFBFBD><EFBFBD><EFBFBD><EFBFBD>8λ<EFBFBD><EFBFBD>16λ<EFBFBD>ķ<EFBFBD>ʽ<EFBFBD><EFBFBD>дsdram...");


  /*<2A><>8λ<38><CEBB>ʽ<EFBFBD><CABD>д<EFBFBD><D0B4><EFBFBD>ݣ<EFBFBD><DDA3><EFBFBD>У<EFBFBD><D0A3>*/
  
  /* <20><>SDRAM<41><4D><EFBFBD><EFBFBD>ȫ<EFBFBD><C8AB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ0 <20><>SDRAM_SIZE<5A><45><EFBFBD><EFBFBD>8λΪ<CEBB><CEAA>λ<EFBFBD><CEBB> */
  for (counter = 0x00; counter < SDRAM_SIZE; counter++)
  {
    *(__IO uint8_t*) (SDRAM_BANK_ADDR + counter) = (uint8_t)0x0;
  }
  
  /* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SDRAMд<4D><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>  8λ */
  for (counter = 0; counter < SDRAM_SIZE; counter++)
  {
    *(__IO uint8_t*) (SDRAM_BANK_ADDR + counter) = (uint8_t)(ubWritedata_8b + counter);
  }
  
  /* <20><>ȡ SDRAM <20><><EFBFBD>ݲ<EFBFBD><DDB2><EFBFBD><EFBFBD><EFBFBD>*/
  for(counter = 0; counter<SDRAM_SIZE;counter++ )
  {
    ubReaddata_8b = *(__IO uint8_t*)(SDRAM_BANK_ADDR + counter);  //<2F>Ӹõ<D3B8>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
    
    if(ubReaddata_8b != (uint8_t)(ubWritedata_8b + counter))      //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݣ<EFBFBD><DDA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȣ<EFBFBD><C8A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,<2C><><EFBFBD>ؼ<EFBFBD><D8BC><EFBFBD>ʧ<EFBFBD>ܽ<EFBFBD><DCBD><EFBFBD><EFBFBD><EFBFBD>
    {
      SDRAM_ERROR("8λ<EFBFBD><EFBFBD><EFBFBD>ݶ<EFBFBD>д<EFBFBD><EFBFBD><EFBFBD>󣡳<EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD>ã<EFBFBD>%d",counter);
      return 0;
    }
  }
	
  
  /*<2A><>16λ<36><CEBB>ʽ<EFBFBD><CABD>д<EFBFBD><D0B4><EFBFBD>ݣ<EFBFBD><DDA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
  
  /* <20><>SDRAM<41><4D><EFBFBD><EFBFBD>ȫ<EFBFBD><C8AB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ0 */
  for (counter = 0x00; counter < SDRAM_SIZE/2; counter++)
  {
    *(__IO uint16_t*) (SDRAM_BANK_ADDR + 2*counter) = (uint16_t)0x00;
  }
  
  /* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SDRAMд<4D><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>  16λ */
  for (counter = 0; counter < SDRAM_SIZE/2; counter++)
  {
    *(__IO uint16_t*) (SDRAM_BANK_ADDR + 2*counter) = (uint16_t)(uhWritedata_16b + counter);
  }
  
    /* <20><>ȡ SDRAM <20><><EFBFBD>ݲ<EFBFBD><DDB2><EFBFBD><EFBFBD><EFBFBD>*/
  for(counter = 0; counter<SDRAM_SIZE/2;counter++ )
  {
    uhReaddata_16b = *(__IO uint16_t*)(SDRAM_BANK_ADDR + 2*counter);  //<2F>Ӹõ<D3B8>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
    
    if(uhReaddata_16b != (uint16_t)(uhWritedata_16b + counter))      //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݣ<EFBFBD><DDA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȣ<EFBFBD><C8A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,<2C><><EFBFBD>ؼ<EFBFBD><D8BC><EFBFBD>ʧ<EFBFBD>ܽ<EFBFBD><DCBD><EFBFBD><EFBFBD><EFBFBD>
    {
      SDRAM_ERROR("16λ<EFBFBD><EFBFBD><EFBFBD>ݶ<EFBFBD>д<EFBFBD><EFBFBD><EFBFBD>󣡳<EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD>ã<EFBFBD>%d",counter);

      return 0;
    }
  }

  
  SDRAM_INFO("SDRAM<EFBFBD><EFBFBD>д<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>"); 
  /*<2A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>return 1 */
  return 1;
  

}


/*********************************************END OF FILE**********************/