ldeyun/STM32H750XB_RT-THREAD
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STM32H750XB_RT-THREAD/38-SAI—音频/SAI—MP3播放器/User/main.c

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STM32H750 RTThread 例程
2025-07-21 06:34:29 +00:00
/**
******************************************************************
* @file main.c
* @author fire
* @version V1.0
* @date 2018-xx-xx
* @brief <EFBFBD><EFBFBD>V1.2.0<EFBFBD>汾<EFBFBD>⽨<EFBFBD>Ĺ<EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><EFBFBD>
******************************************************************
* @attention
*
* ʵ<EFBFBD><EFBFBD>ƽ̨:Ұ<EFBFBD><EFBFBD> STM32H750<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* <EFBFBD><EFBFBD>̳ :http://www.firebbs.cn
* <EFBFBD>Ա<EFBFBD> :http://firestm32.taobao.com
*
******************************************************************
*/
#include "stm32h7xx.h"
#include "main.h"
#include "./led/bsp_led.h"
#include "./usart/bsp_debug_usart.h"
#include "./sd_card/bsp_sdio_sd.h"
#include "./key/bsp_key.h"
#include "./delay/core_delay.h"
#include "./wm8978/bsp_wm8978.h"
#include "./mp3Player/mp3Player.h"
/* FatFs includes component */
#include "ff.h"
#include "ff_gen_drv.h"
#include "sd_diskio.h"
/**
******************************************************************************
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
******************************************************************************
*/
char SDPath[4]; /* SD<53>߼<EFBFBD><DFBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>·<EFBFBD><C2B7> */
FATFS fs; /* FatFs<46>ļ<EFBFBD>ϵͳ<CFB5><CDB3><EFBFBD><EFBFBD> */
FIL fnew; /* file objects */
extern Diskio_drvTypeDef SD_Driver;
/**
* @brief CPU L1-Cache enable.
* @param None
* @retval None
*/
static void CPU_CACHE_Enable(void)
{
/* Enable I-Cache */
SCB_EnableICache();
/* Enable D-Cache */
SCB_EnableDCache();
//<2F><>Cache<68><65><EFBFBD><EFBFBD>write-through<67><68>ʽ
//SCB->CACR|=1<<2;
}
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @param <EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
int main(void)
{
FRESULT result;
/* ϵͳʱ<CDB3>ӳ<EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>480MHz */
SystemClock_Config();
CPU_CACHE_Enable();
LED_GPIO_Config();
LED_BLUE;
/* <20><>ʼ<EFBFBD><CABC>USART1 <20><><EFBFBD><EFBFBD>ģʽΪ 115200 8-N-1 */
DEBUG_USART_Config();
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̷<EFBFBD>
FATFS_LinkDriver(&SD_Driver, SDPath);
//<2F><><EFBFBD>ⲿSD<53><44><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD>ϵͳ<CFB5><CDB3><EFBFBD>ļ<EFBFBD>ϵͳ<CFB5><CDB3><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>SD<53><44><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>
result = f_mount(&fs,"0:",1);
if(result!=FR_OK)
{
printf("\n SD<53><44><EFBFBD>ļ<EFBFBD>ϵͳ<CFB5><CDB3><EFBFBD><EFBFBD>ʧ<EFBFBD><CAA7>\n");
while(1);
}
printf("WM8978¼<EFBFBD><EFBFBD><EFBFBD>ͻطŹ<EFBFBD><EFBFBD><EFBFBD>\n");
/* <20><><EFBFBD><EFBFBD>WM8978оƬ<D0BE><C6AC><EFBFBD>˺<EFBFBD><CBBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD>CPU<50><55>GPIO */
if (wm8978_Init()==0)
{
printf("<EFBFBD><EFBFBD><EFBFBD>ⲻ<EFBFBD><EFBFBD>WM8978оƬ!!!\n");
while (1); /* ͣ<><CDA3> */
}
printf("<EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD>WM8978<EFBFBD>ɹ<EFBFBD>\n");
while(1)
{
mp3PlayerDemo("0:/mp3/<2F>Ź<EFBFBD><C5B9><EFBFBD>-<2D><><EFBFBD><EFBFBD>֮<EFBFBD><D6AE>.mp3");
mp3PlayerDemo("0:/mp3/<2F>Ź<EFBFBD><C5B9><EFBFBD>-ȫ<><C8AB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>.mp3");
}
}
/**
* @brief System Clock <EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* system Clock <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:
* System Clock source = PLL (HSE)
* SYSCLK(Hz) = 480000000 (CPU Clock)
* HCLK(Hz) = 240000000 (AXI and AHBs Clock)
* AHB Prescaler = 2
* D1 APB3 Prescaler = 2 (APB3 Clock 120MHz)
* D2 APB1 Prescaler = 2 (APB1 Clock 120MHz)
* D2 APB2 Prescaler = 2 (APB2 Clock 120MHz)
* D3 APB4 Prescaler = 2 (APB4 Clock 120MHz)
* HSE Frequency(Hz) = 25000000
* PLL_M = 5
* PLL_N = 192
* PLL_P = 2
* PLL_Q = 4
* PLL_R = 2
* VDD(V) = 3.3
* Flash Latency(WS) = 4
* @param None
* @retval None
*/
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
/** <20><><EFBFBD>õ<EFBFBD>Դ<EFBFBD><D4B4><EFBFBD>ø<EFBFBD><C3B8><EFBFBD>
*/
HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
/** <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѹ
*/
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
/** <20><>ʼ<EFBFBD><CABC>CPU<50><55>AHB<48>͡<EFBFBD>APB<50><42><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 5;
RCC_OscInitStruct.PLL.PLLN = 192;
RCC_OscInitStruct.PLL.PLLP = 2;
RCC_OscInitStruct.PLL.PLLQ = 4;
RCC_OscInitStruct.PLL.PLLR = 2;
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
RCC_OscInitStruct.PLL.PLLFRACN = 0;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
}
/** <20><>ʼ<EFBFBD><CABC>CPU<50><55>AHB<48>͡<EFBFBD>APB<50><42><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
|RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
{
}
}
/****************************END OF FILE***************************/
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