ldeyun/STM32H750XB_RT-THREAD
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STM32H750XB_RT-THREAD/26-27-LTDC—液晶显示/刷外部FLASH程序（如何恢复字库）/User/main.c

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STM32H750 RTThread 例程
2025-07-21 06:34:29 +00:00
/**
******************************************************************
* @file main.c
* @author fire
* @version V1.0
* @date 2019-xx-xx
* @brief <EFBFBD><EFBFBD>V1.5.0<EFBFBD>汾<EFBFBD>⽨<EFBFBD>Ĺ<EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><EFBFBD>
******************************************************************
* @attention
*
* ʵ<EFBFBD><EFBFBD>ƽ̨:Ұ<EFBFBD><EFBFBD> STM32H750<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* <EFBFBD><EFBFBD>̳ :http://www.firebbs.cn
* <EFBFBD>Ա<EFBFBD> :http://firestm32.taobao.com
*
******************************************************************
*/
#include "stm32h7xx.h"
#include "main.h"
#include "./led/bsp_led.h"
#include "./usart/bsp_debug_usart.h"
#include "./sd_card/bsp_sdio_sd.h"
#include "./key/bsp_key.h"
#include "./delay/core_delay.h"
/* FatFs includes component */
#include "ff.h"
#include "ff_gen_drv.h"
#include "sd_diskio.h"
#include "./flash/bsp_qspi_flash.h"
#include "RES_MGR.h"
/**
******************************************************************************
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
******************************************************************************
*/
char SDPath[4]; /* SD<53>߼<EFBFBD><DFBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>·<EFBFBD><C2B7> */
extern FATFS sd_fs;
FRESULT res_sd; /* <20>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
extern char src_dir[];
uint8_t BSP_QSPI_Erase_Chip(void);
extern FATFS flash_fs;
extern Diskio_drvTypeDef SD_Driver;
/**
* @brief CPU L1-Cache enable.
* @param None
* @retval None
*/
static void CPU_CACHE_Enable(void)
{
/* Enable I-Cache */
SCB_EnableICache();
/* Enable D-Cache */
SCB_EnableDCache();
//<2F><>Cache<68><65><EFBFBD><EFBFBD>write-through<67><68>ʽ
//SCB->CACR|=1<<2;
}
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @param <EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
uint8_t state = QSPI_ERROR;
int main(void)
{
HAL_Init();
/* ϵͳʱ<CDB3>ӳ<EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>480MHz */
SystemClock_Config();
CPU_CACHE_Enable();
LED_GPIO_Config();
LED_BLUE;
/* <20><>ʼ<EFBFBD><CABC>USART1 <20><><EFBFBD><EFBFBD>ģʽΪ 115200 8-N-1 */
DEBUG_USART_Config();
Key_GPIO_Config();
QSPI_FLASH_Init();
QSPI_Set_WP_High();
/*д״̬<D7B4>Ĵ<EFBFBD><C4B4><EFBFBD>*/
/*<2A><>flash<73><68><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD>ò<EFBFBD><C3B2><EFBFBD>*/
QSPI_FLASH_WriteStatusReg(1,0X00);
QSPI_FLASH_WriteStatusReg(2,0X00);
QSPI_FLASH_WriteStatusReg(3,0X60);
printf("\r\nFlash Status Reg1 is 0x%02X,\r\n", QSPI_FLASH_ReadStatusReg(1));
printf("\r\nFlash Status Reg2 is 0x%02X,\r\n", QSPI_FLASH_ReadStatusReg(2));
printf("\r\nFlash Status Reg3 is 0x%02X,\r\n", QSPI_FLASH_ReadStatusReg(3));
QSPI_Set_WP_TO_QSPI_IO();
// //FMC_Bank1_R->BTCR[0] |= (1 << 24);
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̷<EFBFBD>
FATFS_LinkDriver(&SD_Driver, SDPath);
//<2F><><EFBFBD>ⲿSD<53><44><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD>ϵͳ<CFB5><CDB3><EFBFBD>ļ<EFBFBD>ϵͳ<CFB5><CDB3><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>SD<53><44><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>
res_sd = f_mount(&sd_fs,"0:",1);
if(res_sd != FR_OK)
{
printf("f_mount ERROR!<21><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SD<53><44>Ȼ<EFBFBD><C8BB><EFBFBD><EFBFBD><EFBFBD>¸<EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>!");
LED_RED;
while(1);
}
printf("\r\n <20><>һ<EFBFBD><D2BB>KEY1<59><31>ʼ<EFBFBD><CABC>д<EFBFBD>ֿⲢ<D6BF><E2B2A2><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC><EFBFBD>FLASH<53><48> \r\n");
printf("\r\n ע<><D7A2><EFBFBD>ò<EFBFBD><C3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>FLASH<53><48>ԭ<EFBFBD><D4AD><EFBFBD>ݻᱻɾ<E1B1BB><C9BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD> \r\n");
while(HAL_GPIO_ReadPin(GPIOA,GPIO_PIN_0)==0);
while(HAL_GPIO_ReadPin(GPIOA,GPIO_PIN_0)==1);
printf("\r\n <20><><EFBFBD>ڽ<EFBFBD><DABD><EFBFBD><EFBFBD><EFBFBD>Ƭ<EFBFBD><C6AC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>ܳ<EFBFBD><DCB3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĵȺ<C4B5>...\r\n");
// BSP_QSPI_Erase_Chip();
// for(int i = 16; i < 32; i++)
// {
// state = BSP_QSPI_Erase_Block(i*16);
// if(state != QSPI_OK)
// printf("<22><><EFBFBD><EFBFBD>Blockʧ<6B><CAA7>\n");
// else
// printf("OK\n");
// }
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>¼Ŀ¼<C4BF><C2BC>Ϣ<EFBFBD>ļ<EFBFBD> */
Make_Catalog(src_dir,0);
/* <20><>¼ Ŀ¼<C4BF><C2BC>Ϣ<EFBFBD><CFA2>FLASH*/
Burn_Catalog();
/* <20><><EFBFBD><EFBFBD> Ŀ¼ <20><>¼<EFBFBD><C2BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>FLASH*/
Burn_Content();
/* У<><D0A3><EFBFBD><EFBFBD>¼<EFBFBD><C2BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
Check_Resource();
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɣ<EFBFBD>ͣ<EFBFBD><CDA3> */
while(1)
{
}
}
/**
* @brief System Clock <EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* system Clock <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:
* System Clock source = PLL (HSE)
* SYSCLK(Hz) = 480000000 (CPU Clock)
* HCLK(Hz) = 240000000 (AXI and AHBs Clock)
* AHB Prescaler = 2
* D1 APB3 Prescaler = 2 (APB3 Clock 120MHz)
* D2 APB1 Prescaler = 2 (APB1 Clock 120MHz)
* D2 APB2 Prescaler = 2 (APB2 Clock 120MHz)
* D3 APB4 Prescaler = 2 (APB4 Clock 120MHz)
* HSE Frequency(Hz) = 25000000
* PLL_M = 5
* PLL_N = 192
* PLL_P = 2
* PLL_Q = 4
* PLL_R = 2
* VDD(V) = 3.3
* Flash Latency(WS) = 4
* @param None
* @retval None
*/
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
/** <20><><EFBFBD>õ<EFBFBD>Դ<EFBFBD><D4B4><EFBFBD>ø<EFBFBD><C3B8><EFBFBD>
*/
HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
/** <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѹ
*/
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
/** <20><>ʼ<EFBFBD><CABC>CPU<50><55>AHB<48><42>APB<50><42><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 5;
RCC_OscInitStruct.PLL.PLLN = 192;
RCC_OscInitStruct.PLL.PLLP = 2;
RCC_OscInitStruct.PLL.PLLQ = 4;
RCC_OscInitStruct.PLL.PLLR = 2;
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
RCC_OscInitStruct.PLL.PLLFRACN = 0;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
while(1);
}
/** <20><>ʼ<EFBFBD><CABC>CPU<50><55>AHB<48><42>APB<50><42><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
|RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
{
while(1);
}
}
/****************************END OF FILE***************************/
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