ldeyun/STM32H750XB_RT-THREAD
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STM32H750XB_RT-THREAD/25-FMC—扩展外部SDRAM/User/main.c

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STM32H750 RTThread 例程
2025-07-21 06:34:29 +00:00
/**
******************************************************************
* @file main.c
* @author fire
* @version V1.0
* @date 2018-xx-xx
* @brief FMC-SDRAM
******************************************************************
* @attention
*
* ʵ<EFBFBD><EFBFBD>ƽ̨:Ұ<EFBFBD><EFBFBD> STM32H750 <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* <EFBFBD><EFBFBD>̳ :http://www.firebbs.cn
* <EFBFBD>Ա<EFBFBD> :http://firestm32.taobao.com
*
******************************************************************
*/
#include "stm32h7xx.h"
#include "main.h"
#include "./led/bsp_led.h"
#include "./delay/core_delay.h"
#include "./mpu/bsp_mpu.h"
#include "./sdram/bsp_sdram.h"
#include "./usart/bsp_debug_usart.h"
void Delay(__IO uint32_t nCount);
void SDRAM_Check(void);
uint32_t RadomBuffer[10000];
uint32_t ReadBuffer[10000];
uint32_t *pSDRAM;
RNG_HandleTypeDef hrng;
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @param <EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
int main(void)
{
long long count=0;
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
/* ϵͳʱ<CDB3>ӳ<EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>480MHz */
SystemClock_Config();
/* Ĭ<>ϲ<EFBFBD><CFB2><EFBFBD><EFBFBD><EFBFBD> MPU<50><55><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ܣ<EFBFBD><DCA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> MPU <20><><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>
DMA ʱ<EFBFBD><EFBFBD>ע<EFBFBD><EFBFBD> Cache <EFBFBD><EFBFBD> <EFBFBD>ڴ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><EFBFBD><EFBFBD>Ե<EFBFBD><EFBFBD><EFBFBD><EFBFBD>⣬
<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ע<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ο<EFBFBD><EFBFBD><EFBFBD><EFBFBD>׽̵̳<EFBFBD> MPU <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>½<EFBFBD> */
// Board_MPU_Config(0, MPU_Normal_WT, 0xD0000000, MPU_32MB);
// Board_MPU_Config(1, MPU_Normal_WT, 0x24000000, MPU_512KB);
SCB_EnableICache(); // ʹ<><CAB9>ָ<EFBFBD><D6B8> Cache
SCB_EnableDCache(); // ʹ<><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Cache
/* LED <20>˿ڳ<CBBF>ʼ<EFBFBD><CABC> */
LED_GPIO_Config();
/* <20><><EFBFBD>ڳ<EFBFBD>ʼ<EFBFBD><CABC> */
DEBUG_USART_Config();
printf("\r\n <20><>ӭʹ<D3AD><CAB9>Ұ<EFBFBD><D2B0> STM32 H750 <20><><EFBFBD><EFBFBD><EFBFBD>塣\r\n");
printf("\r\nҰ<EFBFBD><EFBFBD>STM32H750 SDRAM <20><>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>\r\n");
/*<2A><>ʼ<EFBFBD><CABC>SDRAMģ<4D><C4A3>*/
SDRAM_Init();
/*<2A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʾ<EFBFBD><CABE><EFBFBD>ڶ<EFBFBD>дSDRAM<41><4D><EFBFBD><EFBFBD>*/
LED_BLUE;
/*ѡ<><D1A1>PLL<4C><4C><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ΪRNGʱ<47><CAB1>Դ */
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RNG;
PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_PLL;
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
/*ʹ<><CAB9>RNGʱ<47><CAB1>*/
__HAL_RCC_RNG_CLK_ENABLE();
/*<2A><>ʼ<EFBFBD><CABC>RNGģ<47><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
hrng.Instance = RNG;
HAL_RNG_Init(&hrng);
SDRAM_Test();
printf("<EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>10000<EFBFBD><EFBFBD>SDRAM<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>\r\n");
for(count=0;count<10000;count++)
{
HAL_RNG_GenerateRandomNumber(&hrng,&RadomBuffer[count]);
}
printf("10000<EFBFBD><EFBFBD>SDRAM<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>\r\n");
SDRAM_Check();
while(1);
}
void SDRAM_Check(void)
{
long long count=0,sdram_count=0;
pSDRAM=(uint32_t*)SDRAM_BANK_ADDR;
printf("<EFBFBD><EFBFBD>ʼд<EFBFBD><EFBFBD>SDRAM\r\n");
for(sdram_count=0;sdram_count<SDRAM_SIZE/4;sdram_count++)
{
*pSDRAM=RadomBuffer[count];
count++;
pSDRAM++;
if(count>=10000)
{
count=0;
}
}
printf("д<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD><EFBFBD><EFBFBD>:%d\r\n",(uint32_t)pSDRAM-SDRAM_BANK_ADDR);
count=0;
pSDRAM=(uint32_t*)SDRAM_BANK_ADDR;
printf("<EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD>ȡSDRAM<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ԭ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƚ<EFBFBD>\r\n");
sdram_count=0;
for(;sdram_count<SDRAM_SIZE/4;sdram_count++)
{
if(*pSDRAM != RadomBuffer[count])
{
printf("<EFBFBD><EFBFBD><EFBFBD>ݱȽϴ<EFBFBD><EFBFBD>󡪡<EFBFBD><EFBFBD>˳<EFBFBD>~\r\n");
break;
}
count++;
pSDRAM++;
if(count>=10000)
{
count=0;
}
}
printf("<EFBFBD>Ƚ<EFBFBD>ͨ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD><EFBFBD><EFBFBD>:%d\r\n",(uint32_t)pSDRAM-SDRAM_BANK_ADDR);
if(sdram_count == SDRAM_SIZE/4)
{
LED_GREEN;
printf("SDRAM<EFBFBD><EFBFBD><EFBFBD>Գɹ<EFBFBD>\r\n");
}
else
{
LED_RED;
printf("SDRAM<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʧ<EFBFBD><EFBFBD>\r\n");
}
}
/**
* @brief System Clock <EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* system Clock <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:
* System Clock source = PLL (HSE)
* SYSCLK(Hz) = 480000000 (CPU Clock)
* HCLK(Hz) = 240000000 (AXI and AHBs Clock)
* AHB Prescaler = 2
* D1 APB3 Prescaler = 2 (APB3 Clock 120MHz)
* D2 APB1 Prescaler = 2 (APB1 Clock 120MHz)
* D2 APB2 Prescaler = 2 (APB2 Clock 120MHz)
* D3 APB4 Prescaler = 2 (APB4 Clock 120MHz)
* HSE Frequency(Hz) = 25000000
* PLL_M = 5
* PLL_N = 192
* PLL_P = 2
* PLL_Q = 4
* PLL_R = 2
* VDD(V) = 3.3
* Flash Latency(WS) = 4
* @param None
* @retval None
*/
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
/** <20><><EFBFBD>õ<EFBFBD>Դ<EFBFBD><D4B4><EFBFBD>ø<EFBFBD><C3B8><EFBFBD>
*/
HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
/** <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѹ
*/
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
/** <20><>ʼ<EFBFBD><CABC>CPU<50><55>AHB<48><42>APB<50><42><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 5;
RCC_OscInitStruct.PLL.PLLN = 192;
RCC_OscInitStruct.PLL.PLLP = 2;
RCC_OscInitStruct.PLL.PLLQ = 2;
RCC_OscInitStruct.PLL.PLLR = 2;
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
RCC_OscInitStruct.PLL.PLLFRACN = 0;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
while(1);
}
/** <20><>ʼ<EFBFBD><CABC>CPU<50><55>AHB<48><42>APB<50><42><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
|RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
{
while(1);
}
}
/****************************END OF FILE***************************/
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