167 lines
6.2 KiB
C
167 lines
6.2 KiB
C
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#ifndef __SPI_FLASH_H
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#define __SPI_FLASH_H
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#include "stm32h7xx.h"
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#include <stdio.h>
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/* Private typedef -----------------------------------------------------------*/
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#define sFLASH_ID 0XEF4019 //W25Q256JVEM
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/* QSPI Error codes */
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#define QSPI_OK ((uint8_t)0x00)
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#define QSPI_ERROR ((uint8_t)0x01)
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#define QSPI_BUSY ((uint8_t)0x02)
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#define QSPI_NOT_SUPPORTED ((uint8_t)0x04)
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#define QSPI_SUSPENDED ((uint8_t)0x08)
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/* W25Q256JV Micron memory */
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/* Size of the flash */
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#define QSPI_FLASH_SIZE 24 /* <20><>ַ<EFBFBD><D6B7><EFBFBD>߿<EFBFBD><DFBF>ȷ<EFBFBD><C8B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڴ<EFBFBD><DAB4>ռ<EFBFBD> */
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#define QSPI_PAGE_SIZE 256
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/* QSPI Info */
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typedef struct {
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uint32_t FlashSize; /*!< <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>С */
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uint32_t EraseSectorSize; /*!< <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>С */
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uint32_t EraseSectorsNumber; /*!< <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
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uint32_t ProgPageSize; /*!< <20><><EFBFBD>̲<EFBFBD><CCB2><EFBFBD><EFBFBD><EFBFBD>ҳ<EFBFBD><D2B3><EFBFBD><EFBFBD>С */
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uint32_t ProgPagesNumber; /*!< <20><><EFBFBD>̲<EFBFBD><CCB2><EFBFBD><EFBFBD><EFBFBD>ҳ<EFBFBD><D2B3><EFBFBD><EFBFBD> */
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} QSPI_Info;
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/* Private define ------------------------------------------------------------*/
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/*<2A><><EFBFBD><EFBFBD><EEB6A8>-<2D><>ͷ*******************************/
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/**
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* @brief W25Q256JV<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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*/
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#define W25Q256JV_FLASH_SIZE 0x2000000 /* 128 MBits => 16MBytes */
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#define W25Q256JV_SECTOR_SIZE 0x10000 /* 256 sectors of 64KBytes */
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#define W25Q256JV_SUBSECTOR_SIZE 0x1000 /* 4096 subsectors of 4kBytes */
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#define W25Q256JV_PAGE_SIZE 0x100 /* 65536 pages of 256 bytes */
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#define W25Q256JV_DUMMY_CYCLES_READ 4
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#define W25Q256JV_DUMMY_CYCLES_READ_QUAD 10
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#define W25Q256JV_BULK_ERASE_MAX_TIME 250000
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#define W25Q256JV_SECTOR_ERASE_MAX_TIME 3000
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#define W25Q256JV_SUBSECTOR_ERASE_MAX_TIME 800
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/**
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* @brief W25Q256JV ָ<EFBFBD><EFBFBD>
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*/
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/* <20><>λ<EFBFBD><CEBB><EFBFBD><EFBFBD> */
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#define RESET_ENABLE_CMD 0x66
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#define RESET_MEMORY_CMD 0x99
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#define ENTER_QPI_MODE_CMD 0x38
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#define EXIT_QPI_MODE_CMD 0xFF
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/* ʶ<><CAB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
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#define READ_ID_CMD 0x90
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#define DUAL_READ_ID_CMD 0x92
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#define QUAD_READ_ID_CMD 0x94
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#define READ_JEDEC_ID_CMD 0x9F
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/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
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#define READ_CMD_4BYTE 0x03
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#define QUAD_INOUT_FAST_READ_CMD_4BYTE 0xEC
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/* д<><D0B4><EFBFBD><EFBFBD> */
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#define WRITE_ENABLE_CMD 0x06
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#define WRITE_DISABLE_CMD 0x04
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/* <20>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
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#define READ_STATUS_REG1_CMD 0x05
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#define READ_STATUS_REG2_CMD 0x35
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#define READ_STATUS_REG3_CMD 0x15
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#define WRITE_STATUS_REG1_CMD 0x01
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#define WRITE_STATUS_REG2_CMD 0x31
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#define WRITE_STATUS_REG3_CMD 0x11
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/* <20><><EFBFBD>̲<EFBFBD><CCB2><EFBFBD> */
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#define QUAD_INPUT_PAGE_PROG_CMD_4BYTE 0x34
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#define EXT_QUAD_IN_FAST_PROG_CMD_4BYTE 0x12
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/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
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#define SECTOR_ERASE_CMD_4BYTE 0x21
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#define BLOCK64K_ERASE_CMD_4BYTE 0xDC
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#define CHIP_ERASE_CMD 0xC7
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//#define PROG_ERASE_RESUME_CMD 0x7A
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//#define PROG_ERASE_SUSPEND_CMD 0x75
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#define ENTER_4_BYTE_ADDR_MODE_CMD 0xB7
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/* ״̬<D7B4>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>־ */
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#define W25Q256JV_FSR_BUSY ((uint8_t)0x01) /*!< busy */
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#define W25Q256JV_FSR_WREN ((uint8_t)0x02) /*!< write enable */
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#define W25Q256JV_FSR_QE ((uint8_t)0x02) /*!< quad enable */
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/*<2A><><EFBFBD><EFBFBD><EEB6A8>-<2D><>β*******************************/
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/*QSPI<50>ӿڶ<D3BF><DAB6><EFBFBD>-<2D><>ͷ****************************/
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#define QSPI_FLASH QUADSPI
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#define QSPI_FLASH_CLK_ENABLE() __QSPI_CLK_ENABLE()
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#define QSPI_MDMA_CLK_ENABLE() __HAL_RCC_MDMA_CLK_ENABLE()
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#define QSPI_FORCE_RESET() __HAL_RCC_QSPI_FORCE_RESET()
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#define QSPI_RELEASE_RESET() __HAL_RCC_QSPI_RELEASE_RESET()
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#define QSPI_FLASH_CLK_PIN GPIO_PIN_2
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#define QSPI_FLASH_CLK_GPIO_PORT GPIOB
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#define QSPI_FLASH_CLK_GPIO_ENABLE() __GPIOB_CLK_ENABLE()
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#define QSPI_FLASH_CLK_GPIO_AF GPIO_AF9_QUADSPI
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#define QSPI_FLASH_BK1_IO0_PIN GPIO_PIN_8
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#define QSPI_FLASH_BK1_IO0_PORT GPIOF
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#define QSPI_FLASH_BK1_IO0_CLK_ENABLE() __GPIOF_CLK_ENABLE()
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#define QSPI_FLASH_BK1_IO0_AF GPIO_AF10_QUADSPI
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#define QSPI_FLASH_BK1_IO1_PIN GPIO_PIN_9
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#define QSPI_FLASH_BK1_IO1_PORT GPIOF
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#define QSPI_FLASH_BK1_IO1_CLK_ENABLE() __GPIOF_CLK_ENABLE()
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#define QSPI_FLASH_BK1_IO1_AF GPIO_AF10_QUADSPI
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#define QSPI_FLASH_BK1_IO2_PIN GPIO_PIN_7
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#define QSPI_FLASH_BK1_IO2_PORT GPIOF
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#define QSPI_FLASH_BK1_IO2_CLK_ENABLE() __GPIOF_CLK_ENABLE()
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#define QSPI_FLASH_BK1_IO2_AF GPIO_AF9_QUADSPI
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#define QSPI_FLASH_BK1_IO3_PIN GPIO_PIN_6
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#define QSPI_FLASH_BK1_IO3_PORT GPIOF
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#define QSPI_FLASH_BK1_IO3_CLK_ENABLE() __GPIOF_CLK_ENABLE()
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#define QSPI_FLASH_BK1_IO3_AF GPIO_AF9_QUADSPI
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#define QSPI_FLASH_CS_PIN GPIO_PIN_6
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#define QSPI_FLASH_CS_GPIO_PORT GPIOG
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#define QSPI_FLASH_CS_GPIO_CLK_ENABLE() __GPIOG_CLK_ENABLE()
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#define QSPI_FLASH_CS_GPIO_AF GPIO_AF10_QUADSPI
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void QSPI_FLASH_Init(void);
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uint8_t BSP_QSPI_Init(void);
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uint8_t BSP_QSPI_Erase_Block(uint32_t BlockAddress);
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uint8_t BSP_QSPI_Read(uint8_t* pData, uint32_t ReadAddr, uint32_t Size);
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uint8_t BSP_QSPI_FastRead(uint8_t* pData, uint32_t ReadAddr, uint32_t Size);
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uint8_t BSP_QSPI_Write(uint8_t* pData, uint32_t WriteAddr, uint32_t Size);
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uint8_t BSP_QSPI_Erase_Chip(void);
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static uint8_t QSPI_WriteEnable (void);
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static uint8_t QSPI_AutoPollingMemReady (uint32_t Timeout);
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uint32_t QSPI_FLASH_ReadDeviceID(void);
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uint32_t QSPI_FLASH_ReadID(void);
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uint32_t QSPI_FLASH_ReadStatusReg(uint8_t reg);
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uint32_t QSPI_FLASH_WriteStatusReg(uint8_t reg,uint8_t regvalue);
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void QSPI_Set_WP_High(void);
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void QSPI_Set_WP_TO_QSPI_IO(void);
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void QSPI_FLASH_Wait_Busy(void);
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uint32_t QSPI_EnableMemoryMappedMode(void); //ʹ<><CAB9>ֱ<EFBFBD><D6B1>ӳ<EFBFBD><D3B3>ģʽ
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uint8_t QSPI_ResetMemory(void);
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#endif /* __SPI_FLASH_H */
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