ldeyun/STM32H750XB_RT-THREAD
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STM32H750XB_RT-THREAD/21-DMA—直接存储区访问/DMA—存储器到存储器模式/User/main.c

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STM32H750 RTThread 例程
2025-07-21 06:34:29 +00:00
/**
******************************************************************
* @file main.c
* @author fire
* @version V1.0
* @date 2018-xx-xx
* @brief DMA<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>洢<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>洢<EFBFBD><EFBFBD>ģʽ
******************************************************************
* @attention
*
* ʵ<EFBFBD><EFBFBD>ƽ̨:Ұ<EFBFBD><EFBFBD> STM32H750 <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* <EFBFBD><EFBFBD>̳ :http://www.firebbs.cn
* <EFBFBD>Ա<EFBFBD> :http://firestm32.taobao.com
*
******************************************************************
*/
#include "stm32h7xx.h"
#include "main.h"
#include "./led/bsp_led.h"
#include "./delay/core_delay.h"
#include "./mpu/bsp_mpu.h"
/* <20><><EFBFBD>غ궨<D8BA>壬ʹ<E5A3AC>ô洢<C3B4><E6B4A2><EFBFBD><EFBFBD><EFBFBD>洢<EFBFBD><E6B4A2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>DMA2 */
DMA_HandleTypeDef DMA_Handle;
#define DMA_STREAM DMA2_Stream0
#define DMA_STREAM_CLOCK() __DMA2_CLK_ENABLE()
#define BUFFER_SIZE 32
/* <20><><EFBFBD><EFBFBD>aSRC_Const_Buffer<65><72><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ΪDMA<4D><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ
const<EFBFBD>ؼ<EFBFBD><EFBFBD>ֽ<EFBFBD>aSRC_Const_Buffer<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
const uint32_t aSRC_Const_Buffer[BUFFER_SIZE]={
0x01020304,0x05060708,0x090A0B0C,0x0D0E0F10,
0x11121314,0x15161718,0x191A1B1C,0x1D1E1F20,
0x21222324,0x25262728,0x292A2B2C,0x2D2E2F30,
0x31323334,0x35363738,0x393A3B3C,0x3D3E3F40,
0x41424344,0x45464748,0x494A4B4C,0x4D4E4F50,
0x51525354,0x55565758,0x595A5B5C,0x5D5E5F60,
0x61626364,0x65666768,0x696A6B6C,0x6D6E6F70,
0x71727374,0x75767778,0x797A7B7C,0x7D7E7F80};
/* <20><><EFBFBD><EFBFBD>DMA<4D><41><EFBFBD><EFBFBD>Ŀ<EFBFBD><C4BF><EFBFBD>洢<EFBFBD><E6B4A2> */
__attribute__((at(0x30000000))) uint32_t aDST_Buffer[BUFFER_SIZE];
static void DMA_Config(void);
static void Delay(__IO uint32_t nCount);
static void SystemClock_Config(void);
uint8_t Buffercmp(const uint32_t* pBuffer, uint32_t* pBuffer1, uint16_t BufferLength);
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @param <EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
int main(void)
{
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>űȽϽ<C8BD><CFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
uint8_t TransferStatus;
/* ϵͳʱ<CDB3>ӳ<EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>480MHz */
SystemClock_Config();
/* Ĭ<>ϲ<EFBFBD><CFB2><EFBFBD><EFBFBD><EFBFBD> MPU<50><55><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ܣ<EFBFBD><DCA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> MPU <20><><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>
DMA ʱ<EFBFBD><EFBFBD>ע<EFBFBD><EFBFBD> Cache <EFBFBD><EFBFBD> <EFBFBD>ڴ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><EFBFBD><EFBFBD>Ե<EFBFBD><EFBFBD><EFBFBD><EFBFBD>⣬
<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ע<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ο<EFBFBD><EFBFBD><EFBFBD><EFBFBD>׽̵̳<EFBFBD> MPU <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>½<EFBFBD> */
// Board_MPU_Config(0, MPU_Normal_WT, 0xD0000000, MPU_32MB);
// Board_MPU_Config(1, MPU_Normal_WT, 0x24000000, MPU_512KB);
SCB_EnableICache(); // ʹ<><CAB9>ָ<EFBFBD><D6B8> Cache
// SCB_EnableDCache(); // ʹ<><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Cache
/* LED <20>˿ڳ<CBBF>ʼ<EFBFBD><CABC> */
LED_GPIO_Config();
/* <20><><EFBFBD><EFBFBD>RGB<47><42>ɫ<EFBFBD><C9AB>Ϊ<EFBFBD><CEAA>ɫ */
LED_PURPLE;
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD> */
Delay(0xFFFFFF);
/* DMA<4D><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
DMA_Config();
/* <20>ȴ<EFBFBD>DMA<4D><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
while(__HAL_DMA_GET_FLAG(&DMA_Handle,DMA_FLAG_TCIF0_4)==DISABLE)
{
}
/* <20>Ƚ<EFBFBD>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD><EFBFBD>봫<EFBFBD><EBB4AB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
TransferStatus=Buffercmp(aSRC_Const_Buffer, aDST_Buffer, BUFFER_SIZE);
/* <20>ж<EFBFBD>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD><EFBFBD>봫<EFBFBD><EBB4AB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݱȽϽ<C8BD><CFBD><EFBFBD>*/
if(TransferStatus==0)
{
/* Դ<><D4B4><EFBFBD><EFBFBD><EFBFBD>봫<EFBFBD><EBB4AB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݲ<EFBFBD><DDB2><EFBFBD><EFBFBD><EFBFBD>ʱRGB<47><42>ɫ<EFBFBD><C9AB><EFBFBD><EFBFBD>ʾ<EFBFBD><CABE>ɫ */
LED_RED;
}
else
{
/* Դ<><D4B4><EFBFBD><EFBFBD><EFBFBD>봫<EFBFBD><EBB4AB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱRGB<47><42>ɫ<EFBFBD><C9AB><EFBFBD><EFBFBD>ʾ<EFBFBD><CABE>ɫ */
LED_BLUE;
}
while (1)
{
}
}
/* <20>򵥵<EFBFBD><F2B5A5B5><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD> */
static void Delay(__IO uint32_t nCount)
{
for(; nCount != 0; nCount--);
}
/**
* DMA<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*/
static void DMA_Config(void)
{
HAL_StatusTypeDef DMA_status = HAL_ERROR;
/* ʹ<><CAB9>DMAʱ<41><CAB1> */
DMA_STREAM_CLOCK();
DMA_Handle.Instance = DMA_STREAM;
/* DMA<4D><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1> */
DMA_Handle.Init.Request = DMA_REQUEST_MEM2MEM;
/* <20>洢<EFBFBD><E6B4A2><EFBFBD><EFBFBD><EFBFBD>洢<EFBFBD><E6B4A2>ģʽ */
DMA_Handle.Init.Direction = DMA_MEMORY_TO_MEMORY;
/* ʹ<><CAB9><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
DMA_Handle.Init.PeriphInc = DMA_PINC_ENABLE;
/* ʹ<><CAB9><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
DMA_Handle.Init.MemInc = DMA_MINC_ENABLE;
/* Դ<><D4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ִ<EFBFBD>С(32λ) */
DMA_Handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
/* Ŀ<><C4BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҳ<EFBFBD><D2B2><EFBFBD>ִ<EFBFBD>С(32λ) */
DMA_Handle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
/* һ<>δ<EFBFBD><CEB4><EFBFBD>ģʽ<C4A3><CABD><EFBFBD>洢<EFBFBD><E6B4A2><EFBFBD><EFBFBD><EFBFBD>洢<EFBFBD><E6B4A2>ģʽ<C4A3><CABD><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>ѭ<EFBFBD><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
DMA_Handle.Init.Mode = DMA_NORMAL;
/* DMA<4D><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȼ<EFBFBD>Ϊ<EFBFBD><CEAA> */
DMA_Handle.Init.Priority = DMA_PRIORITY_HIGH;
/* <20><><EFBFBD><EFBFBD>FIFOģʽ */
DMA_Handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
DMA_Handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
/* <20><><EFBFBD><EFBFBD>ģʽ */
DMA_Handle.Init.MemBurst = DMA_MBURST_SINGLE;
/* <20><><EFBFBD><EFBFBD>ģʽ */
DMA_Handle.Init.PeriphBurst = DMA_PBURST_SINGLE;
/* <20><><EFBFBD><EFBFBD>DMA<4D><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
HAL_DMA_Init(&DMA_Handle);
DMA_status = HAL_DMA_Start(&DMA_Handle,(uint32_t)aSRC_Const_Buffer,(uint32_t)aDST_Buffer,BUFFER_SIZE);
/* <20>ж<EFBFBD>DMA״̬ */
if (DMA_status != HAL_OK)
{
/* DMA<4D><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ó<EFBFBD><C3B3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѭ<EFBFBD><D1AD><EFBFBD><EFBFBD>RGB<47><42>ɫ<EFBFBD><C9AB><EFBFBD><EFBFBD>˸ */
while (1)
{
LED_RED;
Delay(0xFFFFFF);
LED_RGBOFF;
Delay(0xFFFFFF);
}
}
}
/**
* <EFBFBD>ж<EFBFBD>ָ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD>Ƿ<EFBFBD><EFBFBD><EFBFBD>ȫ<EFBFBD><EFBFBD><EFBFBD>ȣ<EFBFBD>
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȫ<EFBFBD><EFBFBD><EFBFBD>ȷ<EFBFBD><EFBFBD><EFBFBD>1<EFBFBD><EFBFBD>ֻҪ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݲ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȷ<EFBFBD><EFBFBD><EFBFBD>0
*/
uint8_t Buffercmp(const uint32_t* pBuffer,
uint32_t* pBuffer1, uint16_t BufferLength)
{
/* <20><><EFBFBD>ݳ<EFBFBD><DDB3>ȵݼ<C8B5> */
while(BufferLength--)
{
/* <20>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD>Ƿ<EFBFBD><C7B7><EFBFBD>Ӧ<EFBFBD><D3A6><EFBFBD><EFBFBD> */
if(*pBuffer != *pBuffer1)
{
/* <20><>Ӧ<EFBFBD><D3A6><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˳<EFBFBD><CBB3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0 */
return 0;
}
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD>ĵ<EFBFBD>ַָ<D6B7><D6B8> */
pBuffer++;
pBuffer1++;
}
/* <20><><EFBFBD><EFBFBD><EFBFBD>жϲ<D0B6><CFB2>Ҷ<EFBFBD>Ӧ<EFBFBD><D3A6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
return 1;
}
/**
* @brief System Clock <EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* system Clock <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:
* System Clock source = PLL (HSE)
* SYSCLK(Hz) = 480000000 (CPU Clock)
* HCLK(Hz) = 240000000 (AXI and AHBs Clock)
* AHB Prescaler = 2
* D1 APB3 Prescaler = 2 (APB3 Clock 120MHz)
* D2 APB1 Prescaler = 2 (APB1 Clock 120MHz)
* D2 APB2 Prescaler = 2 (APB2 Clock 120MHz)
* D3 APB4 Prescaler = 2 (APB4 Clock 120MHz)
* HSE Frequency(Hz) = 25000000
* PLL_M = 5
* PLL_N = 192
* PLL_P = 2
* PLL_Q = 4
* PLL_R = 2
* VDD(V) = 3.3
* Flash Latency(WS) = 4
* @param None
* @retval None
*/
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
/** <20><><EFBFBD>õ<EFBFBD>Դ<EFBFBD><D4B4><EFBFBD>ø<EFBFBD><C3B8><EFBFBD>
*/
HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
/** <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѹ
*/
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
/** <20><>ʼ<EFBFBD><CABC>CPU<50><55>AHB<48><42>APB<50><42><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 5;
RCC_OscInitStruct.PLL.PLLN = 192;
RCC_OscInitStruct.PLL.PLLP = 2;
RCC_OscInitStruct.PLL.PLLQ = 2;
RCC_OscInitStruct.PLL.PLLR = 2;
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
RCC_OscInitStruct.PLL.PLLFRACN = 0;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
while(1);
}
/** <20><>ʼ<EFBFBD><CABC>CPU<50><55>AHB<48><42>APB<50><42><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
|RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
{
while(1);
}
}
/****************************END OF FILE***************************/
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