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STM32H750XB_RT-THREAD/0-Bootloader/H750-TWIN-QSPI-BOOTLOADER/User/main.c

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STM32H750 RTThread 例程
2025-07-21 06:34:29 +00:00
/**
******************************************************************
* @file main.c
* @author fire
* @version V1.0
* @date 2018-xx-xx
* @brief USART<EFBFBD><EFBFBD>USART1<EFBFBD>ӷ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
******************************************************************
* @attention
*
* ʵ<EFBFBD><EFBFBD>ƽ̨:Ұ<EFBFBD><EFBFBD> STM32H750<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* <EFBFBD><EFBFBD>̳ :http://www.firebbs.cn
* <EFBFBD>Ա<EFBFBD> :http://firestm32.taobao.com
*
******************************************************************
*/
#include "stm32h7xx.h"
#include "main.h"
#include "./led/bsp_led.h"
#include "./usart/bsp_debug_usart.h"
#include "./flash/bsp_qspi_flash.h"
#include "./sdram/bsp_sdram.h"
typedef enum { FAILED = 0, PASSED = !FAILED} TestStatus;
/* <20><>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ij<EFBFBD><C4B3><EFBFBD> */
#define TxBufferSize1 (countof(TxBuffer1) - 1)
#define RxBufferSize1 (countof(TxBuffer1) - 1)
#define countof(a) (sizeof(a) / sizeof(*(a)))
#define BufferSize (countof(Tx_Buffer)-1)
#define FLASH_WriteAddress 0x2000
#define FLASH_ReadAddress FLASH_WriteAddress
#define FLASH_SectorToErase FLASH_WriteAddress
/* <20><><EFBFBD>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC> */
uint8_t Tx_Buffer[256] = "<EFBFBD><EFBFBD>л<EFBFBD><EFBFBD>ѡ<EFBFBD><EFBFBD>Ұ<EFBFBD><EFBFBD>stm32<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>\r\nhttp://firestm32.taobao.com";
uint8_t Rx_Buffer[BufferSize];
//<2F><>ȡ<EFBFBD><C8A1>ID<49>洢λ<E6B4A2><CEBB>
__IO uint32_t DeviceID = 0;
__IO uint32_t FlashID = 0;
__IO TestStatus TransferStatus1 = FAILED;
// <20><><EFBFBD><EFBFBD>ԭ<EFBFBD><D4AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//void Delay(__IO uint32_t nCount);
TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength);
extern __IO uint8_t QSPIStatusReady;
extern __IO uint8_t QSPITxOK;
extern __IO uint8_t QSPIRxOK;
extern __IO uint8_t QSPICmdOK;
/* Private typedef -----------------------------------------------------------*/
typedef void (*pFunction)(void);
pFunction JumpToApplication;
/* QSPI is used to emulate SPI-NOR*/
#define APPLICATION_ADDRESS QSPI_BASE
/**
* @brief ʹ<EFBFBD><EFBFBD>CPU L1-Cache.
* @param <EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
static void CPU_CACHE_Enable(void)
{
/* ʹ<><CAB9>I-Cache */
SCB_EnableICache();
/* ʹ<><CAB9>D-Cache */
SCB_EnableDCache();
}
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD>CPU L1-Cache.
* @param <EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
static void CPU_CACHE_Disable(void)
{
/* <20><>ֹI-Cache */
SCB_DisableICache();
/* <20><>ֹD-Cache */
SCB_DisableDCache();
}
//#if (DATA_AREA == USE_EXTERNAL_SDRAM) || (CODE_AREA == USE_EXTERNAL_SDRAM)
static void MPU_Config (void)
{
MPU_Region_InitTypeDef MPU_InitStruct;
/* <20><>ֹMPU */
HAL_MPU_Disable();
/* <20><><EFBFBD><EFBFBD>SDRAM<41><4D>MPU */
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.BaseAddress = 0xD0000000;
MPU_InitStruct.Size = MPU_REGION_SIZE_64MB;
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
MPU_InitStruct.Number = MPU_REGION_NUMBER7;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
MPU_InitStruct.SubRegionDisable = 0x00;
//#if (DATA_AREA == USE_EXTERNAL_SDRAM)
// MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
//#else
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
//#endif
HAL_MPU_ConfigRegion(&MPU_InitStruct);
/* ʹ<><CAB9>MPU */
HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
}
//#endif
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @param <EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
int main(void)
{
/* ʹ<><CAB9>CPU Cache */
CPU_CACHE_Enable();
/* STM32H7xx HAL<41><4C><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>
- <EFBFBD><EFBFBD><EFBFBD><EFBFBD>Systick<EFBFBD><EFBFBD>ÿ1<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
- <EFBFBD><EFBFBD>NVIC<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȼ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ4
- ȫ<EFBFBD><EFBFBD>MSP<EFBFBD><EFBFBD>MCU֧<EFBFBD>ְ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD> */
HAL_Init();
/* ϵͳʱ<CDB3>ӳ<EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>480MHz */
SystemClock_Config();
// LED_GPIO_Config();
//#if (DATA_AREA == USE_EXTERNAL_SDRAM) || (CODE_AREA == USE_EXTERNAL_SDRAM)
/* <20><><EFBFBD><EFBFBD>MPU<50><55><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƕ<EFBFBD><C7B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
// MPU_Config();
//#endif
/* <20><><EFBFBD>ô<EFBFBD><C3B4><EFBFBD>1Ϊ<31><CEAA>115200 8-N-1 */
DEBUG_USART_Config();
SDRAM_Init();
//SDRAM_Test();
printf("<EFBFBD><EFBFBD>ӭʹ<EFBFBD><EFBFBD>Ұ<EFBFBD>𿪷<EFBFBD><EFBFBD><EFBFBD> \r\n");
printf("STM32H7<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>С<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>\r\n");
/* 32M<32><4D><EFBFBD><EFBFBD>flash W25Q256<35><36>ʼ<EFBFBD><CABC> */
QSPI_FLASH_Init();
/* Disable CPU L1 cache before jumping to the QSPI code execution */
CPU_CACHE_Disable();
/* Disable Systick interrupt */
SysTick->CTRL = 0;
/* Initialize user application's Stack Pointer & Jump to user application */
JumpToApplication = (pFunction) (*(__IO uint32_t*) (APPLICATION_ADDRESS + 4));
__set_MSP(*(__IO uint32_t*) APPLICATION_ADDRESS);
JumpToApplication();
/* We should never get here as execution is now on user application */
while(1)
{
}
}
/*
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Buffercmp
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD>Ƚ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>е<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƿ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD>-pBuffer1 src<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><EFBFBD>
* -pBuffer2 dst<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><EFBFBD>
* -BufferLength <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD>-PASSED pBuffer1 <EFBFBD><EFBFBD><EFBFBD><EFBFBD> pBuffer2
* -FAILED pBuffer1 <EFBFBD><EFBFBD>ͬ<EFBFBD><EFBFBD> pBuffer2
*/
TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength)
{
while(BufferLength--)
{
if(*pBuffer1 != *pBuffer2)
{
return FAILED;
}
pBuffer1++;
pBuffer2++;
}
return PASSED;
}
/**
* @brief System Clock <EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* system Clock <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:
* System Clock source = PLL (HSE)
* SYSCLK(Hz) = 480000000 (CPU Clock)
* HCLK(Hz) = 240000000 (AXI and AHBs Clock)
* AHB Prescaler = 2
* D1 APB3 Prescaler = 2 (APB3 Clock 120MHz)
* D2 APB1 Prescaler = 2 (APB1 Clock 120MHz)
* D2 APB2 Prescaler = 2 (APB2 Clock 120MHz)
* D3 APB4 Prescaler = 2 (APB4 Clock 120MHz)
* HSE Frequency(Hz) = 25000000
* PLL_M = 5
* PLL_N = 192
* PLL_P = 2
* PLL_Q = 4
* PLL_R = 2
* VDD(V) = 3.3
* Flash Latency(WS) = 4
* @param None
* @retval None
*/
static void SystemClock_Config(void)
{
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
HAL_StatusTypeDef ret = HAL_OK;
/*ʹ<>ܹ<EFBFBD><DCB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ø<EFBFBD><C3B8><EFBFBD> */
HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ƶ<EFBFBD>ʵ<EFBFBD><CAB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϵͳƵ<CDB3><C6B5>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD>ڿ<EFBFBD><DABF><EFBFBD><EFBFBD>Ż<EFBFBD><C5BB><EFBFBD><EFBFBD>ģ<EFBFBD>
<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϵͳƵ<EFBFBD>ʵĵ<EFBFBD>ѹ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD>ĸ<EFBFBD><EFBFBD>¿<EFBFBD><EFBFBD>Բο<EFBFBD><EFBFBD><EFBFBD>Ʒ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֲᡣ */
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
/* <20><><EFBFBD><EFBFBD>HSE<53><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>HSE<53><45>ΪԴ<CEAA><D4B4><EFBFBD><EFBFBD>PLL */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 5;
RCC_OscInitStruct.PLL.PLLN = 192;
RCC_OscInitStruct.PLL.PLLFRACN = 0;
RCC_OscInitStruct.PLL.PLLP = 2;
RCC_OscInitStruct.PLL.PLLR = 2;
RCC_OscInitStruct.PLL.PLLQ = 4;
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
ret = HAL_RCC_OscConfig(&RCC_OscInitStruct);
if(ret != HAL_OK)
{
while(1) { ; }
}
/* ѡ<><D1A1>PLL<4C><4C>Ϊϵͳʱ<CDB3><CAB1>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>ӷ<EFBFBD>Ƶ<EFBFBD><C6B5> */
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | \
RCC_CLOCKTYPE_HCLK | \
RCC_CLOCKTYPE_D1PCLK1 | \
RCC_CLOCKTYPE_PCLK1 | \
RCC_CLOCKTYPE_PCLK2 | \
RCC_CLOCKTYPE_D3PCLK1);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
ret = HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
if(ret != HAL_OK)
{
while(1) { ; }
}
}
/****************************END OF FILE***************************/
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