ldeyun/STM32H750XB_RT-THREAD
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
master
STM32H750XB_RT-THREAD/45-DCMI—OV2640摄像头实验/User/flash/bsp_qspi_flash.h

213 lines
8.6 KiB
C
Raw Permalink Normal View History

STM32H750 RTThread 例程
2025-07-21 06:34:29 +00:00
#ifndef __SPI_FLASH_H
#define __SPI_FLASH_H
#include "stm32h7xx.h"
#include <stdio.h>
/* Private typedef -----------------------------------------------------------*/
//#define sFLASH_ID 0xEF3015 //W25X16
//#define sFLASH_ID 0xEF4015 //W25Q16
//#define sFLASH_ID 0XEF4017 //W25Q64
//#define sFLASH_ID 0XEF4018 //W25Q128
#define sFLASH_ID 0XEF4019 //W25Q256
/* QSPI Error codes */
#define QSPI_OK ((uint8_t)0x00)
#define QSPI_ERROR ((uint8_t)0x01)
#define QSPI_BUSY ((uint8_t)0x02)
#define QSPI_NOT_SUPPORTED ((uint8_t)0x04)
#define QSPI_SUSPENDED ((uint8_t)0x08)
/* W25Q256JV Micron memory */
/* Size of the flash */
#define QSPI_FLASH_SIZE 24 /* <20><>ַ<EFBFBD><D6B7><EFBFBD>߿<EFBFBD><DFBF>ȷ<EFBFBD><C8B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڴ<EFBFBD><DAB4>ռ<EFBFBD> */
#define QSPI_PAGE_SIZE 256
/* QSPI Info */
typedef struct {
uint32_t FlashSize; /*!< <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>С */
uint32_t EraseSectorSize; /*!< <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>С */
uint32_t EraseSectorsNumber; /*!< <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
uint32_t ProgPageSize; /*!< <20><><EFBFBD>̲<EFBFBD><CCB2><EFBFBD><EFBFBD><EFBFBD>ҳ<EFBFBD><D2B3><EFBFBD><EFBFBD>С */
uint32_t ProgPagesNumber; /*!< <20><><EFBFBD>̲<EFBFBD><CCB2><EFBFBD><EFBFBD><EFBFBD>ҳ<EFBFBD><D2B3><EFBFBD><EFBFBD> */
} QSPI_Info;
/* Private define ------------------------------------------------------------*/
/*<2A><><EFBFBD><EFBFBD><EEB6A8>-<2D><>ͷ*******************************/
/**
* @brief W25Q256JV<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*/
#if USE_DUAL_ExtFLASH
#define W25Q256JV_FLASH_SIZE 0x4000000 /* 512 MBits => 64MBytes */
#endif
#define W25Q256JV_FLASH_SIZE 0x2000000 /* 256 MBits => 32MBytes */
#define W25Q256JV_BLOCK_SIZE 0x10000
#define W25Q256JV_SECTOR_SIZE 0x1000 /* 256 sectors of 64KBytes */
//#define W25Q256JV_SUBSECTOR_SIZE 0x1000 /* 4096 subsectors of 4kBytes */
#define W25Q256JV_PAGE_SIZE 0x100 /* 65536 pages of 256 bytes */
#define W25Q256JV_DUMMY_CYCLES_READ 4
#define W25Q256JV_DUMMY_CYCLES_READ_QUAD 10
#define W25Q256JV_BULK_ERASE_MAX_TIME 250000
#define W25Q256JV_SECTOR_ERASE_MAX_TIME 3000
#define W25Q256JV_SUBSECTOR_ERASE_MAX_TIME 800
/**
* @brief W25Q256JV ָ<EFBFBD><EFBFBD>
*/
/* <20><>λ<EFBFBD><CEBB><EFBFBD><EFBFBD> */
#define RESET_ENABLE_CMD 0x66
#define RESET_MEMORY_CMD 0x99
#define ENTER_QPI_MODE_CMD 0x38
#define EXIT_QPI_MODE_CMD 0xFF
/* ʶ<><CAB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define READ_ID_CMD 0x90
#define DUAL_READ_ID_CMD 0x92
#define QUAD_READ_ID_CMD 0x94
#define READ_JEDEC_ID_CMD 0x9F
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define READ_CMD 0x03
#define READ_CMD_4BYTE 0x13
#define FAST_READ_CMD 0x0B
#define FAST_READ_CMD_4BYTE 0x0C
#define DUAL_OUT_FAST_READ_CMD 0x3B
#define DUAL_INOUT_FAST_READ_CMD 0xBB
#define QUAD_OUT_FAST_READ_CMD 0x6B
#define QUAD_INOUT_FAST_READ_CMD 0xEB
#define QUAD_INOUT_FAST_READ_CMD_4BYTE 0xEC
/* д<><D0B4><EFBFBD><EFBFBD> */
#define WRITE_ENABLE_CMD 0x06
#define WRITE_DISABLE_CMD 0x04
/* <20>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define READ_STATUS_REG1_CMD 0x05
#define READ_STATUS_REG2_CMD 0x35
#define READ_STATUS_REG3_CMD 0x15
#define WRITE_STATUS_REG1_CMD 0x01
#define WRITE_STATUS_REG2_CMD 0x31
#define WRITE_STATUS_REG3_CMD 0x11
/* <20><><EFBFBD>̲<EFBFBD><CCB2><EFBFBD> */
#define PAGE_PROG_CMD 0x02
#define QUAD_INPUT_PAGE_PROG_CMD 0x32
#define Enter_4Byte_Addr_Mode_CMD 0xB7
#define QUAD_INPUT_PAGE_PROG_CMD_4BYTE 0x34
#define EXT_QUAD_IN_FAST_PROG_CMD_4BYTE 0x12
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define SECTOR_ERASE_CMD 0x20 //0xD8<44><38><EFBFBD><EFBFBD>64K 0x52<35><32><EFBFBD><EFBFBD>32K 0x20<32><30><EFBFBD><EFBFBD>4K
#define SECTOR_ERASE_CMD_4BYTE 0x21
#define BLOCK32_ERASE_CMD 0x52
#define BLOCK64_ERASE_CMD 0xD8
#define BLOCK64_ERASE_CMD_4BYTE 0xDC
#define CHIP_ERASE_CMD 0xC7
#define PROG_ERASE_RESUME_CMD 0x7A
#define PROG_ERASE_SUSPEND_CMD 0x75
#define ENTER_4_BYTE_ADDR_MODE_CMD 0xB7
/* ״̬<D7B4>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>־ */
#define W25Q256JV_FSR_BUSY ((uint8_t)0x01) /*!< busy */
#define W25Q256JV_FSR_WREN ((uint8_t)0x02) /*!< write enable */
#define W25Q256JV_FSR_QE ((uint8_t)0x02) /*!< quad enable */
#define W25Q256FV_FSR_4ByteAddrMode ((uint8_t)0x01) /*!< 4<>ֽڵ<D6BD>ַģʽ */
/*<2A><><EFBFBD><EFBFBD><EEB6A8>-<2D><>β*******************************/
/*QSPI<50>ӿڶ<D3BF><DAB6><EFBFBD>-<2D><>ͷ****************************/
#define QSPI_FLASH QUADSPI
#define QSPI_FLASH_CLK_ENABLE() __QSPI_CLK_ENABLE()
#define QSPI_MDMA_CLK_ENABLE() __HAL_RCC_MDMA_CLK_ENABLE()
#define QSPI_FORCE_RESET() __HAL_RCC_QSPI_FORCE_RESET()
#define QSPI_RELEASE_RESET() __HAL_RCC_QSPI_RELEASE_RESET()
#define QSPI_FLASH_CLK_PIN GPIO_PIN_2
#define QSPI_FLASH_CLK_GPIO_PORT GPIOB
#define QSPI_FLASH_CLK_GPIO_ENABLE() __GPIOB_CLK_ENABLE()
#define QSPI_FLASH_CLK_GPIO_AF GPIO_AF9_QUADSPI
#define QSPI_FLASH_BK1_IO0_PIN GPIO_PIN_8
#define QSPI_FLASH_BK1_IO0_PORT GPIOF
#define QSPI_FLASH_BK1_IO0_CLK_ENABLE() __GPIOF_CLK_ENABLE()
#define QSPI_FLASH_BK1_IO0_AF GPIO_AF10_QUADSPI
#define QSPI_FLASH_BK1_IO1_PIN GPIO_PIN_9
#define QSPI_FLASH_BK1_IO1_PORT GPIOF
#define QSPI_FLASH_BK1_IO1_CLK_ENABLE() __GPIOF_CLK_ENABLE()
#define QSPI_FLASH_BK1_IO1_AF GPIO_AF10_QUADSPI
#define QSPI_FLASH_BK1_IO2_PIN GPIO_PIN_7
#define QSPI_FLASH_BK1_IO2_PORT GPIOF
#define QSPI_FLASH_BK1_IO2_CLK_ENABLE() __GPIOF_CLK_ENABLE()
#define QSPI_FLASH_BK1_IO2_AF GPIO_AF9_QUADSPI
#define QSPI_FLASH_BK1_IO3_PIN GPIO_PIN_6
#define QSPI_FLASH_BK1_IO3_PORT GPIOF
#define QSPI_FLASH_BK1_IO3_CLK_ENABLE() __GPIOF_CLK_ENABLE()
#define QSPI_FLASH_BK1_IO3_AF GPIO_AF9_QUADSPI
#define QSPI_FLASH_CS_PIN GPIO_PIN_6
#define QSPI_FLASH_CS_GPIO_PORT GPIOG
#define QSPI_FLASH_CS_GPIO_CLK_ENABLE() __GPIOG_CLK_ENABLE()
#define QSPI_FLASH_CS_GPIO_AF GPIO_AF10_QUADSPI
/*QSPI BANK2<4B>ӿڶ<D3BF><DAB6><EFBFBD>-<2D><>ͷ****************************/
#define QSPI_FLASH_BK2_IO0_PIN GPIO_PIN_2
#define QSPI_FLASH_BK2_IO0_PORT GPIOH
#define QSPI_FLASH_BK2_IO0_CLK_ENABLE() __GPIOH_CLK_ENABLE()
#define QSPI_FLASH_BK2_IO0_AF GPIO_AF9_QUADSPI
#define QSPI_FLASH_BK2_IO1_PIN GPIO_PIN_3
#define QSPI_FLASH_BK2_IO1_PORT GPIOH
#define QSPI_FLASH_BK2_IO1_CLK_ENABLE() __GPIOH_CLK_ENABLE()
#define QSPI_FLASH_BK2_IO1_AF GPIO_AF9_QUADSPI
#define QSPI_FLASH_BK2_IO2_PIN GPIO_PIN_9
#define QSPI_FLASH_BK2_IO2_PORT GPIOG
#define QSPI_FLASH_BK2_IO2_CLK_ENABLE() __GPIOG_CLK_ENABLE()
#define QSPI_FLASH_BK2_IO2_AF GPIO_AF9_QUADSPI
#define QSPI_FLASH_BK2_IO3_PIN GPIO_PIN_14
#define QSPI_FLASH_BK2_IO3_PORT GPIOG
#define QSPI_FLASH_BK2_IO3_CLK_ENABLE() __GPIOG_CLK_ENABLE()
#define QSPI_FLASH_BK2_IO3_AF GPIO_AF9_QUADSPI
void QSPI_FLASH_Init(void);
uint8_t BSP_QSPI_Init(void);
uint8_t BSP_QSPI_Erase_Sector(uint32_t SectorAddress);
uint8_t BSP_QSPI_Erase_Block32(uint32_t BlockAddress);
uint8_t BSP_QSPI_Erase_Block64(uint32_t BlockAddress);
uint8_t BSP_QSPI_Erase_Chip(void);
uint8_t BSP_QSPI_FastRead(uint8_t* pData, uint32_t ReadAddr, uint32_t Size);
uint8_t BSP_QSPI_Read(uint8_t* pData, uint32_t ReadAddr, uint32_t Size);
uint8_t BSP_QSPI_Write(uint8_t* pData, uint32_t WriteAddr, uint32_t Size);
uint32_t QSPI_EnableMemoryMappedMode(void); //ʹ<><CAB9><EFBFBD>ڴ<EFBFBD>ӳ<EFBFBD><D3B3>ģʽ
static uint8_t QSPI_ResetMemory(void);
static uint8_t QSPI_WriteEnable(void);
static uint8_t QSPI_AutoPollingMemReady(uint32_t Timeout);
uint32_t QSPI_FLASH_ReadDeviceID(void);
uint32_t QSPI_FLASH_ReadID(void);
uint32_t QSPI_FLASH_ReadStatusReg(uint8_t reg);
uint32_t QSPI_FLASH_WriteStatusReg(uint8_t reg,uint8_t regvalue);
void QSPI_Set_WP_High(void);
void QSPI_Set_WP_TO_QSPI_IO(void);
#endif /* __SPI_FLASH_H */
Reference in New Issue Copy Permalink