86 lines
2.2 KiB
C
86 lines
2.2 KiB
C
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#ifndef __BSP_MPU_H__
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#define __BSP_MPU_H__
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#include "stm32h7xx_hal.h"
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//<2F><><EFBFBD><EFBFBD>MPU->RASR<53>Ĵ<EFBFBD><C4B4><EFBFBD>AP[26:24]λ<><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
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#define MPU_1KB MPU_REGION_SIZE_1KB
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#define MPU_2KB MPU_REGION_SIZE_2KB
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#define MPU_4KB MPU_REGION_SIZE_4KB
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#define MPU_8KB MPU_REGION_SIZE_8KB
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#define MPU_16KB MPU_REGION_SIZE_16KB
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#define MPU_32KB MPU_REGION_SIZE_32KB
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#define MPU_64KB MPU_REGION_SIZE_64KB
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#define MPU_128KB MPU_REGION_SIZE_128KB
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#define MPU_256KB MPU_REGION_SIZE_256KB
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#define MPU_512KB MPU_REGION_SIZE_512KB
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#define MPU_1MB MPU_REGION_SIZE_1MB
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#define MPU_2MB MPU_REGION_SIZE_2MB
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#define MPU_4MB MPU_REGION_SIZE_4MB
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#define MPU_8MB MPU_REGION_SIZE_8MB
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#define MPU_16MB MPU_REGION_SIZE_16MB
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#define MPU_32MB MPU_REGION_SIZE_32MB
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#define MPU_64MB MPU_REGION_SIZE_64MB
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#define MPU_128MB MPU_REGION_SIZE_128MB
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#define MPU_256MB MPU_REGION_SIZE_256MB
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#define MPU_512MB MPU_REGION_SIZE_512MB
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#define MPU_NO_ACCESS ((uint8_t)0x00U)
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#define MPU_PRIV_RW ((uint8_t)0x01U)
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#define MPU_PRIV_RW_URO ((uint8_t)0x02U)
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#define MPU_FULL_ACCESS ((uint8_t)0x03U)
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#define MPU_PRIV_RO ((uint8_t)0x05U)
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#define MPU_PRIV_RO_URO ((uint8_t)0x06U)
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/*<2A><><EFBFBD><EFBFBD>ΪNormal<61><6C>cache<68><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ write-back<63><6B><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cache<68><65>
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*<EFBFBD>ں<EFBFBD><EFBFBD>ʵ<EFBFBD>ʱ<EFBFBD><EFBFBD>(<EFBFBD><EFBFBD>cache<EFBFBD><EFBFBD><EFBFBD>Ծ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ǿ<EFBFBD>Ƹ<EFBFBD><EFBFBD><EFBFBD>)<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݸ<EFBFBD><EFBFBD>µ<EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><EFBFBD>SRAM<EFBFBD>ռ<EFBFBD>
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*<EFBFBD>ر<EFBFBD>ע<EFBFBD>⣺<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>£<EFBFBD>д֮<EFBFBD><EFBFBD>ҪSCB_CleanDCache<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱҪSCB_InvalidateDCache
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*/
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#define MPU_Normal_WB 0x00
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/*<2A><><EFBFBD><EFBFBD>ΪNormal<61><6C>cache<68><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ write-back<63><6B><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cache<68><65>
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*<EFBFBD>ں<EFBFBD><EFBFBD>ʵ<EFBFBD>ʱ<EFBFBD><EFBFBD>(<EFBFBD><EFBFBD>cache<EFBFBD><EFBFBD><EFBFBD>Ծ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ǿ<EFBFBD>Ƹ<EFBFBD><EFBFBD><EFBFBD>)<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݸ<EFBFBD><EFBFBD>µ<EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><EFBFBD>SRAM<EFBFBD>ռ<EFBFBD>
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*<EFBFBD>ر<EFBFBD>ע<EFBFBD>⣺<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>£<EFBFBD>д֮<EFBFBD><EFBFBD>ҪSCB_CleanDCache<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱҪSCB_InvalidateDCache
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*/
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#define MPU_Normal_WBWARA 0x01 //<2F>ⲿ<EFBFBD><E2B2BF><EFBFBD>ڲ<EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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/*<2A><><EFBFBD><EFBFBD>Ϊ normal<61><6C>cache<68><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ Write-through<67><68><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cache<68><65>ͬʱ<CDAC><CAB1>
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*<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͬʱд<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD>ռ<EFBFBD>
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*<EFBFBD>ر<EFBFBD>ע<EFBFBD>⣺<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>£<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڴ<EFBFBD>д<EFBFBD><EFBFBD><EFBFBD>ݣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱҪSCB_InvalidateDCache
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*/
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#define MPU_Normal_WT 0x02
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/*<2A><><EFBFBD><EFBFBD>Ϊ normal<61><6C><EFBFBD><EFBFBD><EFBFBD>ù<EFBFBD><C3B9><EFBFBD>,<2C><><EFBFBD>û<EFBFBD><C3BB><EFBFBD>
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*/
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#define MPU_Normal_NonCache 0x03
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/*<2A><><EFBFBD><EFBFBD>Ϊ Device<63><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD><EFBFBD>ù<EFBFBD><C3B9><EFBFBD>,<2C><><EFBFBD>û<EFBFBD><C3BB><EFBFBD>
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*/
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#define MPU_Device_NonCache 0x04
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void Board_MPU_Config(uint8_t Region ,uint8_t Mode,uint32_t Address,uint32_t Size);
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#endif
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