105 lines
3.3 KiB
C
105 lines
3.3 KiB
C
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/**
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******************************************************************
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* @file main.c
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* @author fire
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* @version V1.0
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* @date 2018-xx-xx
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* @brief <EFBFBD><EFBFBD>V1.2.0<EFBFBD>汾<EFBFBD>⽨<EFBFBD>Ĺ<EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><EFBFBD>
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******************************************************************
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* @attention
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*
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* ʵ<EFBFBD><EFBFBD>ƽ̨:Ұ<EFBFBD><EFBFBD> STM32H750 <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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* <EFBFBD><EFBFBD>̳ :http://www.firebbs.cn
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* <EFBFBD>Ա<EFBFBD> :http://firestm32.taobao.com
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*
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******************************************************************
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*/
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#include "stm32h7xx.h"
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#include "main.h"
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#include "./delay/core_delay.h"
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/**
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* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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* @param <EFBFBD><EFBFBD>
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* @retval <EFBFBD><EFBFBD>
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*/
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int main(void)
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{
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/* ϵͳʱ<CDB3>ӳ<EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>480MHz */
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SystemClock_Config();
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/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD>^_^. */
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while(1)
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{
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}
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}
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/**
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* @brief System Clock <EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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* system Clock <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:
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* System Clock source = PLL (HSE)
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* SYSCLK(Hz) = 480000000 (CPU Clock)
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* HCLK(Hz) = 240000000 (AXI and AHBs Clock)
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* AHB Prescaler = 2
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* D1 APB3 Prescaler = 2 (APB3 Clock 120MHz)
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* D2 APB1 Prescaler = 2 (APB1 Clock 120MHz)
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* D2 APB2 Prescaler = 2 (APB2 Clock 120MHz)
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* D3 APB4 Prescaler = 2 (APB4 Clock 120MHz)
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* HSE Frequency(Hz) = 25000000
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* PLL_M = 5
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* PLL_N = 192
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* PLL_P = 2
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* PLL_Q = 4
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* PLL_R = 2
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* VDD(V) = 3.3
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* Flash Latency(WS) = 4
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* @param None
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* @retval None
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*/
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void SystemClock_Config(void)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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/** <20><><EFBFBD>õ<EFBFBD>Դ<EFBFBD><D4B4><EFBFBD>ø<EFBFBD><C3B8><EFBFBD>
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*/
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HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
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/**<2A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѹ
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*/
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
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while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
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/** <20><>ʼ<EFBFBD><CABC>CPU<50><55>AHB<48><42>APB<50><42><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = 5;
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RCC_OscInitStruct.PLL.PLLN = 192;
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RCC_OscInitStruct.PLL.PLLP = 2;
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RCC_OscInitStruct.PLL.PLLQ = 2;
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RCC_OscInitStruct.PLL.PLLR = 2;
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RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
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RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
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RCC_OscInitStruct.PLL.PLLFRACN = 0;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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{
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}
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/** <20><>ʼ<EFBFBD><CABC>CPU<50><55>AHB<48><42>APB<50><42><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
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|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
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|RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
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RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
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RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
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{
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}
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}
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/****************************END OF FILE***************************/
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