688 lines
39 KiB
C
688 lines
39 KiB
C
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/**
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******************************************************************************
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* @file stm32h7xx_hal_tim_ex.h
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* @author MCD Application Team
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* @version V1.2.0
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* @date 29-December-2017
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* @brief Header file of TIM HAL Extended module.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32H7xx_HAL_TIM_EX_H
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#define __STM32H7xx_HAL_TIM_EX_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32h7xx_hal_def.h"
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/** @addtogroup STM32H7xx_HAL_Driver
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* @{
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*/
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/** @addtogroup TIMEx
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
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* @{
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*/
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/**
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* @brief TIM Hall sensor Configuration Structure definition
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*/
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typedef struct
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{
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uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
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This parameter can be a value of @ref TIM_Input_Capture_Polarity */
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uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
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This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
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uint32_t IC1Filter; /*!< Specifies the input capture filter.
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This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
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This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
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} TIM_HallSensor_InitTypeDef;
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/**
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* @brief TIM Break/Break2 input configuration
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*/
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typedef struct {
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uint32_t Source; /*!< Specifies the source of the timer break input.
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This parameter can be a value of @ref TIMEx_Break_Input_Source */
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uint32_t Enable; /*!< Specifies whether or not the break input source is enabled.
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This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
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uint32_t Polarity; /*!< Specifies the break input source polarity.
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This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity
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Not relevant when analog watchdog output of the DFSDM1 used as break input source */
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} TIMEx_BreakInputConfigTypeDef;
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
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* @{
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*/
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/** @defgroup TIMEx_Channel TIM Extended Channel
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* @{
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*/
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#define TIM_CHANNEL_1 ((uint32_t)0x0000U) /*!< TIM Channel 1*/
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#define TIM_CHANNEL_2 ((uint32_t)0x0004U) /*!< TIM Channel 2*/
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#define TIM_CHANNEL_3 ((uint32_t)0x0008U) /*!< TIM Channel 3*/
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#define TIM_CHANNEL_4 ((uint32_t)0x000CU) /*!< TIM Channel 4*/
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#define TIM_CHANNEL_5 ((uint32_t)0x0010U) /*!< TIM Channel 5*/
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#define TIM_CHANNEL_6 ((uint32_t)0x0014U) /*!< TIM Channel 6*/
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#define TIM_CHANNEL_ALL ((uint32_t)0x003CU) /*!< TIM all Channels */
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/**
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* @}
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*/
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/** @defgroup TIMEx_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
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* @{
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*/
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#define TIM_OCMODE_TIMING ((uint32_t)0x0000U) /*!< TIM Output timing mode */
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#define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0) /*!< TIM Output Active mode */
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#define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1) /*!< TIM Output Inactive mode */
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#define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< TIM Output Toggle mode */
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#define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< TIM PWM mode 1 */
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#define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< TIM PWM mode 2 */
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#define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< TIM Forced Active mode */
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#define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2) /*!< TIM Forced Inactive mode */
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#define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3) /*!< TIM Rettrigerrable OPM mode 1 */
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#define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< TIM Rettrigerrable OPM mode 2 */
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#define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< TIM Combined PWM mode 1 */
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#define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< TIM Combined PWM mode 2 */
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#define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< TIM Asymetruc PWM mode 1 */
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#define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!< TIM Asymetruc PWM mode 2 */
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/**
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* @}
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*/
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/** @defgroup TIMEx_ClearInput_Source TIM Extended Clear Input Source
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* @{
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*/
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#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001U) /*!< TIM Clear input source connected to ETR */
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#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002U) /*!< TIM Clear input source connected to OCREFClear */
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#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000U) /*!< TIM Clear input source None */
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/**
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* @}
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*/
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/** @defgroup TIMEx_Break2_Input_enable_disable TIMEX Break input 2 Enable
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* @{
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*/
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#define TIM_BREAK2_DISABLE ((uint32_t)0x00000000U) /*!< TIM Break2 disabled */
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#define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E) /*!< TIM Break2 enabled */
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/**
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* @}
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*/
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/** @defgroup TIMEx_Break2_Polarity TIM Extended Break Input 2 Polarity
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* @{
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*/
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#define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000U) /*!< TIM Break2 polarity low */
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#define TIM_BREAK2POLARITY_HIGH ((uint32_t)TIM_BDTR_BK2P) /*!< TIM Break2 polarity high */
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/**
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* @}
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*/
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/** @defgroup TIMEx_Trigger_Selection TIM Trigger Selection
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* @{
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*/
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#define TIM_TS_ITR4 ((uint32_t)0x0100000) /*!< TIM Internal trigger 4 */
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#define TIM_TS_ITR5 ((uint32_t)0x0100010) /*!< TIM Internal trigger 5 */
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#define TIM_TS_ITR6 ((uint32_t)0x0100020) /*!< TIM Internal trigger 6 */
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#define TIM_TS_ITR7 ((uint32_t)0x0100030) /*!< TIM Internal trigger 7 */
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#define TIM_TS_ITR8 ((uint32_t)0x0100040) /*!< TIM Internal trigger 8 */
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/**
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* @}
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*/
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/** @defgroup TIM_Event_Source TIM Extended Event Source
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* @{
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*/
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#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
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#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
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#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
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#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
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#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
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#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
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#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
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#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
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#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */
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/**
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* @}
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*/
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/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
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* @{
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*/
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#define TIM_DMABASE_CR1 (0x00000000U) /*!< TIM DMA Base Address is CR1 */
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#define TIM_DMABASE_CR2 (0x00000001U) /*!< TIM DMA Base Address is CR2 */
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#define TIM_DMABASE_SMCR (0x00000002U) /*!< TIM DMA Base Address is SMCR */
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#define TIM_DMABASE_DIER (0x00000003U) /*!< TIM DMA Base Address is DIER */
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#define TIM_DMABASE_SR (0x00000004U) /*!< TIM DMA Base Address is SR */
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#define TIM_DMABASE_EGR (0x00000005U) /*!< TIM DMA Base Address is EGR */
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#define TIM_DMABASE_CCMR1 (0x00000006U) /*!< TIM DMA Base Address is CCMR1 */
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#define TIM_DMABASE_CCMR2 (0x00000007U) /*!< TIM DMA Base Address is CCMR2*/
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#define TIM_DMABASE_CCER (0x00000008U) /*!< TIM DMA Base Address is CCER */
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#define TIM_DMABASE_CNT (0x00000009U) /*!< TIM DMA Base Address is CNT */
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#define TIM_DMABASE_PSC (0x0000000AU) /*!< TIM DMA Base Address is PSC */
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#define TIM_DMABASE_ARR (0x0000000BU) /*!< TIM DMA Base Address is ARR */
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#define TIM_DMABASE_RCR (0x0000000CU) /*!< TIM DMA Base Address is RCR */
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#define TIM_DMABASE_CCR1 (0x0000000DU) /*!< TIM DMA Base Address is CCR1 */
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#define TIM_DMABASE_CCR2 (0x0000000EU) /*!< TIM DMA Base Address is CCR2 */
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#define TIM_DMABASE_CCR3 (0x0000000FU) /*!< TIM DMA Base Address is CCR3 */
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#define TIM_DMABASE_CCR4 (0x00000010U) /*!< TIM DMA Base Address is CCR3 */
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#define TIM_DMABASE_BDTR (0x00000011U) /*!< TIM DMA Base Address is BDTR */
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#define TIM_DMABASE_DCR (0x00000012U) /*!< TIM DMA Base Address is DCR */
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#define TIM_DMABASE_DMAR (0x00000013U) /*!< TIM DMA Base Address is DMAR */
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#define TIM_DMABASE_AF1 (0x00000014U) /*!< TIM DMA Base Address is AF1 */
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#define TIM_DMABASE_CCMR3 (0x00000015U) /*!< TIM DMA Base Address is CCMR3 */
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#define TIM_DMABASE_CCR5 (0x00000016U) /*!< TIM DMA Base Address is CCR5 */
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#define TIM_DMABASE_CCR6 (0x00000017U) /*!< TIM DMA Base Address is CCR6 */
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#define TIM_DMABASE_AF2 (0x00000018U) /*!< TIM DMA Base Address is AF2 */
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#define TIM_DMABASE_AF3 (0x00000019U) /*!< TIM DMA Base Address is AF3 */
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#define TIM_DMABASE_TISEL (0x0000001AU) /*!< TIM DMA Base Address is TISEL */
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/**
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* @}
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*/
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/** @defgroup TIMEx_Remap TIM Extended Remapping
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* @{
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*/
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#define TIM_TIM1_ETR_GPIO (0x00000000) /* !< TIM1_ETR is connected to GPIO */
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#define TIM_TIM1_ETR_ADC1_AWD1 (0x0000C000) /* !< TIM1_ETR is connected to ADC1 AWD1 */
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#define TIM_TIM1_ETR_ADC1_AWD2 (0x00010000) /* !< TIM1_ETR is connected to ADC1 AWD2 */
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#define TIM_TIM1_ETR_ADC1_AWD3 (0x00014000) /* !< TIM1_ETR is connected to ADC1 AWD3 */
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#define TIM_TIM1_ETR_ADC3_AWD1 (0x00018000) /* !< TIM1_ETR is connected to ADC3 AWD1 */
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#define TIM_TIM1_ETR_ADC3_AWD2 (0x0001C000) /* !< TIM1_ETR is connected to ADC3 AWD2 */
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#define TIM_TIM1_ETR_ADC3_AWD3 (0x00020000) /* !< TIM1_ETR is connected to ADC3 AWD3 */
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#define TIM_TIM1_ETR_COMP1_OUT (0x00004000) /* !< TIM1_ETR is connected to COMP1 OUT */
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#define TIM_TIM1_ETR_COMP2_OUT (0x00008000) /* !< TIM1_ETR is connected to COMP2 OUT */
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#define TIM_TIM8_ETR_GPIO (0x00000000) /* !< TIM8_ETR is connected to GPIO */
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#define TIM_TIM8_ETR_ADC2_AWD1 (0x0000C000) /* !< TIM8_ETR is connected to ADC2 AWD1 */
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#define TIM_TIM8_ETR_ADC2_AWD2 (0x00010000) /* !< TIM8_ETR is connected to ADC2 AWD2 */
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#define TIM_TIM8_ETR_ADC2_AWD3 (0x00014000) /* !< TIM8_ETR is connected to ADC2 AWD3 */
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#define TIM_TIM8_ETR_ADC3_AWD1 (0x00018000) /* !< TIM8_ETR is connected to ADC3 AWD1 */
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#define TIM_TIM8_ETR_ADC3_AWD2 (0x0001C000) /* !< TIM8_ETR is connected to ADC3 AWD2 */
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#define TIM_TIM8_ETR_ADC3_AWD3 (0x00020000) /* !< TIM8_ETR is connected to ADC3 AWD3 */
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#define TIM_TIM8_ETR_COMP1_OUT (0x00004000) /* !< TIM8_ETR is connected to COMP1 OUT */
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#define TIM_TIM8_ETR_COMP2_OUT (0x00008000) /* !< TIM8_ETR is connected to COMP2 OUT */
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#define TIM_TIM2_ETR_GPIO (0x00000000) /* !< TIM2_ETR is connected to GPIO */
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#define TIM_TIM2_ETR_COMP1_OUT (0x0000C000) /* !< TIM2_ETR is connected to COMP1 OUT */
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#define TIM_TIM2_ETR_COMP2_OUT (0x00010000) /* !< TIM2_ETR is connected to COMP2 OUT */
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#define TIM_TIM2_ETR_RCC_LSE (0x00014000) /* !< TIM2_ETR is connected to RCC LSE */
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#define TIM_TIM2_ETR_SAI1_FSA (0x00018000) /* !< TIM2_ETR is connected to SAI1 FS_A */
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#define TIM_TIM2_ETR_SAI1_FSB (0x0001C000) /* !< TIM2_ETR is connected to SAI1 FS_B */
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#define TIM_TIM3_ETR_GPIO (0x00000000) /* !< TIM3_ETR is connected to GPIO */
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#define TIM_TIM3_ETR_COMP1_OUT (0x00000000) /* !< TIM3_ETR is connected to COMP1 OUT */
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#define TIM_TIM5_ETR_GPIO (0x00000000) /* !< TIM5_ETR is connected to GPIO */
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#define TIM_TIM5_ETR_SAI2_FSA (0x00000000) /* !< TIM5_ETR is connected to SAI2 FS_A */
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#define TIM_TIM5_ETR_SAI2_FSB (0x00000000) /* !< TIM5_ETR is connected to SAI2 FS_B */
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#define TIM_TIM1_BKR_GPIO (0x00000000) /* !< TIM1_BKR is connected to GPIO */
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#define TIM_TIM1_BKR_COMP1_OUT (0x00000002) /* !< TIM1_BKR is connected to COMP1 OUT */
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#define TIM_TIM1_BKR_COMP2_OUT (0x00000004) /* !< TIM1_BKR is connected to COMP2 OUT */
|
||
|
|
#define TIM_TIM1_BKR_DFSDM_BRK0 (0x00000000) /* !< TIM1_BKR is connected to DFSDM BRK0 */
|
||
|
|
|
||
|
|
#define TIM_TIM8_BKR_GPIO (0x00000000) /* !< TIM8_BKR is connected to GPIO */
|
||
|
|
#define TIM_TIM8_BKR_COMP1_OUT (0x00000002) /* !< TIM8_BKR is connected to COMP1 OUT */
|
||
|
|
#define TIM_TIM8_BKR_COMP2_OUT (0x00000004) /* !< TIM8_BKR is connected to COMP2 OUT */
|
||
|
|
#define TIM_TIM8_BKR_DFSDM_BRK2 (0x00000000) /* !< TIM8_BKR is connected to DFSDM BRK2 */
|
||
|
|
|
||
|
|
#define TIM_TIM15_BKR_GPIO (0x00000000) /* !< TIM15_BKR is connected to GPIO */
|
||
|
|
#define TIM_TIM15_BKR_COMP1_OUT (0x00000002) /* !< TIM15_BKR is connected to COMP1 OUT */
|
||
|
|
#define TIM_TIM15_BKR_COMP2_OUT (0x00000004) /* !< TIM15_BKR is connected to COMP2 OUT */
|
||
|
|
#define TIM_TIM15_BKR_DFSDM_BRK0 (0x00000000) /* !< TIM15_BKR is connected to DFSDM BRK0 */
|
||
|
|
|
||
|
|
#define TIM_TIM16_BKR_GPIO (0x00000000) /* !< TIM16_BKR is connected to GPIO */
|
||
|
|
#define TIM_TIM16_BKR_COMP1_OUT (0x00000002) /* !< TIM16_BKR is connected to COMP1 OUT */
|
||
|
|
#define TIM_TIM16_BKR_COMP2_OUT (0x00000004) /* !< TIM16_BKR is connected to COMP2 OUT */
|
||
|
|
#define TIM_TIM16_BKR_DFSDM_BRK1 (0x00000000) /* !< TIM16_BKR is connected to DFSDM BRK1 */
|
||
|
|
|
||
|
|
#define TIM_TIM17_BKR_GPIO (0x00000000) /* !< TIM17_BKR is connected to GPIO */
|
||
|
|
#define TIM_TIM17_BKR_COMP1_OUT (0x00000002) /* !< TIM17_BKR is connected to COMP1 OUT */
|
||
|
|
#define TIM_TIM17_BKR_COMP2_OUT (0x00000004) /* !< TIM17_BKR is connected to COMP2 OUT */
|
||
|
|
#define TIM_TIM17_BKR_DFSDM_BRK2 (0x00000000) /* !< TIM17_BKR is connected to DFSDM BRK2 */
|
||
|
|
|
||
|
|
#define TIM_TIM1_BKR2_GPIO (0x00000000) /* !< TIM1_BKR2 is connected to GPIO */
|
||
|
|
#define TIM_TIM1_BKR2_COMP1_OUT (0x00000002) /* !< TIM1_BKR2 is connected to COMP1 OUT */
|
||
|
|
#define TIM_TIM1_BKR2_COMP2_OUT (0x00000004) /* !< TIM1_BKR2 is connected to COMP2 OUT */
|
||
|
|
#define TIM_TIM1_BKR2_DFSDM_BRK1 (0x00000000) /* !< TIM1_BKR2 is connected to DFSDM BRK0 */
|
||
|
|
|
||
|
|
#define TIM_TIM8_BKR2_GPIO (0x00000000) /* !< TIM8_BKR2 is connected to GPIO */
|
||
|
|
#define TIM_TIM8_BKR2_COMP1_OUT (0x00000002) /* !< TIM8_BKR2 is connected to COMP1 OUT */
|
||
|
|
#define TIM_TIM8_BKR2_COMP2_OUT (0x00000004) /* !< TIM8_BKR2 is connected to COMP2 OUT */
|
||
|
|
#define TIM_TIM8_BKR2_DFSDM_BRK3 (0x00000000) /* !< TIM8_BKR2 is connected to DFSDM BRK3 */
|
||
|
|
|
||
|
|
#define TIM_TIM1_TI1_GPIO (0x00000000) /* !< TIM1_TI1 is connected to GPIO */
|
||
|
|
#define TIM_TIM1_TI1_COMP1_OUT (0x00000001) /* !< TIM1_TI1 is connected to COMP1 OUT */
|
||
|
|
|
||
|
|
#define TIM_TIM8_TI1_GPIO (0x00000000) /* !< TIM8_TI1 is connected to GPIO */
|
||
|
|
#define TIM_TIM8_TI1_COMP2_OUT (0x00000001) /* !< TIM8_TI1 is connected to COMP2 OUT */
|
||
|
|
|
||
|
|
#define TIM_TIM2_TI4_GPIO (0x00000000) /* !< TIM2_TI4 is connected to GPIO */
|
||
|
|
#define TIM_TIM2_TI4_COMP1_OUT (0x01000000) /* !< TIM2_TI4 is connected to COMP1 OUT */
|
||
|
|
#define TIM_TIM2_TI4_COMP2_OUT (0x02000000) /* !< TIM2_TI4 is connected to COMP2 OUT */
|
||
|
|
#define TIM_TIM2_TI4_COMP1COMP2_OUT (0x03000000) /* !< TIM2_TI4 is connected to COMP2 OUT OR COMP2 OUT */
|
||
|
|
|
||
|
|
#define TIM_TIM3_TI1_GPIO (0x00000000) /* !< TIM3_TI1 is connected to GPIO */
|
||
|
|
#define TIM_TIM3_TI1_COMP1_OUT (0x00000001) /* !< TIM3_TI1 is connected to COMP1 OUT */
|
||
|
|
#define TIM_TIM3_TI1_COMP2_OUT (0x00000002) /* !< TIM3_TI1 is connected to COMP2 OUT */
|
||
|
|
#define TIM_TIM3_TI1_COMP1COMP2_OUT (0x00000003) /* !< TIM3_TI1 is connected to COMP2 OUT OR COMP2 OUT */
|
||
|
|
|
||
|
|
#define TIM_TIM5_TI1_GPIO (0x00000000) /* !< TIM5_TI1 is connected to GPIO */
|
||
|
|
#define TIM_TIM5_TI1_CAN_TMP (0x00000001) /* !< TIM5_TI1 is connected to CAN TMP */
|
||
|
|
#define TIM_TIM5_TI1_CAN_RTP (0x00000002) /* !< TIM5_TI1 is connected to CAN RTP */
|
||
|
|
|
||
|
|
#define TIM_TIM15_TI1_GPIO (0x00000000) /* !< TIM15_TI1 is connected to GPIO */
|
||
|
|
#define TIM_TIM15_TI1_TIM2_CH1 (0x00000001) /* !< TIM15_TI1 is connected to TIM2 CH1 */
|
||
|
|
#define TIM_TIM15_TI1_TIM3_CH1 (0x00000002) /* !< TIM15_TI1 is connected to TIM3 CH1 */
|
||
|
|
#define TIM_TIM15_TI1_TIM4_CH1 (0x00000003) /* !< TIM15_TI1 is connected to TIM4 CH1 */
|
||
|
|
#define TIM_TIM15_TI1_RCC_LSE (0x00000004) /* !< TIM15_TI1 is connected to RCC LSE */
|
||
|
|
#define TIM_TIM15_TI1_RCC_CSI (0x00000005) /* !< TIM15_TI1 is connected to RCC CSI */
|
||
|
|
#define TIM_TIM15_TI1_RCC_MCO2 (0x00000006) /* !< TIM15_TI1 is connected to RCC MCO2 */
|
||
|
|
|
||
|
|
#define TIM_TIM15_TI2_GPIO (0x00000000) /* !< TIM15_TI2 is connected to GPIO */
|
||
|
|
#define TIM_TIM15_TI2_TIM2_CH2 (0x00000100) /* !< TIM15_TI2 is connected to TIM2 CH2 */
|
||
|
|
#define TIM_TIM15_TI2_TIM3_CH2 (0x00000200) /* !< TIM15_TI2 is connected to TIM3 CH2 */
|
||
|
|
#define TIM_TIM15_TI2_TIM4_CH2 (0x00000300) /* !< TIM15_TI2 is connected to TIM4 CH2 */
|
||
|
|
|
||
|
|
#define TIM_TIM16_TI1_GPIO (0x00000000) /* !< TIM16 TI1 is connected to GPIO */
|
||
|
|
#define TIM_TIM16_TI1_RCC_LSI (0x00000001) /* !< TIM16 TI1 is connected to RCC LSI */
|
||
|
|
#define TIM_TIM16_TI1_RCC_LSE (0x00000002) /* !< TIM16 TI1 is connected to RCC LSE */
|
||
|
|
#define TIM_TIM16_TI1_WKUP_IT (0x00000003) /* !< TIM16 TI1 is connected to WKUP_IT */
|
||
|
|
|
||
|
|
#define TIM_TIM17_TI1_GPIO (0x00000000) /* !< TIM17 TI1 is connected to GPIO */
|
||
|
|
#define TIM_TIM17_TI1_SPDIF_FS (0x00000001) /* !< TIM17 TI1 is connected to RCC LSI */
|
||
|
|
#define TIM_TIM17_TI1_RCC_HSE1MHZ (0x00000002) /* !< TIM17 TI1 is connected to RCC LSE */
|
||
|
|
#define TIM_TIM17_TI1_RCC_MCO1 (0x00000003) /* !< TIM17 TI1 is connected to RCC MCO1 */
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup TIMEx_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define TIM_GROUPCH5_NONE (uint32_t)0x00000000 /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
|
||
|
|
#define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
|
||
|
|
#define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
|
||
|
|
#define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
|
||
|
|
|
||
|
|
|
||
|
|
/** @defgroup TIMEx_Break_Input TIM Extended Break input
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define TIM_BREAKINPUT_BRK ((uint32_t)(0x00000001)) /* !< Timer break input */
|
||
|
|
#define TIM_BREAKINPUT_BRK2 ((uint32_t)(0x00000002)) /* !< Timer break2 input */
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define TIM_BREAKINPUTSOURCE_BKIN ((uint32_t)(0x00000001)) /* !< An external source (GPIO) is connected to the BKIN pin */
|
||
|
|
#define TIM_BREAKINPUTSOURCE_COMP1 ((uint32_t)(0x00000002)) /* !< The COMP1 output is connected to the break input */
|
||
|
|
#define TIM_BREAKINPUTSOURCE_COMP2 ((uint32_t)(0x00000004)) /* !< The COMP2 output is connected to the break input */
|
||
|
|
#define TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)(0x00000008)) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define TIM_BREAKINPUTSOURCE_DISABLE ((uint32_t)(0x00000000)) /* !< Break input source is disabled */
|
||
|
|
#define TIM_BREAKINPUTSOURCE_ENABLE ((uint32_t)(0x00000001)) /* !< Break input source is enabled */
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define TIM_BREAKINPUTSOURCE_POLARITY_LOW ((uint32_t)(0x00000001)) /* !< Break input source is active low */
|
||
|
|
#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH ((uint32_t)(0x00000000)) /* !< Break input source is active_high */
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* Exported macro ------------------------------------------------------------*/
|
||
|
|
/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* Private macro -------------------------------------------------------------*/
|
||
|
|
/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define IS_TIM_REMAP(__REMAP__) (((__REMAP__) <= (uint32_t)0x0001C01F))
|
||
|
|
|
||
|
|
#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \
|
||
|
|
((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
|
||
|
|
|
||
|
|
#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
|
||
|
|
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
|
||
|
|
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
|
||
|
|
((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1))
|
||
|
|
|
||
|
|
#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \
|
||
|
|
((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
|
||
|
|
|
||
|
|
#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \
|
||
|
|
((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
|
||
|
|
|
||
|
|
#define IS_TIM_TISEL(TISEL) (((TISEL) == TIM_TIM1_TI1_GPIO) ||\
|
||
|
|
((TISEL) == TIM_TIM1_TI1_COMP1_OUT) ||\
|
||
|
|
((TISEL) == TIM_TIM8_TI1_GPIO) ||\
|
||
|
|
((TISEL) == TIM_TIM8_TI1_COMP2_OUT) ||\
|
||
|
|
((TISEL) == TIM_TIM2_TI4_GPIO) ||\
|
||
|
|
((TISEL) == TIM_TIM2_TI4_COMP1_OUT) ||\
|
||
|
|
((TISEL) == TIM_TIM2_TI4_COMP2_OUT) ||\
|
||
|
|
((TISEL) == TIM_TIM2_TI4_COMP1COMP2_OUT) ||\
|
||
|
|
((TISEL) == TIM_TIM3_TI1_GPIO) ||\
|
||
|
|
((TISEL) == TIM_TIM3_TI1_COMP1_OUT) ||\
|
||
|
|
((TISEL) == TIM_TIM3_TI1_COMP2_OUT) ||\
|
||
|
|
((TISEL) == TIM_TIM3_TI1_COMP1COMP2_OUT) ||\
|
||
|
|
((TISEL) == TIM_TIM5_TI1_GPIO) ||\
|
||
|
|
((TISEL) == TIM_TIM5_TI1_CAN_TMP) ||\
|
||
|
|
((TISEL) == TIM_TIM5_TI1_CAN_RTP) ||\
|
||
|
|
((TISEL) == TIM_TIM15_TI1_GPIO) ||\
|
||
|
|
((TISEL) == TIM_TIM15_TI1_TIM2_CH1) ||\
|
||
|
|
((TISEL) == TIM_TIM15_TI1_TIM3_CH1) ||\
|
||
|
|
((TISEL) == TIM_TIM15_TI1_TIM4_CH1) ||\
|
||
|
|
((TISEL) == TIM_TIM15_TI1_RCC_LSE) ||\
|
||
|
|
((TISEL) == TIM_TIM15_TI1_RCC_CSI) ||\
|
||
|
|
((TISEL) == TIM_TIM15_TI1_RCC_MCO2) ||\
|
||
|
|
((TISEL) == TIM_TIM15_TI2_GPIO) ||\
|
||
|
|
((TISEL) == TIM_TIM15_TI2_TIM2_CH2) ||\
|
||
|
|
((TISEL) == TIM_TIM15_TI2_TIM3_CH2) ||\
|
||
|
|
((TISEL) == TIM_TIM15_TI2_TIM4_CH2) ||\
|
||
|
|
((TISEL) == TIM_TIM16_TI1_GPIO) ||\
|
||
|
|
((TISEL) == TIM_TIM16_TI1_RCC_LSI) ||\
|
||
|
|
((TISEL) == TIM_TIM16_TI1_RCC_LSE) ||\
|
||
|
|
((TISEL) == TIM_TIM16_TI1_WKUP_IT) ||\
|
||
|
|
((TISEL) == TIM_TIM17_TI1_GPIO) ||\
|
||
|
|
((TISEL) == TIM_TIM17_TI1_SPDIF_FS) ||\
|
||
|
|
((TISEL) == TIM_TIM17_TI1_RCC_HSE1MHZ) ||\
|
||
|
|
((TISEL) == TIM_TIM17_TI1_RCC_MCO1))
|
||
|
|
|
||
|
|
#define IS_TIM_BKR2REMAP(BK2RREMAP) (((BKR2REMAP) == TIM_TIM1_BKR_GPIO) ||\
|
||
|
|
((BKR2REMAP) == TIM_TIM1_BKR_GPIO) ||\
|
||
|
|
((BKR2REMAP) == TIM_TIM1_BKR_GPIO) ||\
|
||
|
|
((BKR2REMAP) == TIM_TIM1_BKR_GPIO) ||\
|
||
|
|
((BKR2REMAP) == TIM_TIM1_BKR_GPIO) ||\
|
||
|
|
((BKR2REMAP) == TIM_TIM1_BKR_GPIO) ||\
|
||
|
|
((BKR2REMAP) == TIM_TIM1_BKR_GPIO) ||\
|
||
|
|
((BKR2REMAP) == TIM_TIM1_BKR_GPIO))
|
||
|
|
|
||
|
|
#define IS_TIM_BKRREMAP(BKRREMAP) (((BKRREMAP) == TIM_TIM1_BKR_GPIO) ||\
|
||
|
|
((BKRREMAP) == TIM_TIM1_BKR_COMP1_OUT) ||\
|
||
|
|
((BKRREMAP) == TIM_TIM1_BKR_COMP2_OUT) ||\
|
||
|
|
((BKRREMAP) == TIM_TIM1_BKR_DFSDM_BRK0) ||\
|
||
|
|
((BKRREMAP) == TIM_TIM8_BKR_GPIO) ||\
|
||
|
|
((BKRREMAP) == TIM_TIM8_BKR_COMP1_OUT) ||\
|
||
|
|
((BKRREMAP) == TIM_TIM8_BKR_COMP2_OUT) ||\
|
||
|
|
((BKRREMAP) == TIM_TIM8_BKR_DFSDM_BRK2) ||\
|
||
|
|
((BKRREMAP) == TIM_TIM15_BKR_GPIO) ||\
|
||
|
|
((BKRREMAP) == TIM_TIM15_BKR_COMP1_OUT) ||\
|
||
|
|
((BKRREMAP) == TIM_TIM15_BKR_COMP2_OUT) ||\
|
||
|
|
((BKRREMAP) == TIM_TIM15_BKR_DFSDM_BRK0) ||\
|
||
|
|
((BKRREMAP) == TIM_TIM16_BKR_GPIO) ||\
|
||
|
|
((BKRREMAP) == TIM_TIM16_BKR_COMP1_OUT) ||\
|
||
|
|
((BKRREMAP) == TIM_TIM16_BKR_COMP2_OUT) ||\
|
||
|
|
((BKRREMAP) == TIM_TIM16_BKR_DFSDM_BRK1) ||\
|
||
|
|
((BKRREMAP) == TIM_TIM17_BKR_GPIO) ||\
|
||
|
|
((BKRREMAP) == TIM_TIM17_BKR_COMP1_OUT) ||\
|
||
|
|
((BKRREMAP) == TIM_TIM17_BKR_COMP2_OUT) ||\
|
||
|
|
((BKRREMAP) == TIM_TIM17_BKR_DFSDM_BRK2))
|
||
|
|
|
||
|
|
#define IS_TIM_ETRREMAP(ETRREMAP) (((ETRREMAP) == TIM_TIM1_ETR_GPIO) ||\
|
||
|
|
((ETRREMAP) == TIM_TIM1_ETR_ADC1_AWD1) ||\
|
||
|
|
((ETRREMAP) == TIM_TIM1_ETR_ADC1_AWD2) ||\
|
||
|
|
((ETRREMAP) == TIM_TIM1_ETR_ADC1_AWD3) ||\
|
||
|
|
((ETRREMAP) == TIM_TIM1_ETR_ADC3_AWD1) ||\
|
||
|
|
((ETRREMAP) == TIM_TIM1_ETR_ADC3_AWD2) ||\
|
||
|
|
((ETRREMAP) == TIM_TIM1_ETR_ADC3_AWD3) ||\
|
||
|
|
((ETRREMAP) == TIM_TIM1_ETR_COMP1_OUT) ||\
|
||
|
|
((ETRREMAP) == TIM_TIM1_ETR_COMP2_OUT) ||\
|
||
|
|
((ETRREMAP) == TIM_TIM8_ETR_GPIO) ||\
|
||
|
|
((ETRREMAP) == TIM_TIM8_ETR_ADC2_AWD1) ||\
|
||
|
|
((ETRREMAP) == TIM_TIM8_ETR_ADC2_AWD2) ||\
|
||
|
|
((ETRREMAP) == TIM_TIM8_ETR_ADC2_AWD3) ||\
|
||
|
|
((ETRREMAP) == TIM_TIM8_ETR_ADC3_AWD1) ||\
|
||
|
|
((ETRREMAP) == TIM_TIM8_ETR_ADC3_AWD2) ||\
|
||
|
|
((ETRREMAP) == TIM_TIM8_ETR_ADC3_AWD3) ||\
|
||
|
|
((ETRREMAP) == TIM_TIM8_ETR_COMP1_OUT) ||\
|
||
|
|
((ETRREMAP) == TIM_TIM8_ETR_COMP2_OUT) ||\
|
||
|
|
((ETRREMAP) == TIM_TIM2_ETR_GPIO) ||\
|
||
|
|
((ETRREMAP) == TIM_TIM2_ETR_COMP1_OUT) ||\
|
||
|
|
((ETRREMAP) == TIM_TIM2_ETR_COMP2_OUT) ||\
|
||
|
|
((ETRREMAP) == TIM_TIM2_ETR_RCC_LSE) ||\
|
||
|
|
((ETRREMAP) == TIM_TIM2_ETR_SAI1_FSA) ||\
|
||
|
|
((ETRREMAP) == TIM_TIM2_ETR_SAI1_FSB) ||\
|
||
|
|
((ETRREMAP) == TIM_TIM3_ETR_GPIO) ||\
|
||
|
|
((ETRREMAP) == TIM_TIM3_ETR_COMP1_OUT) ||\
|
||
|
|
((ETRREMAP) == TIM_TIM5_ETR_GPIO) ||\
|
||
|
|
((ETRREMAP) == TIM_TIM5_ETR_SAI2_FSA) |\
|
||
|
|
((ETRREMAP) == TIM_TIM5_ETR_SAI2_FSB))
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
/* End of private macro ------------------------------------------------------*/
|
||
|
|
|
||
|
|
/* Exported functions --------------------------------------------------------*/
|
||
|
|
/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
|
||
|
|
* @brief Timer Hall Sensor functions
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
/* Timer Hall Sensor functions **********************************************/
|
||
|
|
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig);
|
||
|
|
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
|
||
|
|
|
||
|
|
void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
|
||
|
|
void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
|
||
|
|
|
||
|
|
/* Blocking mode: Polling */
|
||
|
|
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
|
||
|
|
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
|
||
|
|
/* Non-Blocking mode: Interrupt */
|
||
|
|
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
|
||
|
|
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
|
||
|
|
/* Non-Blocking mode: DMA */
|
||
|
|
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
|
||
|
|
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
|
||
|
|
* @brief Timer Complementary Output Compare functions
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
/* Timer Complementary Output Compare functions *****************************/
|
||
|
|
/* Blocking mode: Polling */
|
||
|
|
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||
|
|
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||
|
|
|
||
|
|
/* Non-Blocking mode: Interrupt */
|
||
|
|
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||
|
|
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||
|
|
|
||
|
|
/* Non-Blocking mode: DMA */
|
||
|
|
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
|
||
|
|
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
|
||
|
|
* @brief Timer Complementary PWM functions
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
/* Timer Complementary PWM functions ****************************************/
|
||
|
|
/* Blocking mode: Polling */
|
||
|
|
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||
|
|
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||
|
|
|
||
|
|
/* Non-Blocking mode: Interrupt */
|
||
|
|
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||
|
|
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||
|
|
/* Non-Blocking mode: DMA */
|
||
|
|
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
|
||
|
|
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
|
||
|
|
* @brief Timer Complementary One Pulse functions
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
/* Timer Complementary One Pulse functions **********************************/
|
||
|
|
/* Blocking mode: Polling */
|
||
|
|
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||
|
|
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||
|
|
|
||
|
|
/* Non-Blocking mode: Interrupt */
|
||
|
|
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||
|
|
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
|
||
|
|
* @brief Peripheral Control functions
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
/* Extended Control functions ************************************************/
|
||
|
|
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
|
||
|
|
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
|
||
|
|
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
|
||
|
|
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig);
|
||
|
|
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
|
||
|
|
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
|
||
|
|
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
|
||
|
|
HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection , uint32_t Channel);
|
||
|
|
HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
|
||
|
|
* @brief Extended Callbacks functions
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
/* Extended Callback *********************************************************/
|
||
|
|
void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim);
|
||
|
|
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
|
||
|
|
* @brief Extended Peripheral State functions
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
/* Extended Peripheral State functions **************************************/
|
||
|
|
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
/* End of exported functions -------------------------------------------------*/
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
/* Private functions----------------------------------------------------------*/
|
||
|
|
/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
/* End of private functions --------------------------------------------------*/
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* __STM32H7xx_HAL_TIM_EX_H */
|
||
|
|
|
||
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|